Memory modules, electronic devices, and data migration methods

Abstract

To implement a low-cost memory expansion solution for server systems, memory modules, electronic devices, and data migration methods are provided. A solution in which cold and hot migrations are performed jointly by using processing modules within the memory module and components outside the module can reduce the workload on the processing module, and to help implement a low-cost memory expansion solution for server systems, it has a simpler R&D process and requires lower labor and R&D costs than a solution in which the integrated unit within the memory module is redeveloped to perform cold and hot migrations independently. Furthermore, the power pins of the gold finger connector within the memory module are redefined as pins with a width greater than the original power pin width, resulting in improved through-current capability of the power pins and increased power supply. This increased power supply can support a larger array of storage media within the memory module to further expand the server system's memory.

Description

Technical Field

[0001] Cross - reference to related applications This application claims priority to Chinese Patent Application No. 202310685185.3, titled "MEMORY MODULE AND ELECTRONIC DEVICE", filed with the China National Intellectual Property Administration on June 9, 2023, and Chinese Patent Application No. 202410133042.6, titled "MEMORY MODULE, ELECTRONIC DEVICE, AND DATA MIGRATION METHOD", filed with the China National Intellectual Property Administration on January 30, 2024, and both are hereby incorporated by reference in their entirety into this specification.

[0002] This application relates to the field of memory technology, and particularly to memory modules, electronic devices, and data migration methods.

Background Art

[0003] In conventional server systems, memory and the central processing unit (CPU) are typically encapsulated together on the server mainboard. However, the number of memory modules that can be encapsulated in a processor is limited by rack size. See, for example, Figure 1. Currently, most mainstream servers are mounted in 19-inch racks, which limit the maximum width of the server mainboard to approximately 430 mm. Due to these size limitations, when using the current mainstream memory control design with 8 channels, a maximum of 32 dual inline memory modules (DIMMs) (DIMM per channel, DPC) can be placed on the server mainboard in 2 dual inline memory modules (DIMMs) (DIMM per channel, DPC) mode. For example, 32 double data rate synchronous dynamic random access memory (DDR SRAM) modules can be placed. DDR SRAM is abbreviated as DDR in Figure 1. Some CPUs can use memory control designs with up to 12 channels, but the system can only support 1 DPC mode during implementation. When a dual-processor configuration is implemented, a maximum of 24 DIMMs can be placed. In conclusion, it is difficult to improve memory performance and memory capacity in conventional server systems.

[0004] To address the limitations of conventional server systems in terms of limited memory performance and capacity, the industry has proposed new server systems. (See Figure 2.) In these new server systems, DDR is encapsulated on the server mainboard, with several memory modules further located outside the mainboard. Application-specific integrated circuits (ASICs) and DDR are encapsulated within each memory module, and the CPU connects to the ASIC within each memory module via a serial bus to access the DDR within that module. While the new server system allows for expansion using more DDR outside the mainboard, the DDR within memory modules has a longer access delay than the DDR on the mainboard. For example, accessing DDR on the mainboard typically requires only a few nanoseconds (ns), whereas accessing DDR in memory modules requires tens of nanoseconds. Currently, to reduce the access delay of frequently accessed data, some solutions exist where the ASIC within the memory module is used to migrate frequently accessed data from the memory module to the mainboard. However, these solutions require the redevelopment of the ASIC within the memory module, resulting in high labor and research and development costs. This is not helpful in implementing low-cost design concepts for server systems.

[0005] Therefore, further research is needed on low-cost memory expansion solutions for server systems. [Overview of the Initiative]

[0006] This application provides a memory module, an electronic device, and a data migration method for implementing a low-cost memory expansion solution for server systems. [Means for solving the problem]

[0007] According to a first aspect, the present invention provides a memory module including a processing module and a goldfinger connector connected to the processing module. The goldfinger connector is configured to plug into a component outside the memory module to implement a communication connection between a component inside the memory module and a component outside the memory module. The processing module is configured to receive read / write requests from the component outside the memory module via the goldfinger connector, access at least one storage medium in the memory module based on the read / write request, and transmit access frequency information for each storage address corresponding to at least one storage medium in the memory module to the component outside the memory module via the goldfinger connector. The access frequency information for each storage address is used by the component outside the memory module to transfer data stored in storage addresses whose access frequency is greater than a hotness threshold to a storage medium connected to the processor.

[0008] When cold and hot migration functions are implemented using memory modules, the processing module within the memory module may be configured to transmit access frequency information of the storage medium within the memory module to the external components in order to complete the cold and hot migration in cooperation with the external components. In this way, only the information transmission function may be newly added to the memory module, based on its ability to access the storage medium. Compared to a solution in which the ASIC within the memory module is redeveloped to independently implement the memory migration function, this approach may have lower development difficulty and introduce lower additional development and labor costs. In this way, low-cost memory expansion of the server can be implemented.

[0009] In a possible design, the processing module may include a first integration unit and a second integration unit. The first integration unit is connected to at least one storage medium within the memory module, and the goldfinger connector is connected to both the first and second integration units. The first integration unit is configured to receive read / write requests from components outside the memory module via the goldfinger connector and to access at least one storage medium within the memory module based on the read / write requests. The second integration unit is configured to send access frequency information for each storage address corresponding to at least one storage medium within the memory module to components outside the memory module via the goldfinger connector.

[0010] In the aforementioned design, the first integration unit may be understood as an ASIC within an existing memory module. The second integration unit is newly added to the memory module, and as a result, the server's cold and hot migration solution can be implemented by developing the second integration unit without requiring the redevelopment of the first integration unit. Compared to redeveloping the first integration unit, developing the second integration unit has a simpler research and development process. For example, the arrangement and wiring of the original components within the first integration unit do not need to be modified, and there is no need to consider how to arrange the position of the components to avoid interference caused to the original function of the first integration unit by the cold and hot migration function, resulting in lower labor and research and development costs. It can be seen that the memory module can implement the cold and hot migration solution, improve the server's memory performance, and introduce the least possible additional cost. This helps implement low-cost memory expansion of the server without increasing the load on the first integration unit within the memory module.

[0011] In the possible embodiments of the design described above, one or more reserved pins of the Goldfinger connector are defined as out-of-band communication pins, and the second integration unit is connected to the out-of-band communication pins via an out-of-band communication bus. In this way, after the memory module is plugged into the components outside the memory module via the Goldfinger connector, the out-of-band communication bus may perform the connection between the second integration unit and the Goldfinger connector, or the connection between the second integration unit and the components outside the memory module. The second integration unit may send access frequency information for each storage address of at least one storage medium in the memory module to the components outside the memory module via the connection.

[0012] In a further possible embodiment, the out-of-band communication pins transmit access frequency information by using differential signaling. In this case, pins B68 and B69 of the Goldfinger connector may be defined as two transmit pins, and pins A68 and A69 of the Goldfinger connector may be defined as two receive pins. The second integration unit is configured to send access frequency information for each storage address of at least one storage medium in the memory module to the Goldfinger connector via pins B68 and B69, and to receive the returned information from the Goldfinger connector via pins A68 and A69, in order to transfer the access frequency information to an external component via the Goldfinger connector. The returned information may be sent to the Goldfinger connector by an external component, for example. In this way, differential signaling can be transferred between the second integration unit and the external component via the two transmit pins and the two receive pins.

[0013] In possible embodiments of the design described above, the memory module may further include control address lines, and the first integration unit is connected to at least one storage medium in the memory module via the control address lines. The first integration unit is specifically configured to access at least one storage medium in the memory module by adjusting a control address (CA) signal on the control address lines. A second integration unit is specifically configured to determine, based on changes in the CA signal on the control address lines, access frequency information for a storage address corresponding to at least one storage medium in the memory module in which the second integration unit is installed, within a predetermined period. According to this design, since read / write operations on storage addresses are triggered and performed using the CA signal, the second integration unit can detect the access status of each storage address in real time by monitoring changes in the CA signal, which helps improve the accuracy of collecting statistics on access frequency information.

[0014] In a possible design, the processing module may contain only one integration unit, which is connected between at least one storage medium within the memory module and a goldfinger connector. Thus, the original first integration unit within the memory module can be simply modified to jointly implement cold and hot migration solutions by using the modified first integration unit and components outside the module together. The structure of the processing module is simple, and communication between multiple integration units is unnecessary. This helps reduce communication loss.

[0015] It will be understood that a processing module may optionally include three or more integration units. Each integration unit shares some of the functions of the processing module, and three or more integration units jointly perform all of the functions of the processing module. There are many possible embodiments that are not listed one by one in this specification.

[0016] In a possible design, the first positive pin is located in the area where pins B1 to B6 of the Goldfinger connector are installed, and the first ground pin is located in the area where pins A1 to A6 of the Goldfinger connector are installed, with both the width of the first positive pin and the first ground pin being greater than a preset width, which is the standard defined width of the original pin.

[0017] In the aforementioned design, the power pins of the gold finger connector are redefined, resulting in a pin width greater than that of the original power pins as defined by standard. This allows for an increase in the area of ​​the conductive springs corresponding to the power pins to improve the through-current capability of the power pins and to increase the power supplied by the power pins. Furthermore, the increased power supply can support the arrangement of more storage media within the memory module, further expanding the memory module's storage capacity.

[0018] In the possible embodiments of the design described above, given that there are six groups of original power pins, the number of redefined power pins may be any value less than six. It is assumed that the preset width is K. In this case:

[0019] In some possible embodiments, there is one group of power pins after redefinition. In this case, the widths of both the first positive pin and the first ground pin can be configured as 11K. For example, if the original pin width is 0.3mm, the widths of both the first positive pin and the first ground pin can be configured as 3.3mm. In this way, only one group of power pins is arranged in the area where the original B1 to B6 pins of the goldfinger connector are installed, and as a result, the pin width of the group of power pins can be maximized to maximize the power supply capability, and the through-current capability of the power pins can be maximized.

[0020] In some other possible embodiments, there are two groups of power pins after redefinition. In this case, the width of each first positive pin and each first ground pin may both be configured as 5K, or the width of one first positive pin and one first ground pin may be configured as 7K, and the width of the other first positive pin and the other first ground pin may be configured as 3K. For example, if the width of the original pins is 0.3mm, the widths of the two first positive pins and the two first ground pins may all be configured as 1.5mm, or the width of one first positive pin and one first ground pin may be 2.1mm, and the width of the other first positive pin and the other first ground pin may be 0.9mm. In this way, two groups of power pins are arranged in the area where the original B1 to B6 pins of the Goldfinger connector are installed, and as a result, the pin width of the power pins can be increased, the power supply capacity of the power pins can be improved, and the Goldfinger connector can be plugged in and unplugged better than a Goldfinger connector with only one group of power pins. Furthermore, the width of the power pins in both groups is configured to be greater than the width of the original power pins, and as a result, the power supply capacity of each group of power pins can be greater than the power supply capacity of the original power pins. In this way, even if only one of the groups of power pins is used for power, a good power efficiency can be achieved.

[0021] In several other possible embodiments, there are three groups of power pins after redefinition. In this case, the width of each first positive pin and each first ground pin can both be configured as 3K. For example, if the original pin width is 0.3mm, the three first positive pins and the three first ground pins can all be configured as 0.9mm. In this way, the three groups of power pins are arranged in the area where the original B1 to B6 pins of the Goldfinger connector are installed, and as a result, the pin width of the power pins can be increased, the power supply capacity of the power pins can be improved, and the Goldfinger connector has less frictional force than a Goldfinger connector with only one or two groups of power pins, making flexible plugging and unplugging of the Goldfinger connector easier. Also, the three groups of power pins are configured to have the same width, and as a result, the three groups of power pins can have the same power supply capacity. This helps to balance the power of the different power pins on the Goldfinger connector.

[0022] It should be noted that after redefinition, there may be more than three groups of power pins, and alternatively, there may be four or five groups of power pins, for example. However, in a solution with four or five groups of power pins, the width of the power pins in one or more groups is the same as the width of the original power pins. The improvement in the power supply capacity of the solution is limited, but plugging in and unplugging is more convenient. Therefore, in some possible designs, in scenarios with high requirements for plugging in and unplugging, four or five groups of power pins may be configured to meet the requirements for flexible plugging in and unplugging. In scenarios with high requirements for power supply capacity, one, two, or three groups of power pins may be configured to meet the high power supply requirements.

[0023] In possible embodiments of the design described above, the first positive pin and the first ground pin may be made of gold-plated copper, and as a result the power pins have the advantages of a beautiful appearance, good corrosion resistance, wear resistance, and convenient maintenance.

[0024] According to a second aspect, the present application provides an electronic device. The electronic device may be any device having cold and hot transition capabilities, such as a server, or a computer device having a display screen and a server. The electronic device may include a memory module in either the first aspect or a design of the first aspect.

[0025] In possible designs, the electronic device may further include an electronic device mainboard and a media management board. The electronic device mainboard includes a processor and at least one first storage medium, and each memory module includes at least one second storage medium, with the number of memory modules being N, where N is a positive integer. Any memory module is configured to send access frequency information to the media management board for each second storage address corresponding to at least one second storage medium in the memory module within a pre-configured period. The media management board is configured to send access frequency information to the processor for each second storage address corresponding to each second storage medium in each of the N memory modules within a pre-configured period. The processor is configured to move data stored in target second storage addresses with an access frequency greater than a hotness threshold to the first storage medium, and to move data stored in target first storage addresses with an access frequency less than a coldness threshold to the second storage medium, based on access frequency information for each first storage address corresponding to at least one first storage medium within a pre-configured period, and access frequency information for each second storage address corresponding to each second storage medium in N memory modules within a pre-configured period.

[0026] In the foregoing solution, the delay in the processor's access to the first storage medium within the electronic device main board is smaller than the delay in the processor's access to the second storage medium within the memory module. Therefore, the hot data within the memory module is transferred to the electronic device main board, and as a result, the processor can access the hot data more quickly, and the data access performance can be improved. The cold data within the electronic device main board is transferred to the memory module, and as a result, the occupancy of the cold data within the electronic device main board can also be released, and the storage capacity of the hot data can be increased.

[0027] In a possible design, the processing module includes a first integrated unit and a second integrated unit. The first integrated unit within any memory module is configured to access at least one second storage medium within the memory module in which the first integrated unit is installed. The second integrated unit within any memory module is configured to send the access frequency information of each second storage address within at least one second storage medium within the memory module in which the second integrated unit is installed within a preset period to the media management board.

[0028] In the foregoing design, compared with the cold and hot migration solutions of the new server system, thus, one second integrated unit is additionally added to the existing memory module, and the frequently accessed data within the second storage medium within the memory module in which the second integrated unit is installed may be transferred to the first storage medium within the electronic device main board via the second integrated unit, and there is no need to redevelop the first integrated unit within the memory module. Compared with redeveloping the first integrated unit, the operation of developing the second integrated unit has a simpler research and development process and requires low labor costs and research and development costs. It can be seen that this solution can not only improve the memory performance of the server, but also introduce additional costs as low as possible. This helps to implement a low-cost memory expansion solution for the server system.

[0029] In a possible design, the media management board may include a third integrated unit and a fourth integrated unit. The third integrated unit is separately connected to the fourth integrated unit and the second integrated unit in each memory module. The fourth integrated unit is further connected to the processor. The third integrated unit receives access frequency information of each second storage address in the memory module within a preset period sent by the second integrated unit in each memory module, collects access frequency information of each second storage address in N memory modules within the preset period, and is configured to send the collected access frequency information to the fourth integrated unit. The fourth integrated unit is configured to send the collected access frequency information of each second storage address in N memory modules within the preset period to the processor.

[0030] In the aforementioned design, the third integrated unit may be understood as an integrated unit within the existing media management board. The fourth integrated unit is additionally added to the media management board, and the access frequency corresponding to each memory module may be sent to the processor via the fourth integrated unit. The third integrated unit does not need to execute the transfer, and the impact on the original communication procedure of the third integrated unit is reduced as much as possible. In other words, this design can implement cold and hot migration solutions based on the original component architecture of the server as much as possible, reduce the redevelopment of the original components, and minimize the impact on the functions of the original components.

[0031] In a further possible design, to implement the communication connection between the fourth integrated unit and the processor, reduce costs, and improve communication quality, the fourth integrated unit and the processor may be connected via a universal serial bus (USB) or a peripheral component interconnect express (PCIe) bus.

[0032] In another possible design, the media management board may alternatively include only one integration unit. The integration unit is configured to connect separately to the processing module within each memory module and to the processor in the electronic device mainboard, to receive access frequency information for each second memory address within each memory module within a predetermined period, sent by the processing module within each memory module, to collect access frequency information for each second memory address within N memory modules within the predetermined period, and to send the collected access frequency information to the processor in the electronic device mainboard. In this design, the structure of the media management board is simple, and communication between multiple integration units is unnecessary. This helps reduce communication loss. Alternatively, in yet another possible design, the media management board may include three or more integration units. Each integration unit shares some functions of the media management board, and three or more integration units jointly perform all functions of the media management board. There are many possible embodiments not listed one by one herein.

[0033] According to a third aspect, the present application provides a data migration method. The method may be performed by a memory module in either the first aspect or the design of the first aspect, or by an electronic device in either the second aspect or the design of the second aspect. The method includes the steps of: obtaining cold and hot migration instructions, the cold and hot migration instructions conveying at least one of cold data in a first memory address associated with a processor, or address information of a second memory address associated with a memory module; sending hot data in a second memory address to a processor in an electronic device based on the address information of the second memory address conveyed by the cold and hot migration instructions; and storing the cold data in the first memory address conveyed by the cold and hot migration instructions in the second memory address.

[0034] In this specification, “associated” may be understood as “logically connected” or “functionally accessible.” For example, a first memory address associated with a processor is a memory address that can be directly accessed by the processor in the electronic device mainboard, and may, for example, be a memory address located within the electronic device mainboard. The memory address is directly connected to the processor in the electronic device mainboard, and the internal data of the memory address may be directly accessed by the processor in the electronic device mainboard. Similarly, a second memory address associated with a memory module is a memory address that can be directly accessed by the processing module in the memory module, and may, for example, be a memory address located within the memory module. The memory address is directly connected to the processing module in the memory module, and the internal data of the memory address may be directly accessed by the processing module in the memory module.

[0035] In a possible design, prior to the step of obtaining cold and hot transition instructions, the method may further include the steps of accessing one or more second storage addresses associated with a memory module and sending access frequency information for each second storage address associated with the memory module to a media management board in the electronic device.

[0036] According to a fourth aspect, the present application provides a cold and hot data transfer device. The cold and hot data transfer device may be a processing unit within a memory module, for example, a processing module. The device includes an acquisition module configured to acquire cold and hot transfer instructions, the acquisition module conveying at least one of cold data in a first storage address associated with a processor or address information of a second storage address associated with a memory module; a transceiver module configured to send hot data in a second storage address to a processor in an electronic device based on the address information of the second storage address conveyed by the cold and hot transfer instructions; and a storage module configured to store the cold data in the first storage address conveyed by the cold and hot transfer instructions in the second storage address.

[0037] According to a fifth aspect, the present application provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a cold and hot data transfer device, a method according to the third aspect or any one of the third aspects is carried out.

[0038] According to the sixth aspect, the present application provides a computer program product. When the computer program product is executed on a data transfer device, a method according to the third aspect or one of the third aspects is carried out.

[0039] The design of the first embodiment is also applicable to the second through sixth embodiments. For corresponding beneficial effects, please refer to the technical effects that can be achieved by the corresponding design of the first embodiment. Further details are not provided here. [Brief explanation of the drawing]

[0040] [Figure 1] This is an example diagram of the arrangement of server mainboards within a rack. [Figure 2]This is an example of a diagram of the new server's system architecture. [Figure 3] This is an example of a diagram illustrating an application scenario for the server described in this application. [Figure 4] This is an example of a diagram of the server system architecture according to this application. [Figure 5a] This is an example of a diagram of a specific server architecture according to this application. [Figure 5b] This is an example of a diagram illustrating a specific architecture of another server according to this application. [Figure 6a] This is an example of a diagram illustrating the product structure of a memory module according to this application. [Figure 6b] This is an example of a diagram illustrating the product structure of another memory module according to this application. [Figure 7] This is an example of a diagram comparing the structure of the gold finger connector before and after redefinition according to this application. [Figure 8] This is an example of a diagram showing the possible power pin configurations before and after redefinition according to this application. [Figure 9] This is an example of a schematic flowchart illustrating the interaction between the cold and hot transition solutions provided in this application. [Figure 10] This is an example of a diagram of the internal circuitry of a memory module according to this application. [Figure 11] This is an example of a diagram of the internal circuitry of another memory module according to this application. [Figure 12] This is an example of a diagram illustrating the structure of a data transfer device according to this application. [Modes for carrying out the invention]

[0041] The present application will be described in detail below with reference to the attached drawings.

[0042] Several terms used in this application are explained and described below. Please note that these explanations are provided to facilitate understanding by those skilled in the art and are not intended to limit the scope of protection claimed in this application.

[0043] 1. Storage medium and storage address Storage media are generally made of semiconductor materials and are configured to temporarily store operational data and exchange data with external memory such as hard disks. Storage media include several types of memory, such as dynamic random access memory (DRAM) and double data rate synchronous dynamic random access memory (DDR SRAM). DDR SRAM is also commonly referred to simply as DDR.

[0044] A memory address is an identifier for a memory location, and data stored in a storage medium can be found by using an index of memory addresses. In some scenarios, a storage medium may contain multiple memory cells, and each memory cell may have its own memory address. For example, hexadecimal is used as an example. Assume that a complete storage medium contains 17 memory cells, and the physical addresses of these memory cells are sequentially 0x0000 to 0x0010. In this case, 0x0000 represents the memory address of the first memory cell of the storage medium, 0x0001 represents the memory address of the second memory cell of the storage medium, ..., 0x0010 represents the memory address of the 17th memory cell of the storage medium. Indeed, with advancements in storage technology, the memory addresses of memory cells may be represented using a virtual address scheme in the future, and the physical addresses corresponding to the virtual addresses may be found by querying a pre-configured address mapping table.

[0045] 2. Memory controller The memory controller is configured to manage data exchange between the storage medium and the processing unit. The memory controller may be a separate chip or it may be integrated into the storage medium or the processing unit. Please refer to Figure 2 for further details. In a new server system, the server mainboard and the memory modules may each have their own memory controllers. The memory controller in the server mainboard may be integrated into, for example, the central processing unit (CPU), and the memory controller in the memory module may be integrated into, for example, an application-specific integrated circuit (ASIC).

[0046] 3. Gold finger connector (connecting finger) Goldfinger connectors, also known as edgeboard connectors, are typically used in scenarios where a storage medium is connected to a slot and a graphics card is connected to a graphics card slot, and are used for transmitting all signals between the two connected components. Goldfinger connectors generally contain a number of gold-yellow conductive springs. The surface of the goldfinger connector is gold-plated, and the conductive springs are arranged in a finger-like pattern, hence the common name "goldfinger connector."

[0047] The above explains some of the terms used in this application, and the following describes possible application scenarios of this application.

[0048] In possible embodiments, the memory module may be integrated into the server, or it may be located in a memory slot within the server housing, for example, or it may be plugged into the server mainboard. Figure 3 is an example diagram of a possible application scenario according to this application. In this application scenario, an example is used in which the server is a rack server and the rack server is located in the reserved central position of the rack. It will be understood that the rack server may be alternatively located in other positions in the rack, for example, outside one or more of the four directions: up, down, left, or right, in order to reduce the number of racks it is installed in.

[0049] It should be understood that the application scenarios described above are merely examples. The memory module provided in this application may be used in other possible scenarios, and is not limited to the examples described above. For example, the memory module may be integrated as an alternative to any type of server, such as a tower server, blade server, high-density server, or cabinet server. As another example, the memory module may be integrated as an alternative to a non-server, for example, integrated to a terminal device, or used as additional memory obtained by expansion to improve the storage capacity of the terminal device. As yet another example, the memory module may be integrated as an alternative to a vehicle, or used as a medium for storing vehicle-specific information or other non-key information to expand the vehicle's storage space. Examples are not listed one by one in this specification. It should be noted that the application scenarios described in this application are intended to more clearly illustrate the technical solutions in this application and do not constitute limitations on the technical solutions provided in this application.

[0050] In recent years, with the continuous development of semiconductor technology, the processing power and number of cores of processors have basically doubled or tripled every two years. However, the development of memory technology has lagged behind, basically increasing by two or three times every three years. After many years of asynchronous development, the total memory capacity of servers has increased, but in reality, the memory capacity of each core within the server's internal processor has gradually decreased. In particular, the memory bandwidth of servers has decreased more clearly. Consequently, the delay in memory access by the processor has not decreased, but has increased by 30%.

[0051] To address this imbalance in processor and memory development, the industry has proposed a new server system, as shown in Figure 2. However, as explained in the background technology, this new server system requires the redesign of the ASIC within the memory module. In addition to accessing the DDR within the memory module where the ASIC is installed, it is also necessary to migrate frequently accessed data from the DDR within the memory module to the DDR on the server mainboard. In this case, the device arrangement within the original ASIC in the memory module must be manually modified. Not only do new devices need to be added to perform the new function, but consideration must also be given to preventing interference in signal transmission between devices performing the two functions. While the server's memory access performance is improved, it comes at enormous labor and R&D costs, placing significant workload pressure on the ASIC within the memory module.

[0052] In consideration of the above issues, this application provides a memory module that does not require modification of the ASIC within an existing memory module, or requires only minor modification of the ASIC within an existing memory module, in order to jointly implement cold and hot migration solutions with components outside the module. As a result, additional costs are introduced as little as possible in the memory expansion process, and the workload on the memory module is reduced.

[0053] Based on the foregoing, the solutions provided in this application will be described in detail below with reference to the attached drawings.

[0054] The following “first storage medium” is a storage medium within an electronic device mainboard (e.g., a server mainboard), and it should be noted that the first storage medium is connected to a processor within the electronic device mainboard, and the internal data of the first storage medium may be directly accessed by the processor within the electronic device mainboard. The “second storage medium” is a storage medium within a memory module. The second storage medium is directly connected to a processing module within the memory module, and the internal data of the second storage medium may be directly accessed by the processing module within the memory module. Therefore, the following “first storage medium” may also be replaced with a storage medium within an electronic device mainboard, a storage medium associated with a processor, a storage medium connected to a processor, or another similar name, and the “second storage medium” may also be replaced with a storage medium within a memory module, a storage medium associated with a memory module, a storage medium connected to a processing module within a memory module, or another similar name. This is not particularly limited in this application. Furthermore, embodiments of the first or second storage medium may be memory or external memory. This is not specifically limited.

[0055] Figure 4 is a diagram of the system architecture of the server according to this application. The system architecture includes a server main board 410, a media management board 420, and N memory modules such as memory module 431, memory module 432, ..., and memory module 43N, where N is a positive integer. From the perspective of memory modules, the server main board 410 and the media management board 420 may be considered components outside of the memory modules. Below, we will first describe the structure and connectivity of the components within the server system.

[0056] The server mainboard 410, also called the mainboard, system board, or motherboard, is mounted within the chassis and is a core component of the server. The server mainboard 410 may include a processor 411 and at least one first storage medium. Figure 4 uses an example where eight first storage mediums are included, and the first storage mediums are DDR, named DDR01, DDR02, ..., and DDR08. The processor 411 may be, for example, a CPU. In some scenarios, the processor 411 may alternatively be a graphics processing unit (GPU), a neural network processing unit (NPU), etc. The processor 411 may be connected separately to DDR01-DDR08. Specifically, the processor 411 may be connected to DDR01-DDR08 via a memory controller integrated into the processor 411. For example, when 2DPC mode is used, one memory controller may be connected to two DDRs. Therefore, four memory controllers need to be integrated into the processor 411. As another example, when 1DPC mode is used, one memory controller may be connected to one DDR. Therefore, eight memory controllers need to be integrated into the processor 411. Since DDR01 to DDR08 are close to the processor 411 and can be directly accessed by the processor 411, in some scenarios DDR01 to DDR08 are also referred to as near-end memory or one-level (L1) memory of the processor 411.

[0057] The media management board 420 is an integrated board configured to manage storage media such as hard disks and memory modules within the server, and may be configured to manage the temperature, occupancy, indicator status, etc., of these storage media. The media management board 420 may include a third integrated unit 421 and a fourth integrated unit 422. The third integrated unit 421 may be, for example, the original complex programmable logic device (CPLD) (not shown in Figure 2) in the new server system shown in Figure 2, or another unit or module with processing capabilities, and is configured to perform the original management operations on the storage media. The fourth integrated unit 422 may be, for example, an ASIC, or another unit or module with processing capabilities, and is a component added to the new server system shown in Figure 2. Furthermore, a local bus and an external bus may be added based on the addition of the fourth integrated unit 422 to the media management board 420. The local bus is configured to connect the fourth integration unit 422 and the third integration unit 421, and the external bus is configured to connect the fourth integration unit 422 and the processor 411 located in the server mainboard 410. The type of external bus may be, for example, a universal serial bus (USB) or a peripheral component interconnect express (PCIe) bus, or another type of full-duplex communication bus, such as a universal asynchronous receiver / transmitter (UART) bus or an inter-integrated circuit (I) bus. 2 C) This may be a bus or a serial peripheral interface (SPI) bus. This is not specifically limited.

[0058] It will be understood that the media management board 420 may optionally include only one integration unit or three or more integration units. When only one integration unit is included, the integration unit is configured to perform all the work of the third integration unit 421 and the fourth integration unit 422 in this application. When three or more integration units are included, each integration unit is configured to share some of the work of the media management board 420, and the three or more integration units jointly complete all the work of the media management board 420. The following explanation is provided only by using an example in which the media management board 420 includes two integration units. Other solutions may be implemented with reference to the example. The example is not described in this application.

[0059] A memory module is a module located outside the server mainboard 410 and configured to expand memory (or memory and external memory). A memory module may include a processing module, at least one second storage medium, and a goldfinger connector. When the server includes multiple memory modules, the number of second storage mediums in different memory modules may be the same or different. For example, in the example in Figure 4, memory module 431 includes four second storage mediums, memory module 432 includes three second storage mediums, and memory module 43N includes five second storage mediums; the number of second storage mediums included in each memory module may differ. However, this is merely an optional embodiment. In an actual product, at least two memory modules may include the same number of second storage mediums, or all memory modules may include the same number of second storage mediums. This is not specifically limited.

[0060] Memory module 431 is used as an example. Memory module 431 includes a processing module 4311, a goldfinger connector 4312, and four second storage media. These four second storage media are named DDR11, DDR12, DDR13, and DDR14, respectively. Processing module 4311 may include one or more integration units. For example, it may include only one integration unit. See Figure 5a. The integration unit may be connected between the goldfinger connector 4312 and at least one of the second storage media DDR11 to DDR14. The integration unit may be understood as an ASIC within an existing memory module, or it may be any other circuit or chip capable of performing processing functions, such as an FPGA. Another example includes two integration units. See Figure 5b. Processing module 4311 may include a first integration unit 43111 and a second integration unit 43112. The first integration unit 43111 may be, for example, an ASIC, such as the original ASIC in the memory module of the new server system shown in Figure 2, or another unit or module having processing capabilities. The first integration unit 43111 may be connected separately to DDR11-DDR14, or it may be connected to DDR11-DDR14 via a memory controller integrated into the first integration unit 43111, for example. The first integration unit 43111 may further be connected to the processor 411 in the server mainboard 410, or it may be connected to the processor 411 via a serial bus X4 with four memory channels, a serial bus X8 with eight memory channels, a serial bus X16 with sixteen memory channels, etc., and to the goldfinger connector 4312. Since the second storage medium is far from the processor 411, the processor 411 needs to communicate with the first integration unit 43111 to access the second storage medium indirectly. Therefore, in some scenarios, the second storage medium is also called the processor 411's remote end memory or two-level (L2) memory.Furthermore, the second integration unit 43112 may be, for example, a field programmable gate array (FPGA), or another unit or module with processing capabilities, or it may be an added component to the memory module 431 in the new server system shown in Figure 2. Additionally, a local bus and an out-of-band communication bus may be added based on the addition of the second integration unit 43112 to the memory module 431. The local bus is configured to connect the second integration unit 43112 and the first integration unit 43111, and the out-of-band communication bus is configured to provide a connection between the second integration unit 43112 and the third integration unit 421 in the media management board 420. The out-of-band communication bus may be any type of full-duplex communication bus, e.g., a high-speed interconnection bus (e.g., a Hisport bus), a UART bus, etc. 2 It may be a C-bus or an SPI bus. This is not specifically limited.

[0061] In some scenarios, in addition to the processing module, goldfinger connector, and second storage medium, each memory module may further include a printed circuit board (PCB). For example:

[0062] For example, Figure 6a is a diagram of the product structure of a memory module according to this application. In this structure, an example is used in which the processing module includes only one integrated unit. For example, the integrated unit may be an ASIC as shown in the figure, or any other circuit or chip capable of performing processing functions, such as an FPGA. This is not specifically limited. For example, the integrated unit is an ASIC. The ASIC may be located in the central region of the PCB, or at least one second storage medium may be evenly distributed on both sides of the ASIC. For example, when the second storage medium is DDR and the memory module includes four DDRs, the four DDRs may be evenly distributed in the region above and below the ASIC. For example, two DDRs may be located in the region above the ASIC and two DDRs may be located in the region below the ASIC.

[0063] In another example, Figure 6b is a diagram of the product structure of another memory module according to this application. In this configuration, an example is used in which the processing module includes two integration units, one of which is an ASIC and the other is an FPGA. As shown in Figure 6b, the ASIC and FPGA may be arranged side by side in the central region of the PCB, or at least one second storage medium may be evenly distributed on both sides of the ASIC and FPGA. For example, when the second storage medium is DDR and the memory module includes four DDRs, the four DDRs may be evenly distributed in the region above and below the ASIC and FPGA. For example, two DDRs may be placed in the region above the ASIC and FPGA, and two DDRs may be placed in the region below the ASIC and FPGA.

[0064] Furthermore, the goldfinger connectors may be arranged at any edge position on the PCB, for example, at any one or more edges in four directions: top, bottom, left, and right. For example, in Figures 6a and 6b, the goldfinger connectors are arranged on the right edge of the PCB. Three small rectangular regions may protrude side by side from the right edge of the PCB, and a portion of a conductive spring may be attached to the right edge of each small rectangular region. The position and function of these conductive springs are defined so that the defined conductive springs can be plugged into the server main board 410 and the media management board 420 to implement communication connections between the memory module and the server main board 410 and between the memory module and the media management board 420. For example, the processing module in the memory module shown in Figure 4 is separately connected to the processor 411 in the server mainboard 410 and the third integration unit 421 in the media management board 420; the integration unit in the memory module shown in Figure 5a is separately connected to the processor 411 in the server mainboard 410 and the third integration unit 421 in the media management board 420; or the first integration unit in the memory module shown in Figure 5b is connected to the processor 411 in the server mainboard 410, and the second integration unit in the memory module shown in Figure 5b is connected to the third integration unit 421 in the media management board 420. Further features such as supplying power to each component in the memory module by an external power supply may also be implemented. Goldfinger connectors are provided within the memory module, and as a result, the memory module can be flexibly plugged in or unplugged to connect or disconnect between the memory module and the server mainboard and between the memory module and the media management board.

[0065] It will be understood that the structure of memory modules 432 through 43N is similar to that of memory module 431. See, for example, Figure 4. Memory module 432 may include a processing module 4321, a goldfinger connector 4322, and three second storage media, which are designated as DDR21, DDR22, and DDR23, respectively, ..., and memory module 43N may include a processing module 43N1, a goldfinger connector 43N2, and five second storage media, which are designated as DDR N1, DDR N2, DDR N3, DDR N4, and DDR N5, respectively. For example, the processing module within each memory module includes two integrated units. See Figures 4 and 5b. The processing module 4321 in the memory module 432 may include a first integration unit 43211 and a second integration unit 43212, ..., and the processing module 43N1 in the memory module 43N may include a first integration unit 43N11 and a second integration unit 43N12.

[0066] Furthermore, the components and their locations shown in Figures 5a and 5b are merely possible partitioning methods for the server system. The partitioning method is simply a logical functional partitioning. In actual implementation, all or some of the components may be integrated into a physical entity or physically separated. For example, in yet another example, the processing module within each memory module may alternatively include three or more integration units, each integration unit sharing some of the functions of the processing module, and the three or more integration units jointly performing all of the functions of the processing module. In yet another example, the media management board 420 may alternatively include just one integration unit, and this integration unit completes all of the functions of the media management board 420. Alternatively, the media management board 420 may include three or more integration units, each integration unit sharing some of the functions of the media management board 420, and the three or more integration units jointly performing all of the functions of the media management board 420.

[0067] Furthermore, processing modules within different memory modules may contain the same or different numbers of integration units. For example, a processing module in memory module 431 may contain one integration unit, a processing module in memory module 432 may contain two integration units, a processing module in memory module 431 may contain two integration units, a processing module in memory module 432 may contain one integration unit, a processing module in memory module 431 may contain one integration unit, a processing module in memory module 432 may contain three integration units, and so on. Examples are not listed one by one in this specification.

[0068] Furthermore, Figures 4, 5a, or 5b illustrate only examples of the main components within the server mainboard 410, media management board 420, or memory module. The server mainboard 410, media management board 420, or memory module may optionally include more or fewer components than those shown in the figures. For example, in some scenarios, the server mainboard 410 may further include a power supply, input / output (I / O) bus, hard disk drive, etc. In some other scenarios, in addition to the server mainboard 410, media management board 420, and memory module, the server may further include disks, hard disks, chassis housing, etc. Many other possible cases are not listed one by one herein.

[0069] Furthermore, Figures 4, 5a, or 5b merely illustrate possible architectures of electronic devices using a server as an example. When the electronic device is a different device, the server mainboard may also be interchangeable with another mainboard in synchronous manner. In other words, the server mainboard may be understood as the electronic device mainboard. When the electronic device is a server, the electronic device mainboard may specifically be the server mainboard. When the electronic device is a mobile phone, the electronic device mainboard may specifically be the mobile phone mainboard. When the electronic device is a computer, the electronic device mainboard may specifically be the computer mainboard. The rest can be inferred by analogy. Examples are not listed one by one in this application.

[0070] The above describes the differences in system architecture between the server provided in this application and the existing new server shown in Figure 2. In addition to the differences in system architecture, this application further redefines some of the pins of the goldfinger connector in the memory module within the server.

[0071] The following section details the differences between the structure and pin definition of the Goldfinger connector before and after redefinition, using an example where the Goldfinger connector is defined according to the enterprise and data center SSD form factor (EDSFF). It should be noted that EDSFF is merely an example and does not constitute a limitation on the technical solution to be protected in this application. In specific implementation, customized standards or other standard specifications capable of performing the functions of the Goldfinger connector to be protected in this application may be used instead.

[0072] Figure 7 is a diagram comparing the structure of the Goldfinger connector before and after redefinition according to this application. Figure 7(A) is a top view of the Goldfinger connector before redefinition, Figure 7(B) is a right side view of a part of the Goldfinger connector before redefinition, Figure 7(C) is a top view of the Goldfinger connector after redefinition, and Figure 7(D) is a right side view of a part of the Goldfinger connector after redefinition. As can be seen from the comparison, the differences between the Goldfinger connector after redefinition and the Goldfinger connector before redefinition mainly include the following two points.

[0073] In possible embodiments, this application provides a goldfinger connector having fewer than six groups of power pins.

[0074] Refer to Figures 7(A) and 7(B). The pre-redefinition Goldfinger connector has six groups of power pins, each group of power pins containing one positive pin (VCC) and one ground pin (GND). According to the EDSFF specification, the positions and input signals of the six groups of power pins are shown in Table 1.1 below. It is assumed that the width of each power pin specified in the standard is 0.3 mm (i.e., preset width K). In this case, the parameter information for the six groups of power pins is shown in Table 1.2 below.

[0075] [Table 1]

[0076] [Table 2]

[0077] Referring to Tables 1.1 and 1.2, and Figures 7(A) and 7(B), in the pre-redefinition Goldfinger connector, pins B1 through B6 are defined as six positive pins, and pins A1 through A6 are defined as six ground pins, corresponding one-to-one with the six positive pins. The rated voltage for each group of power pins is 29V, the rated current for each group of power pins is 1.1A, and the rated temperature range is -40°C to -85°C. Although the rated voltage is 29V, the Goldfinger connector in the memory module typically uses an operating voltage of 12V. Specifically, each group of power pins may receive an operating voltage of 12V and then supply an operating voltage of 12V to the memory module on which the power pins are installed. Therefore, according to the power pin parameter design, the pre-redefinition Goldfinger connector has a total of six groups of power pins, each group of power pins has a rated current of 1.1A, and each group of power pins has an operating voltage of 12V. Therefore, the maximum power that can be supplied by the pre-redefinition goldfinger connector is 1.1A × 6 × 12V = 79.8W.

[0078] Unlike the pre-redefinition Goldfinger connector, the redefined Goldfinger connector may include groups of fewer than six power pins, and these power pins include at least one group of first power pins. The pin widths of both the first positive pin and the first ground pin in the first power pins are greater than the pin widths of the positive pin and ground pin in the original power pins, i.e., greater than 0.3 mm. See, for example, Figures 7(C) and 7(D). In one example, the redefined Goldfinger connector may include only one group of large power pins (i.e., first power pins). The positive pins (i.e., first positive pins) in the group of large power pins occupy the entire area where the original pins B1 through B6 are located, and the ground pins (i.e., first ground pins) occupy the entire area where the original pins A1 through A6 are located. The locations and input signals of the power pin groups may be shown in Table 2.1 below, and the parameter information for the power pin groups may be shown in Table 2.2 below.

[0079] [Table 3]

[0080] [Table 4]

[0081] Next, referring to Tables 2.1, 2.2, Figure 7(C), and Figure 7(D), in the redefined goldfinger connector having only one group of power pins, any pin from pins B1 to B6 may be selected and defined as the positive pin, or any pin from pins A1 to A6 may be selected and defined as the ground pin. For example, in Table 2.1, pin B1 is defined as the positive pin and pin A1 is defined as the ground pin. When the original width of each pin is 0.3 mm and the pin spacing is 0.6 mm, the width of each pin after redefinition can be increased to 3.3 mm. Thus, although the operating voltage is still 12 V, the area of ​​the conductive spring corresponding to the redefined power pin is almost doubled compared to the original six power pins with a pin width of 0.3 mm, because the pin width has been increased to 3.3 mm. Tests have shown that the through-current capability of the conductive spring in this area can be increased to at least 30 A. Therefore, the maximum power that can be supplied by the Goldfinger connector after redefinition can reach 30A × 12V = 360W, which is four times the 79W before redefinition.

[0082] Because the power supplied by the power pins is increased, the increased power supply can support the placement of more second storage media within the memory module. For example, currently, the power consumption of each DDR is approximately 10W to 15W, and the power consumption of other components and circuits within the memory module is approximately 20W. When the pre-redefinition Goldfinger connector is used, the maximum power supplied by the power pins of the Goldfinger connector can only reach 79.8W, excluding the 20W supplied to other components and circuits within the memory module, so the remaining 59.8W of power can only be supplied for a maximum of 4 to 6 DDRs. That is, a maximum of 4 to 6 DDRs can be encapsulated in each memory module. When the redefined Goldfinger connector is used, the power supplied by the power pins of the Goldfinger connector can reach 360W, excluding the 20W supplied to other components and circuits within the memory module, so the remaining 340W can be further supplied for 22 to 34 DDRs. Therefore, 22 to 34 DDRs can be encapsulated in each memory module. This will significantly expand the server's storage capacity.

[0083] It should be noted that after increasing the number of DDR modules, the power consumption of the memory controller also increases accordingly. As a result, the power consumption of other components and circuits within the memory module also increases accordingly. Therefore, the number of DDR modules that can actually be increased for memory module expansion is less than 22-34. Experimental verification shows that even considering memory controllers with increased power consumption, the redefined Goldfinger connector can still support expansion using specifications for more than 10 DDR modules, and that memory expansion using this specification is sufficient for current use.

[0084] Furthermore, Figure 7 provides an explanation only by using an example in which the redefined goldfinger connector includes one group of power pins. However, in actual products, the redefined goldfinger connector may include any number of power pins from 1 to 5. For example, Figure 8 shows some possible cases of power pins before and after redefinition according to this application.

[0085] Figure 8(A) shows the structure of the power pins before redefinition. In this structure, the pin width of each pin is 0.3 mm, and the pin spacing between the center points of two adjacent pins is 0.6 mm. Therefore, the area where the original pins B1-B6 or the original pins A1-A6 are installed occupies a total width of 3.6 mm. The power pin structure before redefinition defines six groups of power pins within the 3.6 mm width where the original pins B1-B6 or the original pins A1-A6 are installed, with a distance of 0.3 mm between the edges of two adjacent pins.

[0086] Figures 8(B), (C), (D), (E), and (F) show five redefined power pin structures. Each of the five redefined power pin structures redefines one, two, three, four, and five groups of power pins within a 3.6mm width range where the original pins B1-B6 or A1-A6 are located. Compared to the pre-redefined power pin structure shown in Figure 8(A), each of the redefined power pin structures contains at least one power pin with a pin width greater than 0.3mm. Furthermore, the pin width of the power pins typically decreases as the number of arranged power pins increases. To facilitate understanding of this solution, each of the redefined power pin structures is described separately and in detail below.

[0087] In a possible redefinition solution, Figure 8(B) shows a structure in which only one group of power pins exists after redefinition. In this structure, pin A1 is defined as the ground pin and pin B1 is defined as the positive pin. Ground pin A1 occupies the area between the left edge shown in the figure of the original pin A1 and the right edge shown in the figure of the original pin A6, and positive pin B1 occupies the area between the left edge shown in the figure of the original pin B1 and the right edge shown in the figure of the original pin B6. In addition to the 0.3 mm space maintained between the pins and the left edge of the goldfinger connector, the remaining 3.3 mm may all be used to accommodate the conductive springs of the pins. In other words, the width of the conductive springs corresponding to the redefined ground pin A1 or positive pin B1 may be increased up to 3.3 mm.

[0088] In another possible redefinition solution, Figures 8(C1) and 8(C2) show two structures in which, after redefinition, there are two groups of power pins. In this structure, pins A3 and A5 are defined as two ground pins, and pins B3 and B5 are defined as two positive pins. Apart from the 0.3 mm maintained space between the pins and the left edge of the goldfinger connector, and the 0.3 mm maintained space between the edges of adjacent pins, the remaining 3 mm may all be used to accommodate conductive springs for the two ground pins or the two positive pins. For example, in the structure shown in Figure 8(C1), the conductive springs for the ground pins and positive pins may have the same width. For example, the ground pin A3 occupies the region between the left edge shown in the diagram of the original pin A1 and the right edge shown in the diagram of the original pin A3; the ground pin A5 occupies the region between the left edge shown in the diagram of the original pin A4 and the right edge shown in the diagram of the original pin A6; the positive pin B3 occupies the region between the left edge shown in the diagram of the original pin B1 and the right edge shown in the diagram of the original pin B3; and the positive pin B5 occupies the region between the left edge shown in the diagram of the original pin B4 and the right edge shown in the diagram of the original pin B6. In this way, the width of the conductive spring corresponding to any positive pin or any ground pin may be increased to 1.5 mm. As another example, in the structure shown in (C2) of Figure 8, the ground pin or the positive pin may have different widths. For example, ground pin A3 occupies the region between the left edge shown in the diagram of the original pin A1 and the right edge shown in the diagram of the original pin A4; ground pin A5 occupies the region between the left edge shown in the diagram of the original pin A5 and the right edge shown in the diagram of the original pin A6; positive pin B3 occupies the region between the left edge shown in the diagram of the original pin B1 and the right edge shown in the diagram of the original pin B4; and positive pin B5 occupies the region between the left edge shown in the diagram of the original pin B5 and the right edge shown in the diagram of the original pin B6. In this way, the width of the conductive springs corresponding to ground pin A3 and positive pin B3 may be increased to 2.1 mm, or the width of the conductive springs corresponding to ground pin A5 and positive pin B5 may be increased to 0.9 mm.

[0089] In yet another possible redefinition solution, Figures 8(D1) and 8(D2) show two structures in which three groups of power pins exist after redefinition. In this structure, pins A2, A4, and A5 are defined as three ground pins, and pins B2, B4, and B5 are defined as three positive pins. In addition to the 0.3 mm maintained space between the pins and the left edge of the goldfinger connector, and the 0.6 mm maintained space total between the edges of two groups of adjacent pins, the remaining 2.7 mm may all be used to accommodate conductive springs for the three ground pins or the three positive pins. For example, in the structure shown in Figure 8(D1), the conductive springs for the ground pins and positive pins may have the same width. For example, ground pin A2 occupies the region between the left edge shown in the diagram of the original pin A1 and the right edge shown in the diagram of the original pin A2; ground pin A4 occupies the region between the left edge shown in the diagram of the original pin A3 and the right edge shown in the diagram of the original pin A4; ground pin A5 occupies the region between the left edge shown in the diagram of the original pin A5 and the right edge shown in the diagram of the original pin A6; positive pin B2 occupies the region between the left edge shown in the diagram of the original pin B1 and the right edge shown in the diagram of the original pin B2; positive pin B4 occupies the region between the left edge shown in the diagram of the original pin B3 and the right edge shown in the diagram of the original pin B4; and positive pin B5 occupies the region between the left edge shown in the diagram of the original pin B5 and the right edge shown in the diagram of the original pin B6. In this way, the width of the conductive spring corresponding to any positive pin or any ground pin may be increased to 0.9 mm. As another example, in the structure shown in Figure 8(D2), the ground pins or positive pins may have different widths. For example, ground pin A2 occupies the area between the left edge of the original pin A1 shown in the figure and the right edge of the original pin A2 shown in the figure; ground pin A4 occupies the area between the left edge of the original pin A3 shown in the figure and the right edge of the original pin A5 shown in the figure; ground pin A5 occupies the area of ​​the original pin A6; positive pin B2 occupies the area between the left edge of the original pin B1 shown in the figure and the right edge of the original pin B2 shown in the figure; positive pin B4 occupies the area between the left edge of the original pin B3 shown in the figure and the right edge of the original pin B5 shown in the figure; and positive pin B5 occupies the area of ​​the original pin B6.In this way, the width of the conductive spring corresponding to the ground pin A2 and the positive pin B2 may be increased to 0.9 mm, the width of the conductive spring corresponding to the ground pin A4 and the positive pin B4 may be increased to 1.5 mm, and the width of the conductive spring corresponding to the ground pin A5 and the positive pin B5 may remain at 0.3 mm.

[0090] In yet another possible redefinition solution, Figure 8(E) shows a structure in which four groups of power pins exist after redefinition. In this structure, pins A2, A4, A5, and A6 are defined as ground pins, and pins B2, B4, B5, and B6 are defined as positive pins. Grounding pin A2 occupies the area between the left edge shown in the diagram of the original pin A1 and the right edge shown in the diagram of the original pin A3; grounding pin A4 occupies the area of ​​the original pin A4; grounding pin A5 occupies the area of ​​the original pin A5; grounding pin A6 occupies the area of ​​the original pin A6; positive pin B2 occupies the area between the left edge shown in the diagram of the original pin B1 and the right edge shown in the diagram of the original pin B3; positive pin B4 occupies the area of ​​the original pin B4; positive pin B5 occupies the area of ​​the original pin B5; and positive pin B6 occupies the area of ​​the original pin B6. In this way, the width of the conductive springs corresponding to grounding pin A2 and positive pin B2 may be increased to 1.5 mm, or the width of the conductive springs corresponding to grounding pins A4, A5, A6, positive pins B4, B5, and B6 may remain at 0.3 mm.

[0091] In yet another possible redefinition solution, Figure 8(F) shows a structure in which five groups of power pins exist after redefinition. In this structure, pins A2, A3, A4, A5, and A6 are defined as ground pins, and pins B2, B3, B4, B5, and B6 are defined as positive pins. Ground pin A2 occupies the area of ​​the original pin A1, ground pin A3 occupies the area of ​​the original pin A2, ground pin A4 occupies the area between the left edge of the original pin A3 shown in the diagram and the right edge of the original pin A4 shown in the diagram, ground pin A5 occupies the area of ​​the original pin A5, ground pin A6 occupies the area of ​​the original pin A6, positive pin B2 occupies the area of ​​the original pin B1, positive pin B3 occupies the area of ​​the original pin B2, positive pin B4 occupies the area between the left edge of the original pin B3 shown in the diagram and the right edge of the original pin B4 shown in the diagram, positive pin B5 occupies the area of ​​the original pin B5, and positive pin B6 occupies the area of ​​the original pin B6. In this way, the width of the conductive springs corresponding to the ground pin A4 and the positive pin B4 may be increased to 0.9 mm, while the width of the conductive springs corresponding to the ground pins A2, A3, A5, A6, B2, B3, B5, and B6 may remain at 0.3 mm.

[0092] Please note that Figure 8 is just one example of several types of pin arrangements. This example is illustrated by using an example where the same numbered pins are selected as the positive and ground pins. However, in actual products, the ground pins may be defined by selecting any one to five pins from pins A1 to A6, and the positive pins may be defined by selecting any one to five pins from pins B1 to B6. The selected ground and positive pins may have the same or different numbers. For example, in another example, pins A2 and A5 may be selected as two ground pins, and pins B2 and B4 may also be selected as two positive pins. This is simply a difference in pin numbers, provided that the corresponding ground and positive pins are defined at the same locations on the front and back of the PCB.

[0093] Furthermore, the widths of the positive and ground pins shown above are merely examples provided to ensure that the power pins can cover as much of the area where the original pins B1-B6 and A1-A6 are installed as possible. However, in actual scenarios, all defined positive pins may cover only a portion of the area where the original pins B1-B6 are installed, and all defined ground pins may cover only a portion of the area where the original pins A1-A6 are located. For example, (C1) in Figure 8 is used as an example. In another example, the pin width of the ground pin A3 and positive pin B3 may be alternatively configured as 1 mm, and the pin width of the ground pin A5 and positive pin B5 may be alternatively configured as 1.5 mm. Such configurations cannot completely cover the entire area where the original pins B1-B6 and A1-A6 are installed, but the power supply capacity of the power source can also be increased because the width of the conductive springs is increased.

[0094] Furthermore, any number of power pins within groups of 1 to 5 power pins may be redefined, but considering that fewer power pins may make it more difficult to plug in or unplug the Goldfinger connector, two or three larger power pins may be redefined within the area where the original power pins are located to strike a balance between flexible plugging and unplugging and high power supply. In this way, power supply capability is improved while maintaining the flexibility of plugging in and unplugging the Goldfinger connector.

[0095] It should be understood that the above explanation is provided only by using an example where the pin width defined in the EDSFF standard is 0.3 mm. This is merely for the purpose of simplifying the explanation of the solution, and the pin width is not limited to this value. As the EDSFF standard evolves, the pin width may also change to a different value. Alternatively, when the EDSFF standard is applied to a different field, the standard to which it is applied may alternatively specify that the pin width is a different value. Alternatively, due to process manufacturing tolerances, the pin width cannot be strictly limited to 0.3 mm, but will fluctuate around 0.3 mm. However, any power pins that implement higher power supply according to the pin combination solution provided in this application are included within the scope of protection of this application.

[0096] Furthermore, the above describes a method for obtaining greater power supply capability by redefining power pins, using only a memory expansion scenario as an example to implement memory expansion using large-scale specifications. This solution may be further applied to any other scenarios requiring high-power modules, such as accelerator cards or GPU cards. The power pins of the Goldfinger connector on the accelerator card or GPU card are redefined to provide higher power supply to accelerator cards and GPU cards and to support the deployment of more accelerator cards or GPU cards. The scenarios to which the solution of redefining the power pins of the Goldfinger connector is applicable are not limited in this application.

[0097] Furthermore, since the power pins of the Goldfinger connector are redefined, the power connector plugged into the Goldfinger connector also needs to be adjusted accordingly. For example, when the Goldfinger connector is redefined to have two groups of power pins (input pins), the power connector may also be redefined to have two groups of power pins (output pins). Alternatively, even if the power connector is not redefined and the original design of six groups of power pins is still used, according to the redefinition solution provided in this application, after the two are plugged in, the original six groups of power pins in the power connector can still contact the power pins on the redefined Goldfinger connector, and as a result, the redefined Goldfinger connector can still be compatible with the original power connector. Alternatively, even if the Goldfinger connector is not redefined and the power pins of the power connector are redefined in this way, the Goldfinger connector can still be compatible with the redefined power connector. With this power pin redefinition solution, the Goldfinger connector can be adapted to either the original or the redefined power connector, and good compatibility and fitment of the Goldfinger connector can be found.

[0098] In another possible embodiment, the application further provides a Goldfinger connector having newly added out-of-band communication pins. Compared to the Goldfinger connector before redefinition, the Goldfinger connector may enable communication between a processing module within the memory module and a media management board outside the memory module via the newly added out-of-band communication pins. For example, the architecture shown in Figure 5b is used as an example. The newly added out-of-band communication pins may enable communication between a second integration unit within the memory module and a third integration unit 421 in the media management board 420 outside the memory module, and may be configured to enable cold and hot migration solutions based on the second integration unit by providing hardware support for the second integration unit within the memory module to transmit access frequency information to the third integration unit 421 outside the memory module.

[0099] Specifically, please refer further to Figures 7(A) and 7(C). Compared to the pre-redefinition goldfinger connector, the redefined goldfinger connector has an additional group of out-of-band communication pins, which may be connected to a second integration unit in the memory module via an out-of-band communication bus. In this way, after the memory module is plugged into the media management board 420 via the goldfinger connector, the out-of-band communication bus may connect the second integration unit to the goldfinger connector, thereby connecting the second integration unit to a third integration unit 421 in the media management board 420. In this way, the second integration unit may send access frequency information for each second memory address in the memory module to the third integration unit 421 via the out-of-band communication bus and the out-of-band communication pins on the goldfinger connector. Out-of-band communication pins may be defined by selecting reserved pins on the Goldfinger connector, such as pins B68, B69, A68, A69, A70, and S2 of the EDSFF specification.

[0100] In some scenarios, the out-of-band communication pin may perform the transmission of access frequency information by using differential signaling. In this case, according to the EDSFF specification, an example of the location and input signal of the out-of-band communication pin may be configured as shown in Table 3 below.

[0101] [Table 5]

[0102] Referring together to Table 3 and Figure 7(C), on the redefined goldfinger connector, reserved pins B68 and B69 may be defined as two transmit pins for differential signals, and reserved pins A68 and A69 may be defined as two receive pins for differential signals, and conductive springs corresponding to the four pins may be attached to idle positions on the right edge of the PCB to perform the corresponding out-of-band communication function. In this way, the second integration unit may send access frequency information for each second memory address in the memory module in which the second integration unit is installed to the third integration unit 421 via defined pins B68 and B69, and may receive information returned by the third integration unit 421, such as response information indicating successful reception, via defined pins A68 and A69.

[0103] In some examples, the pin width of each transmit pin or each receive pin, and the pin spacing between adjacent transmit pins or adjacent receive pins, may remain the same as in the Goldfinger connector configuration before redefinition. For example, the pin width of each transmit pin and each receive pin may be configured as 0.3 mm, and the pin spacing between two adjacent transmit pins or two adjacent receive pins may be configured as 0.6 mm. However, this is merely an optional embodiment. In another optional embodiment, the pin width of one or more transmit pins, the pin width of one or more receive pins, the pin spacing between one or more groups of adjacent transmit pins, or the pin spacing between one or more groups of adjacent receive pins may remain different from the Goldfinger connector configuration before redefinition. This is not specifically limited.

[0104] It should be understood that the locations of the transmit pins, receive pins, and conductive springs shown above are merely examples. In other scenarios, different reserved pins may be selected as transmit or receive pins, or the conductive springs may be encapsulated at a different location on the PCB. This is not specifically limited.

[0105] Based on the two differences described above, the definitions of the pins on the redefined Goldfinger connector based on Table 4 are explained below by using an example in which the two groups of power pins are redefined. Note that this example uses a Goldfinger connector that conforms to the EDSFF standard. However, it should be understood that the same design concepts may be applicable to any existing or future information security standards. For example, the standard may be the Common Criteria of Information Technical Security Evaluation Methodology (CEM), the Technical Specification Standard OCP, or other similar standards. This is not particularly limited in this application.

[0106] [Table 6A] [Table 6B]

[0107] Please refer to Table 4. Compared to the pre-redefinition Goldfinger connector, the pin definitions for pins B7-B67, B70, A7-A67, and A70 on the redefined Goldfinger connector remain unchanged. Pins B1 and B5 are defined as two positive pins, pins A2 and A4 are defined as two ground pins, the original reserved pins B67 and B68 are defined as two transmit pins for differential signals, and the original reserved pins A67 and A68 are defined as two receive pins for differential signals. Additionally, pins B2-B4, B6, A1, A3, A5, and A6 are not defined, but the area where these pins would be located is occupied by large power pins after the redefinition. Therefore, these pins do not exist.

[0108] In this application, the pins on the goldfinger connector are redefined by using the two differences described above, which in turn improves the power supply capability of the goldfinger connector, allowing more second storage media to be placed within the memory module, and the redefined goldfinger connector can be further adapted to the updated memory module, more specifically, to the receive and send capabilities of the newly added second integrated unit in the memory module, and provides support for implementing the following cold and hot data migration solutions.

[0109] It should be noted that the foregoing is merely one example of possible redefinition methods. Specific pins selected as power pins or out-of-band communication pins may be determined by those skilled in the art based on requirements or practice. This is not particularly limited in this application.

[0110] Furthermore, in this application, the conductive spring may be made of any material having conductive properties, such as gold-plated copper, beryllium copper, manganese steel, phosphor bronze, brass, iron, or stainless steel. The shape of the conductive spring may be designed based on actual product requirements, and may be set to a rectangle as shown in Figure 7, or to a bent shape. In addition to performing the conductive function, a bent conductive spring can also contact the mating connector via its bent end, resulting in the two connected components being closer together, less prone to misalignment, and maintaining the reliability of the connection between the two components.

[0111] Furthermore, with advancements in mechanical manufacturing technology, more materials and forms may be developed for conductive springs. However, any solution that results in a larger power pin by combining the original power pins, or any solution in which cold and hot transitions are performed based on a second integrated unit by adding out-of-band communication pins, is within the scope of protection of this application. This is not limited to this application.

[0112] The above describes the specific differences between the Goldfinger connector in the memory module provided in this application and the Goldfinger connector in existing memory modules. Furthermore, this application provides solutions for performing cold and hot migrations for server data. Specific embodiments of the cold and hot migration solutions are described below.

[0113] To facilitate the explanation of the solution, each storage address corresponding to the first storage medium will be referred to as the first storage address, and each storage address corresponding to the second storage medium will be referred to as the second storage address. However, it should be understood that this does not constitute any limitation to this application.

[0114] For example, the server architecture shown in Figure 5b is used as an example. Figure 9 is a schematic flowchart of the interaction of the cold and hot data migration solution according to this application. As shown in Figure 9, the cold and hot data migration procedure includes the following steps:

[0115] Step 901: The first integration unit accesses one or more second memory addresses within the memory module in which the first integration unit is installed.

[0116] For example, for each memory module, a first integration unit within the memory module may be connected via control address lines to all memory cells contained in each first storage medium within the memory module. When the processor 411 needs to read / write data in a particular memory module, the processor 411 may send a read / write request to the first integration unit within the memory module. Based on the read / write request, the first integration unit determines which memory cell needs to be accessed, then enables the memory cell to be accessed by adjusting the high / low levels of the control address lines, and then stores data in the memory cell or reads data from the memory cell. There may be one, more, or all memory cells that need to be accessed. This is not specifically limited.

[0117] Step 902: The second integration unit sends access frequency information for each second memory address in the memory module in which the second integration unit is installed to the third integration unit.

[0118] For example, a second integration unit in any memory module may periodically monitor each control address line located within the memory module. If a level jump occurs on a particular control address line within the period of each cycle, the second integration unit may determine the memory cell accessed based on the jump status, determine the second storage address to which the accessed memory cell belongs, or further update the access frequency of the second storage address. Then, when the period of each cycle ends, the second integration unit may send the access frequency of each second storage address within the memory module in which the second integration unit is installed to a third integration unit. Specifically, the access frequency may be sent to the third integration unit via an out-of-band communication bus additionally added to the memory module and a newly added out-of-band communication pin on the goldfinger connector.

[0119] For example, statistics on the access frequency of each second memory address within a memory module may be collected in a second access frequency table. The second access frequency table may be stored locally in the second integration unit, or it may be stored outside the second integration unit, for example, in the first integration unit or the second storage medium. The second access frequency table may include each second memory address within the memory module and its corresponding access frequency, and the refresh operation may be performed, for example, once every two seconds, based on a preset period duration. Each second memory address may include the address of only one memory cell or the addresses of multiple memory cells. For example, when second memory address assignment is performed based on the space of one memory cell, the number of memory cells included in the memory module is also the number of second memory addresses included in the memory module. When second memory address assignment is performed based on the space of two or more memory cells, the number of second memory addresses included in the memory module is less than the number of memory cells, and the number of memory cells corresponding to different second memory addresses may be the same or different. This is not specifically limited.

[0120] For example, in a particular case, Table 5.1 shows a second access frequency table obtained by assigning a second storage address within the memory module 431 based on the space of multiple memory cells.

[0121] [Table 7]

[0122] As shown in Table 5.1, memory module 431 has a total of 17 memory cells. Memory cells 1 through 6 are assigned the first second memory address, i.e., 0x0000 to 0x0005, and this second memory address has been accessed 10 times so far. Memory cell 7 is assigned the second second memory address, i.e., 0x0006, and this second memory address has been accessed 5 times so far. Memory cells 8 through 14 are assigned the third second memory address, i.e., 0x0007 to 0x000D, and this second memory address has not been accessed so far. Memory cells 15 through 17 are assigned the fourth second memory address, i.e., 0x000E to 0x0010, and this second memory address has been accessed 15 times so far.

[0123] It is assumed that at a specific moment in the current cycle, the second integration unit 43112 determines, based on the level jump status of the control address lines in the memory module 431, that the memory cell accessed this time is one of the seventh through tenth memory cells. In this case, the second integration unit 43112 may update the second access frequency table to Table 5.2 below.

[0124] [Table 8]

[0125] Please refer to Tables 5.1 and 5.2 together. Since the 7th memory cell is accessed, the access count of the second memory address 0x0006 corresponding to the 7th memory cell is increased by 1, and updated to 6. Since the 8th through 10th memory cells are accessed, the access counts of the second memory addresses 0x0007 to 0x000D corresponding to the 8th through 10th memory cells are also increased by 1, and updated to 1.

[0126] It should be made clear that the above explanation is provided only by using an example in which a table conveys the access frequency of each second storage medium unit. This application is not limited to the fact that access frequency can be conveyed only within a table. For example, in another example, access frequency may be conveyed by other means such as an access frequency bar graph, an access frequency diagram, a stack, or a queue. This is not specifically limited.

[0127] Step 903: The third integration unit collects statistics to obtain access frequency information for each second memory address within each memory module.

[0128] For example, a second integration unit within each memory module may send a second access frequency table for the memory module in which the second integration unit is installed to a third integration unit 421, based on the same period. After receiving the second access frequency tables for each memory module, the third integration unit 421 obtains a larger second access frequency table by combination. Thus, the larger second access frequency table may include the access frequencies of all second memory addresses within each memory module during the same period. Because the same time reference is used, the comparability of the second access frequency tables is good.

[0129] Step 904: The third integration unit sends access frequency information for each second memory address within each memory module to the fourth integration unit.

[0130] For example, the third integration unit 421 may send a large second access frequency table to the fourth integration unit 422 via a local bus between the third integration unit 421 and the fourth integration unit 422.

[0131] Step 905: The fourth integration unit sends access frequency information for each second memory address within each memory module to the processor.

[0132] For example, the media management board 420 and the server main board 410 may be connected via an external bus. The fourth integration unit 422 may, after receiving a large second access frequency table from the third integration unit 421, send the second access frequency table to the processor 411 via the external bus. The external bus may be, for example, USB or PCIe.

[0133] Step 906: The processor determines the first storage address of the target where cold data resides and the second storage address of the target where hot data resides, based on the access frequency information of each first storage address and the access frequency information of each second storage address.

[0134] For example, the processor 411 may also monitor the access frequency of each first memory address directly connected to the processor 411, based on the same period as the second integration unit. For example, a first access frequency table may be provided in the processor 411. The first access frequency table contains the access frequency of each first memory address in the server mainboard 410 in the current period. After receiving the second access frequency table from the fourth integration unit 422, the processor 411 may, by interpretation, obtain the access frequency of all second memory addresses in all memory modules, and then, based on the access frequency of all second memory addresses, determine which second memory addresses have a high access frequency (e.g., an access frequency greater than a hotness threshold), and determine these second memory addresses as the target second memory addresses where hot data resides. The processor may also determine, based on the access frequency of all first memory addresses, first memory addresses with low access frequency (e.g., access frequency less than the coldness threshold), and may determine these first memory addresses as the first memory addresses of the target where the cold data resides. The hotness threshold is greater than the coldness threshold. For example, in some scenarios, the hotness threshold may be set to 10 and the coldness threshold may be set to 2.

[0135] Step 907: The processor sends cold and hot transition instructions to the first integration unit, which include cold data in the target's first memory address and / or address information in the target's second memory address.

[0136] Here, the address information of the target's second memory address may be, for example, the physical address of the target's second memory address.

[0137] For example, after determining the first memory address of the target where cold data resides, the processor 411 may first read the cold data stored at the first memory address of the target by using a memory controller integrated into the processor 411, and then, using the address information of the second memory address of the target where the read cold data and / or hot data resides, refer to the memory module where the amount of the read cold data and the second memory address of the target where the hot data resides are located, and generate one or more cold and hot transition instructions, and then send one or more cold and hot transition instructions to the first integrated unit in one or more memory modules. The cold and hot transition instructions may include only cold data, or only address information of the second memory address of the target where the hot data resides, or may include both cold data and address information of the second memory address of the target where the hot data resides.

[0138] For example, if there is no second memory address for a target where hot data resides, but there is a first memory address for a target where cold data resides, the processor 411 may generate cold and hot migration instructions based on the cold data in the first memory address of the target. For example, if the amount of cold data is small, the processor 411 may directly generate cold and hot migration instructions based on all the cold data to migrate the cold data in the server mainboard 410 to available memory modules as quickly as possible and free up space on the server mainboard 410, or it may send cold and hot migration instructions to the first integration unit in the memory module with the smallest occupation. Conversely, if the amount of cold data is large, the processor 411 may generate multiple cold and hot migration instructions by dividing the cold data to balance the memory module occupation while migrating the cold data in the server mainboard 410 to available memory modules, or it may send multiple cold and hot migration instructions to the first integration unit in multiple memory modules with small occupations.

[0139] As another example, when there is no first memory address for a target where cold data resides, but there is a second memory address for a target where hot data resides, the processor 411 may add the physical address of the second memory address of the target contained in each memory module to the corresponding cold and hot transition instructions, based on the memory module to which the second memory address of the target belongs, or it may send cold and hot transition instructions to the memory modules, and as a result each memory module returns the local hot data within the memory module to the processor 411.

[0140] As another example, when there is a first memory address for a target where cold data resides and a second memory address for a target where hot data resides, the processor 411 may select several memory modules that currently have small occupancies based on the occupancy status of each memory module, or it may use these memory modules and the memory module where the hot data resides as candidate memory modules. Then, for candidate memory modules where the second memory address for the target does not reside in any of these candidate memory modules, the processor may generate corresponding cold and hot migration instructions based on only a portion of the cold data in order to store the cold data evenly on the server mainboard 410 by using the large amount of available space in the candidate memory module, or it may send cold and hot migration instructions to the first integration unit in the candidate memory module. For candidate memory modules in which the target's second memory address resides, the processor may generate corresponding cold and hot transition instructions based on the target's second memory address or the target's second memory address and a portion of the cold data, or send the cold and hot transition instructions to a first integration unit in the candidate memory module, which, if instructed to return the hot data containing the candidate memory module, will have the available space in the candidate memory module further used to store the cold data within the server mainboard 410. Naturally, the second memory address and the cold data are communicated in a single cold and hot transition instruction and sent to the first integration unit. This is merely an optional embodiment. In another embodiment, different cold and hot transition instructions may be generated based on the second memory address and cold data and sent to the same first integration unit. This is not particularly limited in this application.

[0141] Step 908: The first integration unit sends the hot data in the target's second memory address to the processor, based on the address information of the target's second memory address conveyed by the cold and hot transition instructions.

[0142] For example, the first integration unit may read hot data in the target's second memory address using a locally integrated memory controller and then send the hot data to the processor 411 via a serial bus. The serial bus supports memory semantics and may transmit memory data and control signals for the memory data via a serial bus protocol that supports memory semantics.

[0143] Furthermore, for example, cold and hot transition instructions may convey the physical address of the target's second memory address, and the first integration unit may directly access the physical address to retrieve the hot data stored at the target's second memory address. The physical addresses of the target's second memory address may be contiguous or discontinuous; this is not specifically limited.

[0144] Step 909: The first integration unit stores the cold data in the first memory address of the target, as communicated by the cold and hot transition instructions, in the second memory address in the memory module in which the first integration unit is installed.

[0145] Here, the first integration unit may store the cold data in the target's first memory address in the target's second memory address, or it may store the cold data in the second memory address of another idle, or it may store part of the cold data in the target's second memory address and part of the cold data in the second memory address of another idle. This is not specifically limited.

[0146] Step 910: The processor stores the hot data in the target's second memory address in the first memory address on the server mainboard.

[0147] Furthermore, for example, after the processor 411 receives hot data in the target's second memory address sent by any first integration unit, it may store the hot data in the target's first memory address, or it may store the hot data in the first memory address of another idle, or it may store part of the hot data in the target's first memory address and part of the hot data in the first memory address of another idle. This is not specifically limited.

[0148] In the aforementioned cold and hot migration solution, the delay in processor access to the first storage medium within the server mainboard is smaller than the delay in processor access to the second storage medium within the memory module. Therefore, hot data in the memory module is migrated to the server mainboard, allowing the processor to access the hot data more quickly and improving data access performance. Cold data in the server mainboard is migrated to the memory module, freeing up the space occupied by the cold data within the server mainboard and increasing the storage capacity for hot data. By improving the access speed of hot data and increasing the storage capacity of hot data, the server's memory performance can be improved.

[0149] It will be understood that the above describes a cold and hot data migration method using only the server architecture shown in Figure 5b as an example. In another example, when the server uses the architecture shown in Figure 5a, the processing module in the memory module includes only one integration unit. The integration unit may be connected between a goldfinger connector in the memory module in which the integration unit is installed and at least one second storage medium in the memory module in which the integration unit is installed, or it may be configured to perform all the functions of the first and second integration units in the method embodiment shown in Figure 9, including steps 901, 902, 907, 908, and 909 in Figure 9. For example, the integration unit may receive read / write requests from the media management board 420 via a goldfinger connector in the memory module in which the integration unit is installed, and based on the read / write requests, may access at least one second storage medium in the memory module in which the integration unit is installed, and then transmit to the media management board 420 via the goldfinger connector access frequency information for each second storage address corresponding to at least one second storage medium in the memory module in which the integration unit is installed, within a predetermined period, and as a result the media management board 420 sends the access frequency information to the processor 411 in the server main board 410, and the processor 411 determines the first storage address of the target where cold data resides and the second storage address of the target where hot data resides. The integration unit may further receive cold and hot transition instructions from the processor 411 via a goldfinger connector in the memory module in which the integration unit is installed. Cold and hot transition instructions include address information for cold data in a first memory address associated with the processor (i.e., the first memory address of the target) and / or a second memory address associated with the memory module (i.e., the second memory address of the target).The integration unit may, in accordance with cold and hot migration instructions, send the hot data in the target's second memory address to the processor 411 via the goldfinger connector, or it may store the cold data in the target's first memory address in the second memory address in the memory module 431 where the integration unit is installed, in order to perform cold and hot data migration operations.

[0150] Alternatively, in yet another example, a processing module within any memory module may be divided into three or more integrated units, each integrated unit sharing some of the processing module's functions, and the three or more integrated units jointly performing all of the processing module's functions.

[0151] Similarly, in another example, when the server uses the architecture shown in Figure 5a, the media management board 421 includes only one integration unit. The integration unit may be connected between the goldfinger connector in any memory module and the processor 411 in the server mainboard 410, and may be configured to perform all the functions of the third integration unit 421 and the fourth integration unit 422 in the method embodiment shown in Figure 9, including steps 903, 904, and 905 in Figure 9. For example, the integration unit may receive access frequency information for each second memory address in the memory module where the processing module is installed, sent by the processing module in any memory module via the goldfinger connector, or it may collect statistics on the access frequency information for each second memory address in each memory module, and then send the statistics to the processor 411 to help the processor 411 and the memory module implement the aforementioned cold and hot migration solutions.

[0152] Alternatively, in yet another example, the media management board 420 may include three or more integrated units. Each integrated unit shares some of the functions of the media management board 420, and the three or more integrated units jointly perform all of the functions of the media management board 420.

[0153] For concepts, explanations, detailed descriptions, and other steps related to the cold and hot transition solutions in this part of the content, please refer to the description of the content in the method embodiment shown in Figure 9. Further details are not provided here.

[0154] In the aforementioned solution, it will be understood that the processing module within the memory module and the media management board outside the memory module jointly perform cold and hot data migration operations. The processing module within the memory module may be configured to send only access frequency information of the storage medium within the memory module to the components outside the module, or specific memory migration operations may be performed on the side of the components outside the module. Therefore, if the processing module contains only one integration unit, even if the integration unit is obtained by improving an existing ASIC within the memory module, the integration unit only needs to add information sending functionality based on the original memory access functionality of the ASIC. Compared to a solution that requires redeveloping an ASIC for an existing new server system to perform the memory migration function as a whole, the difficulty of development is lower, and lower additional development and labor costs can be introduced based on implementing cold and hot migration solutions to further implement low-cost memory expansion of servers. If the processing module contains at least two integration units, one of the integration units (e.g., the first integration unit) may remain the original ASIC. One or two new integration units (e.g., a second integration unit) are added to the memory module, and frequently accessed data in the second storage medium within the memory module where the one or two new integration units are installed may be migrated to the first storage medium within the server mainboard via the one or two new integration units in conjunction with components outside the module, without the need to redevelop the original integration unit within the memory module. Compared to redeveloping the original integration unit, developing one or two new integration units has a simpler research and development process. For example, there is no need to consider how to arrange components corresponding to different functions on one unit, or how to route wiring to enhance interference prevention between different functional components, and the required labor costs and research and development costs are lower.Regardless of the number of integrated units included in the processing module, cold and hot migration solutions can be implemented using the server system provided in this application, resulting in improved server memory performance without increasing the workload of the original integrated units in the memory module, and with the additional costs to be kept as low as possible. This helps implement cost-reduction design concepts in the process of expanding server memory.

[0155] The above describes specific embodiments of cold and hot migration solutions from the perspective of node interactions across the entire server system. Below, from the perspective of internal embodiments of memory modules, we describe the tasks borne by each component within a memory module when cold and hot migration solutions are implemented, as well as some other functions.

[0156] The system architecture shown in Figure 5b is used as an example. Figure 10 is a diagram of the internal circuitry of a memory module according to this application. In the diagram, a memory module 431 is used as an example. As shown in Figure 10, in addition to including a first integration unit 43111, a second integration unit 43112, at least one second storage medium (e.g., DDR11 to DDR14), and a goldfinger connector 4312, the memory module 431 may further include a power module (power, PWR) 4314, at least one indicator (e.g., a read / write status indicator 43151 and a memory module indicator 43152), at least one temperature transducer (temperature transducer, TMP) (e.g., TMP43161 and TMP43162), flash memory (flash) 4317, and data lines, control address lines, and other communication lines that perform the connection relationships shown in the diagram. A PCB may also be included. The components within the memory module 431 are arranged at corresponding locations on the PCB, and two interconnected components may be connected via in-board wiring on the PCB.

[0157] Only the board arrangement relationships of the memory module 431 are described herein, and it should be noted that in some scenarios, multi-board arrangements may be configured alternatively. For example, the memory module 431 includes multiple PCBs that overlap each other, and the components within the memory module 431 are arranged separately on the multiple PCBs. Components arranged on one PCB are connected via in-board wiring, and components arranged on different PCBs are connected via inter-board wiring. The overlap of the multiple PCBs may be complete, partial, or some PCBs may partially overlap while others completely overlap. In this way, overlapping arrangements can be performed in space, resulting in a reduction in the footprint of the memory module and enabling a miniaturized design of the memory module.

[0158] Furthermore, the component composition of the memory module shown in Figure 10 is merely an example, and the memory module may optionally include more or fewer components than those shown in the figure. For example, in some embodiments, the memory module 431 may further include integration units other than the first integration unit 43111 and the second integration unit 43112, and the other integration unit may be configured to share the work of the first integration unit 43111 or the second integration unit 43112. As another example, in some other embodiments, the DDRC may not optionally be integrated into the first integration unit 43111, and may, for example, be used as an independent device, integrated into the second integration unit 43112, or integrated into another non-integrated unit. As yet another example, in some other embodiments, the memory module 431 may not optionally include the PWR 4314, but may be directly powered by using an external power supply to save the volume occupied by the memory module 431. As yet another example, in some other embodiments, the memory module 431 may optionally include more or fewer indicators than two, or more or fewer TMPs than two. Many possible embodiments still exist that are not individually listed in this application.

[0159] The following will describe each component within the memory module in detail, using the component composition shown in Figure 10 as an example.

[0160] The first integration unit 43111 includes a high-speed serial protocol (compute express link, CXL) interface and at least one DDR controller (DDR controller, DDRC). The CXL may be connected to serial pin a1 on the goldfinger connector 4312 via a serial bus. The serial bus may be, for example, an X16 bus with 16 serial transmit channels as shown in the figure, or an X4 bus or an X8 bus. This is not limited to these. The number of DDRCs also depends on the memory mode and the number of DDRs of the memory module 431. For example, when 2DPC mode is used, one DDRC may be connected to two DDRs. Since the memory module 431 contains four DDRs, the first integration unit 43111 may include two DDRCs, for example, DDRC0 and DDRC1. DDRC0 is connected to DDR11 and DDR12 via data lines, and DDR1 is connected to DDR13 and DDR14 via data lines. The data lines may be configured to perform the transmission of data signals, for example, DQ signals. In a data read scenario, the DDRC may determine when to receive read data based on the DQ signal sent by the connected DDR. In a data write scenario, the DDR may determine when to trigger data reception based on the DQ signal sent by the connected DDRC. For example, in some scenarios, data read and write depend on the DQ signal and the data strobe signal DQS. The DQS signal is transmitted on a DQS signal line, and each chip has a DQS data line (not shown) configured to transmit the DQS signal used as a reference for read and write. The DQS signal can be received by the DDRC and DDR in real time. In a data read scenario, after receiving the DQ signal from the DDR, the DDRC may compare the DQ signal with the DQS signal. When the edges of the DQ signal align with the edges of the DQS signal (for example, when the rising edge of the DQ signal aligns with the rising edge of the DQS signal), the DDRC begins reading the data stored in the memory cell.In contrast, in a data writing scenario, after receiving the DQ signal from DDRC, DDR may compare the DQ signal with the DQS signal. When the center of the DQ signal aligns with the center of the DQS signal (for example, when the pulse center of the DQ signal aligns with the pulse center of the DQS signal), DDR begins writing data to the memory cell. Furthermore, DDRC0 may be further connected to each memory cell in DDR11 and DDR12 via control address lines, and DDR1 may be further connected to each memory cell in DDR13 and DDR14 via control address lines. The control address lines are configured to perform the transmission of control address (CA) signals. The control address lines generally include row control address lines and column control address lines. For example, suppose there are M rows and N columns of memory cells. In this case, the control address lines may include M row control address lines and N column control address lines. When data in a specific memory cell needs to be read / written, the DDR may first send an enable level on the row control address line of the row in which the memory cell is located to drive the row in which the memory cell is located to enable the memory cell, or it may send an enable level on the column control address line of the column in which the memory cell is located to drive the memory cell to enable the memory cell. In this case, the DDR can read / write data in the enabled memory cell. In this process, the CA signal on the row control address line of the row in which the memory cell to be read / written is located and the CA signal on the column control address line of the column in which the memory cell to be read / written is located are presented as enable levels, and CA signals on other control address lines are presented as invalid levels. In some embodiments, the enable level may be a "1" level and the invalid level may be a "0" level. Alternatively, in some other embodiments, the enable level may be a "0" level and the invalid level may be a "1" level.

[0161] It should be noted that the first integration unit 43111 may further include other interfaces in addition to CXL, such as a clock interface b2 and a status interface b3. The clock interface b2 may be connected to a clock pin a2 on the Goldfinger connector 4312 via a reference clock signal line Ref_clk, and is configured to receive a reference clock signal transmitted via a clock pin a2 on the Goldfinger connector 4312. The reference clock signal may be sent, for example, by a processor 411, and the first integration unit 43111 may provide a reference clock to each component in the memory module 431 based on the received reference clock signal. The status interface b3 may be connected to a management pin a3 on the Goldfinger connector 4312 via an out-of-band management bus SMBUS, and is configured to receive status request messages transmitted via a management pin a3 on the Goldfinger connector 4312. The status request messages may be sent, for example, by a processor 411, and are used to obtain relevant status information of the memory module 431, such as temperature. In this case, the first integration unit 43111 may, based on a status request message, obtain the temperatures collected by TMP43161 and TMP43162 installed at different locations on the memory module 431, and return the temperature or processed temperature to the processor 411 via the SMBUS and management pin a3 on the goldfinger connector 4312.

[0162] Furthermore, the first integration unit 43111 may be further connected to a read / write status indicator 43151 via a line. When reading / writing data in DDR11 to DDR14, the first integration unit 43111 may send an ON instruction to the read / write status indicator 43151, or send an OFF instruction to the read / write status indicator 43151 after the read / write is complete, in order to notify an external party in a timely manner whether the memory module 431 is reading / writing by controlling whether the read / write status indicator 43151 is in an ON state.

[0163] Furthermore, the code or instructions for performing the aforementioned functions by the first integration unit 43111 may be stored in FLASH4317. The first integration unit 43111 is connected to FLASH4317 via a serial peripheral interface (SPI) and retrieves the necessary code or instructions from FLASH4317 via SPI as needed to perform the aforementioned functions.

[0164] The second integration unit 43112 may be connected to all control address lines in the memory module 431 and may be configured to monitor the CA signals on these control address lines in real time. When the second integration unit 43112 detects a level jump in the CA signal on a particular control address line, it parses the jump, determines the memory cell accessed by the first integration unit 43111, and further determines the second memory address to which that memory cell belongs. In some scenarios, the second integration unit 43112 may also store a second access frequency table. The second access frequency table includes multiple second memory addresses and their corresponding access frequencies. Multiple second memory addresses are obtained by partitioning DDR11-DDR14. For example, it is assumed that DDR11-DDR14 totals 128GB. 33,554,432 second memory addresses may be obtained by partitioning in a manner that divides each 4KB into one second memory address. The second integration unit 43112 may periodically update the second access frequency table. In each cycle, the second integration unit 43112 may, after determining that one second memory address has been accessed, increment the access frequency of the second memory address in the second access frequency table by 1 until the end of the current cycle, in order to obtain the second access frequency table corresponding to the current cycle. The second integration unit 43112 may be further connected to the out-of-band communication pin a4 on the goldfinger connector 4312 via an out-of-band communication bus. The out-of-band communication bus may be, for example, the Hisport bus shown in the figure. Correspondingly, the out-of-band communication pin a4 on the goldfinger connector 4312 is correspondingly the Hisport pin, and the Hisport pin may be further connected to the third integration unit 421 in the media management board 420. After each cycle has ended, the second integration unit 43112 may send the second access frequency table for the current cycle to the third integration unit 421 via the Hisport bus and Hisport pins on the Goldfinger connector 4312.The second integration unit 43112 may refresh the second access frequency table, for example, by resetting the access frequency of all second memory addresses in the second access frequency table to 0, or by initiating the update operation of the second access frequency table for the next cycle.

[0165] In addition to the serial pin a1, clock pin a2, management pin a3, and Hisport pin a4 described above, the Goldfinger connector 4312 may further include a power pin a5. The power pin a5 is connected to the PWR 4314 in the memory module 431 and is configured to receive a 12V power signal transmitted by the processor 411 and provide the power signal to the PWR 4314. The PWR 4314 performs voltage division on the 12V power signal to obtain several power sub-signals, such as 1.3V and 1.2V power sub-signals, and then provides several power sub-signals separately for the first integration unit 43111, the second integration unit 43112, and DDR11 through DDR14. The Goldfinger connector 4312 may further include a status control pin a6. The status control pin a6 is connected to the memory module indicator 43152. When memory module 431 is faulty, the memory module indicator 43152 may receive illumination instruction information sent by processor 411 via status control pin a6 on goldfinger connector 4312, or it may illuminate the memory module indicator 43152 based on the illumination instruction information to notify an external party of the faulty state of memory module 431 in a timely manner.

[0166] Referring to the above description of the components within the memory module 431, when implementing cold and hot migration solutions, the processor 411 may send a read / write request to the CXL of the first integration unit 43111 via serial pin a1 on the goldfinger connector 4312. Based on the read / write request, the first integration unit 43111 determines the memory cell to be accessed and sends a read / write instruction to the DDRC connected to the DDR where the memory cell is installed. Based on the read / write instruction, the DDRC sends a CA signal to the control address line corresponding to the memory cell and performs a read / write operation on the data stored in the memory cell after the memory cell has been enabled. After detecting a change in the CA signal, the second integration unit 43112 determines the accessed memory cell based on the changed CA signal, updates the access frequency in the second access frequency table for the current cycle of the second storage address to which the memory cell belongs, continues to monitor the CA signal until the current cycle ends, and sends the final second access frequency table to the third integration unit 421 via the Hisport bus and Hisport pin a4 on the Goldfinger connector 4312. Subsequently, the third integration unit 421 collects statistics on the access frequency table of each memory module and communicates with the fourth integration unit 422, sending the second access frequency tables of all memory modules to the processor 411. The processor 411 performs statistical analysis on the second access frequency table of each memory module and the access frequency of each first storage address in the server mainboard 410 to determine the hot data in each memory module and the cold data in the server mainboard 410. Furthermore, the processor 411 communicates with the first integration unit in each memory module, resulting in the exchange of hot data in each memory module and cold data in the server mainboard 410. For specific embodiments of subsequent operations, please refer directly to Figure 9. Details will not be explained again here.

[0167] Similarly, when the server system uses the architecture shown in Figure 5a, Figure 11 is a diagram of the internal circuitry of another memory module according to this application. In the figure, memory module 431 is still used as an example. In memory module 431, the integration unit may further include a Hisport interface b4 in addition to including a clock interface b2 and a status interface b3. A Hisport pin a4 on the goldfinger connector 4312 is connected to the Hisport interface b4 of the integration unit via the Hisport bus. The integration unit may send access frequency information for the current cycle to the goldfinger connector 4312 via the Hisport interface b4, and then send the access frequency information to the media management board 420 via the goldfinger connector 4312. For the function and connectivity of the interfaces and components in Figure 11, see the above description of the interfaces and components in Figure 10. Further details are not described here again.

[0168] It will be understood that the above explanation is provided only by using examples in which the Goldfinger connector redefinition solution or cold and hot migration solution is applied in the server field. In actual scenarios, the Goldfinger connector redefinition solution may be applicable to any device connected via a Goldfinger connector and having power pins on the Goldfinger connector. To further extend the specifications of the device on which the Goldfinger connector is installed, greater power supply capacity can be implemented by combining the original number of power pins with a smaller number of power pins. The cold and hot migration solution may be applicable to any solution having two storage media. To quickly access hot data, improve the storage capacity of the storage media on which the hot data is installed, and improve the storage performance of a storage device having two storage media, hot data in a storage medium with a large access delay is migrated to a storage medium with a small access delay, and cold data in a storage medium with a small access delay is migrated to a storage medium with a large access delay.

[0169] Based on the aforementioned structure and functional principles of the memory module, the present application may further provide a data migration method. The method may be performed by a memory module or an electronic device (e.g., a server). The method includes the steps of: obtaining cold and hot migration instructions, the cold and hot migration instructions conveying cold data in a first memory address associated with a processor and / or address information of a second memory address associated with a memory module; sending hot data in a second memory address to a processor in an electronic device based on the address information of the second memory address conveyed by the cold and hot migration instructions; and storing the cold data in the first memory address conveyed by the cold and hot migration instructions in the second memory address.

[0170] In this specification, “associated” may be understood as “logically connected” or “functionally accessible.” For example, a first memory address associated with a processor is a memory address that can be directly accessed by the processor in the electronic device mainboard, and may, for example, be a memory address located within the electronic device mainboard. The memory address is directly connected to the processor in the electronic device mainboard, and the internal data of the memory address may be directly accessed by the processor in the electronic device mainboard. Similarly, a second memory address associated with a memory module is a memory address that can be directly accessed by the processing module in the memory module, and may, for example, be a memory address located within the memory module. The memory address is directly connected to the processing module in the memory module, and the internal data of the memory address may be directly accessed by the processing module in the memory module.

[0171] Optionally, prior to the step of obtaining cold and hot transition instructions, the method may further include the steps of accessing one or more second storage addresses in the memory module and sending access frequency information for each second storage address in the memory module to a media management board in the electronic device.

[0172] Please note that for the specific implementation process of the method, please refer to the relevant explanation in Figure 9. Further details will not be explained here.

[0173] According to the method described above, the present application may further provide a data migration device. Figure 12 shows a possible structure of the data migration device. The data migration device 1200 may be a chip or a circuit. The data migration device 1200 may correspond to a memory module, for example, a processing module within a memory module, or a first and second integration unit in the method described above. The data migration device 1200 may perform steps of the method corresponding to the first and second integration units in the embodiment shown in Figure 9. As shown in Figure 12, the data migration device 1200 may include an acquisition module 1210, a transceiver module 1220, and a storage module 1230.

[0174] In this application, the acquisition module 1210 may acquire cold and hot transition instructions, which transmit cold data in a first memory address associated with the processor and / or address information for a second memory address associated with the memory module. The transceiver module 1220 may send hot data in the second memory address to the processor in the electronic device based on the address information for the second memory address transmitted by the cold and hot transition instructions. The memory module 1230 may store the cold data in the first memory address transmitted by the cold and hot transition instructions in the second memory address.

[0175] For a concept, description, detailed description, and other steps of the data transfer device 1200 related to the technical solution provided in this application, please refer to the description of the method or other embodiments described above. Further details are not described here again.

[0176] For the functions of the modules within the data migration device 1200, it will be understood that you should refer to the embodiments of the corresponding method embodiments. Further details will not be described here.

[0177] It should be understood that the division of the data migration device 1200 into units is merely a logical functional division. In actual implementation, all or part of the units may be integrated into a single physical entity, or they may be physically separated. This is not specifically limited.

[0178] Furthermore, based on the foregoing, this application further provides an electronic device. The electronic device may be, for example, a server, or may include a server. For example, in some embodiments, the electronic device may be a computer device having a display screen and a server. The computer device may further include peripherals such as a hard disk, speaker, microphone, mouse, or keyboard, or it may further include built-in devices such as a driver or input / output interface.

[0179] This application further provides a chip. The chip may include any one or more modules of a processing module or a media management board, or any one or more integration units of a first integration unit, a second integration unit, a third integration unit, and a fourth integration unit, or further include a processor, or further include an interface. Any one or more components are configured to read instructions via the interface in order to perform the corresponding method in the embodiment shown in Figure 9.

[0180] This application further provides a computer-readable storage medium for storing computer programs. When a computer program is executed, a method is carried out by any of the components of the embodiment shown in Figure 9.

[0181] This application further provides a computer program product. When the computer program product is in operation, a method is carried out that is performed by any of the components of the embodiment shown in Figure 9.

[0182] The foregoing description represents only specific embodiments of this application and is not intended to limit the scope of protection of this application. Any modifications or substitutions readily understood by those skilled in the art within the scope of the technical scope disclosed herein shall fall within the scope of protection of this application. Accordingly, the scope of protection of this application shall be subject to the scope of protection of the claims. [Explanation of Symbols]

[0183] 410 Server Mainboard 411 processors 420 Media Management Board 421 Third Integrated Unit 422 Fourth Integrated Unit 431~43N Memory Modules 4311 Processing Module 43111 First Integrated Unit 43112 Second Integrated Unit 4312 Gold Finger Connector 4314 Power Module 43151 Read / Write Status Indicator 43152 Memory Module Indicator 43161 Temperature Transducer 43162 Temperature Transducer 4317 Flash Memory 1200 Data Migration Device 1210 Acquisition Module 1220 Transceiver Module 1230 Memory Module

Claims

1. A memory module comprising a processing module and a gold finger connector connected to the processing module, The gold finger connector is configured to plug into a component outside the memory module in order to establish a communication connection between a component inside the memory module and a component outside the memory module. The processing module is configured to receive read / write requests from the components outside the memory module via the goldfinger connector, access at least one storage medium within the memory module based on the read / write requests, and transmit access frequency information for each storage address corresponding to at least one storage medium within the memory module within a predetermined period to the components outside the memory module via the goldfinger connector, and the access frequency information for each storage address is used by the components outside the memory module to transfer data stored in storage addresses whose access frequency is greater than a hotness threshold to a storage medium connected to the processor. Memory module.

2. The processing module comprises a first integration unit and a second integration unit, the first integration unit being connected to at least one storage medium in the memory module, and the goldfinger connector being connected to the first integration unit and the second integration unit. The first integrated unit is configured to receive read / write requests from the components outside the memory module via the goldfinger connector and to access at least one storage medium within the memory module based on the read / write requests. The second integration unit is configured to send the access frequency information for each storage address corresponding to at least one storage medium in the memory module during the pre-configured period to the components outside the memory module via the goldfinger connector. The memory module according to claim 1.

3. One or more reserved pins of the Goldfinger connector are defined as out-of-band communication pins, and the second integration unit is connected to the out-of-band communication pins via an out-of-band communication bus. The second integration unit is configured to send the access frequency information for each storage address to the goldfinger connector via the out-of-band communication bus and the out-of-band communication pins. The memory module according to claim 2.

4. The out-of-band communication pin transmits the access frequency information using differential signals, with pins B68 and B69 of the Goldfinger connector defined as two transmit pins, and pins A68 and A69 of the Goldfinger connector defined as two receive pins. The second integration unit is configured to send the access frequency information for each storage address to the Goldfinger connector via pins B68 and B69, and to receive the returned information from the Goldfinger connector via pins A68 and A69. The memory module according to claim 3.

5. The memory module further comprises control address lines, and the first integrated unit is connected via the control address lines to at least one storage medium within the memory module. The first integration unit is particularly configured to access at least one storage medium in the memory module by adjusting the control address CA signal on the control address line, The second integration unit is particularly configured to determine, based on changes in the CA signal on the control address line, the access frequency information within the pre-set period for the storage address corresponding to at least one storage medium in the memory module in which the second integration unit is installed. A memory module according to any one of claims 2 to 4.

6. The memory module according to claim 1, wherein the processing module comprises one integration unit, the integration unit is connected between at least one storage medium in the memory module and the goldfinger connector.

7. A memory module according to any one of claims 2 to 6, wherein a first positive pin is located in the region where pins B1 to B6 of the gold finger connector are installed, and a first ground pin is located in the region where pins A1 to A6 of the gold finger connector are installed, and the widths of both the first positive pin and the first ground pin are greater than a preset width, the preset width being the original pin width as defined in the standard.

8. The memory module according to claim 7, wherein the preset width is K, and the widths of both the first positive pin and the first ground pin are 11K.

9. The memory module according to claim 7, wherein there are two first positive pins and two first ground pins, and the preset width is K, the width of each first positive pin and each first ground pin is both 5K, or the width of one first positive pin and one first ground pin is 7K and the width of the other first positive pin and the other first ground pin is 3K.

10. The memory module according to claim 7, having three first positive pins and three first ground pins, wherein the width of each first positive pin and each first ground pin is 3K when the preset width is K.

11. The memory module according to any one of claims 7 to 10, wherein the first positive pin and the first ground pin are made of gold-plated copper.

12. An electronic device comprising a memory module according to any one of claims 1 to 11.

13. The system further comprises an electronic device main board and a media management board, wherein the electronic device main board comprises a processor and at least one first storage medium, and the memory module comprises at least one second storage medium, and the number of memory modules is N, where N is a positive integer. Any memory module is configured to send access frequency information for each second storage address corresponding to at least one second storage medium within the memory module to the media management board during a pre-configured period. The media management board is configured to send access frequency information of each second storage address corresponding to each second storage medium in each of the N memory modules within the pre-set period to the processor. The processor is configured to move data stored in target second storage addresses with an access frequency greater than a hotness threshold to the first storage medium, and to move data stored in target first storage addresses with an access frequency less than a coldness threshold to the second storage medium, based on access frequency information for each first storage address corresponding to at least one first storage medium within the pre-configured period, and access frequency information for each second storage address corresponding to each second storage medium in each of the N memory modules within the pre-configured period. The electronic device according to claim 12.

14. The processing module within the aforementioned memory module comprises a first integration unit and a second integration unit, The first integration unit in any memory module is configured to access the at least one second storage medium in the memory module in which the first integration unit is installed. The second integration unit in any memory module is configured to send the access frequency information within the pre-set period for each second storage address corresponding to the at least one second storage medium in the memory module in which the second integration unit is installed to the media management board. The electronic device according to claim 13.

15. The media management board comprises a third integration unit and a fourth integration unit, the third integration unit being separately connected to the fourth integration unit and the second integration unit in each memory module, and the fourth integration unit being further connected to the processor. The third integration unit is configured to receive the access frequency information of each second storage address in the memory module within the preset period, which has been sent by the second integration unit in each memory module, to collect the access frequency information of each second storage address in the N memory modules within the preset period, and to send the collected access frequency information to the fourth integration unit. The fourth integration unit is configured to send the collected access frequency information of each second storage address in the N memory modules within the pre-configured period to the processor. The electronic device according to claim 13 or 14.

16. A data migration method, wherein the method is performed by a memory module according to any one of claims 1 to 11, or by an electronic device according to any one of claims 12 to 15, and the method is A step of obtaining cold and hot migration instructions, wherein the cold and hot migration instructions convey at least one of cold data in a first memory address associated with the processor, or address information in a second memory address associated with the memory module. The steps include sending hot data in the second storage address to the processor in the electronic device based on the address information of the second storage address conveyed by the cold and hot transition instructions, The steps include storing the cold data in the first storage address, as conveyed by the cold and hot transition instructions, in the second storage address, and Methods that include...

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