AI edge computing method and system based on FPGA and MCU

Abstract

The application relates to the technical field of intelligent servo control, and provides an AI edge calculation method and system based on FPGA and MCU, which comprises the following steps: analyzing macro task instructions to generate a composite control strategy package; collecting original physical signals at an ultrahigh sampling rate, performing real-time filtering and difference through a hardware pipeline, combining historical control outputs and target position values, calculating and outputting digital state data packages; concurrently executing AI vibration prediction and dynamic PID control in the current servo cycle to generate a second micro-vibration state prediction value, querying a dynamic gain scheduling table according to a second real-time state vector, combining a real-time tracking error to generate a final PID control output; converting the final PID control output into a digital duty cycle instruction by using the FPGA, and generating a physical electrical signal by a hardware PWM generator to complete a full-hardware servo closed loop. The application cooperatively integrates high-frequency multi-modal perception and AI predictive calculation to construct a hardware servo closed loop of heterogeneous calculation.

Description

Technical Field

[0001] This invention relates to the field of intelligent servo control technology, and in particular to an AI edge computing method and system based on FPGA and MCU. Background Technology

[0002] With the widespread application of intelligent robots and high-speed servo systems in intelligent manufacturing, automated agriculture, and other fields, real-time suppression of high-frequency micro-vibrations has become a key technology for ensuring high-speed operation and precision control. How to detect and actively suppress high-frequency micro-vibrations at the end effector in real time under conditions of high-speed start-stop and load changes, effectively compensating for the limitations of traditional MCU-based controllers in sensing accuracy and real-time capabilities, and addressing the insufficient control bandwidth caused by the lack of FPGA parallel hardware processing capabilities, has become a crucial issue that servo drive systems urgently need to address in improving operational cycle time and positioning accuracy.

[0003] Chinese patent application CN116090520A discloses a data processing system and method. The method is set on an FPGA SoC and includes: an MCU and a data processing module implemented on the FPGA. The MCU is used to parse the AI ​​model to obtain the computational data of each layer of the AI ​​model. It is also used to take the first layer of the AI ​​model as the current layer of the AI ​​model, and after the current layer of the AI ​​model is completed, take the next layer of the AI ​​model as the current layer of the AI ​​model. Whenever an AI model is taken as the current layer of the AI ​​model, it controls the input of the computational data of the current layer of the AI ​​model to the accelerator unit and controls the input of the result data of the previous layer of the AI ​​model adjacent to the current layer of the AI ​​model to the data processing module. The data processing module is used to perform parallel computation of the current layer of the AI ​​model based on the obtained data.

[0004] However, current technology still faces many challenges. Traditional MCU-based servo controllers, when performing high-speed motion tasks, typically cannot pre-configure their control parameters based on macroscopic task instructions and are limited by low sampling rates and serial bus latency. When a robotic arm starts and stops at high speed in an industrial quality inspection scenario, its end effector inevitably generates high-frequency micro-vibrations. Due to the lack of high-speed parallel sensing and processing capabilities of FPGAs, the controller struggles to capture vibration signals with high fidelity. Furthermore, because the fixed-gain control logic can only perform passive hysteresis compensation, the controller cannot actively suppress vibrations in their early stages. This forces the end-effector vision system to spend extra time waiting for the vibrations to naturally decay before it can begin precise imaging or positioning, significantly extending the work cycle and severely restricting the overall production efficiency of the production line. Summary of the Invention

[0005] To achieve the above objectives, this invention provides an AI edge computing method based on FPGA and MCU, the specific technical solution of which is as follows:

[0006] The MCU parses the macro-level task instructions issued by the upper-level robot master control, generates a composite control strategy package containing an AI vibration prediction model and a dynamic gain scheduling table, loads the composite control strategy package onto the FPGA, uses the AI ​​vibration prediction model to generate micro-vibration state prediction values, and outputs PID control output based on the micro-vibration state prediction values ​​and the dynamic gain scheduling table.

[0007] The raw physical signals are acquired concurrently at an ultra-high sampling rate using the hardware logic unit of the FPGA. The acquired raw physical signals are filtered and differentially processed in real time through the hardware digital signal processing pipeline of the FPGA to obtain the state sequence. Combined with historical control output and target position value, a digital state data packet including the input state vector, real-time tracking error and scheduler basic state vector is calculated and output.

[0008] Within the current servo cycle, the hardware calculation of AI vibration prediction and dynamic PID control is performed concurrently by the FPGA. The AI ​​vibration prediction model calculates the input state vector to generate the second micro-vibration state prediction value. Based on the combined second real-time state vector, the dynamic gain scheduling table is queried. Combined with the real-time tracking error, the final PID control output is calculated and generated.

[0009] The final PID control output is converted into a digital duty cycle instruction by the hardware arithmetic logic unit inside the FPGA, and the hardware PWM generator inside the FPGA generates physical electrical signals in real time according to the digital duty cycle instruction, thus completing the full hardware servo closed loop of the AI ​​edge computing.

[0010] Furthermore, the method for outputting PID control output includes:

[0011] The macroscopic task instructions issued by the upper-level robot master controller are analyzed, dynamic influencing factors are extracted to generate a vibration feature profile, and based on the vibration feature profile and task accuracy requirements, a composite control strategy package is decided and generated; the macroscopic task instructions include target pose, motion velocity curve, end-effector load mass and task accuracy requirements.

[0012] The weight data packet of the AI ​​vibration prediction model is quantized using an MCU to generate quantized AI prediction model weights. These quantized weights are then written at high speed into the on-chip memory of the FPGA to complete hardware instantiation. Based on the state vector of the current servo cycle, the predicted micro-vibration state value for the next servo cycle is calculated and generated. The state vector includes the FPGA's state during the servo cycle. The set of physical state data collected in real time from its sensor interface, including servo cycles The motor position, motor speed, motor current, and control output of the previous cycle;

[0013] The dynamic gain scheduling table is written into the FPGA's access memory area. Based on the real-time state vector composed of the micro-vibration state prediction value and the state vector, the dynamic PID gain coefficient is queried and obtained using the dynamic gain scheduling table. Combined with the real-time tracking error, the PID control output is output.

[0014] Furthermore, the dynamic influencing factors include the motion velocity curve and the end load mass;

[0015] The motion velocity curve is analyzed to extract instantaneous dynamic parameters, including peak acceleration and peak jerk.

[0016] The peak acceleration is the maximum absolute value of acceleration extracted by the MCU from the entire motion curve described by the motion velocity curve; the peak jerk is the maximum absolute value of the rate of change of acceleration extracted by the MCU from the motion velocity curve.

[0017] Furthermore, the method for outputting the digital status data packet includes:

[0018] Based on the preset ultra-high sampling rate, the hardware interface and hardware parallelism of the FPGA are used to concurrently sample the original physical signals containing the original vibration signal, the original position signal and the original current signal under the time index of the same high frequency sampling clock, and generate a digital sampling sequence including digital acceleration sampling value, digital position count value and digital current sampling value.

[0019] The digital sampling sequence is filtered in parallel in real time using the hardware digital signal processing pipeline of FPGA to obtain digital acceleration value, position estimate value and digital current value, and hardware real-time differential is performed on the position estimate value to obtain derived velocity value, which is then combined and output as a state sequence.

[0020] Using the hardware logic units of the FPGA, an input state vector is generated based on the state sequence and the historical control output of the previous cycle. The real-time tracking error is calculated using the target position value and the position estimate. The scheduler's basic state vector is generated by combining the digital acceleration value and the derived velocity value. The output is a time-synchronized digital state data packet containing the input state vector, the real-time tracking error, and the scheduler's basic state vector.

[0021] Furthermore, the method for obtaining the derived speed value is as follows: the hardware differentiator pipeline embedded inside the FPGA immediately performs real-time differential analysis on the obtained position estimate;

[0022] The real-time differential refers to obtaining the position estimate of the current servo cycle, subtracting the position estimate of the previous servo cycle held by the register, obtaining the position change within a sampling period, and multiplying the position change by the ultra-high sampling rate used as the time scale to calculate the derived velocity value.

[0023] Furthermore, the method for generating the final PID control output includes:

[0024] Within the current servo cycle, using the AI ​​vibration prediction model instantiated on the FPGA, and based on the quantized AI prediction model weights, the input state vector is forward-propagated in hardware calculation to generate the second micro-vibration state prediction value for the next servo cycle.

[0025] Within the current servo cycle, the second micro-vibration state prediction value and the scheduler's basic state vector are combined into a second real-time state vector. The second real-time state vector is then used to query the dynamic gain scheduling table in real time to obtain the second dynamic PID gain coefficient. Finally, the PID control output is calculated by combining the real-time tracking error.

[0026] Furthermore, the method for generating the physical electrical signal includes:

[0027] Using the hardware arithmetic logic unit inside the FPGA, hardware scaling transformation is performed on the final PID control output to calculate and generate digital duty cycle instructions.

[0028] By utilizing the hardware PWM generator inside the FPGA, physical electrical signals are generated in real time based on digital duty cycle instructions and preset PWM switching frequencies, thus completing a fully hardware servo closed loop for AI edge computing.

[0029] An AI edge computing system based on FPGA and MCU is used to implement the above-mentioned AI edge computing method based on FPGA and MCU. The system includes a system heterogeneous configuration module, a state-aware distribution module, a parallel computation module, and a hardware output module.

[0030] The system heterogeneous configuration module is used to parse the macro-level task instructions issued by the upper-level robot master control using the MCU, generate a composite control strategy package containing an AI vibration prediction model and a dynamic gain scheduling table, load the composite control strategy package onto the FPGA, generate micro-vibration state prediction values ​​using the AI ​​vibration prediction model, and output PID control output based on the micro-vibration state prediction values ​​and the dynamic gain scheduling table.

[0031] The state-aware distribution module is used to concurrently acquire raw physical signals at an ultra-high sampling rate using the hardware logic unit of the FPGA, and to perform real-time filtering and differential processing on the acquired raw physical signals through the hardware digital signal processing pipeline of the FPGA to obtain a state sequence. Combining historical control outputs and target position values, it calculates and outputs a digital state data packet including the input state vector, real-time tracking error and scheduler basic state vector.

[0032] The parallel calculation module is used to concurrently perform hardware calculations of AI vibration prediction and dynamic PID control using FPGA within the current servo cycle. The AI ​​vibration prediction model calculates the input state vector to generate the second micro-vibration state prediction value, and based on the combined second real-time state vector, queries the dynamic gain scheduling table, and calculates and generates the final PID control output by combining the real-time tracking error.

[0033] The hardware output module is used to convert the final PID control output into a digital duty cycle instruction using the hardware arithmetic logic unit inside the FPGA, and the hardware PWM generator inside the FPGA generates physical electrical signals in real time according to the digital duty cycle instruction, thus completing the full hardware servo closed loop of AI edge computing.

[0034] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0035] This invention utilizes an MCU to offline analyze macroscopic tasks to pre-configure the AI ​​model and dynamic gain scheduling table of an FPGA. The FPGA then integrates the vibration prediction value of the AI ​​with the current state within the real-time servo cycle to dynamically adjust the PID gain. This improves upon the problems of lag in control response and incomplete suppression of high-frequency micro-vibrations caused by traditional fixed-parameter controllers that rely solely on passive compensation based on the current error.

[0036] This invention utilizes the hardware parallelism and pipeline of FPGA to perform ultra-high sampling rate acquisition and real-time hardware preprocessing of multimodal physical signals under the same clock index, thereby improving the problems of high-frequency micro-vibration signal distortion, aliasing and data timing mismatch caused by the limitations of sampling rate and bus delay in traditional MCU.

[0037] This invention utilizes an FPGA to concurrently compute AI vibration prediction and dynamic PID control within the same servo cycle, and integrates the predictive vibration information of the AI ​​in real time to instantaneously adjust the gain of the PID controller. This avoids the problems of failure in suppressing high-frequency micro-vibrations at the end and excessively long positioning waiting time caused by traditional controllers that rely solely on current error for hysteresis compensation.

[0038] This invention utilizes the hardware arithmetic logic unit and PWM generator inside the FPGA to instantly convert digital control commands generated by AI edge computing into physical drive signals, constructing a fully hardware servo closed loop from state perception, AI prediction, control decision-making to physical execution, thus avoiding the control execution delay and bandwidth limitations caused by software processing and bus communication in traditional MCUs. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a flowchart illustrating the principle of the AI ​​edge computing method based on FPGA and MCU of the present invention.

[0041] Figure 2 This is a functional block diagram of the AI ​​edge computing system based on FPGA and MCU of the present invention. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] Example 1

[0044] Please see Figure 1 As shown, this embodiment provides an AI edge computing method based on FPGA and MCU, including:

[0045] The S1000 uses the MCU to parse macroscopic task instructions issued by the upper-level robot main controller. Generate an AI-integrated vibration prediction model and dynamic gain scheduling table Composite control strategy package The composite control strategy package Loaded onto the FPGA, utilizing the AI ​​vibration prediction model Generate micro-vibration state prediction values Based on the predicted value of the micro-vibration state and the dynamic gain scheduling table Output PID control output .

[0046] Specifically, this step aims to utilize the microcontroller unit (MCU), which acts as the system policy manager, to execute macro-level task commands issued by the upper-level robot master controller. Predictive analysis enables the system to perform analysis before task execution, targeting specific tasks such as end-point load quality. and motion speed curve The corresponding AI vibration prediction model is selected. and its weighted data packets The final quantized AI model weights and the corresponding dynamic gain scheduling table By injecting a Field Programmable Gate Array (FPGA) as an AI servo real-time controller, the transformation from passive instruction execution to an active control unit with task scenario perception and vibration prediction capabilities is realized, laying a predictive heterogeneous computing foundation for end-effector micro-vibration suppression in high-speed start-stop scenarios.

[0047] Further, step S1000 includes:

[0048] Step S1100: Analyze the macro-level task instructions issued by the upper-level robot main controller. Extracting dynamic influencing factors to generate vibration characteristic profiles And based on vibration characteristics, a profile was created. and mission accuracy requirements Make decisions and generate composite control strategy packages. The macro-task instructions Including target pose Motion speed curve End-load quality and mission accuracy requirements .

[0049] Specifically, this step aims to utilize the MCU's offline computing capabilities to send macroscopic task instructions to the upper-level robot controller before the task begins. The analysis transforms the abstract task description into a concrete, computable profile of vibration characteristics. Based on this profile, an optimal composite control strategy package is generated. Including AI vibration prediction models Dynamic gain scheduling table And optional feedforward harmonic canceller parameters This ensures that the AI ​​model and control parameters loaded onto the FPGA can be customized for the inertial shocks and vibration modes of the current task, achieving a preventative suppression rather than a passive compensation control method.

[0050] In the specific implementation process, the MCU processes the input macroscopic task instructions. Analysis was performed to extract key dynamic influencing factors. Among them, It represents the target pose, and its data type is usually coordinates and attitude vectors, which are used to define the target position and orientation of the robot end effector in the task space; This represents the motion velocity curve, whose data structure is a set of function parameters describing the motion trajectory, used to define the movement of the end effector from the current state to the target pose. The temporal changes of velocity, acceleration, and jerk during the process; This represents the end-load mass, expressed in kilograms (kg), used by the MCU to calculate the total system inertia, and is the predicted dominant resonant frequency. and the estimated amplitude impact factor Key physical inputs; This represents the accuracy requirement for the task. It is a scalar value that defines the allowable error range, in millimeters or micrometers, and is used as a constraint for optimizing vibration suppression strategies.

[0051] The MCU further analyzes the motion speed curve. Analysis is performed to extract the instantaneous dynamic parameters that have the most direct impact on vibration and shock, namely peak acceleration. and peak jerk Among them, peak acceleration It is the MCU from the motion speed curve The maximum absolute value of acceleration, analytically extracted from the entire described motion curve, is used to correlate with the end load mass. Calculate the peak inertial force and peak jerk as defined by Newton's second law. It is the MCU from the motion speed curve The maximum absolute value of the rate of change of acceleration extracted from the analysis is used to characterize the smoothness or aggression of the motion start-stop phase. If the peak acceleration... The larger the peak accelerometer, the more severe the instantaneous impact on the flexible structure of the robotic arm and the easier it is to induce high-frequency micro-vibrations; conversely, if the peak accelerometer is smaller... The smaller the value, the smoother the motion.

[0052] After extracting the aforementioned dynamic influencing factors, the MCU calls the internally stored robot dynamic profiling analysis algorithm. Generate a quantified vibration feature profile The specific process formula is as follows:

[0053] ;

[0054] in, The vibration characteristic profile is represented by the MCU based on macroscopic task instructions. This is a quantitative physical description of the high-frequency micro-vibrations that will occur in the robot's end effector. Its value is an eigenvector containing multiple estimated vibration parameters, i.e., the estimated dominant resonant frequency. , Estimated amplitude impact factor and the estimated vibration decay time ; The robot dynamics profiling and analysis algorithm is a computational function embedded within the MCU, built upon a robot dynamics model or an offline-trained empirical data model. It is used to process macroscopic task instructions from higher layers. It translates into the underlying physical vibration characteristics to achieve pre-diagnosis of vibration problems; This indicates the estimated dominant resonant frequency, measured in Hertz (Hz), and is determined by the current end-load mass. Together with the inherent physical characteristics of the robotic arm, it is used to characterize the vibration frequency that the system is most easily excited in this task; This represents the estimated amplitude impact factor, which is a scalar value that quantifies the impact intensity and is used to characterize the impact caused by the end-load mass. and motion speed curve peak acceleration and peak jerk The expected initial amplitude of the micro-vibrations caused by the combined factors; This represents the estimated vibration decay time, a time constant characterizing the rate of decay, measured in seconds (s). It is used to quantify the system's inherent damping's ability to dissipate expected vibrations. If the estimated vibration decay time... A longer value indicates that the vibration has a strong time-series dependence.

[0055] The MCU generates a vibration feature profile. The basis for decision-making is the vibration decay time, which characterizes the time-dependent nature of the vibration. and the amplitude impact factor characterizing the impact amplitude and in the form of macro-level task instructions Task accuracy requirements To optimize constraints, the internally fixed strategy optimization selection algorithm is invoked. Decisions are made and optimal composite control strategy packages are generated in non-volatile memory. The specific process formula is as follows:

[0056] ;

[0057] in, This indicates a composite servo strategy package, which includes an AI vibration prediction model. Dynamic gain scheduling table and parameters of feedforward harmonic canceller The structured data set is used as the core configuration data for the FPGA to perform real-time control in subsequent steps; This represents a strategy optimization selection algorithm used to perform a nonlinear mapping from a physical profile to the optimal combination of AI architecture and control parameters; This refers to an AI vibration prediction model, whose data content is the algorithm selected by the policy optimization. Dynamically selected neural network architecture and its corresponding weight data package Used for real-time prediction of vibration feature profiles on FPGAs The described micro-vibrations; The dynamic gain scheduling table, a set of multidimensional lookup table data, is used in FPGAs to implement real-time, nonlinear dynamic adjustment of PID gain. This scheduling table is integrated with the AI ​​vibration prediction model. Matching; The parameters of the feedforward harmonic canceller are a set of control parameters configured for the internal signal generator of the FPGA, used when vibration characteristic profiles are displayed. Dominant resonant frequency When the amplitude is clear and accounts for a high proportion, an analog signal is actively generated on the FPGA. The canceling signals, which are of the same frequency but out of phase, directly weaken the dominant harmonic at its source.

[0058] Step S1200: Use the MCU to generate the AI ​​vibration prediction model. Weighted data packets Quantization is performed to generate quantized AI prediction model weights. The quantized AI prediction model weights Hardware instantiation is completed by high-speed writing to the FPGA's internal on-chip memory, based on the current servo cycle. state vector Calculate and generate the next servo cycle Predicted value of micro-vibration state .

[0059] Specifically, this step aims to transform the AI ​​vibration prediction model generated in step S1100. The corresponding weighted data packet In the form of hardware optimization, the quantified weights of the AI ​​prediction model are... The signal is injected at high speed and solidified into the on-chip memory of the FPGA, enabling the FPGA to predict micro-vibrations in real time within a microsecond-level servo cycle and output the next servo cycle. Predicted value of micro-vibration state .

[0060] In the specific implementation process, to ensure the AI ​​vibration prediction model To implement extremely low-latency hardware inference on an FPGA, the MCU needs to process the weight data packet corresponding to the model before transmitting it via the bus. Data processing is performed. This data processing is implemented by a quantization function running on the MCU, which processes the weighted data packets. The floating-point neural network weights and biases contained therein are converted into hardware-friendly 8-bit integer data, such as INT8, to obtain the quantized AI prediction model weights. .

[0061] Subsequently, the MCU uses a high-speed configuration bus, such as AXI-Lite or SPI bus, to configure the quantized AI prediction model weights. All quantized weights and biases are written at high speed to a designated address space in the dedicated on-chip Block Random Access Memory (BRAM) within the FPGA. The BRAM serves as a high-speed cache resource for the FPGA, providing microsecond-level or even nanosecond-level data access for the FPGA's hardware logic, ensuring the smooth operation of the AI ​​vibration prediction model. It can complete the full prediction calculation within an extremely short servo cycle.

[0062] Furthermore, the FPGA's hardware logic is designed as a reconfigurable AI computing core, also known as a neural network overlay. This AI computing core is a pre-synthesized general-purpose neural network hardware acceleration architecture, and its computational behavior is not fixed. For example, determining whether its computational behavior is to perform feedforward computation of a feedforward neural network (FNN) or loop computation of a long short-term memory (LSTM) network depends on whether it reads the quantized AI prediction model weights from the block random access memory (BRAM). Content and topology.

[0063] When the weights of the quantized AI prediction model After being fully written into Block Random Access Memory (BRAM), the AI ​​computing core accesses the quantized AI prediction model weights at high speed. The data, based on its predefined internal neural network topology, adaptively performs corresponding calculations to complete the AI ​​vibration prediction model. The process of instantiating on FPGA hardware.

[0064] In the current servo cycle Hardware-based AI vibration prediction model Based on the current servo cycle of the FPGA Collected state vectors As input, it calls the quantized AI prediction model weights stored in Block Random Access Memory (BRAM) in real time. Perform hardware calculations to calculate and output the parameters for the next servo cycle before the current cycle ends. Predicted value of micro-vibration state Wherein, the current servo cycle state vector It is the FPGA in the servo cycle The physical state data, including the current servo cycle, is collected in real time from its sensor interfaces, such as encoders and current sensors. Motor position, motor speed, motor current, and the previous servo cycle The control output is used as the AI ​​vibration prediction model. During the servo cycle Real-time input for performing predictions.

[0065] Step S1300: The dynamic gain scheduling table is... Write to the FPGA's access memory area based on micro-vibration state prediction values and state vector The combined real-time state vector Using dynamic gain scheduling table Query and obtain dynamic PID gain coefficient Combined with real-time tracking error Output PID control output .

[0066] Specifically, this step aims to integrate the AI ​​vibration prediction model generated by the MCU decision in S1100. Matching dynamic gain scheduling table High-speed injection into the FPGA's delayed access memory area, i.e., dedicated registers (control registers) or look-up tables (LUTs), enables the FPGA's PID control unit to evolve from a fixed-gain passive actuator into an adaptively adjustable dynamic-gain PID control unit, allowing it to perform servo cycles on the microsecond scale. Within, according to the next servo cycle output in step S1200 Predicted value of micro-vibration state Instantly adjust the current servo cycle The control gain.

[0067] In the specific implementation process, the MCU uses a high-speed configuration bus, such as AXI-Lite, to transmit the dynamically generated gain scheduling table. Write the data to the specified hardware address on the FPGA. To achieve extremely low latency in the PID control loop, the data writing in this step differs from writing to the BRAM in step S1200; instead, it involves writing the dynamic gain scheduling table. The data is written to dedicated hardware registers within the FPGA or directly mapped to the on-chip LUT memory area. Registers or LUTs are chosen because the FPGA's servo control logic, such as the multiplier in the PID unit, requires low-latency or single-cycle access to these gain parameters. Therefore, the output ports of these registers or LUTs are directly connected to the data path input of the PID algorithm via hard connections, ensuring the real-time and synchronous nature of control signal updates.

[0068] After the ultra-low latency hardware mapping is completed, the FPGA's PID controller is instantiated from a fixed-gain unit to a dynamic-gain PID hardware unit. The execution process of this dynamic-gain PID hardware unit is as follows:

[0069] ;

[0070] in, This represents the PID control output, which is the output of the FPGA during the current servo cycle. The final control signal calculated internally is used to directly drive the servo motor or actuator of the robot's end effector to perform motion and actively suppress micro-vibrations; The discrete-time index representing the servo cycle, with a step size of two adjacent servo cycles. The time interval between these intervals is used to define the time base of the entire real-time control system; This represents the real-time state vector, which is the state vector of the FPGA in the current servo cycle. The hardware-integrated function used to query the dynamic gain scheduling table. The index vector includes the current servo cycle of the FPGA in step S1200. Collected state vectors For example, the current servo cycle Real-time speed, real-time acceleration, and AI-predicted next servo cycle. Predicted value of micro-vibration state ; Indicates the current servo cycle The real-time tracking error is the error of the FPGA in the current servo cycle. The positional deviation is calculated in real time, in millimeters or radians, and is used to quantify the difference between the current state and the desired state. The integral term representing the error is the accumulator inside the FPGA that tracks historical real-time tracking errors. The result of discrete accumulation is used to quantify the cumulative steady-state error of the system; The differential term representing the error is the result of the FPGA's internal differential converter taking into account the current real-time tracking error. Tracking error compared to the previous cycle Discrete difference calculations are performed to predict the trend of error changes, thereby providing damping to suppress system oscillations; The dynamic PID gain coefficients are all derived from the dynamic gain scheduling table. In the current servo cycle The value is obtained through instantaneous calculation or table lookup, and its value varies with the real-time state vector. A scalar value that changes in real time.

[0071] This represents the dynamic proportional gain coefficient, used to determine the PID controller's response to the current real-time tracking error. The response intensity; This represents the dynamic integral gain coefficient, used to determine the PID controller's response to accumulated errors. Elimination speed to eliminate steady-state error; This represents the dynamic differential gain coefficient, used to determine the PID controller's response to future error changes. The response strength, which is based on the vibration prediction of the AI, i.e., the next servo cycle. Predicted value of micro-vibration state Dynamic adjustments are made to achieve predictive damping.

[0072] Through the aforementioned dynamic gain scheduling mechanism, the PID controller can achieve high performance in each servo cycle. It can instantly adjust the three dynamic PID gain coefficients to achieve hardware-level linkage between AI prediction and real-time control logic.

[0073] The S2000 utilizes FPGA hardware logic units to achieve ultra-high sampling rates. Concurrently acquire raw physical signals, and use the FPGA's hardware digital signal processing pipeline to perform real-time filtering and differential processing on the acquired raw physical signals to obtain a state sequence, which is then combined with historical control outputs. and target position value Calculate and output the input state vector Real-time tracking error and scheduler base state vector Digital status data packets.

[0074] Specifically, this step aims to address the physical bottleneck of traditional MCUs, which are limited by the Nyquist sampling rule and bus delays, preventing them from sensing the high-frequency micro-vibrations described in the technical problem. The goal is to leverage the hardware parallelism of an FPGA to process raw physical signals from multiple sensors on the end effector in real-time and concurrently into digitally synchronized state data packets with strictly synchronized timestamps required for subsequent steps. This bypasses the MCU's data path, laying the data foundation for microsecond-level predictive suppression.

[0075] Further, step S2000 includes:

[0076] Step S2100, based on the preset ultra-high sampling rate By utilizing the dedicated hardware interface and hardware parallelism of the FPGA, the servo cycle of the same high-frequency sampling clock can be achieved. The system concurrently samples the original physical signals, including the original vibration signal, the original position signal, and the original current signal, to generate digital acceleration sample values. Digital position count value and digital current sampling value digital sampling sequence .

[0077] Specifically, this step aims to utilize the dedicated I / O units and hardware parallelism of the FPGA to perform ultra-high frequency sampling on the input raw physical signal, far exceeding the requirements of Faster-Than-Nyquist (FTN) sampling, and output a distortion-free, strictly timestamped digital sampling sequence. The goal is to achieve an ultra-high sampling rate far exceeding the high-frequency micro-vibration frequency described in the technical problem. Concurrent data acquisition is performed to ensure that the real physical waveform of high-frequency micro-vibrations is captured with high fidelity, avoiding signal aliasing caused by traditional low-speed sampling.

[0078] The original physical signals specifically include the original vibration signals from the accelerometer, the original position signals from the motor encoder, and the original current signals from the motor phase currents.

[0079] In the specific implementation, the FPGA uses its high-speed analog-to-digital converter (ADC) interface or serial interface, such as I2S or SPI, at a preset ultra-high sampling rate. The servo cycle is obtained by performing an instantaneous sampling and quantization conversion on the raw vibration signal of the accelerometer over a continuous time period. Corresponding digital acceleration sample value .in, The discrete-time index representing the high-frequency sampling clock, i.e., the servo period, is used to define the ultra-high sampling rate. The time base.

[0080] In parallel, the FPGA continuously decodes and counts the raw position signals of the motor encoder over continuous time using its internal dedicated Quadrature Encoder Interface (QEI) hardware unit, and performs this decoding at a preset ultra-high sampling rate. Take a snapshot to obtain the servo cycle. Corresponding digital position count value This ensures strict time synchronization between position data and acceleration data, i.e., digital position count values. and digital acceleration sample values .

[0081] In parallel, the FPGA utilizes its high-speed analog-to-digital converter interface to achieve a preset ultra-high sampling rate. The servo cycle is obtained by performing an instantaneous sampling and quantization conversion on the raw current signal of the motor phase current over a continuous time period. Corresponding digital current sampling value This ensures the accuracy of current data, i.e., digital current sample values. Strict temporal synchronization with acceleration and position data.

[0082] In summary, the above process is a hardware concurrent sampling process. This process utilizes the FPGA's dedicated hardware interfaces, such as high-speed analog-to-digital converter interfaces and quadrature encoder interfaces, to achieve sampling within the same high-frequency sampling clock time index. It concurrently samples, analyzes, and digitizes continuous raw physical signals from sensors. The final output is a set of raw digital sequences with strictly synchronized timestamps. That is, the digital sampling sequence, which constitutes the servo cycle. A snapshot of the system's physical state.

[0083] Step S2200: The digital sampling sequence is subjected to parallel real-time filtering using the FPGA's hardware digital signal processing pipeline to obtain the digital acceleration value. Location estimate and digital current value and the estimated position value Perform hardware real-time differential to obtain derived speed values Combine and output the state sequence.

[0084] Specifically, this step aims to utilize the hardware-embedded digital signal processing (DSP) pipeline within the FPGA to perform deterministic real-time preprocessing on the digital sampling sequence output from step S2100. The goal is to instantaneously convert the noisy digital sampling sequence into a high-fidelity state sequence and derive advanced state information in parallel. This ensures that the input data acquired by the computational core in subsequent steps is low-distortion, low-latency, and complete.

[0085] In the specific implementation process, this step utilizes the parallel capabilities of the FPGA to configure a dedicated hardware filter pipeline for each signal stream in the original digital sequence. Digital acceleration sampling values. and digital current sampling value The signal stream flows in parallel through a hardware digital filter pipeline, implemented in the hardware digital signal processing DSP and embedded within the FPGA, for real-time noise reduction, such as an FIR filter. The FIR filtering process utilizes the DSP logic, hardware coefficients, and stored historical sample values ​​embedded within the FPGA to process the acquired digital acceleration sample values. and digital current sampling value It performs real-time weighted summation, i.e., FIR filtering. The purpose of this hardware filter pipeline is to instantaneously convert the noisy raw digital sequence into a high-fidelity signal stream, i.e., digital acceleration values. and digital current value This provides lossless, high-quality input data for subsequent steps.

[0086] While the above filtering process is being executed in parallel, the digital position count value... The signal stream flows through a dedicated hardware position filter, such as a Kalman filter or low-pass filter embedded in the FPGA logic, to obtain a high-fidelity position estimate. .

[0087] Obtaining high-fidelity position estimates Subsequently, the hardware differentialr pipeline embedded within the FPGA immediately performs real-time differential analysis. The real-time differential analysis process involves: acquiring the current servo cycle... Location estimate Subtract the previous servo cycle held by the register. Location estimate This yields the position change over a sampling period. Subsequently, this position change is multiplied by the ultra-high sampling rate, which serves as the time scale. Thus, in the same servo cycle Instantaneous calculation of the physical servo cycle Derived speed value .

[0088] To avoid affecting the derived speed value The noise amplification problem caused by performing a second difference, i.e. ,in, Indicates the servo cycle The derived acceleration value, Indicates the previous servo cycle The derived velocity value. The noise amplification problem is fatal to the prediction accuracy of AI; therefore, in subsequent steps, it is preferable to directly use physically measured digital acceleration values. To replace the derived acceleration value It provides a higher fidelity acceleration state.

[0089] In summary, the above describes the parallel preprocessing process in a hardware pipeline, illustrating how an FPGA utilizes its internally embedded digital signal processing (DSP) logic to filter high-noise digital acceleration sample values. and digital current sampling value These are converted into high-fidelity signals, i.e., digital acceleration values. and digital current value At the same time, it also describes how FPGAs utilize their hardware differentiators to obtain high-fidelity position estimates. Perform a difference operation to generate a high-fidelity derivation speed value with low latency. The final output is a set of high-fidelity, preprocessed and derived, time-synchronized state sequences. .

[0090] Step S2300: Utilizing the FPGA's hardware logic units, based on the state sequence and the previous cycle... Historical control output Combine to generate input state vector Using target location value and location estimates Calculate real-time tracking error and combine digital acceleration values and derived speed value Generate scheduler basic state vector The output time-synchronized includes the input state vector. Real-time tracking error and scheduler base state vector Digital status data packets.

[0091] Specifically, this step aims to leverage the hardware parallelism and internal routing resources of the FPGA to instantaneously construct the state sequence output from step S2200 into a digital state data packet with strictly synchronized timestamps required for subsequent steps. Its purpose is to ensure that within each microsecond-level cycle... Both can perform concurrent computation based on identical and time-synchronized data snapshots, eliminating data latency and timing mismatches in traditional bus architectures from a physical perspective, and laying the foundation for core data paths to achieve high-frequency predictive control.

[0092] In the specific implementation process, this step utilizes the hardware logic units inside the FPGA, such as dedicated register arrays and combinational logic circuits, to index the time of each high-frequency sampling clock. Next, perform the following concurrent operations:

[0093] First, the state sequences after multiple concurrent processing are... and the previous cycle Historical control output Combine them to construct the current servo cycle. Input state vector ,in, Indicates the previous cycle The historical control output is maintained for one cycle by the registers inside the FPGA, which is used to provide control decision information for the previous servo cycle.

[0094] Meanwhile, the hardware subtractor inside the FPGA obtains the current servo cycle. Target position value set by the upper-level planner And subtract the current servo cycle calculated in real time. Location estimate This hardware subtraction operation occurs within the same servo cycle. Completed instantaneously, its output is the servo cycle. Real-time tracking error This error value is the core basis for implementing feedback control.

[0095] Also in the same clock cycle Within the FPGA, the hardware logic unit obtains the current servo cycle calculated in real time. Derivative velocity value and the current servo cycle Digital acceleration values Subsequently, in the same servo cycle These two scalar values, representing the current physical state of the system, are combined into a two-dimensional vector containing velocity and acceleration, which is the servo cycle. Scheduler base state vector .

[0096] Ultimately, the FPGA utilizes its internal high-speed, configurable routing logic to perform parallel fan-out. Specifically, the input state vector... The output register is physically hard-connected to the corresponding input register in subsequent step S3100; simultaneously, error is tracked in real time. and scheduler base state vector Each of the output registers is also physically hard-connected to the corresponding input register in step S3200.

[0097] In summary, the above describes a hardware-parallel state vector construction process. This process describes how the FPGA can perform servo cycles within the same high-frequency sampling clock. Next, utilizing its internal combinational logic and arithmetic unit, it combines multiple high-fidelity status signals from step S2200 and the previous servo cycle. Historical control output and target location value Concurrently combine and calculate to generate time-synchronized digital state data packets. , including the input state vector Real-time tracking error and the scheduler's basic state vector .

[0098] The S3000, within the current servo cycle, utilizes the FPGA to concurrently perform hardware calculations for AI vibration prediction and dynamic PID control, based on the AI ​​vibration prediction model. For the input state vector Calculations are performed to generate the second micro-vibration state prediction. And based on the combined second real-time state vector Query the dynamic gain scheduling table Combined with real-time tracking error Calculate and generate the final PID control output. .

[0099] Specifically, this step aims to leverage the massively parallel computing capabilities of the FPGA to achieve high performance in each microsecond-level servo cycle. Within, based on the digital status data packet output in step S2300, including Real-time tracking error and the scheduler's basic state vector And the AI ​​prediction model weights generated in step S1200 and stored in the Block Random Access Memory (BRAM). The dynamic gain scheduling table stored in the register or LUT in step S1300. It concurrently executes hardware calculations for two core algorithms: AI vibration prediction and dynamic PID control, and fuses the results in real time to ultimately generate the servo cycle. Unified final PID control output It achieves deep hardware-level collaboration between AI prediction and PID gain adjustment, applying precise predictive suppression before micro-vibrations generate significant errors, thereby eradicating the generation of high-frequency micro-vibrations at the physical level.

[0100] Further, step S3000 includes:

[0101] Step S3100: Within the current servo cycle, utilize the AI ​​vibration prediction model instantiated on the FPGA. Based on the weights of the quantified AI prediction model For the input state vector Perform forward propagation hardware calculations to generate the next servo cycle. Second micro-vibration state prediction value .

[0102] Specifically, this step aims to utilize the AI ​​vibration prediction model instantiated within the FPGA in step S1200. In each microsecond-level servo cycle Internally, based on the input state vector fed in parallel in the digital state data packet in step S2300. And the AI ​​prediction model weights loaded in step S1200 and quantized in BRAM This involves performing a high-speed, deterministic forward propagation hardware computation. Its purpose is to concurrently compute the results for the next servo cycle. Second micro-vibration state prediction value .

[0103] In the specific implementation process, during the servo cycle of the current high-frequency sampling clock Below, an AI vibration prediction model is implemented in the FPGA hardware. With input state vector As real-time input, it rapidly calls the AI ​​prediction model weights stored in BRAM. Perform a complete forward propagation hardware computation in the current servo cycle. Before ending, calculate and output the parameters for the next servo cycle. Second micro-vibration state prediction value The forward propagation hardware computation process and the dynamic PID control in the subsequent step S3200 are executed in complete parallel within the FPGA, ensuring that both are completed within the same microsecond-level servo cycle. Each component completes its respective computational task.

[0104] Step S3200: Within the current servo cycle, the predicted value of the second micro-vibration state is... and scheduler base state vector Combined into a second real-time state vector And using the second real-time state vector Real-time query of dynamic gain scheduling table To obtain the second dynamic PID gain coefficient, combined with the real-time tracking error. Calculate the final PID control output .

[0105] Specifically, this step aims to achieve this in every microsecond-level servo cycle. Internally, the AI ​​prediction information concurrently output from step S3100 is fused in real time using FPGA, namely the second micro-vibration state prediction value. The real-time tracking error fed in parallel with the digital status data packet in step S2300 and scheduler base state vector And by querying the dynamic gain scheduling table instantiated in step S1300. The second dynamic PID gain coefficient is calculated instantaneously, and the current servo cycle is finally generated. Unified final PID control output The aim is to directly translate the predictive capabilities of AI into the action adjustments of the PID controller, thereby achieving predictive damping and effectively suppressing high-frequency micro-vibrations.

[0106] In the specific implementation, this step is executed by the dynamic PID hardware logic embedded within the FPGA, and this process is completely parallel to the AI ​​vibration prediction in step S3100 mentioned above. This dynamic PID hardware logic will schedule the scheduler's basic state vector... and concurrently acquired second micro-vibration state prediction values Instantaneous combination constructs a complete, second real-time state vector for gain scheduling. .

[0107] Next, using this second real-time state vector As an address or index, it allows for low-latency lookups of the hardware-based dynamic gain scheduling table. This allows for the instantaneous acquisition of the current servo cycle. A set of second dynamic PID gain coefficients .in, Indicates the servo cycle The second dynamic proportional gain coefficient; Indicates the servo cycle The second dynamic integral gain coefficient; Indicates the servo cycle The second dynamic differential gain coefficient.

[0108] Using the obtained second dynamic PID gain coefficient Real-time tracking error acquired concurrently The current servo cycle is calculated using three hardware-based arithmetic units: a proportional gain, an integral accumulator, and a differential difference unit. The final PID control output .

[0109] The S4000 utilizes the hardware arithmetic logic unit within the FPGA to output the final PID control. Convert to digital duty cycle instruction The PWM is generated by a dedicated hardware PWM generator inside the FPGA based on the digital duty cycle instruction. Real-time generation of physical electrical signals This completes the full hardware servo closed loop for AI edge computing.

[0110] Specifically, this step aims to utilize a dedicated hardware output module within the FPGA, such as a Pulse Width Modulation (PWM) generator, to convert the digital control instructions calculated in step S3200, i.e., the final PID control output, into a digital control output. Instantly converted into physical electrical signals that can directly drive the motor power stage. The purpose is to ensure that the entire "perception-prediction-decision-execution" control loop, from perception in step S2000 to execution in step S4000, is completely within the FPGA hardware, using an ultra-high sampling rate. The system operates by completely eliminating any delays caused by external bus communication or software processing, providing hardware execution assurance for the effective suppression of high-frequency micro-vibrations.

[0111] Further, step S4000 includes:

[0112] Step S4100: Utilize the hardware arithmetic logic unit within the FPGA to process the final PID control output. Perform hardware scaling operations to calculate and generate digital duty cycle instructions. .

[0113] Specifically, this step aims to utilize the hardware arithmetic logic unit inside the FPGA to process the final PID control output from step S3200. Instantly converts into the digital duty cycle instruction required by the PWM generator in the subsequent step S4200. The purpose is to ensure a seamless data flow of control signals from decision-making to execution within the FPGA, maintaining the low latency characteristics of the entire hardware closed loop.

[0114] In the specific implementation, the hardware arithmetic logic unit inside the FPGA, such as the ALU, dedicated multiplier, adder, or lookup table, controls the final PID output of the input. Perform a hardware-level scaling transformation or mapping operation, thus achieving the same cycle. Instantaneous calculation of the digital duty cycle instruction used to drive the PWM generator .

[0115] This operation is performed by a hardware-based scaling transformation function embedded in the FPGA logic. The implementation, its function is to output the final PID control. The physical units, such as volts or amperes, are linearly or non-linearly mapped to a range of representations of the PWM duty cycle, such as a normalized value from 0 to 1 or a fixed-point representation from 0 to the PWM counter period value.

[0116] Step S4200: Utilize the dedicated hardware PWM generator within the FPGA, based on the digital duty cycle instruction... and the preset PWM switching frequency Real-time generation of physical electrical signals This completes the full hardware servo closed loop for AI edge computing.

[0117] Specifically, this step aims to utilize the dedicated, high-precision hardware PWM generator within the FPGA to generate the digital duty cycle instruction output in step S4100. Instantly converted into a physical electrical signal that can directly drive an external power circuit. The goal is to completely eliminate latency in the execution phase by fully integrating PWM generation into a high-speed hardware closed loop within the FPGA, thereby ensuring the ultimate realization of ultra-high bandwidth in the entire "sensing-prediction-decision-execution" process.

[0118] In the specific implementation, the FPGA's internal dedicated, high-precision hardware PWM generator generates the PWM according to the digital duty cycle instructions. and the preset PWM switching frequency Real-time generation of high-frequency PWM pulse sequences, i.e., physical electrical signals. This process is automatically completed by a dedicated PWM hardware peripheral within the FPGA, requiring no additional computing resources or software intervention. The physical electrical signal... Then, the output is directly sent to the external power drive circuit through the FPGA's I / O pins, completing the low-latency conversion from digital control commands to physical drives.

[0119] Specifically, this step, along with the sensing in step S2000 and the calculation in step S3000, works in tandem to construct a complete, all-hardware FPGA internal servo closed loop. This closed loop executes the entire "sensing-prediction-decision-execution" servo loop process in a pipelined manner within the FPGA hardware, achieving ultra-high control bandwidth. The entire loop runs completely within the hardware in a closed loop, without any external bus communication or software intervention. Therefore, the operating frequency of the control loop can far exceed the control bottleneck of a few kHz caused by the limitations of traditional MCUs due to bus bandwidth, operating system scheduling, and interrupt latency.

[0120] This hardware-level high-bandwidth servo closed-loop system, equipped with AI predictive capabilities, can respond in real time and effectively suppress the high-frequency micro-vibrations described in the technical issues. For example, in industrial quality inspection scenarios, the robot's end effector can achieve immediate stopping and stabilization, significantly reducing the time lost waiting for vibration to stabilize and improving the work cycle. In plant factory scenarios, the robotic gripper can maintain extremely high stability control when contacting flexible targets, such as strawberries, effectively avoiding target damage and grasping failure caused by end-effector tremors.

[0121] Example 2

[0122] This embodiment, based on Embodiment 1, provides an AI edge computing system based on FPGA and MCU, such as... Figure 2 As shown, the system includes a system heterogeneous configuration module, a state-aware distribution module, a parallel computation module, and a hardware output module.

[0123] The system heterogeneous configuration module is used to parse macroscopic task instructions issued by the upper-level robot main control using the MCU. Generate an AI-integrated vibration prediction model and dynamic gain scheduling table Composite control strategy package The composite control strategy package Loaded onto the FPGA, utilizing the AI ​​vibration prediction model Generate micro-vibration state prediction values Based on the predicted value of the micro-vibration state and the dynamic gain scheduling table Output PID control output .

[0124] The state-aware distribution module is used to utilize the hardware logic units of the FPGA at an ultra-high sampling rate. Concurrently acquire raw physical signals, and use the FPGA's hardware digital signal processing pipeline to perform real-time filtering and differential processing on the acquired raw physical signals to obtain a state sequence, which is then combined with historical control outputs. and target position value Calculate and output the input state vector Real-time tracking error and scheduler base state vector Digital status data packets.

[0125] The parallel calculation module is used to concurrently perform hardware calculations for AI vibration prediction and dynamic PID control using the FPGA within the current servo cycle, based on the AI ​​vibration prediction model. For the input state vector Calculations are performed to generate the second micro-vibration state prediction. And based on the combined second real-time state vector Query the dynamic gain scheduling table Combined with real-time tracking error Calculate and generate the final PID control output. .

[0126] The hardware output module is used to output the final PID control using the hardware arithmetic logic unit inside the FPGA. Convert to digital duty cycle instruction The PWM is generated by a dedicated hardware PWM generator inside the FPGA based on the digital duty cycle instruction. Real-time generation of physical electrical signals This completes the full hardware servo closed loop for AI edge computing.

[0127] The parts of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of corresponding technical solutions in the prior art have not been described in detail to avoid excessive elaboration.

[0128] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An AI edge computing method based on FPGA and MCU, characterized in that, include: The MCU parses the macro-level task instructions issued by the upper-level robot master control, generates a composite control strategy package containing an AI vibration prediction model and a dynamic gain scheduling table, loads the composite control strategy package onto the FPGA, uses the AI ​​vibration prediction model to generate micro-vibration state prediction values, and outputs PID control output based on the micro-vibration state prediction values ​​and the dynamic gain scheduling table. The raw physical signals are acquired concurrently at an ultra-high sampling rate using the hardware logic unit of the FPGA. The acquired raw physical signals are filtered and differentially processed in real time through the hardware digital signal processing pipeline of the FPGA to obtain the state sequence. Combined with historical control output and target position value, a digital state data packet including the input state vector, real-time tracking error and scheduler basic state vector is calculated and output. Within the current servo cycle, the hardware calculation of AI vibration prediction and dynamic PID control is performed concurrently by the FPGA. The AI ​​vibration prediction model calculates the input state vector to generate the second micro-vibration state prediction value. Based on the combined second real-time state vector, the dynamic gain scheduling table is queried. Combined with the real-time tracking error, the final PID control output is calculated and generated. The final PID control output is converted into a digital duty cycle instruction by the hardware arithmetic logic unit inside the FPGA, and the hardware PWM generator inside the FPGA generates physical electrical signals in real time according to the digital duty cycle instruction, thus completing the full hardware servo closed loop of the AI ​​edge computing.

2. The AI ​​edge computing method based on FPGA and MCU according to claim 1, characterized in that, The method for outputting PID control output includes: The macroscopic task instructions issued by the upper-level robot master controller are analyzed, dynamic influencing factors are extracted to generate a vibration feature profile, and based on the vibration feature profile and task accuracy requirements, a composite control strategy package is decided and generated; the macroscopic task instructions include target pose, motion velocity curve, end-effector load mass and task accuracy requirements. The weight data packet of the AI ​​vibration prediction model is quantized using an MCU to generate quantized AI prediction model weights. The quantized AI prediction model weights are then written into the on-chip memory of the FPGA at high speed to complete hardware instantiation. Based on the state vector of the current servo cycle, the micro-vibration state prediction value for the next servo cycle is calculated and generated. The state vector includes a set of physical state data collected in real time by the FPGA from its sensor interface during the servo cycle, including the motor position, motor speed, motor current, and control output of the previous cycle. The dynamic gain scheduling table is written into the FPGA's access memory area. Based on the real-time state vector composed of the micro-vibration state prediction value and the state vector, the dynamic PID gain coefficient is queried and obtained using the dynamic gain scheduling table. Combined with the real-time tracking error, the PID control output is output.

3. The AI ​​edge computing method based on FPGA and MCU according to claim 2, characterized in that, The dynamic influencing factors include the motion velocity curve and the end load mass; The motion velocity curve is analyzed to extract instantaneous dynamic parameters, including peak acceleration and peak jerk. The peak acceleration is the maximum absolute value of acceleration extracted by the MCU from the entire motion curve described by the motion velocity curve; the peak jerk is the maximum absolute value of the rate of change of acceleration extracted by the MCU from the motion velocity curve.

4. The AI ​​edge computing method based on FPGA and MCU according to claim 1, characterized in that, The method for outputting the digital status data packet includes: Based on the preset ultra-high sampling rate, the hardware interface and hardware parallelism of the FPGA are used to concurrently sample the original physical signals containing the original vibration signal, the original position signal and the original current signal under the time index of the same high frequency sampling clock, and generate a digital sampling sequence including digital acceleration sampling value, digital position count value and digital current sampling value. The digital sampling sequence is filtered in parallel in real time using the hardware digital signal processing pipeline of FPGA to obtain digital acceleration value, position estimate value and digital current value, and hardware real-time differential is performed on the position estimate value to obtain derived velocity value, which is then combined and output as a state sequence. Using the hardware logic units of the FPGA, an input state vector is generated based on the state sequence and the historical control output of the previous cycle. The real-time tracking error is calculated using the target position value and the position estimate. The scheduler's basic state vector is generated by combining the digital acceleration value and the derived velocity value. The output is a time-synchronized digital state data packet containing the input state vector, the real-time tracking error, and the scheduler's basic state vector.

5. The AI ​​edge computing method based on FPGA and MCU according to claim 4, characterized in that, The method for obtaining the derived speed value is as follows: the hardware differentiator pipeline embedded inside the FPGA immediately performs real-time differential on the obtained position estimate. The real-time differential refers to obtaining the position estimate of the current servo cycle, subtracting the position estimate of the previous servo cycle held by the register, obtaining the position change within a sampling period, and multiplying the position change by the ultra-high sampling rate used as the time scale to calculate the derived velocity value.

6. The AI ​​edge computing method based on FPGA and MCU according to claim 1, characterized in that, The method for generating the final PID control output includes: Within the current servo cycle, using the AI ​​vibration prediction model instantiated on the FPGA, and based on the quantized AI prediction model weights, the input state vector is forward-propagated in hardware calculation to generate the second micro-vibration state prediction value for the next servo cycle. Within the current servo cycle, the second micro-vibration state prediction value and the scheduler's basic state vector are combined into a second real-time state vector. The second real-time state vector is then used to query the dynamic gain scheduling table in real time to obtain the second dynamic PID gain coefficient. Finally, the PID control output is calculated by combining the real-time tracking error.

7. The AI ​​edge computing method based on FPGA and MCU according to claim 1, characterized in that, The method for generating the physical electrical signal includes: Using the hardware arithmetic logic unit inside the FPGA, hardware scaling transformation is performed on the final PID control output to calculate and generate digital duty cycle instructions. By utilizing the hardware PWM generator inside the FPGA, physical electrical signals are generated in real time based on digital duty cycle instructions and preset PWM switching frequencies, thus completing a fully hardware servo closed loop for AI edge computing.

8. An AI edge computing system based on FPGA and MCU, used to implement the AI ​​edge computing method based on FPGA and MCU as described in any one of claims 1-7, characterized in that, The system includes a system heterogeneous configuration module, a state-aware distribution module, a parallel computation module, and a hardware output module; The system heterogeneous configuration module is used to parse the macro-level task instructions issued by the upper-level robot master control using the MCU, generate a composite control strategy package containing an AI vibration prediction model and a dynamic gain scheduling table, load the composite control strategy package onto the FPGA, generate micro-vibration state prediction values ​​using the AI ​​vibration prediction model, and output PID control output based on the micro-vibration state prediction values ​​and the dynamic gain scheduling table. The state-aware distribution module is used to concurrently acquire raw physical signals at an ultra-high sampling rate using the hardware logic unit of the FPGA, and to perform real-time filtering and differential processing on the acquired raw physical signals through the hardware digital signal processing pipeline of the FPGA to obtain a state sequence. Combining historical control outputs and target position values, it calculates and outputs a digital state data packet including the input state vector, real-time tracking error and scheduler basic state vector. The parallel calculation module is used to concurrently perform hardware calculations of AI vibration prediction and dynamic PID control using FPGA within the current servo cycle. The AI ​​vibration prediction model calculates the input state vector to generate the second micro-vibration state prediction value, and based on the combined second real-time state vector, queries the dynamic gain scheduling table, and calculates and generates the final PID control output by combining the real-time tracking error. The hardware output module is used to convert the final PID control output into a digital duty cycle instruction using the hardware arithmetic logic unit inside the FPGA, and the hardware PWM generator inside the FPGA generates physical electrical signals in real time according to the digital duty cycle instruction, thus completing the full hardware servo closed loop of AI edge computing.

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