Chip control method and device, electronic equipment, chip and storage medium

Abstract

The invention provides a chip control method and device, electronic equipment, a chip and a storage medium, and relates to the field of chips.The method comprises the steps that according to a target operator scheduled and executed in the chip, a memory scheduling strategy associated with the target operator is determined; wherein the memory scheduling strategy is used for indicating a running time period of a memory unit in the chip in at least one power consumption mode, and the running time period is associated with an access time period of the memory unit when the target operator is executed; and scheduling the memory unit based on the memory scheduling strategy to enable the memory unit to enter a corresponding power consumption mode in the operation period. Therefore, the memory unit can maintain the non-low power consumption mode in the memory access time window required for executing the target operator and automatically enter the low power consumption mode in the other time periods, the electric leakage loss in the idle time period is remarkably reduced, meanwhile, the additional energy consumption caused by frequent full-amount wakeup is avoided, the energy efficiency ratio of the memory unit can be effectively improved, and the user experience is improved. And the adaptive capability of the chip under the dynamic load is enhanced.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip control method, apparatus, electronic device, chip, and storage medium. Background Technology

[0002] In integrated circuit design, memory cells, as key modules within a chip, typically exist as independent functional units with fixed power management mechanisms and operational state control logic. In related technologies, memory cells often employ static power management, where their operating state is determined by preset, fixed timing strategies, lacking the ability to perceive actual workload. This results in memory cells potentially maintaining high power consumption during inactive periods, or experiencing performance degradation due to wake-up delays when access is needed, causing unnecessary static and dynamic power consumption and hindering improvements in the overall energy efficiency of the chip. Summary of the Invention

[0003] This application proposes a chip control method, apparatus, electronic device, chip, and storage medium to at least partially solve one of the technical problems in the related art.

[0004] One embodiment of this application proposes a chip control method, including: Based on the target operator scheduled for execution in the chip, a memory scheduling policy associated with the target operator is determined; wherein, the memory scheduling policy is used to indicate the runtime segment of the memory unit in the chip in at least one power consumption mode, the runtime segment being associated with the access period of the memory unit when the target operator is executed; The memory unit is scheduled based on the memory scheduling policy so that the memory unit enters the corresponding power consumption mode during the runtime.

[0005] Another embodiment of this application proposes a chip control device, including: The first determining module is configured to determine a memory scheduling strategy associated with the target operator based on the target operator scheduled to be executed in the chip; wherein the memory scheduling strategy is configured to indicate the runtime segment of the memory unit in the chip in at least one power consumption mode, and the runtime segment is associated with the access period of the memory unit when the target operator is executed; The scheduling module is used to schedule the memory unit based on the memory scheduling policy, so that the memory unit enters the corresponding power consumption mode during the runtime.

[0006] Another embodiment of this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the chip control method as described in the foregoing aspect.

[0007] Another aspect of this application provides a chip including an interface circuit and a processing circuit coupled to each other, the interface circuit being used to input or output signals, and the processing circuit being configured to perform the chip control method as described in the foregoing aspect.

[0008] In another aspect of this application, a non-transitory computer-readable storage medium is provided, on which computer program instructions are stored, which, when executed by a processor, implement the chip control method as described in the foregoing aspect.

[0009] Another aspect of this application provides a computer program product having a computer program stored thereon, which, when executed by a processor, implements the chip control method as described in the foregoing aspect.

[0010] The chip control method, apparatus, electronic device, chip, and storage medium proposed in this application determine the associated memory scheduling strategy based on the target operator scheduled for execution in the chip, and dynamically schedule memory units based on the memory scheduling strategy. Since the execution characteristics of the target operator (such as data access mode, lifecycle, etc.) directly determine the memory access requirements, by establishing a semantic association between "operator-memory", the active and inactive periods of memory units can be accurately predicted. The memory scheduling strategy is used to indicate the runtime of the memory unit in at least one power mode (such as low-power mode and non-low-power mode) when executing the target operator (which can indirectly indicate the activation timing and switching sequence of at least one power mode), so that the memory unit maintains a non-low-power mode during the memory access time window required when executing the target operator, and automatically enters a low-power mode during other periods. As a result, memory state management has transformed from the traditional passive and static mode to an active, task-driven fine-grained control, significantly reducing leakage current loss during idle periods and avoiding additional energy consumption caused by frequent full wake-ups. This can effectively improve the energy efficiency ratio of memory units and enhance the chip's adaptability under dynamic loads, making it particularly suitable for high-throughput, low-latency computationally intensive scenarios such as artificial intelligence (AI) inference and real-time signal processing.

[0011] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0012] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic flowchart of a chip control method provided for an exemplary embodiment of this application; Figure 2 A schematic flowchart of another chip control method provided for an exemplary embodiment of this application; Figure 3 A schematic flowchart illustrating yet another chip control method provided for an exemplary embodiment of this application; Figure 4 A schematic diagram illustrating the computational process of a dot product operator provided for an exemplary embodiment of this application; Figure 5 A schematic diagram of a computing task carried by a PE provided for an exemplary embodiment of this application; Figure 6 A schematic diagram illustrating the data flow process during PE operation, provided as an exemplary embodiment of this application; Figure 7 A schematic diagram of the structure of an AI computing memory chip provided for an exemplary embodiment of this application; Figure 8 A schematic diagram of a memory access model corresponding to a dot product operator provided for an exemplary embodiment of this application; Figure 9 A schematic diagram of a memory scheduling strategy corresponding to a dot product operator provided for an exemplary embodiment of this application; Figure 10 A schematic flowchart of another chip control method provided for an exemplary embodiment of this application; Figure 11 A schematic diagram of the structure of a chip control device provided for an exemplary embodiment of this application; Figure 12 A schematic diagram of the structure of an electronic device provided for an exemplary embodiment of this application; Figure 13 This is a schematic diagram of the structure of a chip proposed in an exemplary embodiment of this application. Detailed Implementation

[0013] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0014] In embedded devices, memory units are the primary source of power consumption. To reduce power consumption and improve energy efficiency, dynamic power management technology has become a research hotspot in both academia and industry.

[0015] In related technologies, low-power solutions for memory cells mainly rely on low-frequency hardware counting: by setting a fixed upper limit for counting, the memory cell starts counting when it meets the low-power conditions, and when the count value reaches the set upper limit, the memory cell switches states and enters a low-power state. Taking memory cells including Low Power Double Data Rate SDRAM (Synchronous Dynamic Random Access Memory) (LPDDR) as an example, the state switching of the chips and the idle control of the Double Data Rate Synchronous Dynamic Random Access Memory (DDR) physical layer interface (DDRPHY Interface, DFI) all rely on this low-frequency counting scheme. The memory cell configures the idle duration of the command channel through a reserved timing parameter register t_powerdown. When the memory cell, such as Dynamic Random Access Memory (DRAM), is idle within this duration, it will automatically enter the powerdown (power-down) low-power state.

[0016] Since the memory unit is an independent module, it maintains its own state independently and does not dynamically adjust according to business needs. This leads to the following two typical drawbacks in the above solution: Power consumption issue: When service access stops, the memory unit does not immediately switch to a low-power state; instead, it waits for the hardware counter to reach a pre-set upper limit. During this process, the memory unit remains in a relatively high-power operating state, resulting in unnecessary power consumption. For example, in an intermittently operating embedded device, there may be a long idle period after service processing, but because the hardware counter has not reached its upper limit, the memory unit cannot enter a low-power state in time, continuously consuming power.

[0017] Performance Loss Issue: When a memory unit enters a low-power state, it only exits this state when real-time business requests arrive. However, exiting a low-power state takes time, and during this period, some refresh commands may not be sent in time. After exiting the low-power state, these unsent refresh commands still need to be processed, which slows down the memory unit's response speed and impacts the overall system performance. For example, in real-time systems requiring rapid response, the delay in exiting the low-power state and the time spent processing unsent refresh commands may prevent the system from processing business requests promptly, affecting normal system operation.

[0018] Therefore, in view of at least one of the problems existing in the above-mentioned related technologies, this application proposes a chip control method, apparatus, electronic device, chip and storage medium.

[0019] The following description, with reference to the accompanying drawings, describes a chip control method, apparatus, electronic device, chip, and storage medium according to embodiments of this application.

[0020] Figure 1 This is a schematic flowchart of a chip control method provided for an exemplary embodiment of this application.

[0021] It should be noted that the chip control method of this application embodiment can be applied to a chip control device. In some possible embodiments, the chip control device can be configured in an electronic device or a chip so that the electronic device or chip can perform chip control functions. Additionally, in some possible embodiments, the chip control device can also be software in an electronic device.

[0022] In any embodiment of this application, the chip can be integrated into an electronic device. The chip includes a Central Processing Unit (CPU), an Image Signal Processing (ISP), an Application-Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Field-Programmable Gate Array (FPGA), a System-on-Chip (SOC), a Reduced Instruction Set Computer (RISC), etc., which will not be listed here.

[0023] The electronic devices mentioned include, but are not limited to, terminals and personal computers. A terminal is a user-side entity used to receive or transmit signals, such as a mobile phone. Terminals can also be called terminal equipment, user equipment (UE), mobile station (MS), mobile terminal equipment (MT), etc. Terminals can be communication-enabled vehicles, smart cars, mobile phones, wearable devices, tablets, computers with wireless transceiver capabilities, virtual reality (VR) terminals, augmented reality (AR) terminals, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc. The embodiments of this application do not limit the specific technology or device form used in the terminal.

[0024] like Figure 1 As shown, the chip control method may include the following steps S101 to S102: Step S101: Determine the memory scheduling strategy associated with the target operator based on the target operator scheduled to be executed in the chip; wherein, the memory scheduling strategy is used to indicate the runtime of the memory unit in the chip in at least one power consumption mode, and the runtime is associated with the access period of the memory unit when the target operator is executed.

[0025] The target operator is associated with the task executed by the chip; the target operators associated with different tasks may be the same or different, and this application embodiment does not limit this.

[0026] The target operators include, but are not limited to: embedding, root mean square normalization (RMSNorm), quantization, dequantization, addition / multiplication, activation functions, etc.

[0027] The memory units include, but are not limited to, DRAM. DRAM includes, but is not limited to, DDR, LPDDR, Graphics Double Data Rate Synchronous Dynamic Random Access Memory (GDDR), High Bandwidth Memory (HBM), etc.

[0028] The memory access behavior and access periods of the chip can differ when executing different target operators. Therefore, the memory scheduling strategies associated with different target operators can be different. The memory scheduling strategy associated with each target operator indicates the runtime of the memory unit in at least one power mode when executing that target operator. The runtime of each power mode is associated with the memory access period of the memory unit when the chip executes that target operator.

[0029] Among them, power consumption modes include, but are not limited to: low power consumption mode and non-low power consumption mode.

[0030] In this embodiment, a memory scheduling strategy associated with the target operator can be determined based on the target operator scheduled to be executed in the chip.

[0031] For example, the memory scheduling strategy associated with the target operator can be determined before the chip schedules the execution of the target operator.

[0032] For example, when the chip schedules the execution of a target operator, the memory scheduling strategy associated with that target operator can be determined.

[0033] For example, the memory scheduling strategy associated with the target operator can be determined during the chip scheduling execution of the target operator.

[0034] Step S102: Schedule memory units based on memory scheduling strategy so that memory units enter the corresponding power consumption mode during runtime.

[0035] In the embodiments of this application, memory units can be dynamically scheduled based on a memory scheduling strategy associated with the target operator, so that the memory units enter the power consumption mode corresponding to the runtime segment indicated by the memory scheduling strategy.

[0036] The chip control method of this application determines the associated memory scheduling strategy based on the target operator scheduled for execution in the chip, and dynamically schedules memory units based on the memory scheduling strategy. Since the execution characteristics of the target operator (such as data access mode, lifecycle, etc.) directly determine the memory access requirements, by establishing a semantic association between "operator-memory", the active and inactive periods of memory units can be accurately predicted. The memory scheduling strategy is used to indicate the runtime of the memory unit in at least one power mode (such as low-power mode, non-low-power mode) when executing the target operator (which can indirectly indicate the activation timing and switching sequence of at least one power mode), so that the memory unit maintains a non-low-power mode during the memory access time window required when executing the target operator, and automatically enters a low-power mode during other periods. As a result, memory state management has shifted from the traditional passive and static mode to an active, task-driven fine-grained control, significantly reducing leakage current loss during idle periods and avoiding additional energy consumption caused by frequent full wake-ups. This can effectively improve the energy efficiency ratio of memory units and enhance the chip's adaptability under dynamic loads, making it particularly suitable for computationally intensive scenarios with high throughput and low latency, such as AI inference and real-time signal processing.

[0037] As one possible implementation method, Figure 2 A schematic flowchart of another chip control method provided for an exemplary embodiment of this application.

[0038] It should be noted that the chip control method can be executed alone, or it can be executed together with any embodiment of this application or any possible implementation in the embodiment, or it can be executed together with any technical solution in the related technology. The embodiments of this application do not limit this.

[0039] like Figure 2 As shown, the chip control method may include the following steps S201 to S203: Step S201: Determine the memory scheduling strategy associated with the target operator based on the target operator scheduled to be executed in the chip; wherein, the memory scheduling strategy is used to indicate the runtime of the memory unit in the chip in at least one power consumption mode, and the runtime is associated with the access period of the memory unit when the target operator is executed.

[0040] It should be noted that the explanation of step S201 can be found in the relevant description in any embodiment of this application, and will not be repeated here.

[0041] Step S202: The target operator is scheduled to multiple processing units in the chip so that the multiple processing units can perform parallel processing on the input data input to each processing unit based on the target operator.

[0042] Input data refers to the data currently input to the processing unit (Process Engine, or PE). The input data differs for different processing units.

[0043] The input data of multiple processing units is obtained by splitting the total input data of the chip. The input data of different processing units do not overlap, so that the input data input to itself can be processed in parallel by multiple processing units.

[0044] As an example, taking the chip's total input data as including the input matrix A determined by the input features based on the deep learning model and the weight matrix W of the deep learning model, the chip performs tensor computation (A×W) of A and W. A and W can be split into multiple parts and input into multiple processing units in parallel for processing.

[0045] The input features include, but are not limited to, text features, image features, audio features, and video features. The input features are related to the application scenario of the deep learning model. For example, if the deep learning model is used for text classification, the input features can be text features; if it's used for image classification, the input features can be image features; and if it's used for speech recognition, the input features can be audio features.

[0046] In the embodiments of this application, target operators can be scheduled to multiple processing units in the chip according to the target operators scheduled to be executed in the chip, so that multiple processing units can perform parallel processing on the input data input to each processing unit based on the target operators.

[0047] Step S203: Schedule memory units based on memory scheduling strategy so that memory units enter the corresponding power consumption mode during runtime.

[0048] In this embodiment of the application, the memory units in the chip can also be dynamically scheduled according to the memory scheduling policy associated with the target operator scheduled to be executed in the chip, so that the memory units enter the corresponding power consumption mode during the runtime segment indicated by the memory scheduling policy.

[0049] In any embodiment of this application, a first thread can schedule target operators to multiple processing units in the chip, while a second thread can schedule memory units based on a memory scheduling strategy associated with the target operators; wherein the first thread is independent of the second thread.

[0050] Therefore, the multi-threaded collaborative mechanism of using a first-thread scheduling operator and a second-thread independent scheduling of memory units can not only effectively reduce processing latency, but also significantly reduce chip power consumption.

[0051] The chip control method of this application schedules memory units based on a memory scheduling strategy associated with the target operator, while scheduling the target operator to multiple processing units in the chip. This enables multiple processing units to process the input data input to each processing unit in parallel based on the target operator, thereby improving and reducing the overall processing latency of the chip and increasing the system throughput efficiency.

[0052] As one possible implementation method, Figure 3 This is a flowchart illustrating yet another chip control method provided for an exemplary embodiment of this application.

[0053] It should be noted that the chip control method can be executed alone, or it can be executed together with any embodiment of this application or any possible implementation in the embodiment, or it can be executed together with any technical solution in the related technology. The embodiments of this application do not limit this.

[0054] like Figure 3 As shown, in any embodiment of this application, the memory scheduling strategy associated with the target operator can be determined using steps S301 to S302: Step S301: Determine the memory access model associated with the target operator based on the memory access behavior of the chip during the execution of the target operator; wherein, the memory access model is used to indicate the access period during the execution of the target operator where memory access behavior exists.

[0055] It should be noted that the explanations of the target operator and memory unit in the foregoing embodiments also apply to this embodiment, and will not be repeated here.

[0056] In this embodiment, a memory access model associated with the target operator can be determined in advance based on the memory access behavior of the chip during the execution of the target operator; wherein, the memory access model is used to indicate the access period during the execution of the target operator where memory access behavior exists, and the non-access period where no memory access behavior exists (such as when the chip does not need to access memory units during computation).

[0057] In any embodiment of this application, the memory access behavior of the chip during the execution of the target operator can be monitored and sampled according to the configured sampling interval to obtain sampling data, and the memory access model associated with the target operator can be determined based on the sampling data.

[0058] By appropriately configuring the sampling interval, key information about memory access behavior can be effectively captured without affecting the normal operation of the chip, resulting in representative sampled data. This sampled data contains detailed information about memory access behavior during the execution of the target operator.

[0059] As an example, taking an AI computing and storage chip that integrates computing and storage, and the target operator as a dot product operator, the calculation process for "processing the dot product of K-dimensional vectors" by the dot product operator can be as follows: Figure 4 As shown, matrix A is M×K, representing M K-dimensional vectors; matrix B is K×N, representing N K-dimensional vectors; and matrix C is M×N, the dot product of matrices A and B. During the dot product calculation, matrices A and B are divided into multiple tiles for parallel processing. Each processing unit (PE) in the AI ​​computing memory chip is responsible for calculating the dot product of these tiles, resulting in a sub-matrix (Block). Merging the sub-matrices output by multiple PEs yields the final matrix C.

[0060] The computational tasks carried by each PE can be as follows: Figure 5 As shown, each PE is responsible for the dot product of a row of K-dimensional vectors in matrix A and a column of K-dimensional vectors in matrix B. The arrows indicate the direction of data flow, showing how each PE obtains data from the input data and performs calculations.

[0061] In the time dimension, for the dot product of K-dimensional vectors, each PE stores 1 / N of the data, processes it, and sends it to the next matrix. The data flow during the computation is as follows: Figure 6 As shown, the process is as follows: Input phase: M K-dimensional vectors and N K-dimensional vectors are input into the AI ​​computing and storage chip; Data allocation: These vectors are allocated to various PEs, where each PE stores 1 / N of the data, meaning the data is segmented and distributed to different PEs for parallel processing; Computation phase: Each PE performs dot product calculations on its allocated data; Data transfer: After the calculation is completed, the PE passes the result to the next matrix; Periodic process: The data processing flow of each PE is periodic, which means that the execution process can be predicted during the dot product operator business scheduling, resulting in better scheduling of memory behavior.

[0062] In summary, during the dot product operator service scheduling process, the PE (Preprocessor) periodically performs load (receive), compute, and store (send) operations. During the compute phase, the PE loads memory data into a cache segment for computation. If fixed timing parameters are used to maintain memory state switching, there is a power consumption and performance loss issue described in related technologies when reading data in segments each time.

[0063] To address the aforementioned issues, this application proposes a memory scheduling strategy that can be dynamically adjusted based on actual business needs. Specifically, the task scheduling unit (TSU) in the AI ​​computing and memory chip simultaneously schedules the memory units. The structure of the AI ​​computing and memory chip can be as follows: Figure 7 As shown, it includes multiple PEs, TSUs and coprocessors for parallel processing, wherein the coprocessor is used to determine the operator to be scheduled based on the actual business.

[0064] The dynamic adjustment logic of the memory scheduling strategy mainly includes the following two parts: Part 1: Preparation Phase: Analyze the memory access models of various operators supported by AI computing and memory chips, such as typical operators including: embedding, RMSnorm, quantization, dequantization, dot product, addition / multiplication, activation functions, etc.

[0065] The memory access model can be captured through the statistical functions inside the AI ​​computing memory chip, and the process includes the following steps: 1. Configure the sampling interval required for chip statistics, and use the loop mode to perform statistics on the sampled data, exporting the statistical results in real time; 2. Configure the chip to start executing operators, such as starting the dot product operator, and based on the configured sampling interval, monitor and sample the memory access behavior of memory units during the chip's execution of the dot product operator to obtain sampled data, and use loop mode to perform statistics on the sampled data; 3. After repeated testing, the memory access model during the execution of the corresponding operator can be obtained.

[0066] For example, the memory access model corresponding to the dot product operator "processing the dot product of K-dimensional vectors" can be abstracted as follows: Figure 8 As shown, during the access periods (such as T1 and T2) indicated by the memory access model where memory access behavior exists, the memory cell operates in a non-low-power mode; during the non-access periods (such as T3) indicated by the memory access model where no memory access behavior exists, the memory cell operates in a low-power mode.

[0067] Part Two: Implementation Phase: Based on the access models of different operators obtained in Part One, customize memory scheduling strategies associated with different operators. For example, operator A corresponds to scheduling strategy a, operator B corresponds to scheduling strategy b, etc.

[0068] For example, for the memory access model corresponding to the dot product operator "processing the dot product of K-dimensional vectors", a model can be formulated as follows: Figure 9 The memory scheduling strategy shown is "cycled with a period of T1+T2+T3, working in a non-low power mode (such as the best performance mode) during the T1~T2 time period, and entering a low power mode (such as the lowest power mode) during the T3 time period".

[0069] The TSU module in the AI ​​computing and storage chip schedules the dot product operator while maintaining an independent thread to periodically issue memory scheduling policies to memory units.

[0070] In summary, during the execution of operators by AI computing and memory chips, the access behavior of memory units is periodic. When the coprocessor schedules operators, the TSU can synchronously and dynamically schedule the memory scheduling strategy associated with the operators to reduce the power consumption of the chip.

[0071] In any embodiment of this application, the memory access model is also used to indicate at least one of the following: the data flow path within the access period; the sequential relationship between memory access behaviors corresponding to different access periods; and the cyclical relationship between memory access behaviors corresponding to different access periods.

[0072] Still with Figure 8 The memory access model shown is used as an example. The memory access model associated with the dot product operator is used to indicate the data flow path within time periods T1, T2, and T3, the order of memory access behaviors corresponding to time periods T1, T2, and T3, and the cyclical characteristics of memory access behaviors corresponding to time periods T1, T2, and T3.

[0073] Understandably, understanding the sequential and cyclical characteristics of different memory access behaviors helps predict and schedule memory accesses, improve memory access efficiency, and reduce access conflicts and latency.

[0074] Step S302: Determine the memory scheduling strategy associated with the target operator based on the memory access model associated with the target operator.

[0075] The memory scheduling strategy is used to indicate the runtime of memory cells in the chip in at least one power consumption mode. The runtime is associated with the access period of the memory cell when the target operator is executed.

[0076] It should be noted that the explanation of the memory scheduling strategy in the foregoing embodiments also applies to this embodiment, and will not be repeated here.

[0077] In this embodiment of the application, the memory scheduling strategy associated with the target operator can be determined based on the memory access model associated with the target operator.

[0078] In any embodiment of this application, at least one power consumption mode includes a low-power mode and a non-low-power mode. During the access period indicated by the memory access model where memory access behavior exists, the memory scheduling policy instructs the memory unit to operate in a non-low-power mode; during the non-access period indicated by the memory access model where no memory access behavior exists, the memory scheduling policy instructs the memory unit to operate in a low-power mode.

[0079] In summary, during memory access periods, memory cells operate in non-low-power mode to ensure high bandwidth and low latency for data access. During non-access periods, when there is no memory access requirement, memory cells automatically switch to low-power mode, significantly reducing static leakage current and dynamic power consumption. Furthermore, the low-power mode during non-access periods effectively reduces local power density and heat accumulation on the chip, helping to suppress chip temperature rise and prevent frequency throttling or reliability degradation due to overheating, thus improving the long-term stability and lifespan of the chip.

[0080] It should be noted that steps S301 to S302 can be executed in advance. After determining the memory scheduling strategy associated with the target operator, the association between the target operator and the memory scheduling strategy can be established and stored. Thus, in this application, during the implementation stage of the target operator, i.e. when the chip is scheduled to execute the target operator, the above association can be queried based on the target operator to obtain the memory scheduling strategy associated with the target operator, and the memory unit can be dynamically scheduled based on the memory scheduling strategy so that the memory unit enters the corresponding power consumption mode during the runtime.

[0081] The chip control method of this application determines the memory access model associated with the target operator based on the memory access behavior of the chip during the execution of the target operator, and determines the memory scheduling strategy associated with the target operator accordingly. This enables precise matching between memory resource management and the access requirements of specific computing tasks, improves the rationality and reliability of memory scheduling strategy formulation, and avoids resource waste and performance bottlenecks in traditional static scheduling. Specifically, by keeping memory active during access periods and promptly switching to low-power mode during non-access periods, a balance between power consumption and performance is achieved, effectively reducing energy consumption, suppressing chip temperature rise, and ensuring the real-time performance of data access and system stability.

[0082] As one possible implementation method, Figure 10 A schematic flowchart of another chip control method provided for an exemplary embodiment of this application.

[0083] It should be noted that the chip control method can be executed alone, or it can be executed together with any embodiment of this application or any possible implementation in the embodiment, or it can be executed together with any technical solution in the related technology. The embodiments of this application do not limit this.

[0084] like Figure 10 As shown, the chip control method may include the following steps S1001 to S1003: Step S1001: Determine the memory scheduling strategy associated with the target operator based on the target operator scheduled to be executed in the chip; wherein, the memory scheduling strategy is used to indicate the runtime of the memory unit in the chip in at least one power mode, the runtime is associated with the access period of the memory unit when the target operator is executed, and the at least one power mode includes a low power mode and a non-low power mode.

[0085] It should be noted that the explanation of step S1001 can be found in the relevant description in any embodiment of this application, and will not be repeated here.

[0086] Step S1002: In response to the arrival of the first moment, the scheduled memory unit enters a low-power mode; wherein, the first moment is the start moment of the runtime segment of the low-power mode indicated by the memory scheduling policy.

[0087] In the embodiments of this application, when the first moment is reached (i.e., the start moment of the runtime segment of the low-power mode indicated by the memory scheduling strategy), the memory unit can be immediately scheduled to enter the low-power mode to reduce chip power consumption.

[0088] Step S1003: In response to the arrival of the second time, the scheduled memory unit exits the low-power mode and enters the non-low-power mode; wherein the second time is located before the start time of the runtime segment of the non-low-power mode indicated by the memory scheduling policy.

[0089] It should be noted that when a memory cell enters a low-power mode (such as hibernation mode), its internal circuitry is shut down or its frequency is reduced to decrease leakage power consumption. When the memory cell needs to be accessed again, a wake-up operation must be performed to restore the internal circuitry to normal operating conditions. This process involves a physical delay (i.e., wake-up latency). If the wake-up operation is not initiated until the actual memory access begins, the memory cell will not be able to respond in time.

[0090] To address the aforementioned issues, this application proposes a mechanism to wake up memory cells (exiting low-power mode to enter non-low-power mode) based on an early wake-up mechanism. Specifically, upon reaching a second time point, the memory cell can be scheduled to exit low-power mode and enter non-low-power mode; where the second time point is located before the start time of the runtime segment of the non-low-power mode indicated by the memory scheduling policy.

[0091] In any embodiment of this application, the second moment is located after the start time of the low-power mode runtime segment and before the start time of the non-low-power mode runtime segment. The time interval between the second moment and the start time of the non-low-power mode runtime segment can be determined based on the duration of the memory cell entering low-power mode (e.g., sleep time) and the amount of unprocessed data on the chip.

[0092] It should be noted that, considering the longer a memory cell remains in low-power mode, the more severe the decay of its internal state (such as voltage and bias), and the longer the wake-up time may be. Therefore, in this application, the longer the duration, the larger the time interval for early wake-up should be to ensure sufficient recovery. That is, the time interval and the duration can be positively correlated.

[0093] It should also be noted that if the chip has a large backlog of unprocessed data (i.e., a large amount of unprocessed data), it indicates that the system is about to enter a high-load state and needs to respond to memory access requests more quickly. In this case, memory units should be woken up even earlier to avoid memory latency becoming a performance bottleneck. That is, the time interval and duration can also be positively correlated.

[0094] In summary, by dynamically determining the wake-up advance interval based on the duration of the low-power mode and the amount of unprocessed data, the memory wake-up mechanism becomes adaptive and intelligent. This ensures timely service recovery after high load or deep sleep, while avoiding energy waste during light load or short sleep. It effectively balances the contradiction between system performance, response latency, and power consumption, making it suitable for scenarios with dual requirements of energy efficiency and real-time performance, such as heterogeneous computing, edge AI, and real-time processing.

[0095] The chip control method of this application, through a timely sleep mechanism and an early wake-up mechanism, can effectively reduce power consumption while ensuring system performance, achieving synergistic optimization of energy efficiency. Specifically, the timely sleep mechanism ensures that memory units quickly enter a low-power mode during non-access periods, avoiding resource idleness and reducing unnecessary static power consumption; the early wake-up mechanism, based on wake-up latency requirements and system load status, initiates a memory recovery process before access, ensuring that the memory is ready when a task arrives, thereby avoiding processing delays caused by wake-up lag. The synergistic effect of these two mechanisms suppresses power loss and prevents performance degradation, significantly improving the chip's energy efficiency and real-time response under dynamic loads.

[0096] To achieve the above embodiments, this application also proposes a chip control device.

[0097] Figure 11 This is a schematic diagram of the structure of a chip control device provided for an exemplary embodiment of this application.

[0098] like Figure 11 As shown, the chip control device 1100 may include a first determining module 1110 and a scheduling module 1120.

[0099] The first determining module 1110 is used to determine a memory scheduling strategy associated with the target operator based on the target operator scheduled to be executed in the chip; wherein the memory scheduling strategy is used to indicate the runtime segment of the memory unit in the chip in at least one power consumption mode, and the runtime segment is associated with the access period of the memory unit when the target operator is executed. The scheduling module 1120 is used to schedule memory units based on memory scheduling strategies so that memory units enter the corresponding power consumption mode during runtime.

[0100] In one implementation of this application, the memory scheduling strategy associated with the target operator is determined using the following modules: The second determining module is used to determine the memory access model associated with the target operator based on the memory access behavior of the chip during the execution of the target operator; wherein, the memory access model is used to indicate the access period during the execution of the target operator where memory access behavior exists. The third determining module is used to determine the memory scheduling strategy associated with the target operator based on the memory access model associated with the target operator.

[0101] In one implementation of this application, at least one power consumption mode includes a low-power mode and a non-low-power mode. During the access period indicated by the memory access model, the memory scheduling policy instructs memory units to operate in a non-low-power mode. During non-access periods indicated by the memory access model where no memory access activity occurs, the memory scheduling policy instructs memory cells to operate in a low-power mode.

[0102] In one implementation of this application, the scheduling module 1120 is configured to: in response to reaching a first time, schedule a memory unit to enter a low-power mode; wherein the first time is the start time of the runtime segment of the low-power mode indicated by the memory scheduling strategy; and in response to reaching a second time, schedule a memory unit to exit the low-power mode to enter a non-low-power mode; wherein the second time is located before the start time of the runtime segment of the non-low-power mode indicated by the memory scheduling strategy.

[0103] In one implementation of this application, the second moment is located after the start time of the low-power mode runtime segment and before the start time of the non-low-power mode runtime segment. The time interval between the second moment and the start moment of the non-low-power mode runtime is determined based on the duration of the memory cell entering low-power mode and the amount of unprocessed data on the chip.

[0104] In one implementation of this application, the second determining module is used to: monitor and sample the memory access behavior of the chip during the execution of the target operator according to the configured sampling interval, and obtain sampling data; and determine the memory access model associated with the target operator based on the sampling data.

[0105] In one implementation of this application, the memory access model is further used to indicate at least one of the following: the data flow path within the access period; the sequential relationship between memory access behaviors corresponding to different access periods; and the cyclical relationship between memory access behaviors corresponding to different access periods.

[0106] In one implementation of this application, the scheduling module 1120 is further configured to: schedule target operators to multiple processing units in the chip, so that the multiple processing units can perform parallel processing on the input data input to each processing unit based on the target operators.

[0107] In one implementation of this application, the scheduling module 1120 is used to: schedule target operators to multiple processing units in the chip through a first thread; and schedule memory units based on a memory scheduling strategy through a second thread; wherein the first thread is independent of the second thread.

[0108] It should be noted that the foregoing explanation of any chip control method embodiment also applies to the chip control device of that embodiment, and will not be repeated here.

[0109] In the chip control device of this application embodiment, a memory scheduling strategy associated with the target operator scheduled for execution in the chip is determined, and memory units are dynamically scheduled based on the memory scheduling strategy. Since the execution characteristics of the target operator (such as data access mode, lifecycle, etc.) directly determine the memory access requirements, by establishing a semantic association between "operator-memory", the active and inactive periods of memory units can be accurately predicted. The memory scheduling strategy is used to indicate the runtime of the memory unit in at least one power mode (such as low-power mode, non-low-power mode) when executing the target operator (which can indirectly indicate the activation timing and switching sequence of at least one power mode), so that the memory unit maintains a non-low-power mode during the memory access time window required when executing the target operator, and automatically enters a low-power mode during other periods. As a result, memory state management has shifted from the traditional passive and static mode to an active, task-driven fine-grained control, significantly reducing leakage current loss during idle periods and avoiding additional energy consumption caused by frequent full wake-ups. This can effectively improve the energy efficiency ratio of memory units and enhance the chip's adaptability under dynamic loads, making it particularly suitable for computationally intensive scenarios with high throughput and low latency, such as AI inference and real-time signal processing.

[0110] To implement the above embodiments, this application also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the chip control method as described in any of the foregoing embodiments.

[0111] Figure 12 This is a schematic diagram of the structure of an electronic device provided for an exemplary embodiment of this application. For example, the electronic device 1200 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0112] Reference Figure 12 The electronic device 1200 may include one or more of the following components: a processing component 1202, a memory 1204, a power component 1206, a multimedia component 1208, an audio component 1210, an input / output (I / O) interface 1212, a sensor component 1214, and a communication component 1216.

[0113] Processing component 1202 typically controls the overall operation of electronic device 1200, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 1202 may include one or more processors 1220 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 1202 may include one or more modules to facilitate interaction between processing component 1202 and other components. For example, processing component 1202 may include a multimedia module to facilitate interaction between multimedia component 1208 and processing component 1202.

[0114] Memory 1204 is configured to store various types of data to support the operation of electronic device 1200. Examples of such data include instructions for any application or method operating on electronic device 1200, contact data, phonebook data, messages, pictures, videos, etc. Memory 1204 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0115] Power component 1206 provides power to various components of electronic device 1200. Power component 1206 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 1200.

[0116] Multimedia component 1208 includes a screen that provides an output interface between the electronic device 1200 and the user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a Touch Panel, the screen may be implemented as a touchscreen to receive input signals from the user. The Touch Panel includes one or more touch sensors to sense touches, swipes, and gestures on the Touch Panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 1208 includes a front-facing camera and / or a rear-facing camera. When the electronic device 1200 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0117] Audio component 1210 is configured to output and / or input audio signals. For example, audio component 1210 includes a microphone (MIC) configured to receive external audio signals when electronic device 1200 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 1204 or transmitted via communication component 1216. In some embodiments, audio component 1210 also includes a speaker for outputting audio signals.

[0118] I / O interface 1212 provides an interface between processing component 1202 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0119] Sensor assembly 1214 includes one or more sensors for providing state assessments of various aspects of electronic device 1200. For example, sensor assembly 1214 may detect the on / off state of electronic device 1200, the relative positioning of components such as the display and keypad of electronic device 1200, changes in position of electronic device 1200 or a component of electronic device 1200, the presence or absence of user contact with electronic device 1200, orientation or acceleration / deceleration of electronic device 1200, and temperature changes of electronic device 1200. Sensor assembly 1214 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 1214 may also include an optical sensor, such as a complementary metal-oxide-semiconductor (CMOS) or charge-coupled device (CCD) image sensor, for use in imaging applications. In some embodiments, sensor assembly 1214 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0120] Communication component 1216 is configured to facilitate wired or wireless communication between electronic device 1200 and other devices. Electronic device 1200 can access wireless networks based on communication standards, such as WiFi, 4G, or 5G, or combinations thereof. In one exemplary embodiment, communication component 1216 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 1216 further includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID), Infrared Data Association (IrDA), Ultra-Wideband (UWB), Bluetooth, and other technologies.

[0121] In an exemplary embodiment, the electronic device 1200 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0122] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 1204 including instructions, which can be executed by a processor 1220 of an electronic device 1200 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0123] To implement the above embodiments, this application also proposes a chip, wherein the chip includes an interface circuit and a processing circuit coupled to each other. The interface circuit is used to input or output signals, and the processing circuit is configured to execute the chip control method provided in any of the foregoing embodiments.

[0124] Figure 13 This is a schematic diagram of the structure of a chip proposed in an exemplary embodiment of this application. See also... Figure 13 The diagram shown is a schematic representation of the structure of chip 1300, but it is not limited to this.

[0125] Chip 1300 includes processing circuit 1301, which is configured to execute any of the above chip control methods.

[0126] In some embodiments, chip 1300 further includes one or more interface circuits 1302. Optionally, interface circuit 1302 is connected to memory 1303, and interface circuit 1302 can be used to receive signals from memory 1303 or other devices, and interface circuit 1302 can be used to send signals to memory 1303 or other devices. For example, interface circuit 1302 can read instructions stored in memory 1303 and send the instructions to processing circuit 1301.

[0127] In some embodiments, the interface circuit 1302 performs at least one of the communication steps such as sending and / or receiving in the above method, while the processing circuit 1301 performs other steps.

[0128] In some embodiments, the terms interface circuit, interface, transceiver pin, transceiver, etc., can be used interchangeably.

[0129] In some embodiments, chip 1300 further includes one or more memories 1303 for storing instructions. Optionally, all or part of the memories 1303 may be located outside of chip 1300.

[0130] To implement the above embodiments, this application also proposes a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the chip control method as described in any of the foregoing method embodiments.

[0131] To implement the above embodiments, this application also proposes a computer program product having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the chip control method as described in any of the foregoing method embodiments.

[0132] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0133] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0134] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0135] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-including system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and compact disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0136] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0137] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0138] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0139] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A chip control method, characterized in that, include: Based on the target operator scheduled for execution in the chip, a memory scheduling policy associated with the target operator is determined; wherein, the memory scheduling policy is used to indicate the runtime segment of the memory unit in the chip in at least one power consumption mode, the runtime segment being associated with the access period of the memory unit when the target operator is executed; The memory unit is scheduled based on the memory scheduling policy so that the memory unit enters the corresponding power consumption mode during the runtime.

2. The method according to claim 1, characterized in that, The memory scheduling strategy associated with the target operator is determined using the following steps: Based on the memory access behavior of the memory unit during the execution of the target operator by the chip, a memory access model associated with the target operator is determined; wherein, the memory access model is used to indicate the access period during the execution of the target operator where memory access behavior exists; Based on the memory access model associated with the target operator, determine the memory scheduling strategy associated with the target operator.

3. The method according to claim 2, characterized in that, The at least one power consumption mode includes a low power consumption mode and a non-low power consumption mode. During the access period indicated by the memory access model where the memory access behavior occurs, the memory scheduling policy instructs the memory unit to operate in a non-low-power mode; During non-access periods indicated by the memory access model where no memory access behavior occurs, the memory scheduling policy instructs the memory unit to operate in a low-power mode.

4. The method according to claim 3, characterized in that, The step of scheduling the memory unit based on the memory scheduling policy to enable the memory unit to enter the corresponding power consumption mode during the runtime includes: In response to the arrival of a first moment, the memory unit is scheduled to enter the low-power mode; wherein, the first moment is the start moment of the runtime segment of the low-power mode indicated by the memory scheduling policy; In response to the arrival of a second time point, the memory unit is scheduled to exit the low-power mode and enter the non-low-power mode; wherein the second time point is located before the start time of the runtime segment of the non-low-power mode indicated by the memory scheduling policy.

5. The method according to claim 4, characterized in that, The second moment is after the start time of the low-power mode runtime segment and before the start time of the non-low-power mode runtime segment; The time interval between the second moment and the start moment of the non-low-power mode runtime segment is determined using the following steps: The time interval is determined based on the duration of the memory unit entering the low-power mode and the amount of unprocessed data in the chip.

6. The method according to claim 2, characterized in that, The step of determining the memory access model associated with the target operator based on the memory access behavior of the memory unit during the execution of the target operator by the chip includes: According to the configured sampling interval, the memory access behavior of the memory unit is monitored and sampled during the execution of the target operator by the chip to obtain sampling data; Based on the sampled data, the memory access model associated with the target operator is determined.

7. The method according to claim 4, characterized in that, The memory access model is also used to indicate at least one of the following: The data flow path during the access period; The sequential relationship between memory access behaviors corresponding to different access time periods; The cyclical relationship between memory access behaviors corresponding to different access periods.

8. The method according to any one of claims 1-7, characterized in that, The method further includes: The target operator is scheduled to multiple processing units in the chip so that the multiple processing units can perform parallel processing on the input data input to each of the processing units based on the target operator.

9. The method according to claim 8, characterized in that, The step of scheduling the target operator to multiple processing units in the chip includes: The target operator is scheduled to the plurality of processing units in the chip via the first thread; Sending the memory scheduling policy to the memory unit includes: The memory units are scheduled by a second thread based on the memory scheduling strategy; wherein the first thread is independent of the second thread.

10. A chip control device, characterized in that, include: The first determining module is configured to determine a memory scheduling strategy associated with the target operator based on the target operator scheduled to be executed in the chip; wherein the memory scheduling strategy is configured to indicate the runtime segment of the memory unit in the chip in at least one power consumption mode, and the runtime segment is associated with the access period of the memory unit when the target operator is executed; The scheduling module is used to schedule the memory unit based on the memory scheduling policy, so that the memory unit enters the corresponding power consumption mode during the runtime.

11. The apparatus according to claim 10, characterized in that, The memory scheduling strategy associated with the target operator is determined using the following modules: The second determining module is used to determine a memory access model associated with the target operator based on the memory access behavior of the memory unit during the execution of the target operator by the chip; wherein, the memory access model is used to indicate the access period during the execution of the target operator where memory access behavior exists; The third determining module is used to determine the memory scheduling strategy associated with the target operator based on the memory access model associated with the target operator.

12. The apparatus according to claim 11, characterized in that, The at least one power consumption mode includes a low power consumption mode and a non-low power consumption mode. During the access period indicated by the memory access model where the memory access behavior occurs, the memory scheduling policy instructs the memory unit to operate in a non-low-power mode; During non-access periods indicated by the memory access model where no memory access behavior occurs, the memory scheduling policy instructs the memory unit to operate in a low-power mode.

13. The apparatus according to claim 12, characterized in that, The scheduling module is used for: In response to the arrival of a first moment, the memory unit is scheduled to enter the low-power mode; wherein, the first moment is the start moment of the runtime segment of the low-power mode indicated by the memory scheduling policy; In response to the arrival of a second time point, the memory unit is scheduled to exit the low-power mode and enter the non-low-power mode; wherein the second time point is located before the start time of the runtime segment of the non-low-power mode indicated by the memory scheduling policy.

14. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the steps of the method as described in any one of claims 1 to 9.

15. A non-transitory computer-readable storage medium having computer program instructions stored thereon, characterized in that, When executed by a processor, the program instructions implement the steps of the method according to any one of claims 1 to 9.

16. A chip, characterized in that, The chip includes an interface circuit and a processing circuit that are coupled to each other. The interface circuit is used to input or output signals, and the processing circuit is used to implement the method of any one of claims 1 to 9.

17. A computer program product, characterized in that, It includes a computer program, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 9.

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