Memory control method and memory storage device

Abstract

The application provides a memory control method and a memory storage device. The method comprises: receiving a data write request from a host system, obtaining a plurality of access characteristics of to-be-written data according to the data write request, calculating a hotness value of the to-be-written data based on a weight dynamic self-adaptive adjustment mechanism according to the plurality of access characteristics, determining a data state of the to-be-written data according to the hotness value, and placing the to-be-written data in a target queue corresponding to the data state. When the state of the target queue meets a preset condition, the plurality of to-be-written data in the target queue are written into an entity block corresponding to the data state. Through the above method, the weight used to calculate the hotness value can be dynamically adjusted, thereby improving the problem that in the related art, the hotness value of data is calculated by relying on a fixed weight, which can cause frequent cold-hot data error classification, and then cause a large number of unnecessary mapping table updates and data migration, and affect the performance and service life of the memory storage device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of memory control, and in particular, to a memory control method and a memory storage device. BACKGROUND

[0002] Conventional memory storage devices are generally equipped with dynamic random access memory (DRAM) to store logical-to-physical mapping tables (L2P tables). As memory storage devices become smaller and smaller and manufacturers consider cost, reducing the capacity and size of dynamic random access memory (DRAM) in memory storage devices has gradually become one of the design choices. In DRAM-less memory storage devices, logical-to-physical mapping tables are stored on non-volatile memory modules.

[0003] The lifetime and performance of non-volatile memory modules, such as NAND flash memory modules, depend on the fine management of hot and cold data. However, conventional hot and cold data shunting strategies rely on fixed weights to calculate the hotness value of data, which can lead to frequent misclassification of hot and cold data, and in turn cause a large number of unnecessary mapping table updates and data migration, affecting the performance and lifetime of memory storage devices. SUMMARY

[0004] Therefore, the present application provides a memory control method and a memory storage device to solve or partially solve the above problems.

[0005] In a first aspect, the present application provides a memory control method for a storage device, wherein the storage device includes a memory module, and the memory module includes a plurality of physical blocks. The memory control method includes: receiving a data write request from a host system, wherein the data write request includes to-be-written data; obtaining a plurality of access characteristics of the to-be-written data according to the data write request; calculating a hotness value of the to-be-written data based on a weight dynamic self-adaptive adjustment mechanism according to the plurality of access characteristics; determining a data state of the to-be-written data and placing the to-be-written data in a target queue corresponding to the data state according to the hotness value; and writing a plurality of to-be-written data in the target queue to the physical block corresponding to the data state in response to the state of the target queue satisfying a preset condition.

[0006] In a second aspect, the present application provides a memory storage device, comprising: a connection interface configured to connect to a host system; a memory module comprising a plurality of physical blocks; and a memory controller electrically coupled to the connection interface and the memory module, and configured to perform the method of the first aspect.

[0007] The present application provides a memory control method and a memory storage device. The method comprises: receiving a data write request from a host system, and obtaining a plurality of access characteristics of to-be-written data according to the data write request. According to the plurality of access characteristics, a heat value of the to-be-written data is calculated based on a weight dynamic self-adaptive adjustment mechanism. According to the heat value, a data state of the to-be-written data is determined, and the to-be-written data is placed in a target queue corresponding to the data state. When a state of the target queue meets a preset condition, the plurality of to-be-written data in the target queue are written into a physical block corresponding to the data state. Through the above method, the weight used to calculate the heat value can be dynamically adjusted, thereby improving the problem in the related art that the heat value of data is calculated by relying on a fixed weight, which can cause frequent misclassification of hot and cold data, and further cause a large number of unnecessary mapping table updates and data migration, and affect the performance and service life of the memory storage device. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly introduced. For those skilled in the art, other drawings can also be obtained without creative labor on the premise of these drawings, and these drawings are within the protection scope of the present application.

[0009] Figure 1 A schematic diagram of an exemplary memory storage system 100 according to an embodiment of the present application is shown.

[0010] Figure 2 A schematic diagram of an exemplary memory storage device 200 according to an embodiment of the present application is shown.

[0011] Figure 3 A flowchart of an exemplary memory control method 300 according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0012] The technical solutions of the present application will be described in detail below with reference to the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0013] It should be particularly noted that similar substitutions and modifications made to this application are obvious to those skilled in the art, and they are all considered to be included in this application. Those skilled in the art can obviously make modifications or appropriate alterations and combinations to the methods and applications described herein without departing from the content, spirit, and scope of this application to implement and apply the technology of this application. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0014] Figure 1 A schematic diagram of an exemplary memory storage system 100 according to an embodiment of this application is shown.

[0015] like Figure 1 As shown, the memory storage system 100 includes a host system 102 and a memory storage device 104. The host system 102 can be any type of computer system, such as a laptop computer, desktop computer, smartphone, tablet computer, industrial computer, etc. The memory storage device 104 is used to store data from the host system 102. The memory storage device 104 may include a solid-state drive, a USB flash drive, or other types of non-volatile storage devices. The host system 102 can be electrically connected to the memory storage device 104 via a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCI Express) interface, a Universal Serial Bus (USB) interface, or other types of connection interfaces. Therefore, the host system 102 can store data to and / or read data from the memory storage device 104.

[0016] The memory storage device 104 may include a connection interface 1041, a memory module 1042, and a memory controller 1043. The connection interface 1041 is used to connect the memory storage device 104 to the host system 102. The memory storage device 104 can communicate with the host system 102 via the connection interface 1041.

[0017] Memory module 1042 is used to store data. Memory module 1042 may include a non-volatile memory module. Memory module 1042 includes an array of memory cells. The memory cells in memory module 1042 store data in the form of voltage. In some embodiments, memory module 1042 may be a NAND flash memory module (NAND Flash).

[0018] The memory controller 1043 is connected to the connection interface 1041 and the memory module 1042. The memory controller 1043 can be used to control the memory storage device 104, for example, the memory controller 1043 can control the connection interface 1041 and the memory module 1042 to perform data access and data management. For example, the memory controller 1043 can include a central processing unit (CPU), a graphics processing unit (GPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations of these devices.

[0019] In some embodiments, the memory controller 1043 is also referred to as a flash memory controller or a flash memory module. The memory module 1042 can receive a sequence of instructions from the memory controller 1043 and read data stored in the memory cells according to the sequence of instructions.

[0020] The memory module 1042 can include a plurality of physical pages, each of which can include a plurality of memory cells and be used to store data non-volatilely. The plurality of physical pages can constitute a physical block. The plurality of physical pages (or memory cells) in a physical block can be erased simultaneously. The memory controller 1043 can include a plurality of logical units to map at least part of the physical pages, and a logical unit can be composed of one or more logical addresses. The mapping relationship between the logical units and the physical pages can be recorded in a logical-to-physical mapping table. In some embodiments, the memory controller 1043 can control the firmware of the flash translation layer (FTL) to convert the logical address (LBA) of the data received from the host system 102 into a physical address (PBA), so as to store the data in the memory storage device 104.

[0021] With the development of technology, smart terminal devices such as mobile phones, tablets, and vehicle-mounted devices have entered people's life and work. These smart terminal devices can provide data storage and access services for users. However, the explosive growth of data volume puts great storage pressure on terminal devices and affects data access efficiency. In this regard, a cold and hot data shunting strategy, which classifies and stores data according to data access frequency to optimize the performance and lifespan of memory storage devices, has emerged. If a certain data is frequently accessed, it is called hot data (for example, operating system metadata, database transaction logs, etc.). If a certain data is rarely accessed, it is called cold data (for example, archived documents, system backups, etc.).

[0022] The memory module can include a plurality of physical blocks, which can be divided into young blocks and old blocks based on the number of erase-write times. The young blocks have fewer erase-write times, and the old blocks have more erase-write times. Hot data needs to be placed in young blocks with high erase-write endurance, while cold data should be directed to old blocks with relatively low erase-write endurance to achieve global wear leveling of the memory storage device. The young blocks can also be referred to as low-wear blocks.

[0023] Non-volatile memory modules, such as NAND Flash, are widely used in memory storage devices such as SD (Secure Digital), eMMC (embedded MultiMediaCard), UFS (Universal Flash Storage), SSD (Solid State Drive), etc. Their lifespan and performance depend on the fine management of cold and hot data.

[0024] In related technologies, the cold and hot data shunting strategy uses a fixed threshold (for example, data with more than 10 accesses per day is hot data). This shunting method with a fixed threshold cannot adapt to the dynamic changes of host system load (for example, high load during the day and low load at night), which may cause cold and hot data shunting to lag, reducing the accuracy of cold and hot data shunting, and failing to achieve efficient global wear leveling of the memory storage device.

[0025] For example, during a server peak period (write IOPS (Input / Output Operations Per Second) is greater than 100,000), the response speed of hot data needs to be prioritized. During the peak period, the amount of hot data increases dramatically. The fixed threshold cold and hot data judgment method will cause a large amount of hot data to be stored in the young block, resulting in insufficient space in the young block. The remaining hot data that should be stored in the young block will be stored in the old block, and subsequent access to these data will cause access delay, "write amplification", and other problems that cause the performance of the memory storage device to decline. In addition, the storage of error blocks will cause invalid data migration (for example, after cold data is marked as hot data, frequent data migration is required to read the data), additional occupation of 30% of the flash bandwidth, and shortening of the service life of the memory storage device.

[0026] In a DRAM-less SSD, a NAND Flash and a static random-access memory (SRAM) with extremely limited internal capacity of the SSD are included. The logical-to-physical mapping table is stored on the NAND Flash, and only the most active part of the mapping items is cached in the SRAM with extremely limited capacity. If the data that should be stored in the SRAM is stored on the NAND Flash, in order to load the correct mapping item, the flash translation layer needs to frequently read the mapping table page from the NAND Flash. This will cause a bandwidth contention with the read and write requests sent by the user to the memory module through the host system, thereby increasing the read and write delay. In addition, frequent reading of the mapping table page from the NAND Flash will also exacerbate the "write amplification" problem, severely restricting the performance and service life of the memory storage device.

[0027] In the related art, in addition to the fixed threshold cold and hot data shunting strategy, the judgment of cold and hot data is also based on a single dimension, for example, based only on access frequency (Access Frequency) to judge, that is, the number of access times of the data block within a unit time is counted, and if it exceeds a fixed threshold, it is determined to be hot data; for another example, only based on the recent access time (Recent Access Time) to judge, that is, through the least recently used algorithm (Least Recently Used, LRU) to mark the data that has not been accessed for a long time as cold data.

[0028] However, with the diversification of application scenarios (for example, mixed database, video stream storage), the single-dimensional hot and cold data judgment method has limitations. For example, although a large file (for example, a 4 GB video file) has a low access frequency, a single access will occupy a large amount of bandwidth, and if such a large file is judged as cold data and stored in a low-performance old block, it may cause the continuous reading performance of the data to decrease; although a small file (for example, a 1 KB log file) has a high access frequency, the data volume is small, and if it is marked as hot data and stored in a young block, the resources of the low-wear young block will be wasted.

[0029] The hot and cold data shunting method used in the related art also has the problem of insufficient real-time performance. The traditional hot and cold data shunting algorithm updates the classification result once an hour, and when the access mode of the host system mutates, the update frequency of the hot and cold data classification result will cause the hot and cold data shunting to lag, thereby causing the hot data to be temporarily stored in a high-wear old block, accelerating the aging of the high-wear block.

[0030] To solve at least the above problems, the present application provides a memory control method and a memory storage device, the method comprising: receiving a data write request from a host system, and obtaining a plurality of access characteristics of to-be-written data according to the data write request. According to the plurality of access characteristics, a hotness value of the to-be-written data is calculated based on a weight dynamic self-adaptive adjustment mechanism, and according to the hotness value, a data state of the to-be-written data is determined and the to-be-written data is placed in a target queue corresponding to the data state. When the state of the target queue meets a preset condition, the plurality of to-be-written data in the target queue is written into an entity block corresponding to the data state. Through the above method, the weight used to calculate the hotness value can be dynamically adjusted, thereby improving the problem that in the related art, the hotness value of the data is calculated by relying on a fixed weight, which may cause frequent hot and cold data misclassification, thereby causing a large number of unnecessary mapping table updates and data migration, and affecting the performance and service life of the memory storage device.

[0031] Figure 2 A schematic diagram of an exemplary memory storage device 200 according to an embodiment of the present application is shown.

[0032] As shown in Figure 2 The memory storage device 200 can receive a data write request 202 from a host system via a connection interface (not shown in the figure) and process the data write request 202 via a flash translation layer 204 in a memory controller 208. The data write request 202 can include to-be-written data to be written into a memory module and a logical address.

[0033] To solve the problem that the traditional cold and hot data shunting based on a single dimension access feature cannot accurately reflect the real situation of data access, thus leading to the problem that in a resource-limited environment, the wrong cold and hot data classification directly leads to the problem that the valuable SRAM cache and low-wear NAND Flash block are occupied by inefficient data. In some embodiments, a hardware circuit or a firmware module can be configured in the flash translation layer 204 to extract the access feature of the to-be-written data based on the data write request 202. The hardware circuit or the firmware module can be a feature extraction unit 212. In some embodiments, the access feature can include access frequency (T), access interval (At), data block size (S), and access pattern (M). Among them, the access frequency can be obtained by maintaining a sliding time window counter within a preset time (for example, within 5 minutes). Each time a data write access is performed, the number of times the corresponding logical address is accessed is incremented by 1. To prevent the counter from overflowing and to achieve normalization, in some embodiments, the access frequency (T) can be saturated calculated using the following formula:

[0034] The above formula indicates that if the access is more than 50 times within 5 minutes, it is considered as the highest frequency 1.0. Among them,

[0035] represents scaling by proportion, for example, will be mapped to . represents limiting the maximum value to 1.0, and the part exceeding is saturated to “1.0”.

[0036] The access interval (At) can be calculated according to the following formula by recording the last access time (t_last) of each logical address range:

[0037] The above formula indicates that if the distance from the current time exceeds 5 minutes (i.e., 300 seconds), the interval factor (At) is reduced to 0. Among them,

[0038] represents the current access time (timestamp), is used to limit the result to be not less than 0.

[0039] The data block size (S) can be calculated according to the following formula by recording the average size of the data segment corresponding to the logical address range:

[0040]

[0041] ​​​​The above formula indicates that the average size of the data segment is greater than 128 KB, which is considered as large block data. Among them, indicates the average size of the data segment, indicates that the maximum limit is 1.0.

[0042] The access mode (M) can be determined by detecting the logical address offset (ALBA) of the continuous data write request. If , it is determined that the access mode is sequential access, and M=1 is marked; otherwise, it is determined that the access mode is random access, and M=0.5 is marked. Among them, indicates the number of logical addresses of the last data write request.

[0043] Each logical address (Logic Block Address, LBA) has a set of metadata (Metadata) associated with it, which is used to describe the access behavior of the logical address (for example, access frequency, access interval, etc.). In the embodiments of the present application, the feature extraction unit 212 can update the metadata of the logical address synchronously after extracting the above-mentioned access features each time the data write request 202 is processed.

[0044] In order to balance the metadata storage overhead and classification accuracy, a hierarchical management strategy is adopted for the metadata. In some embodiments, the logical address space is divided into a plurality of logical units (Logical Unit, LU), each logical unit can be composed of one or more logical addresses, and the metadata area (Page Spare Area) is organized according to the logical unit. Specifically, the overall hot / cold / warm label of each logical unit and its aggregated features (for example, average values of access frequency, access interval, data block size and access mode) can be persisted together with the corresponding logical-to-physical (Logical-to-Physical, L2P) mapping table page (or mapping page) in the metadata area of the first memory module 206. It can be understood that each physical page will have a spare area (Spare Area), and error correction code (Error Correction Code, ECC) and metadata are stored in the spare area.

[0045] Each logical unit is usually composed of a plurality of logical blocks. In some embodiments, the second memory module 210 (for example, static random access memory) can also cache access information of finer granularity (for example, 4KB) logical blocks within its management range for the current active L2P mapping page. These fine-grained metadata are only marked as "dirty" when modified, indicating that the data has been modified, but has not been written back to the first memory module 206, so as to avoid triggering writing to the first memory module 206 every time access is triggered, thereby reducing "write amplification" and improving the performance of the memory storage device.

[0046] When the L2P mapping page to which the fine-grained metadata belongs is swapped out of the second memory module 210 (for example, when the cache space of the second memory module 210 is insufficient or the L2P mapping page to which the metadata belongs is not accessed for a long time), in some embodiments, the metadata and the mapping page corresponding to the metadata can be written in a compressed format to the first memory module 206 to ensure the consistency of the metadata and the mapping page in the first memory module 206, facilitating data recovery after the host system is powered off.

[0047] Through the hierarchical management method described above, under controllable metadata overhead, fine and quantitative description of data access behavior is realized, providing multi-dimensional and non-volatile feature input for accurate heat calculation, overcoming the limitations of the single-dimensional cold and hot data shunting method in related technologies.

[0048] As described above, the fixed-weight heat calculation formula cannot adapt to the changing host system load. In a DRAM-less environment, frequent cold and hot data error classification can cause a large number of unnecessary mapping table updates and data migration, sharply consuming the bandwidth of SRAM and NAND Flash. In view of this, a weight dynamic adaptive adjustment mechanism can be set, which has stability and convergence guarantee. In some embodiments, the trigger condition of the weight dynamic adaptive adjustment mechanism can be set. Specifically, a hot data hit rate (Hit_Rate) can be set, which can be calculated every N minutes. The calculation formula of the hot data hit rate is:

[0049]

[0050] Specifically, the number of data blocks accessed and marked as the first state (for example, hot data) in the past target time period and the total number of data blocks marked as the first state can be obtained, and the first state data hit rate (for example, hot data hit rate) can be calculated according to the number of data blocks and the total number of data blocks. A target hit rate (Target_Hit_Rate) can be set, for example, the first target hit rate can be set to 75%. To improve stability, in some embodiments, a hysteresis interval can be set. When the hot data hit rate is lower than the second target hit rate (for example, 70%) for two consecutive periods, the weight adjustment is triggered; when the hot data hit rate rises to or is higher than the third target hit rate (for example, 73%) or above, the adjustment mode is exited.

[0051] The calculation formula of the heat value (H) is:

[0052]

[0053] wherein, ~ denotes the weight.

[0054] As for the weight iteration algorithm, a heuristic adjustment algorithm based on contribution ratio can be adopted instead of a complex gradient descent algorithm to meet the real-time requirement of the firmware. In some embodiments, the average value (Avg_Feature_Hit) of each access feature on the hot data (i.e., the data in the first state) that is correctly hit in a plurality of (e.g., 3) time windows in the past can be counted. The contribution ratio of each access feature is calculated according to the average value, and the calculation formula is as follows:

[0055]

[0056] wherein, denotes the contribution ratio of the access feature i, denotes the average value of the access feature i, denotes the weight of the access feature i.

[0057] Based on the calculated contribution ratio of each access feature, the first target access feature, i.e., the access feature with the lowest contribution ratio, is found, for example, the access feature j. The weight of the access feature j ( ) is reduced by a step size δ (e.g., reduced by 0.02) to obtain the first weight. The second access feature with the highest contribution ratio is found, for example, the access feature k. The weight of the access feature k ( ) is increased by a step size δ to obtain the second weight.

[0058] As the running time of the system increases, the step size δ can be configured to gradually decay (e.g., decay to 90% of the original value every 24 hours) to make the weight eventually stable. All the weights are re-normalized to ensure that the sum of the weights ~ is 1.

[0059] Further, as the running time of the memory storage device increases, the step size can be configured to gradually decay (e.g., decay to 90% of the original value every 24 hours) to make the weight eventually stable and avoid excessive adjustment in the later period.

[0060] For example, during the random write burst period, the contribution ratio of the access pattern (M) will significantly increase. The weight iteration algorithm based on the embodiments of the present application can automatically increase the weight of the access pattern (M) corresponding to the access pattern (M), so that the algorithm is more inclined to identify the data accessed randomly as hot data.

[0061] According to the adjusted all weights, the plurality of access features, and the hotness calculation formula, the hotness value of the data to be written is calculated. The weight iteration algorithm of the embodiments of the present application can actively adapt to different application load patterns, which significantly improves the cold and hot data classification accuracy and reduces the invalid data migration operation.

[0062] As described above, the cold-hot data shunting strategy based on a single fixed threshold in the related art can cause the size of the hot data pool to be out of balance when the load fluctuates sharply, for example, either reaching a performance bottleneck at high load or wasting resources at low load. In view of this, a double-threshold mechanism can be set, and multiple data states can be defined to achieve dynamic adjustment and classification of cold-hot data.

[0063] In some embodiments, the double threshold includes a first threshold (Q hot) and a second threshold (Q cold), where the first threshold is greater than the second threshold. Based on the double threshold, at least three data states can be defined, for example: a first state, a fifth state, and a sixth state. The first state can be hot data (Hot), the fifth state can be warm data (Warm), and the sixth state can be cold data (Cold). Wherein when the hotness value is greater than or equal to the first threshold, the data state is judged to be the first state, when the hotness value is less than the second threshold, the data state is judged to be the sixth state, and when the hotness value is greater than or equal to the second threshold and less than or equal to the first threshold, the data state is judged to be the fifth state.

[0064] When performing dynamic adjustment, smoothing adjustment can be performed based on IOPS and read-write ratio. In some embodiments, the host system write IOPS (i.e., the frequency of data write requests issued by the host system), the ratio of data read requests and data write requests can be determined in real time. In the case of high load (write IOPS greater than 80k) (for example, the frequency of data write requests is greater than a first target frequency), the first threshold (Q hot) can be slowly reduced from the current value (for example, 0.5) to a first target value (for example, 0.4) and the second threshold (Q cold) can be slowly reduced from the current value (for example, 0.3) to a second target value (for example, 0.2) in a few seconds, thereby smoothly expanding the hot data pool and ensuring the performance of the memory storage device, wherein the first target value is greater than the second target value.

[0065] In the case of low load (write IOPS less than 20k and read-intensive (Read-intensive)), (for example, the frequency of data write requests is less than a second target frequency), the first threshold (Q hot) can be slowly raised from the first reference value (or from the current value) to a third target value (for example, from 0.5 to 0.6), and the second threshold (Q cold) can be slowly raised from the second reference value (or from the current value) to a fourth target value (for example, from 0.3 to 0.4), thereby smoothly shrinking the hot data pool and optimizing the life of the memory storage device, wherein the third target value is greater than the fourth target value.

[0066] On the basis of setting the cold and hot data dynamic adjustment based on the double threshold mechanism, the number of remaining allocable low wear blocks (i.e. young blocks or target blocks) can also be detected to further adjust the shunting strategy of cold and hot data. In some embodiments, when the number of low wear blocks is lower than a target value (for example, 5% of the total blocks), the memory storage device can be forced to perform a "performance priority" mode, the first threshold (Q hot) is reduced from the current value to a fifth target value (for example, 0.35), the second threshold (Q cold) is reduced from the current value to a sixth target value (for example, 0.15), and the non-critical data migration is suspended, wherein the fifth target value is greater than the sixth target value.

[0067] In some embodiments, when the remaining number of low wear blocks is lower than a preset threshold, the first threshold and the second threshold are adjusted to lower emergency target values, and the non-critical data migration is suspended. By increasing the resource emergency triggering mechanism, self-protection can be achieved in extreme cases (for example, block depletion risk).

[0068] Through the distinction of double thresholds and multiple data states, more refined cold and hot data management is achieved, avoiding the frequent jumping (ping-pong effect) of data between different storage blocks due to cold and hot data classification errors, and smoothing the data migration flow. The system resource allocation is strongly related to the external load, achieving the best balance between the performance and the life of the memory storage device.

[0069] Under the DRAM-less architecture, data migration must be accompanied by mapping table updates, which is a very time-consuming process. Unordered data migration can seriously block the normal data write path, and frequent small-grained write operations can cause serious write amplification problems. In view of this, the migration of data can be managed by setting a migration queue and setting priorities. In some embodiments, a first queue, a second queue and a third queue can be set. Among them, the first queue can be a high-priority migration queue, the second queue can be a medium-priority migration queue, and the third queue can be a low-priority migration queue, and the maximum queue length is set for each queue to prevent queue blocking.

[0070] The high-priority first queue can be used to store "extremely hot" data (for example, second state to-be-written data, i.e. hot data with higher hotness value to-be-written data) with a hotness value greater than a first priority threshold (for example, 0.8) or data urgently triggered by the system to maintain performance (for example, when there are insufficient low wear blocks). It is used to process high-priority migration tasks.

[0071] The second queue of medium priority can place the data of normal hot data to cold data or cold data to hot data (e.g., the third state of data to be written) with a hotness value less than or equal to the first priority threshold and greater than or equal to the second priority threshold. The migration task of the regular priority is used for processing.

[0072] The third queue of low priority can be used for data migration triggered by internal adjustment or background wear leveling of warm data (e.g., the fourth state of data to be written) with a hotness value less than the second priority threshold. The background migration task of the low priority is used for processing.

[0073] After managing the data by queues, batch data migration can be performed. In some embodiments, a migration scheduler can be set, which waits for the state of a single queue to meet a preset condition, for example, the preset condition can include that the data accumulates to a preset number (e.g., 8) of migration tasks or the waiting time exceeds a preset time (e.g., 100 ms), and then the migration task is performed, so as to balance the migration delay and the efficiency of batch migration.

[0074] When the amount of data of a single queue is equal to a preset number or the waiting time is greater than or equal to a preset time, the migration scheduler can read the data blocks corresponding to the migration tasks from the old physical address to the internal buffer at one time, and write the data blocks to the low-wear entity block (e.g., the target entity block). After the data blocks are written successfully, a new mapping table page can be generated, which contains all the updated L2P mapping relationships. Through a minimum atomic write operation supported by the memory module, the new mapping table page is atomically written to the mapping area of the first memory module 206. Thus, the operation is the minimum atomic operation unit supported by the first memory module 206, which ensures that even if the system is powered off, the mapping table is consistent with the data state. After the mapping table is written, the mapping table cache is updated in the second memory module 210, and the old data block address is marked as invalid, waiting for garbage collection.

[0075] In some embodiments, for the data that has been written to the entity block, the hotness value is continuously updated according to its access interval characteristics, so that when there is no new access request, the hotness value naturally decays over time. When the updated hotness value of the data is lower than the second threshold, the resource recycling mark is triggered for the entity block to which the data belongs, and the metadata corresponding to the data is removed or downgraded from the cache. The time decay of the above hotness value and the automatic resource recycling mechanism, i.e., the automatic ability of the system to "forget" or "degrade" cold data, solves the problem of "one-time warming and long-term resource occupation" in traditional algorithms, realizes the dynamic and intelligent recycling of storage resources, and is the key to long-term efficient operation of the system.

[0076] In some embodiments, the host I / O (Input / Output) path can be prioritized. The migration engine runs in a separate low-priority background thread. Migration tasks are set as interruptible units (e.g., read / write of a word entity page). At any time, a host I / O request can immediately preempt the channel resources of the first memory module 206 occupied by the migration operation, and the migration task will be suspended after the current minimum operation unit (e.g., programming of one entity page) is completed, and then resumed after the host I / O is idle. For example, during the execution of a background migration write operation, when a new host input / output request is received, the current migration write operation is paused and the host input / output request is processed in priority. After the request processing is completed, the paused migration write operation is resumed. In this way, the front-end input / output request is not affected by the background management operation.

[0077] The method provided by the embodiments of the present application combines a large number of small random migration requests into a large sequential operation, significantly reducing the write amplification effect and command overhead of the first memory module 206. Through atomic transactional operations, the consistency of the mapping table and the data block is ensured, and the robustness of the system in abnormal power-off scenarios is greatly improved. The preemptible scheduling mechanism ensures that the front-end I / O delay is not affected by the background activity.

[0078] Figure 3 A flowchart of an exemplary memory control method 300 according to an embodiment of the present application is shown. The method 300 can be performed by the memory storage system 100, more specifically, by the memory controller 1043 in Figure 2 and used to control the first memory module 206 and the second memory module 210 in Figure 2 The memory module includes a plurality of entity blocks, and the method 300 can include the following steps.

[0079] In step 302, a data write request from a host system is received, and the data write request includes to-be-written data.

[0080] In step 304, a plurality of access features of the to-be-written data are obtained according to the data write request.

[0081] In some embodiments, the plurality of access features include an access frequency, and the method 300 includes: outputting a count value within a preset time via a sliding time window counter (also referred to as a preset time window) according to the data write request; and obtaining the access frequency according to the preset time and the count value.

[0082] In some embodiments, the plurality of access features comprises an access interval, and the method 300 comprises: obtaining a last access time of a logical address range in the memory module; recording a current access time of the logical address range according to the data write request; and obtaining the access interval according to the last access time and the current access time.

[0083] In some embodiments, the plurality of access features comprises a data block size, and the method 300 comprises: recording an average size of a data segment corresponding to a logical address range of the memory module according to the data write request; and obtaining the data block size according to the average size of the data segment.

[0084] In some embodiments, the plurality of access features comprises an access pattern, and the method 300 comprises: determining a logical address offset of the memory module according to the data write request; obtaining a number of logical addresses of a last data write request; and obtaining the access pattern according to the logical address offset and the number of logical addresses.

[0085] In some embodiments, metadata is maintained for a logical address corresponding to the data to be written to record the plurality of access features; and aggregated access features of a logical address space and a hot and cold label are stored persistently in a metadata area of the memory module; and more fine-grained access features of a current active logical address are cached in a static random access memory of the storage device.

[0086] In step 306, a hotness value of the data to be written is calculated based on a weight dynamic adaptive adjustment mechanism according to the plurality of access features.

[0087] In some embodiments, the data state comprises a first state, and before the hotness value of the data to be written is calculated based on the weight dynamic adaptive adjustment mechanism according to the plurality of access features, the method 300 further comprises: obtaining a number of data blocks accessed and marked as the first state in a past target time period; obtaining a total number of data blocks marked as the first state; determining a data hit rate of the first state according to the number of data blocks and the total number of data blocks; and in response to the data hit rate being lower than a second target hit rate for two consecutive periods, triggering the weight dynamic adaptive adjustment mechanism, wherein the second target hit rate is lower than a preset first target hit rate.

[0088] In some embodiments, in response to the data hit rate being higher than a third target hit rate, the weight dynamic adaptive adjustment mechanism is exited, and the third target hit rate is between the first target hit rate and the second target hit rate.

[0089] In some embodiments, an average value of each of the access features in the past target time window on the data block that is correctly hit by the first state is obtained; a contribution ratio of each of the access features is calculated according to the average value; a first target access feature and a second target access feature in the plurality of access features are determined according to the contribution ratio, the contribution ratio of the first target access feature being lower than the contribution ratio of the second target access feature; a weight value corresponding to the first target access feature is reduced by a step to obtain a first weight; a weight value corresponding to the second target access feature is increased by a step to obtain a second weight; and a hotness value of the to-be-written data is calculated according to the adjusted all weights, the plurality of access features and a hotness calculation formula.

[0090] In some embodiments, the value of the step is dynamically attenuated based on system running time.

[0091] In step 308, a data state of the to-be-written data is determined according to the hotness value, and the to-be-written data is placed in a target queue corresponding to the data state.

[0092] In some embodiments, the target queue includes a first queue, a second queue and a third queue, the data state further includes a second state, a third state and a fourth state, and the method 300 further includes: in response to the hotness value being greater than a first priority threshold, determining the data state of the to-be-written data as the second state and placing the to-be-written data in the first queue corresponding to the second state; in response to the hotness value being less than or equal to the first priority threshold and greater than or equal to a second priority threshold, determining the data state of the to-be-written data as the third state and placing the to-be-written data in the second queue corresponding to the third state; and in response to the hotness value being less than the second priority threshold, determining the data state of the to-be-written data as the fourth state and placing the to-be-written data in the third queue corresponding to the fourth state.

[0093] In some embodiments, the data state further includes a fifth state and a sixth state, and the method 300 further includes: determining a frequency of the data write request issued by the host system; in response to the frequency of the data write request being greater than a first target frequency, reducing a first threshold from a current value to a first target value and reducing a second threshold from a current value to a second target value, the first target value being greater than the second target value, and the first threshold being greater than the second threshold.

[0094] In some embodiments, the method 300 further includes: detecting a remaining number of low-wear blocks in the plurality of entity blocks; in response to the remaining number being lower than a preset threshold, adjusting the first threshold and the second threshold to lower emergency target values, and suspending a non-critical data migration operation.

[0095] At step 310, in response to the state of the target queue satisfying a preset condition, multiple pieces of the to-be-written data in the target queue are written to the physical block corresponding to the data state.

[0096] In some embodiments, in response to the amount of data in the target queue being equal to a preset amount or the waiting duration of the target queue being greater than or equal to a preset duration, multiple pieces of the to-be-written data in the target queue are written to the physical block corresponding to the data state.

[0097] In some embodiments, during the process of performing the migration write operation in the background, in response to receiving a new host input / output request, the current migration write operation is paused and the host input / output request is processed in priority; after the host input / output request is processed, the paused migration write operation is resumed.

[0098] In some embodiments, after multiple pieces of the to-be-written data are written to the target physical block, a mapping table entry containing an updated logical-to-physical address mapping relationship is generated; and the mapping table page is written to the mapping area of the memory module through an atomic write operation supported by the memory module, so as to ensure that the data and the mapping table are consistent in state.

[0099] In some embodiments, the method 300 further includes: for the data that has been written to the physical block, continuously updating the hotness value according to the access interval characteristics thereof, so that the hotness value naturally decays over time when there is no new access request; in response to the updated hotness value of the data being lower than a second threshold value, triggering a resource recycling mark for the physical block to which the data belongs, and removing or downgrading the metadata corresponding to the data from the cache.

[0100] In some embodiments, the method 300 further includes: in response to the frequency of the data write request being less than a second target frequency, increasing the first threshold value from a current value to a third target value and increasing the second threshold value from a current value to a fourth target value, the third target value being greater than the fourth target value.

[0101] In some embodiments, the multiple physical blocks include a target block, and the method 300 further includes: determining the number of target blocks; in response to the number of target blocks being less than a target value, decreasing the first threshold value from a current value to a fifth target value and decreasing the second threshold value from a current value to a sixth target value, the fifth target value being greater than the sixth target value.

[0102] The application provides a memory control method and a memory storage device. The method comprises: receiving a data write request from a host system, obtaining a plurality of access characteristics of to-be-written data according to the data write request, calculating a hot degree value of the to-be-written data based on a weight dynamic self-adaptive adjustment mechanism according to the plurality of access characteristics, determining a data state of the to-be-written data according to the hot degree value, and placing the to-be-written data in a target queue corresponding to the data state. When the state of the target queue meets a preset condition, the plurality of to-be-written data in the target queue are written into an entity block corresponding to the data state. Through the above method, the weight used to calculate the hot degree value can be dynamically adjusted, thereby improving the problem that in the related art, the hot degree value of data is calculated by relying on a fixed weight, which can cause frequent cold-hot data error classification, and then cause a large number of unnecessary mapping table updates and data migration, and affect the performance and service life of the memory storage device.

[0103] The above description of the embodiments is only used to help understand the method of the application and its core idea. It should be pointed out that for those skilled in the art, without departing from the principles of the application, some improvements and modifications can be made to the application, and these improvements and modifications also fall within the protection scope of the claims of the application.

Claims

1. A memory control method, characterized in that, A storage device, the storage device including a memory module, the memory module including a plurality of physical blocks, the memory control method including: Receive a data write request from the host system, the data write request including data to be written; obtain multiple access characteristics of the data to be written based on the data write request; Based on the multiple access characteristics, the popularity value of the data to be written is calculated using a weighted dynamic adaptive adjustment mechanism; based on the popularity value, the data state of the data to be written is determined and the data to be written is placed in the target queue corresponding to the data state, wherein the data state includes a first state; Before calculating the popularity value of the data to be written based on multiple access characteristics and a weighted dynamic adaptive adjustment mechanism, the number of data blocks accessed and marked as first state within the past target time period is obtained, and the total number of data blocks marked as first state is obtained; the data hit rate of the first state is determined based on the number of data blocks and the total number of data blocks; in response to the data hit rate being lower than the second target hit rate for two consecutive periods, the weighted dynamic adaptive adjustment mechanism is triggered, wherein the second target hit rate is lower than the preset first target hit rate; wherein calculating the popularity value of the data to be written based on multiple access characteristics and a weighted dynamic adaptive adjustment mechanism includes: obtaining the past target... The average value of each access feature within the time window on the data block of the first state that is correctly hit; the contribution ratio of each access feature is calculated based on the average value; based on the contribution ratio, the first target access feature and the second target access feature are determined among multiple access features, where the contribution ratio of the first target access feature is lower than that of the second target access feature; the weight value corresponding to the first target access feature is reduced by one step to obtain the first weight; the weight value corresponding to the second target access feature is increased by one step to obtain the second weight; based on all the adjusted weights, multiple access features, and the heat calculation formula, the heat value of the data to be written is calculated. In response to the target queue's state meeting a preset condition, multiple pieces of data to be written in the target queue are written into the entity block corresponding to the data's state.

2. The method according to claim 1, characterized in that, The method further includes: In response to the data hit rate being higher than the third target hit rate, the dynamic adaptive adjustment mechanism for weights is exited, wherein the third target hit rate is between the first target hit rate and the second target hit rate.

3. The method according to claim 1, characterized in that, The target queue includes a first queue, a second queue, and a third queue. The data state also includes a second state, a third state, and a fourth state. The step of determining the data state of the data to be written based on the heat value and placing the data to be written in the target queue corresponding to the data state includes: In response to the heat value being greater than the first priority threshold, the data state of the data to be written is determined to be the second state and the data to be written is placed in the first queue corresponding to the second state; In response to the heat value being less than or equal to the first priority threshold and greater than or equal to the second priority threshold, the data state of the data to be written is determined to be the third state and the data to be written is placed in the second queue corresponding to the third state; In response to the heat value being less than the second priority threshold, the data state of the data to be written is determined to be the fourth state, and the data to be written is placed in the third queue corresponding to the fourth state.

4. The method according to claim 1, characterized in that, The step of responding to the target queue's state satisfying a preset condition by writing multiple pieces of data to be written from the target queue into the entity block corresponding to the data state includes: In response to the data volume of the target queue being equal to a preset quantity or the waiting time of the target queue being greater than or equal to a preset time, multiple data items to be written in the target queue are written into the entity block corresponding to the data status.

5. The method according to claim 1, characterized in that, The data state also includes a fifth state and a sixth state, and the method further includes: Determine the frequency of the data write requests issued by the host system; In response to the frequency of the data write request being greater than the first target frequency, the first threshold is reduced from the current value to the first target value and the second threshold is reduced from the current value to the second target value, wherein the first target value is greater than the second target value and the first threshold is greater than the second threshold.

6. The method according to claim 5, characterized in that, The method further includes: In response to the data write request frequency being less than the second target frequency, the first threshold is increased from the current value to the third target value and the second threshold is increased from the current value to the fourth target value, wherein the third target value is greater than the fourth target value.

7. The method according to claim 5, characterized in that, The plurality of entity blocks includes the target block, and the method further includes: Determine the number of target blocks; In response to the number of target blocks being less than a target value, the first threshold is reduced from its current value to a fifth target value and the second threshold is reduced from its current value to a sixth target value, wherein the fifth target value is greater than the sixth target value.

8. The method according to claim 1, characterized in that, The multiple access characteristics include access frequency. The process of obtaining multiple access characteristics of the data to be written based on the data write request includes: Based on the data write request, the count value within a preset time period is output via a sliding time window counter; The access frequency is obtained based on the preset time and the count value.

9. The method according to claim 1, characterized in that, The multiple access characteristics include an access interval. The process of obtaining multiple access characteristics of the data to be written based on the data write request includes: Obtain the last access time of the logical address range in the memory module; Based on the data write request, record the current access time of the logical address range; The access interval is obtained based on the last access time and the current access time.

10. The method according to claim 1, characterized in that, The multiple access characteristics include the data block size. The process of obtaining multiple access characteristics of the data to be written based on the data write request includes: Based on the data write request, record the average size of the data segment corresponding to the logical address range of the memory module; The size of the data block is obtained based on the average size of the data segments.

11. The method according to claim 1, characterized in that, The multiple access features include access patterns. The process of obtaining multiple access features of the data to be written based on the data write request includes: Based on the data write request, determine the logical address offset of the memory module; Get the number of logical addresses from the previous data write request; The access mode is obtained based on the logical address offset and the number of logical addresses.

12. The method according to claim 1, characterized in that, The step of obtaining multiple access characteristics of the data to be written based on the data write request includes: Maintain metadata for the logical address corresponding to the data to be written, in order to record the multiple access characteristics; and The aggregated access characteristics of the logical address space and the hot and cold tags are persistently stored in the metadata area of ​​the memory module. The finer-grained access characteristics of the currently active logical address are cached in the static random access memory of the storage device.

13. The method according to claim 1, characterized in that, The method further includes: The step size is dynamically decreased based on the system runtime.

14. The method according to claim 5, characterized in that, The method further includes: Detect the remaining number of low-wear blocks among the plurality of physical blocks; In response to the remaining quantity falling below a preset threshold, the first threshold and the second threshold are adjusted to lower emergency target values, and non-critical data migration operations are suspended.

15. The method according to claim 4, characterized in that, The step of writing multiple pieces of data to be written from the target queue into the entity block corresponding to the data state includes: After writing multiple pieces of the data to be written into the target entity block, a mapping table page containing the updated logical-to-physical address mapping relationship is generated; The mapping table page is written to the mapping area of ​​the memory module through a single atomic write operation supported by the memory module, so as to ensure that the data is consistent with the state of the mapping table.

16. The method according to claim 1, characterized in that, The step of responding to the target queue's state satisfying a preset condition by writing multiple pieces of data to be written from the target queue into the entity block corresponding to the data state includes: During the background migration write operation, in response to receiving a new host input / output request, the current migration write operation is paused and the host input / output request is processed first. Once the host input / output request has been processed, the suspended migration write operation resumes.

17. The method according to claim 1, characterized in that, The method further includes: For data that has been written into the entity block, its popularity value is continuously updated according to its access interval characteristics, so that the popularity value naturally decays over time when there are no new access requests. In response to the data's updated popularity value falling below a second threshold, a resource reclamation marker is triggered for the entity block to which the data belongs, and the corresponding metadata is removed from the cache or downgraded for storage.

18. A memory storage device, characterized in that, include: Connection interface, used to connect to the host system; The memory module comprises multiple physical blocks; A memory controller, electrically coupled to the connection interface and the memory module, is configured to perform the method as described in any one of claims 1-17.

Images