Method and device for configuring neural network and electronic component for implementing neural network using analog elements

Abstract

A method for configuring a neural network implemented using analog elements includes, for each of a plurality of configurations of a reconfigurable electronic circuit for implementing the neural network, adapting connections between analog elements of the reconfigurable electronic circuit according to the respective configuration to adapt an architecture of the neural network, and evaluating the input signal using a neural network implemented by the corresponding configuration of the reconfigurable electronic circuit to obtain an inference result of the input signal. An electronic component for implementing an analog neural network, such as an electronic component configured using the disclosed method, includes a reconfigurable electronic circuit including a plurality of resistive elements, a plurality of summing elements, and a plurality of switchable connections, each switchable connection is switchable to establish a connection between one of the resistive elements and one of the summing elements.

Description

Technical Field

[0001] This invention relates to the field of neural networks, and specifically proposes a method and apparatus for configuring neural networks, as well as electronic components for implementing neural networks using analog elements. Background Technology

[0002] Embodiments of the present invention relate to a method for configuring a neural network implemented using analog components. In other words, embodiments of the present invention may refer to a method for configuring electronic circuitry to implement an analog neural network. Further embodiments relate to electronic components for implementing an analog neural network. Further embodiments relate to an apparatus for configuring a neural network implemented using analog components. Embodiments of the present invention may relate to a method for performing neural architecture search on analog neural network hardware.

[0003] Neural networks can be used in a variety of applications, such as for evaluating sensor signals. To reduce power consumption as needed, such as in the field of edge sensors, neural networks can be implemented using analog components to perform neural network operations.

[0004] However, analog neural network hardware can be affected by suboptimal neural architectures resulting from engineers' experience-based decisions and mapping errors caused by process deviations in electronic components. These two factors can lead to significant energy redundancy and decreased computational accuracy, respectively. These drawbacks can shorten the battery life of edge sensor systems using embedded analog neural network hardware and potentially cause unacceptable losses in prediction / classification accuracy. Existing methods cannot simultaneously address both of these issues.

[0005] More specifically, the power consumption of analog neural network hardware is linearly related to the number of electronic computing components used, such as inverting summing operational amplifiers as neurons and resistors as synapses. Larger neural network models require more computational resources and therefore consume more power, but their prediction or classification accuracy is not necessarily much higher compared to smaller models. The computational accuracy of analog neural network hardware depends on the extent to which it can replicate the mathematical calculations performed by the software.

[0006] However, hardware is strongly affected by process variations and parasitic effects, which may cause electronic components to deviate from their ideal state, resulting in unclear mathematical expressions of the hardware.

[0007] Analog neural network hardware refers to application-specific integrated circuits (ASICs) and discrete circuits, which have specific circuit structures and can realize the computational functions of artificial neural networks and spike neural networks.

[0008] Accuracy loss represents the difference between the hardware calculation results and the software baseline. Due to imperfections in electronic components, the calculation results obtained by the hardware are worse than those obtained by the software.

[0009] To address these issues, numerous methods and techniques have been developed at both the software and hardware levels. The first category of software methods involves software-based model compression.

[0010] Quantization: The history of quantized neural networks dates back to the 1990s, initially developed to address the limited computational resolution in optical computers [Fiesler et al., 1990] and the challenges of digital hardware implementation of neural networks [Balzer et al., 1991]. More recently, quantized neural networks have garnered significant attention for their powerful ability to reduce model size. For example, as described [Rastegari et al., 2016], reducing bit precision directly from 64 floating-point to 2 fixed-point can save 32 times the memory and increase the speed of digital implementation by 58 times. Furthermore, the use of quantized neural networks has become crucial for analog neural network hardware, particularly due to the limited number of well-separated memory stages exhibited by emerging non-volatile memories such as memristors and ferroelectric field-effect transistors [Zhang et al., 2020]. By minimizing weight resolution according to hardware requirements, neural networks exhibit greater robustness to computational errors caused by process variations. Hardware-aware quantization introduces random noise and process variations into the quantization training process, further enhancing the network's robustness to hardware error sources in analog neural networks [Klachko et al., 2019], thereby achieving a relatively small decrease in precision. However, due to the lack of weight diversity, quantization techniques inevitably lead to a decrease in accuracy compared to a full-precision baseline. This loss of accuracy becomes even more pronounced when the quantized neural network is mapped onto hardware. In general-purpose in-memory computing systems, using mixed-precision neural networks (where weights and activation functions are quantized with different data precisions) can further improve energy efficiency by leveraging low-resolution data converters. However, this advantage cannot be used in purely analog neural network hardware because data converters can only be used at the input stage to generate appropriate analog data representations. If the input signal is sampled directly from the sensor, a data converter cannot be used at all. Therefore, it is difficult to estimate the large mapping error.

[0011] Pruning: To better integrate neural network models into embedded systems, pruning techniques have been proposed to minimize connections and neurons, rather than using quantization to reduce weight resolution. To this end, pruning algorithms score hyperparameters after initial training and remove hyperparameters based on the estimated scores. Similar to quantization, this process also introduces a loss of accuracy into the neural network. To mitigate this loss, the scaled-down model needs to be retrained to restore accuracy [Han et al., 2015]. Many variations of pruning techniques exist, but most are based on this idea. While this approach can significantly reduce the size of neural networks, thereby reducing power consumption when implementing them in analog hardware, it may not guarantee computational accuracy.

[0012] Robust Coding: To improve computational accuracy, a dedicated coding scheme called "noisy neural network compression" is introduced to account for variations (or noise) in phase-change memory. This scheme utilizes redundant devices to preserve symbols, fully leverages the signal range in the hardware, and maintains a certain level of redundancy [Isik et al., 2020]. By employing this coding scheme, accuracy comparable to the baseline can be achieved. However, it should be noted that suboptimal neural architectures cannot be improved. Furthermore, while the coding scheme only enhances the robustness of the neural network to device variations, it does not completely eliminate the possibility of accuracy loss.

[0013] Matrix and Tensor Decomposition: Since artificial neural networks rely heavily on multiplicative accumulation, it is possible to reduce computational cost by decreasing the size of vectors (tensors) and matrices. This can be achieved by utilizing decomposition techniques, such as singular value decomposition [Xue et al., 2013], a mathematical tool that provides low-rank approximations of tensors and matrices. This approach significantly reduces the size of neural networks and lowers hardware power consumption because it requires fewer computational resources. However, it is important to note that this approach does not enhance robustness to changes in hardware processes, and mathematical approximations may introduce additional computational accuracy errors.

[0014] Other methods have also been explored, such as knowledge extraction [Bucilua et al., 2006] and combinations of various techniques. Furthermore, software-based methods have begun to incorporate hardware constraints during compression to enhance the robustness of neural network hardware. However, these methods often face two challenges: first, compression can only optimize model complexity to a certain extent, thus offering limited improvement in hardware power consumption; second, hardware constraints are typically defined based on statistical observations, meaning that actual hardware may differ from the simulation environment. Therefore, while this approach can improve the robustness of neural networks, it cannot completely eliminate mapping errors.

[0015] The second type of software approach relates to Neural Architecture Search (NAS): NAS is an automated process involving searching for optimal neural architectures by treating the hyperparameters of a neural network (such as depth, width, connections, activation function types, etc.) as tunable parameters in an optimization problem [Bergstra et al., 2011]. Therefore, optimization algorithms such as reinforcement learning [Zoph et al., 2016], Bayesian optimization [Kandasamy et al., 2018], and evolutionary algorithms [Stanley et al., 2002] are frequently applied to this process. A typical NAS process involves three steps: first, generating a large set of architectures; second, training the architectures using a backpropagation-based method; and finally, evaluating the architectures, based on the evaluation results, and deciding whether to select the best architecture or generate a new architecture based on the best architecture in the current iteration and proceed to the next iteration. In this case, the architectures are fully optimized to achieve the target score, with only the essential components being retained. This makes NAS an attractive method for deploying neural networks on hardware, as size-optimized neural networks require fewer computational resources. Recently, hardware-software co-search methods have gained popularity (e.g., [Jiang et al., 2020]), in which multiple agents are used to incorporate hardware constraints such as energy consumption into NAS. This allows for further optimization of the neural architecture for specific hardware architectures and improves robustness by introducing hardware-aware training. However, hardware-software co-search methods face challenges due to limited computational resources, as they are only applicable to small to medium-sized models.

[0016] Weighted Diagnostic Neural Networks (WANN) [Gaier et al., 2019] are an evolutionary algorithm that simplifies the search process by utilizing shared, fixed weights and focusing only on meaningful connections when searching for the architecture. This algorithm greatly simplifies the search process as it eliminates the need for backpropagation-based training. However, similar to other NAS algorithms, the architecture still faces the challenge of mapping errors.

[0017] Hardware-side approaches include on-chip learning, which, as the name suggests, involves performing the learning task partially or entirely on hardware. To compute the gradient at each level, the analog neural network hardware must support bidirectional operation. A common approach is to apply an error signal to the output and propagate it through all intermediate nodes. However, in many cases, intermediate results need to be converted back to a digital representation and post-processed. Newly computed values ​​are written to memory via memory update circuitry [Krestinskaya et al., 2019]. Incorporating real hardware into the training method can significantly reduce mapping errors. Further hardware techniques include offset calibration (e.g., [Zhang et al., 2023]). Low-voltage designs and more efficient computational methods also contribute to reduced energy consumption. However, these techniques alone cannot fully address the fundamental problems of current issues such as accuracy loss and energy consumption.

[0018] Therefore, it is preferable to provide a neural network configuration concept implemented using analog elements, which allows for a better trade-off between the high accuracy and low power consumption of neural networks and the low complexity of neural architectures implemented by analog neural network hardware. Summary of the Invention

[0019] This objective can be achieved through the embodiments described in the independent claims.

[0020] Embodiments of the present invention rely on the idea of ​​incorporating analog neural network hardware into the process of searching for network architectures, namely, configuring analog neural network hardware by evaluating input signals using multiple actual hardware configurations. To this end, a reconfigurable electronic circuit composed of multiple analog elements is used to implement the neural network. The search process includes configuring the reconfigurable electronic circuit and, for multiple different configurations of the electronic circuit, evaluating the input signal using the neural network implemented by the corresponding configuration. Therefore, for each configuration, the actual performance of the neural network implemented by that configuration can be tested.

[0021] One embodiment of the present invention provides a method for configuring (or training or designing) a neural network (such as an artificial neural network) for a predetermined application, said neural network being implemented by a plurality of analog elements of a reconfigurable (or programmable) electronic circuit (such as a reconfigurable or programmable integrated circuit). The method includes configuring (or defining) the connections (e.g., switchable connections) between the analog elements of the reconfigurable electronic circuit according to a corresponding configuration for each of a plurality of configurations of the reconfigurable electronic circuit (e.g., each configuration is represented or characterized by selecting elements from available elements of the reconfigurable electronic circuit and an arrangement of the selected elements (e.g., setting connections between elements)). For example, the analog elements of the reconfigurable electronic circuit include a plurality of summing elements and a plurality of resistive elements. The method further includes, for each configuration of the reconfigurable electronic circuit, evaluating an input signal (e.g., an analog input signal) using the neural network implemented by the respective configuration of the reconfigurable electronic circuit to obtain an inference result of the input signal (e.g., the inference result is associated with the respective configuration). For example, the input signal may represent training data.

[0022] In other words, for example, reconfigurable electronic circuits can provide analog neural network hardware for implementing neural networks. Therefore, for example, a neural network can be an analog neural network. For example, an analog neural network can refer to a neural network implemented or computed (at least partially or entirely) by analog computing circuitry, such as through the accumulation of current and / or charge. In other words, each configuration of the analog neural network hardware can represent an implementation of the corresponding architecture of the neural network. For example, a method of configuring a neural network can be called neural network search, for example, searching for configurations that meet predetermined criteria.

[0023] Mapping errors can be completely eliminated by evaluating the input signal using reconfigurable electronic circuitry in appropriate configurations. In other words, compared to conventional methods, neural network search can be performed by evaluating a set of configurations of reconfigurable electronic circuitry. For example, instead of deriving the desired configuration by configuring the hardware to reflect the resolution of the configurable hardware as closely as possible and mapping the desired configuration to analog neural network hardware, embodiments of the present invention employ various configurations of reconfigurable electronic circuitry to evaluate the input signal, thereby taking into account the characteristics of the actual hardware.

[0024] For example, compared to the methods described above (such as NAS), the statistical model of the hardware may not fully reflect the actual hardware implementation, thus failing to completely eliminate mapping errors. However, embodiments of the present invention employ real hardware during the neural network search process, thereby avoiding mapping errors. Even in the hardware-side methods described above, a digitized weight update loop is included, which is limited by the resolution of synapses and data converters, leading to a small amount of mapping error and hindering architecture optimization.

[0025] According to one embodiment, the method further includes evaluating multiple configurations (e.g., relative to predetermined measures or criteria) based on corresponding inference results to select one of the configurations (e.g., as the final configuration, such as the configuration representing the search results or training results, or as the configuration as a starting point to derive more configurations to be evaluated).

[0026] In other words, for example, a method for configuring a neural network can be based on the evaluation of multiple configurations. In contrast, traditional methods might employ backpropagation of error signals, which requires bidirectionality and further implies that weights must be set to specific values ​​based on the results of backpropagation. By comparison, evaluating various configurations of a reconfigurable neural network might mean adjusting the network's structure. Testing various architectures is less complex and takes into account actual hardware, thus avoiding mapping errors.

[0027] For example, compared to conventional methods such as the hardware methods described above, embodiments of the present invention do not require training based on backpropagation, i.e., determining the error contribution of a single node by backpropagating error signals through a neural network. In other words, embodiments of the present invention can perform neural network training without backpropagation.

[0028] According to one embodiment, the method further includes, for each of a plurality of configurations, providing a configuration signal to the reconfigurable electronic circuit to configure the reconfigurable electronic circuit according to the corresponding configuration.

[0029] According to one embodiment, configuring connections between analog elements of a reconfigurable electronic circuit includes setting (e.g., activating and / or deactivating) switchable connections between multiple neuronal elements (e.g., summing elements, such as summing amplifiers) and multiple synaptic elements (e.g., resistive elements, such as resistors) of the reconfigurable electronic circuit, thereby selecting one set of neuronal elements as neurons of a neural network and another set of synaptic elements as synapses of the neural network (e.g., weighted connections of a neural network, such as connections between neurons). For example, configuring connections between analog elements of a reconfigurable electronic circuit includes setting a pairwise switchable connection between one of the multiple neuronal elements and one of the multiple synaptic elements.

[0030] Therefore, for example, by configuring the connections between neuronal elements and synaptic elements, the architecture of a neural network can be defined for the corresponding configuration of a reconfigurable electronic circuit.

[0031] In other words, for example, a reconfigurable electronic circuit may include neuronal elements that can be selected as neurons in a neural network and synaptic elements that can be selected as synapses in a neural network. For example, a synapse is a weighted connection between neurons in a neural network. In other words, a synapse may have an associated weight, for example, the weight being determined by the resistance of the corresponding synaptic element.

[0032] According to one embodiment, the method further includes determining a set of configurations for a neural network, and for each of the set of configurations: configuring the connections between analog elements of a reconfigurable electronic circuit according to the corresponding configuration to adapt (or define) the architecture of the neural network; processing an input signal (e.g., signaling or representing training data) using the neural network implemented by the corresponding configuration of the reconfigurable electronic circuit to obtain an inference result of the input signal (e.g., associated with the corresponding configuration); and evaluating the set of configurations according to the corresponding inference result (e.g., relative to predetermined measures or criteria). According to this embodiment, the method includes determining another set of configurations for the neural network based on the selected configuration if none of the configurations in the set meets the predetermined criteria (e.g., processing further combinations of configurations as a configuration combination, in other words, re-determining the configuration combination). For example, if the selected configuration meets the predetermined criteria, the method may include selecting the selected configuration as the final configuration.

[0033] In other words, embodiments of the present invention can rely on testing various architectures of neural networks, for example, rather than performing error analysis through backpropagation or similar methods.

[0034] According to one embodiment, determining another set of configurations includes modifications to one configuration within a set of configurations for the simulated neural network, determined from one or more aspects of adding neurons, removing neuronal elements, swapping neuronal elements, adding synaptic elements, removing synaptic elements, and swapping synaptic elements of the simulated neural network. For example, modifications are randomly selected within one or more predetermined constraints. For example, the modification type (e.g., addition, removal, swapping) and one or both of the involved elements are randomly selected within one or more predetermined constraints.

[0035] For example, multiple neuronal elements in a reconfigurable electronic circuit can be nominally equal and / or multiple synaptic elements in a reconfigurable electronic circuit can be nominally equal. Therefore, for instance, one element can be selected regardless of the nominal properties of each element (such as resistance or offset).

[0036] In other words, the embodiments can leverage the concept of simulating neural network hardware, utilizing process variations of nominally equal components. In conventional methods, the diversity of weights and biases is obtained through training, while the method disclosed herein can utilize the diversity of weights, biases, and even activation functions obtained through process variations to construct an effective architecture. In this case, process variations are no longer a problem leading to mapping errors, but rather a benefit of having a certain search space.

[0037] In other words, embodiments of the method for performing neural architecture search on such simulated neural network hardware described herein can use evolutionary algorithms to find the optimal architecture, while process variations provide sufficient diversity. Therefore, backpropagation-based training is unnecessary. For example, evolutionary algorithms can be implemented via specific hardware mutations and crossover operations, detailed below. Unlike traditional methods, network architecture search, such as neural network training, is directly applied to simulated neural network hardware, such as reconfigurable electronic circuits.

[0038] According to one embodiment, the method includes storing the final configuration of the neural network in a storage element, such as volatile or non-volatile memory. For example, the storage element is part of an integrated circuit that includes reconfigurable electronic circuitry. Storing the final configuration in the storage element fixes the configuration of the simulated neural network in the desired application.

[0039] Another embodiment of the invention provides an electronic component (such as an ASIC) for implementing an analog neural network, the electronic component including reconfigurable electronic circuitry. The reconfigurable electronic circuitry includes a plurality of resistive elements (such as resistors) (e.g., used as connection weights in the analog neural network, such as synapses). The reconfigurable electronic circuitry also includes a plurality of (e.g., analog) summing elements (e.g., each summing element is configured to provide an output signal that is a function of the sum of a plurality of input signals of the summing element) (e.g., summing amplifiers, such as inverting summing amplifiers, such as operational amplifiers) (e.g., for acting as neurons in the analog neural network). The reconfigurable electronic circuit further includes multiple switchable connections, each switchable connection being switchable to establish (e.g., switchable to connect or disconnect, e.g., switchable to activate or deactivate) a connection (e.g., exactly one) between a resistive element and a summing element (e.g., exactly one), wherein the configuration (e.g., setting) (e.g., determining whether each switchable connection is on or off) of the switchable connections defines the architecture (or topology or structure) of the analog neural network, wherein the summing element serves as a neuron, and the resistive element serves as synaptic weights between neurons or between the input connectors of the analog neural network and neurons.

[0040] The reconfigurable electronic circuit includes switchable connections between resistive and summing elements, allowing the electronic element to be configured in multiple different configurations representing different architectures of an analog neural network. Therefore, different configurations of the electronic element can be evaluated in hardware to implement the neural network, with one configuration being selected as the final configuration for running the neural network. Since the configuration corresponds to one of the tested configurations, the electronic element can implement the neural network in analog elements without incurring mapping errors compared to the training process.

[0041] According to one embodiment, the electronic component includes a cross switch (e.g., referred to as a first cross switch) for providing a switchable connection (e.g., paired connection) between each of the outputs of a plurality of resistive elements and each of the inputs of a summing element. Alternatively or additionally, the electronic component includes a cross switch (e.g., referred to as a second cross switch) for providing a switchable connection (e.g., paired connection) between each of the outputs of a plurality of summing elements and each of the inputs of resistive elements (wherein the second cross switch also provides a switchable connection between each of one or more input connectors of the reconfigurable electronic circuit and each of the inputs of the resistive elements). The cross switch provides switchable connections between each pair of elements in the first and second sets of elements, thus allowing any output of a resistive element to be connected to any input of a summing element, and / or any output of a summing element to any output of a summing element, thereby providing high flexibility in defining the architecture of the neural network.

[0042] According to one embodiment, the electronic component includes one or more storage elements for storing a configuration of switchable connections.

[0043] According to one embodiment, the plurality of resistive elements are nominally equal (e.g., all of the plurality of resistive elements have the same nominal resistance value). Alternatively or additionally, the plurality of summing elements are nominally equal (e.g., all elements in the plurality of summing elements have the same nominal feedback resistance value and the same nominal offset voltage (e.g., as a bias in a neural network)).

[0044] For example, embodiments of the present invention utilize statistical process variations in the fabrication of reconfigurable electronic circuit components to provide different weights and / or activations and / or biases to a neural network by selecting components from a pool of available components in the reconfigurable electronic circuit. In other words, instead of making the architecture robust to process variations as in conventional methods, embodiments of the present invention leverage process variations to provide diversity, thus potentially eliminating the need for training (e.g., in the sense of adjusting weights). Instead, the neural network can be defined purely by selecting components and their interconnections.

[0045] According to one embodiment, the resistance values ​​of the multiple resistive elements deviate between 5% and 50%, or between 5% and 30%. Alternatively or additionally, a summing element is used as an operational amplifier. The operational amplifier offset voltage deviates between 5mV and 100mV, and / or the operational amplifier feedback resistor value deviates between 5% and 50%, or between 5% and 30%. These ranges provide sufficient diversity for the available set of values ​​for weighting, activation, and / or bias.

[0046] According to one embodiment, the electronic component is implemented as an integrated circuit, and the electronic component further includes an input interface (e.g., a digital interface). According to the embodiment, the electronic component is configured to receive a configuration signal via the input interface and configure a switchable connection according to the configuration signal. Therefore, neural network search or neural network configuration can be performed by a separate device, thereby reducing the complexity of the electronic component.

[0047] According to one embodiment, the method includes configuring a reconfigurable electronic circuit according to any embodiment of the electronic components described above.

[0048] Another embodiment of the present invention provides an apparatus for configuring a neural network (e.g., designing a simulated neural network according to a predetermined application) (e.g., application-specific simulation (e.g., simulating an artificial neural network)). The apparatus includes electronic components according to any of the above embodiments and a processing unit (e.g., a CPU unit) configured to perform the method according to any of the above embodiments.

[0049] According to one embodiment, the device is implemented as an integrated electronic circuit. Therefore, the processing unit and the reconfigurable electronic circuit can be integrated into a single integrated circuit. Attached Figure Description

[0050] The embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings, wherein:

[0051] Figure 1 A method for configuring a neural network according to one embodiment is shown.

[0052] Figure 2 An electronic component according to one embodiment is shown.

[0053] Figure 3 Another embodiment for configuring a neural network method is shown.

[0054] Figure 4 An interface for a neural network configuration method according to one embodiment is shown.

[0055] Figure 5A Another embodiment of the method for configuring a neural network is shown.

[0056] Figure 5B This illustrates a traditional approach to configuring a neural network.

[0057] Figure 6 The mutation of the neural network configuration is shown according to one embodiment.

[0058] Figure 7A , 7B The cross operation for deriving the neural network configuration according to the embodiment is shown.

[0059] Figure 8 An example of a neuronal element implemented as an inverting summing amplifier according to an embodiment of the present invention is shown.

[0060] Figure 9 Another embodiment of the electronic component is shown.

[0061] Figure 10 An integrated implementation of electronic components according to one embodiment is shown.

[0062] Figure 11 An implementation of an apparatus for configuring a neural network with an external controller, according to one embodiment, is shown.

[0063] Figure 12 An implementation of an apparatus for configuring a neural network with an external controller and integrated sensors, according to one embodiment, is shown.

[0064] Figure 13 An implementation of an apparatus for configuring a neural network with an integrated controller and integrated sensors, according to an embodiment, is shown.

[0065] Figure 14 An interface for providing input data according to an embodiment is shown.

[0066] Figure 15 An example of a method for simulating the configuration of a neural network is shown.

[0067] Figure 16 shows a simulated network architecture example.

[0068] Figure 17 A comparison between conventional methods and embodiments of the present invention is shown. Detailed Implementation

[0069] Embodiments of the invention will now be described in more detail with reference to the accompanying drawings, in which identical or similar elements, or elements having the same or similar functions, are identified by the same reference numerals or the same names. In the following description, numerous details are set forth in order to provide a comprehensive explanation of the embodiments of this disclosure. However, it will be apparent to those skilled in the art that other embodiments may be implemented without these specific details. Furthermore, unless otherwise specifically stated, features of the different embodiments described herein may be combined with each other.

[0070] Figure 1 A block diagram of a method 100 for configuring a neural network according to one embodiment is shown. According to method 100, the neural network is implemented by a plurality of analog elements of a reconfigurable electronic circuit, for example, as will be described below. Figure 2 Describe it. According to... Figure 1Method 100 includes performing steps 120 and 140 for each of a plurality of configurations 22 of a reconfigurable electronic circuit, for example, referring to Figure 2 The described reconfigurable electronic circuit 12 can be referred to as analog neural network hardware. Step 120 includes configuring connections between analog elements of the reconfigurable electronic circuit according to a corresponding configuration to adapt to the architecture of the neural network. Step 140 includes evaluating an input signal (e.g., one or more input signals or an input signal including one or more elements) using a neural network implemented by the corresponding configuration of the reconfigurable electronic circuit to obtain an inference result of the input signal.

[0071] Therefore, for example, method 100 can incorporate analog neural network hardware 12 into the neural architecture search process, such as through genetic encoding, thus eliminating the need for backpropagation-based training. For instance, in embodiments using multiple nominally equal neuronal and / or synaptic elements, the precise values ​​of individual elements are unknown, and therefore, fine-tuning of individual elements and backpropagation-based training may be infeasible in such embodiments. Instead, according to embodiments, the architecture can be evaluated holistically on actual hardware.

[0072] Figure 2 An electronic component 10 for implementing an analog neural network according to one embodiment is shown. In other words, the electronic component 10 can be configured to implement a neural network using analog elements. The electronic component 10 includes a reconfigurable electronic circuit 12. The electronic circuit includes a plurality of resistive elements 24 and a plurality of summing elements 26. Figure 2 For illustrative purposes, the plurality of resistive elements 24 include resistive elements S1, S2, and S3; and the plurality of summing elements 26 include summing elements N1, N2, and N3. For example, resistive elements can serve as synaptic elements in a neural network implemented by a reconfigurable electronic circuit, and summing elements can serve as neuronal elements in the neural network; these terms may be used hereinafter. The reconfigurable electronic circuit 12 also includes a plurality of switchable connections. Figure 2The diagram shows two switchable connection blocks 321 and 322, each representing multiple switchable connections between each of a plurality of resistive elements and each of a summing element. For example, switchable connection block 321 represents multiple switchable connections, where each switchable connection connects the output of one of the summing elements to the input of one of the resistive elements. Similarly, the switchable connections of block 322 can represent multiple switchable connections, where each connection connects the output of one of the resistive elements to the input of one of the summing elements. For example, multiple switchable connections can include switchable connections between a corresponding output of each synaptic element and a corresponding input of each neuron element, and switchable connections between the respective outputs of each neuron element and the respective inputs of each synaptic element. For example, the reconfigurable electronic circuit 12 can be referred to as analog neural network hardware.

[0073] For example, the summing element can be implemented as an operational amplifier, such as an inverting summing operational amplifier. In this case, the value of the feedback resistor of the operational amplifier can define the slope of the activation function of each neuron, and the offset voltage of the operational amplifier can define the deviation of each neuron represented by the operational amplifier.

[0074] It is important to note that the input of a neuron element can be connected to one or more synaptic elements. Therefore, for example, by setting switchable connections, one or more or all neuron elements can be selected to be connected to each other sequentially or in parallel via synaptic elements, thereby defining the architecture of the neural network, where the synaptic elements, through the resistance of resistive elements, can act as weighted connections between neuron elements.

[0075] In other words, for example, an analog neural network includes multiple summing elements interconnected as neurons, such that a neuron in the analog neural network receives the corresponding outputs of one or more of the multiple neurons as input, each output being weighted by a corresponding weight before being provided as input to the neuron. For example, the input of one summing element has one or more connections to the respective outputs of one or more other summing elements or one or more input connectors of a reconfigurable electronic circuit, the one or more connections including corresponding resistive elements.

[0076] According to one embodiment, the reconfigurable electronic circuit may include more switchable connections, each switchable to establish a connection between one of one or more input interfaces and one of a resistive element. The input interfaces can be used to receive input signals 14 from various elements, such as... Figure 2 As shown. Similarly, reconfigurable electronic circuitry may include further switchable connections ( Figure 2(Not shown in the image), each switchable connection can establish a connection between one output terminal of a neuronal element and one of one or more output terminals, the output terminal being configured to provide an output signal 16. Therefore, the output signal may include one or more elements, each provided to a respective output terminal, which may include the individual elements.

[0077] According to one embodiment, the switchable connection can be implemented in the form of one or more cross switches, such as... Figure 10 As described above. For example, Figure 2 Block 321 in the diagram can represent a first cross switch, and block 322 can represent a second cross switch. Optionally, the reconfigurable electronic circuit 12 may include a third cross switch that receives the output of the neuron element 26 as an input and is connected on the output side to one or more output terminals of the output neurons. For example, each cross switch may include a switchable connection between a pair of input terminals and a pair of output terminals of the corresponding cross switch.

[0078] In other words, switchable connectivity allows neuronal elements to connect to each other via synaptic elements to form a neural network through which input signals provided as input interfaces of input neurons can be propagated to obtain output signals of output neurons of the neural network.

[0079] For example, the neural network defined by the reconfigurable electronic circuit configuration can be forward-connected.

[0080] For example, neuronal elements can be assigned to layers, with each neuron receiving signals from one or more neuronal elements in one or more previous layers, where optionally, one or more layers can be skipped. In other words, for example, a neural network defined by a reconfigurable electronic circuit configuration can include direct connections and skipped connections, as shown in Figure 16.

[0081] According to one embodiment, the neural network may include recurrent connections.

[0082] As an alternative to amplifier-based neurons, according to one embodiment, the neuronal element can be implemented as an integrated-emitting neuron. Therefore, the neural network can be implemented as a spike neural network.

[0083] According to one embodiment, the plurality of resistive elements 24 are nominally equal. In other words, the resistive elements among the plurality of resistive elements 24 may all have the same nominal resistance value, but the resistance values ​​of the resistive elements may be different due to inherent process differences in the manufacturing process of the electronic circuit 12.

[0084] According to one embodiment, the plurality of summing elements 26 are nominally equal. In other words, the nominal resistance values ​​of the feedback resistance and / or offset voltage of the summing elements of the plurality of resistive elements 26 may be the same, but the resistance values ​​and / or offset voltages may differ due to inherent process differences in the manufacturing process of the electronic circuit 12.

[0085] In other words, the ability to change the weights, activations, or biases of a neural network can be achieved by swapping one synaptic element with another or one neuron with another, where the actual values ​​associated with each element may be unknown, and thus such modifications can be made randomly. Therefore, embodiments of the invention rely on the idea of ​​configuring (or searching for) neural network structures by utilizing variations in the production process to adjust the neural network structure.

[0086] In other words, according to one embodiment of the proposed analog neural network hardware system, from a design perspective, all elements of a type (such as neurons and synapses) may be the same, but their actual values ​​are actually different.

[0087] For example, the resistance values ​​of multiple resistive elements may vary between 5% and 50%, or between 5% and 30%.

[0088] For example, the summing element is implemented as an operational amplifier. For example, the deviation range of the operational amplifier offset voltage is between 5mV and 100mV, and / or the deviation range of the operational amplifier feedback resistor value is between 5% and 50%, or between 5% and 30%.

[0089] For example, the resistive element and the summing element can be fixed. For instance, the resistive element can have a fixed resistance, and the summing element can be implemented as an operational amplifier with a fixed offset voltage and / or a fixed resistance of its feedback resistor.

[0090] According to the embodiments, one or more sets of resistive elements and / or summing elements may be used, each set having nominally equivalent elements.

[0091] According to one embodiment, all resistive elements in the reconfigurable electronic circuit are nominally equal.

[0092] According to another embodiment, the reconfigurable electronic circuit may include a plurality of additional resistive elements of nominal equal value, wherein the nominal resistance values ​​of the additional resistive elements are different from those of the plurality of resistive elements 24. The additional resistive elements may be individually connected to the plurality of summing elements via switchable connection methods, for example, in the same manner as the plurality of resistive elements 24.

[0093] According to one embodiment, all summing elements of a reconfigurable electronic circuit are nominally equal.

[0094] According to another embodiment, the reconfigurable electronic circuit may include a plurality of additional summing elements of nominal equal value, wherein the nominal resistance and / or offset voltage of the additional summing elements are different from the nominal resistance and / or offset voltage of the plurality of summing elements 26. The additional summing elements may be individually connected to the plurality of resistive elements via a switchable connection method, for example, in the same manner as the plurality of resistive elements 24.

[0095] For example, existing mixed-signal and digitally evolvable implementations rely on backpropagation-based training, whereas the embodiments described herein may rely on the idea of ​​providing diversity by leveraging process variations, rather than making the architecture robust to process variations. Therefore, once the architecture is found, no additional weight training is required. For example, as... Figure 5A The hardware and netlists may be included in the loop of the evolutionary algorithm. For example, the goal might be to find the optimal combination of hardware to achieve a specific objective. For instance, to derive the architecture to be evaluated, specialized hardware operations such as mutation and crossover can be used, for example, as described below. Figure 6 As shown in Figure 7.

[0096] According to one embodiment, the electronic component includes one or more storage elements for storing a configuration of switchable connections.

[0097] According to one embodiment, one or more storage elements may be non-volatile storage elements. Therefore, they can store configurations after the electronic components are powered off.

[0098] According to another embodiment, one or more storage elements can be implemented as a one-time programmable memory, such as an electronic fuse (eFuses), as follows: Figure 12 As stated above.

[0099] It should be noted that the electronic component 10 may include multiple analog neural network hardware units, such as multiple reconfigurable electronic circuits 12. In this case, the method 100 may include determining the configuration of each of the reconfigurable electronic circuits 12 so that each of them satisfies global optimum.

[0100] The following continues the description. Figure 1 Method 100, wherein the reconfigurable electronic circuit mentioned in the context of method 100 may optionally follow... Figure 2 The electronic circuit 12 is implemented as described, wherein, for example, the analog elements may include neuronal elements (such as summing elements) and synaptic elements (such as resistive elements).

[0101] For example, configuring the connection between analog elements according to step 120 of method 100 may include setting (e.g., enabling or disabling) switchable connections between neuronal and synaptic elements of reconfigurable electronic circuit 12.

[0102] For example, step 120 of configuring the connection may include providing a configuration signal 34 to the reconfigurable electronic circuit 12, such as Figure 2 As illustrated in the example, the reconfigurable electronic circuit 12 is configured according to the corresponding configuration.

[0103] like Figure 1 As shown, method 100 may optionally include step 180 of evaluating multiple configurations based on corresponding inference results to select one of the configurations. To evaluate the configuration, metrics, measurements, or standards may be applied to the corresponding inference results. For example, the metrics or standards on which the evaluation of the configuration is based may include one or more of the following: inference accuracy (e.g., expressed as the magnitude or specification of an error or error signal), energy consumption of the inference process, and time consumption of the inference process.

[0104] For example, method 100 may include iteratively evaluating the configuration of the reconfigurable electronic circuit until the configuration meets predetermined criteria. The predetermined criteria may be based on the metrics described above for evaluating the configuration.

[0105] For example, configurations can be evaluated in groups. That is, method 100 may include evaluating one or more groups of configurations. For example, method 100 may begin by evaluating a first group of configurations. If any configuration in the first group meets a predetermined criterion, that configuration can be selected as the final configuration; if no configuration meets the predetermined criterion, method 100 may continue to derive another group of configurations to be evaluated. In other words, method 100 may include iteratively evaluating configuration groups until a configuration meets a predetermined criterion. The following will combine... Figure 5A A detailed implementation example, including configuration group evaluation, is described.

[0106] Figure 3 A block diagram of a method 200 according to one embodiment is shown. In the example, method 200 may be... Figure 1 Implementation of method 100. For example... Figure 3 As shown, method 200 includes block 201 where an evolutionary algorithm is executed by a controller. For example, in block 201, a configuration of analog neural network hardware, such as reconfigurable electronic circuit 12, such as discrete circuits and integrated circuits, can be derived. The configuration is provided to the analog neural network hardware, which, in block 202 of method 200, performs inference on input signals (such as training data). The results are provided to the controller, which evaluates the inference results and / or further metrics of the inference.

[0107] Therefore, for example, block 202 may include steps 120 and 140 of performing method 100. In the example, block 201 may include step 180 of performing method 100.

[0108] In other words, for example, method 200 views the entire setup as two main parts: the controller and the hardware. The controller can be a circuit or system capable of performing the basic operations required by the evolutionary algorithm and temporarily storing intermediate results. For example, the controller can be implemented as an application-specific integrated circuit (ASIC) or an embedded system based on a microprocessor or field-programmable gate array (FPGA).

[0109] For example, two interaction modes were designed for the search process: exploration and development. In the exploration phase, the controller generates a neural network architecture and sends it to the hardware, which then builds the corresponding neural network. In the development phase, the hardware receives training data from the controller, performs neural network inference, and sends the inference results back to the controller. The controller evaluates the current network architecture and generates more potential architectures based on the evaluation results of the next exploration phase. For example, the entire neural architecture search process continues until the target prediction or classification accuracy is achieved.

[0110] Figure 4 A block diagram of method 300 according to one embodiment is shown. For example, method 300 may be an implementation of method 200 and / or method 100, wherein Figure 4 An example of the interface between the controller and the simulated neural network hardware is shown, in which Figure 4 Blocks 311, 313, 315, and 317 on the software side shown can be executed by the controller, while Figure 4 Blocks 321, 323 and the hardware side shown can be executed by analog neural network hardware.

[0111] Starting from the hardware side, in block 321, control signals can be directly generated based on configuration data stored in memory, which may be part of analog neural network hardware, such as electronic circuitry 10. The control signals define the hardware connections between synapses and neuronal elements. The control signals can be provided to reconfigurable electronic circuitry 12. By performing inference on the hardware in block 323, the inference results and optional other relevant metrics (such as energy consumption and timing penalties) are provided by the hardware to the controller.

[0112] For example, hardware components are indexed and used to generate virtual structures. The controller can, for example, use received inference results and other metrics to determine the corresponding fitness score to evaluate the configuration. An evolutionary algorithm is executed in block 313 based on the hardware utilization marked in the hardware pool (see block 311) and the fitness score. For example, the evolutionary algorithm can start from a previously evaluated configuration, such as a previously evaluated configuration or a configuration selected from a set of previously evaluated configurations, utilizing available resources. A new architecture or generation is generated in the evolutionary algorithm, which should be tested on the hardware, first exported as a netlist, such as a description of the connection settings of the reconfigurable electronic circuit 12, see block 315, and then converted to a binary representation, see block 317. The binary representation can be converted into logic signals and passed to the hardware via a specific communication protocol. The hardware memory will be written according to these logic signals, and the hardware architecture will be changed by passing control signals to the components.

[0113] Figure 5A A block diagram of method 400 according to one embodiment is shown. For example, method 400 may be an implementation of one or more methods 100, 200, 300. Method 500 includes step 501: generating a population of various architectures, in other words, generating a set of architectures for a neural network, for example, generating a set of configurations for reconfigurable electronic circuit 12. For example, step 12 may be performed based on analog elements available in the neural network hardware. Then, the architectures are evaluated one by one by generating a netlist for the currently evaluated architectures in step 502. In other words, configuration signals for configuring the neural network hardware (such as reconfigurable neural network 12) are generated and sent to the hardware in step 520 to configure the analog neural network hardware. In step 522, training data is sent to the neural network hardware, for example, as an input signal. In step 540, inference is performed on the training data by the analog neural network hardware. Note that block 510, consisting of steps 520, 522, and 540, is performed on the analog neural network hardware. In step 550, inference performed on the architectures for the group is evaluated based on inference performance (e.g., accuracy) and / or hardware performance (e.g., power consumption and / or time consumption), and the architectures in the group are ranked. If the best architecture meets the objective, such as a predetermined criterion, it is used as the final architecture; otherwise, the method continues to step 501, generating a new set of architectures, for example, starting from one or more best architectures in the previous group, such as one, two, or four best architectures in the previous group. In step 580, the best architecture is derived, for example, by storing it in simulated neural network hardware.

[0114] Therefore, more generally speaking, Figure 5A The further details described are optional, and method 100 includes step 501 of determining a set of configurations for the neural network. For example, the set of configurations could be... Figure 1This is a portion of the multiple configurations 22. For each of the group configurations, the method may include: step 520 of configuring the connections between analog elements of the reconfigurable electronic circuit according to the corresponding configuration to adapt to the architecture of the neural network; step 540 of processing the input signal using the neural network implemented by the corresponding configuration of the reconfigurable electronic circuit to obtain an inference result of the input signal; and step 550 of evaluating the group configurations based on the corresponding inference result. If none of the group configurations meets a predetermined criterion, method 100 may continue to determine another group configuration of the 501 neural network according to the selected configuration.

[0115] According to one embodiment, the step of determining another set of configurations, such as step 501, is performed by determining a modification relative to a configuration in the configuration group (e.g., the configuration ranked highest relative to a predetermined criterion, according to which the configuration is evaluated), the modification involving one or more of the following in a neural network: adding neurons, removing neuronal elements, swapping neuronal elements, adding synaptic elements, removing synaptic elements, and swapping synaptic elements.

[0116] According to one embodiment, modifications are performed starting from a merged configuration, which is obtained by merging two or more configurations in a merge group, as described below.

[0117] According to one embodiment, the step of determining another set of configurations, such as step 501, is performed by merging two or more configurations in that set, for example, by evaluating the configurations according to a predetermined criterion, whereby the two or more configurations rank highest relative to a predetermined criterion. For example, merging two or more configurations can be done as follows: Figure 7A and Figure 7B The process described herein can be referred to as crossover.

[0118] Figure 5B A conventional software-based neural architecture search is illustrated for comparison: First, in step 591, an initial population is randomly generated, typically consisting of a set of different neural architectures. Second, in step 592, each architecture in the population is trained using backpropagation or weight adjustment to achieve optimal training accuracy. After network training is complete, inference is performed in step 593, and fitness scores are calculated by combining the inference results with other custom constraints. After traversing all architectures in the population, the architectures are ranked according to their individual fitness scores in step 594. If the architecture with the highest score meets the requirements, the search process successfully terminates, and the optimal architecture is output in step 595. Otherwise, the best few architectures (typically two to four) are used to generate a new generation and are used in subsequent exploration steps.

[0119] In contrast, in the examples, embodiments of the present invention do not use backpropagation training or any other techniques to fine-tune the weights, as shown in 5B. Furthermore, instead of performing inference in software, method 500 introduces additional steps to generate a hardware-compatible netlist, enabling inference to be performed directly on the hardware. For example, the output from the hardware would be used directly to calculate the fitness score. Another possibility is to synthesize the fitness score, taking into account other aspects of hardware performance, such as power consumption and timing penalties, which can be directly extracted when performing inference on the hardware.

[0120] The following will provide an example of determining the architecture group mentioned in step 501 of Figure 5.

[0121] According to one embodiment, the process of generating a new set of architectures is as follows: First, the best architectures from the previous set are combined (a process known as crossover) to form a new baseline structure. Second, numerous variations of the baseline structure are created based on mutation operations, which can be categorized as structural mutations and non-structural mutations. Structural mutations refer to directly altering the neural structure by adding, removing, adding, or removing synapses. Structural mutations can directly manipulate synaptic and neuron indices without changing their values, whereas non-structural mutations randomly change the weights and / or biases of synapses and neurons, respectively. For example, in this embodiment, the random changes to the weights and biases of synapses and neurons can be achieved by randomly swapping a synaptic element with another available synaptic element or by randomly swapping a neuron element with another available neuron element, respectively.

[0122] Figure 6 A neural network architecture derived through mutation according to one embodiment is shown. Figure 6 The document describes an exemplary implementation of analog neural network hardware (e.g., reconfigurable electronic circuit 12), which includes synaptic elements, neuronal elements, and connections, such as... Figure 2 The number of synaptic and neuron elements in simulated neural network hardware is limited. Furthermore, in some embodiments, their randomness is limited by process variations. For example, as a commonly used electronic synapse, the resistor's nominal resistance is W, with a tolerance of 20%, which means... This results in random resistance values ​​between 0.8W and 1.2W. This also applies to other key metrics, such as the bias and slope of the activation function. It should be noted that, as mentioned above, other bias values ​​or multiple sets of components with different nominal values ​​can be used. Furthermore, Figure 6 The description also applies to embodiments where components with different nominal values ​​are selected through design. For example... Figure 6 As shown, the simulated neural network hardware includes flexible connections (such as switchable connections) to enable flexible connections with a certain degree of freedom between synapses and neurons.

[0123] As previously described, according to one embodiment, the elements of synapses and neurons have the same nominal value. This means that their true values ​​are unknown to the outside world and should exhibit a statistical distribution. In this case, a non-structural mutation can be transformed into a structural mutation simply by swapping the currently used element with an idle element randomly selected from the hardware pool.

[0124] Figure 6 The right side illustrates various possible mutations that derive new architectures from previous architectures, including structural and non-structural mutations. Structural mutations include mutation 601 (adding connections), mutation 602 (removing connections), mutation 603 (adding neurons), and mutation 604 (removing neurons). Non-structural mutations include mutation 605 (updating weights) and mutation 606 (updating biases).

[0125] Figure 7A and Figure 7B This paper presents a scheme to resolve hardware conflicts when determining a new architecture. Hardware conflicts can arise due to the constraint of available hardware resources on component selection, and appropriate mechanisms must be used to resolve them. For mutations, components are released or locked in the controller after removal and addition, preventing reuse during exploration. Nevertheless, cross-operations (i.e., combining two previous architectures) can still be affected by hardware conflicts. We propose a two-step approach to address this constraint: First, mutation is performed only once, minimizing the differences between the two variants of the new architecture. Second, used components are marked as "occupied" in a centralized list, reducing their inheritance probability elsewhere to zero. Figure 7A and Figure 7B As shown.

[0126] In the following sections, embodiments of synaptic elements and neuronal elements will be described, as they can be based on... Figure 1 Method 100 and according to Figure 2 The electronic circuitry or any other embodiment described herein may be used to implement it.

[0127] According to one embodiment, the neuronal element, such as a summing element, is implemented as an operational amplifier, for example, as an inverting summing amplifier, as follows: Figure 8 As shown.

[0128] Figure 8 An example of a neuronal element implemented as an inverting summing amplifier according to one embodiment is shown. Figure 8 As shown, the neurons of the neural network can be implemented as an inverting summing amplifier 826, including a feedback resistor 828 and an offset voltage 829. Figure 8 In the example, the input of amplifier 826 is connected to three synapses 824, each of which is implemented by a resistor.

[0129] For example, the mathematical expression for an artificial neuron can be:

[0130]

[0131] Where, x in,x w x Let and b represent the input, synaptic weights, and bias, respectively. Furthermore, f(x) is a non-linear activation function, and Y... OUT It is the output of the neuron. For example... Figure 8 As shown, the function can be implemented in hardware using circuitry. Without considering any process variations or hardware limitations, the amplifier output is:

[0132]

[0133] This is exactly the same as the accumulation-multiplication operation performed by artificial neurons. In fact, amplifiers typically have nonlinearity and saturation maxima, so they can be viewed as activation functions similar to tanh, such as... Figure 8 As shown in Figure 890, the function can be rewritten as follows:

[0134]

[0135] In this way, the circuit has a complete artificial neuron function, where the input resistors R1, R2, and R3 are the weights, and any other resistors belong to the neurons.

[0136] As mentioned earlier, the circuit may be affected by resistance ΔR. x and ΔR FB and amplifier offset ΔV OFFSET The process changes affect the slope and midpoint of the amplifier's transfer function.

[0137]

[0138] This change will be reflected in changes to the weights and biases. In traditional methods, this change can lead to computational errors, thereby reducing inference accuracy.

[0139] According to embodiments of the present invention, hardware-induced computational errors can be addressed, and even utilized to maintain diversity in the neural architecture search process. For example, the specific steps are as follows: First, resistors and amplifiers with feedback resistors are categorized into synaptic element pools and neuron element pools. Second, an evolutionary algorithm selects elements from the two pools and connects them via configurable hardware connections. Then, an input voltage derived from training data or other input signals is applied, and the result is calculated.

[0140] Various embodiments of the electronic component 10 that can be used with the analog neural network hardware 12 will be described below. Generally, the method 100 for configuring the neural network (e.g., referred to as an evolutionary algorithm) can be executed either on-chip or off-chip. In other words, the processing unit that controls the method, for example in the sense of providing configuration, evaluating inference results, and determining further configuration results when needed, can be implemented either as part of an electronic component in the form of an integrated circuit or as a separate component that can be connected to the electronic component 10 for configuring and configuring the neural network.

[0141] In other words, the method can be used for a wide range of customized applications, such as edge sensor systems that require minimal power consumption and compact AI models to perform tasks such as early prediction, classification, and motion control. The analog neural network hardware performs computations in the analog domain, providing a direct analog interface between the sensor and the neural network.

[0142] Figure 9 Another embodiment of the electronic component 10 is shown, for example, referred to as analog neural network hardware 90. Therefore, Figure 9 Any details described herein may be presented individually or in any combination thereof. Figure 2 It is implemented in electronic component 10.

[0143] like Figure 2 The reconfigurable electronic circuit 12 may include one or more output terminals (such as...) Figure 9 The input buffer 46 in the diagram represents) and / or one or more input interfaces ( Figure 9 (Represented by output neuron 42 in the text).

[0144] According to one embodiment, the electronic component includes a memory, such as memory 52. ​​Memory 52 can store configuration data, upon which configuration signals 34 can be provided. Additionally, the memory can also store operational control data for controlling the multiplexer 55 to switch between signal inputs used to receive signals (e.g., sensor signals in cases where the neural network is dedicated to evaluating sensor signals) and training inputs provided during the neural network search process during operation. The signal inputs and training inputs can be provided via corresponding interfaces 62 and 64. For example, the signal inputs can be provided via analog interface 62, but in other examples, the electronic component may include digital interfaces and digital-to-analog converters. For example, the input signal 14 provided to the reconfigurable electronic circuit is an analog signal.

[0145] In other words, for example, memory 52 can be used to store the configuration of the network architecture and the instructions required to run the hardware. Memory 52 can enable and disable flexible connections 32, which can connect input buffers 46, output neurons 42, synaptic elements 24, and neuronal elements 26, thereby building a neural architecture on hardware.

[0146] For example, the dedicated number of input buffers and output neurons will be enabled based on the application and will not change during the exploration phase.

[0147] For example, output signal 16 will be read directly from the output neuron.

[0148] According to one embodiment, electronic component 10 can support two modes: a working mode and a search mode (in which a neural network architecture is configured). In working mode, the analog neural network core is connected to signal sources such as sensors, data converters, and any other input signal sources for prediction and classification tasks. In search mode, the input is short-circuited to the controller, which sends training input data to the hardware. The training input data is then directly propagated to the neural network. Switching between the two modes can be achieved using an analog multiplexer.

[0149] Figure 10 Another embodiment of the electronic component 10 is shown. According to this embodiment, the switchable connection is implemented as cross switches 321, 322, and 323. The input of cross switch 321 is connected to input interface 46, and the output of neuron element 26 and the output of cross switch 321 are connected to synaptic element 24. The input of cross switch 322 is connected to the output of synaptic element 24, and the output of cross switch 322 is connected to the input of neuron element 26. The input of cross switch 323 is connected to the output of neuron element 26, and the output of cross switch 323 is connected to the input of output terminal 44. It should be noted that... Figure 10 The implementation and arrangement of the described switchable connections can be independent of Figure 10 This is achieved through other features described.

[0150] For example, the analog input interface is responsible for receiving and buffering analog signals from external sensor systems or analog training data converted by a D / A converter.

[0151] According to one embodiment, a crossbar switch is used to establish physical connections between components. In the example, the CPU configures it via a global memory bus, and the configuration settings are stored in local memory located near the crossbar switch.

[0152] According to one embodiment, a group of resistors may represent the synaptic element used in the example. The resistors may be flexibly or switchably connected to the output of the input buffer and cross-connected to the input and output of the amplifier-based neuron.

[0153] According to one embodiment, the amplifier (neuron-based) array includes the neuronal elements used in the example. Similar to resistors, they can be flexibly connected via crossovers.

[0154] According to one embodiment, the output buffer consists of multiple analog buffers or amplifier-based neurons. These elements can pass analog results to an output with specific driving capabilities.

[0155] like Figure 10 As shown, according to one embodiment, the electronic component includes a processing unit 70, such as a central processing unit (CPU). For example, the processing unit 70 may be configured to control a neural network search process. For example, for each of a plurality of configurations of the reconfigurable electronic circuitry for the neural network, the processing unit 70 may provide configuration signals to the reconfigurable electronic circuitry to configure the connections between analog elements of the reconfigurable electronic circuitry according to the corresponding configuration to adapt to the architecture of the neural network, and provide input signals to the reconfigurable electronic circuitry to evaluate the input signals using the neural network implemented by the corresponding configuration of the reconfigurable electronic circuitry, thereby obtaining an inference result of the input signals.

[0156] For example, processing unit 70 can be configured to derive the configuration to be evaluated, evaluate the reasoning results, and select the final configuration. In other words, processing unit 70 can perform... Figure 2 The steps of block 201 or Figure 3 The steps of blocks 311, 313, 315, and 317 are described above. Optionally, electronic component 10 may further include a global memory 72 and a digital interface 74 for receiving programs or commands.

[0157] For example, digital interfaces facilitate communication between an internal central processing unit (CPU) and an external controller. They can write programs and commands to the hardware and read intermediate results from it.

[0158] For example, there are two ways to implement a central processing unit: one is a complete processor, such as RISC-V; the other is a dedicated digital processing unit capable of performing the operations developed in this study.

[0159] In the example, global memory can be used to store programs and intermediate results.

[0160] Figure 11An apparatus 11 for configuring a neural network according to one embodiment is shown. The apparatus 11 includes electronic components 10 and a processing unit 81, such as a microcontroller or FPGA. The processing unit 81 is configured to perform... Figure 10 The steps described in processing unit 70.

[0161] according to Figure 10 In some embodiments, the electronic component may include a digital interface 85 for communicating with the processing unit 81. In other words, the processing unit 81 may act as an external controller for the electronic component 10, for example, for controlling the configuration / search of the neural network, such as with... Figure 10 The embodiments differ, in which the processing unit 70 is part of the electronic component 10.

[0162] In other words, the control unit can be integrated, such as Figure 10 The processing unit 70 can also be embedded, such as... Figure 11 The processing unit 81 is located within the embedded system. In embedded systems, the control unit can be implemented using an external controller (such as a microcontroller, FPGA, etc.). Figure 11 As shown. For example, on the chip, only the interface to local memory can be retained for writing network configuration. Embedded solutions may be particularly suitable for companies specializing in sensor systems, as these companies do not require complex digital systems, or the design / cost of on-chip digital systems is affordable.

[0163] like Figure 11 As shown, device 11 may include a digital-to-analog converter 82 for converting an input signal, including training data provided by processing unit 81, into an analog signal. Similarly, device 11 may also include an analog-to-digital converter 83 for converting an output signal, including inference results provided by reconfigurable electronic circuitry, into a digital signal for processing by processing unit 70.

[0164] It is worth noting that once a suitable neural architecture has been found using the suggested method, the dashed blocks can be removed.

[0165] Figure 12 Another embodiment of device 11 is shown. (Compared to...) Figure 11 Compared to the previous embodiment, Figure 12 The device 11 further includes a multiplexer 55 and analog input interfaces 62 and 64 for receiving input signals during operation, such as sensor signals and input signals carrying training data, such as... Figure 9The device 11 may optionally further include one or more sensors 38, for example, for sensing one or more physical parameters. The device 11 may be configured to evaluate one or more signals provided by the one or more sensors 38 using reconfigurable electronic circuitry 12. Optionally, the one or more sensors 38 may be part of an integrated circuit including electronic components 10.

[0166] For example, such as Figure 12 As shown, the local memory for storing electronic components with switchable connection configurations can optionally be implemented as a one-time memory (such as an eFuse). A one-time memory can refer to a memory that is irreversibly programmable and stores information in a non-volatile manner. For example, after finding the final configuration of the reconfigurable electronic circuit 10, the configuration can be stored in the eFuse-type memory of the electronic component so that it can still be used after the power to the electronic component is disconnected.

[0167] in other words, Figure 12 Device 11 in the diagram could be an example of a hardware implementation integrating sensors and a sensor analog front-end. The dashed block represents the disconnection after the architecture is found. If one-time memory (eFuse) is used, the architecture cannot be changed after final chip testing.

[0168] Figure 13 Another embodiment of device 11 is shown, illustrating a fully integrated embodiment 2 of device 11. For example, all components can be integrated into a single integrated circuit, such as an ASIC. Figure 10 Compared to the previous embodiment, Figure 13 The device 11 also includes a multiplexer 55 and analog input interfaces 62 and 64 for receiving input signals, such as sensor signals and input signals carrying training data, such as... Figure 9 As described. Figure 13 As shown, the analog decision circuit or analog-to-digital converter 78 can be used to provide the processing unit 70 with a digital signal representing the reasoning result. Figure 13 The device 11 may include a sensor 38, for example, such as Figure 12 The device 11 is described.

[0169] In other words, all components can be integrated onto a single ASIC. To achieve this, an integrated D / A converter generates training data from the CPU 70, while additional analog decision circuitry or an A / D converter is needed to convert the analog calculation results into digital format. The digitized results can be used for further architectural exploration or read directly via a digital interface. This implementation approach could be particularly interesting for sensor system vendors who want users or researchers to explore their own applications using the provided sensors.

[0170] Regarding the storage elements used to store reconfigurable electronic circuit configurations, typical memory (such as SRAM, DRAM, or any non-volatile memory) or one-time programmable memory (such as eFuse) can be used, depending on the intended use of the hardware. For example, typical memory allows a user to run the methods described herein on the hardware to customize reconfigurable electronic circuits and corresponding neural networks for autonomous applications. For this purpose, for example, one could use... Figure 10 (with integrated controller) and Figure 11 The embodiment described in (with external controller) is particularly attractive to researchers, engineers, and companies looking to explore and validate its applications and designs. The use of one-time programmable memory and integration of the sensor and its corresponding analog front-end into the system can be beneficial. Neural network configuration is completed during the chip testing phase. Figure 12 As shown, to achieve this functionality, an additional interface is needed to access the neural network's input. A multiplexer (MUX) 55 is used to switch training inputs from an external controller and real sensor inputs. However, because the one-time programmable memory can only be programmed once, the neural network architecture cannot be changed after programming during the final testing phase. This is particularly interesting for companies offering compact sensor solutions within a single chip.

[0171] Figure 14 An embodiment of a data interface for analog neural network hardware is shown, such as an interface provided by reconfigurable electronic circuitry 12. For example, electronic component 10 or reconfigurable electronic circuitry 12 may include an analog interface for receiving input data 14.

[0172] According to one embodiment, for example Figure 14 As shown in option 1 of the upper panel, input data 14 can be provided by one or more sensor modules. According to this embodiment, the sensor module includes a sensor 38a for sensing one or more physical parameters and an analog front end for providing the analog input signal 14. Therefore, in this example, the input signal for searching the neural network can be provided by the sensor.

[0173] According to another embodiment, for example Figure 14 As shown in option 2 of the lower panel, input data 14 can be provided by the CPU 70 through a digital-to-analog processing unit 71, which can convert the digital signal provided by the CPU 70 into an analog input signal 14. Therefore, according to this embodiment, the input signal for searching the neural network can be provided by the processing unit, for example, based on the training dataset.

[0174] In other words, in option 1, such as Figure 14As shown, the analog signals received by the sensor module can be directly used as input to the analog neural network hardware. This decision is made by the analog neural network hardware, which uses the network obtained through the proposed method to evaluate the analog input signal. However, using the proposed method to find a suitable hardware architecture using direct sensor input can be challenging. This is primarily because it requires generating various combinations of sensor inputs to create a comprehensive training dataset. Another approach (such as...) Figure 14 Option 2 (shown in the text) uses a digital-to-analog converter (D / A converter). This converter can be installed between the digital computing system 70 (such as a microprocessor) and the analog neural network hardware 12 to generate a dataset from the microprocessor. This approach also facilitates the regular use of the analog neural network hardware, treating it as a processing unit within a larger computing system.

[0175] Therefore, more generally, analog method 100 may include providing input signal 14 by using microprocessor 70 to provide input data and converting the input data from digital to analog to provide the input signal. Alternatively, analog method 100 may include providing input signal through one or more sensing units to sense physical parameters.

[0176] Figure 15 An embodiment of the simulation method 100 is shown. According to... Figure 15 This method uses a circuit simulation 1512 (e.g., using the LTspice module) to simulate the analog neural network. However, it should be noted that... Figure 15 The method described therein can be an embodiment of the present invention, namely, by means of... Figure 15 The reconfigurable electronic circuit 12, composed of elements of the synaptic pool 1598 and neuron pool 1599, performs corresponding operations to replace circuit simulation.

[0177] like Figure 15As shown, the verification setup is used to validate the effectiveness of the proposed method. Synaptic pools 1598 and neuron pools 1599 are generated based on the tolerances of the actual hardware components. At the core of the controller, the evolutionary algorithm 1501 samples synapses and neurons from the hardware pools to construct new architectures and generations. The architecture under test is first converted into a netlist (see block 1502) and exported to LTspice 1512 for simulating circuit behavior. Additionally, LTspice receives input signals 1514 from the application and verifies them using a “Bipedal Walker-v3” simulation 1573. The electrical signals obtained from the circuit simulation tool are converted into appropriate data representations and sent to the application and the algorithm. The application calculates a score for the current architecture. Other hardware metrics (such as power consumption or timing penalties) can be sent directly to the algorithm, which combines the application-calculated scores and hardware metrics into a comprehensive fit score. Based on the score, the algorithm decides whether to end the evolution with the best architecture or begin the next generation with some of the best architectures from the current generation.

[0178] The "Bipedal Walker-v3," used to validate our proposed method, represents a typical control task. It includes 24 inputs from various sensors: 14 sensors measure angular velocity and speed at different locations, and 10 lidar sensors measure distance. Based on the sensor inputs, a neural network derived from our method calculates control signals. These signals are then used to control motors responsible for the movement of the left and right knees and hip joints. This control mechanism enables the bipedal walker to move forward while maintaining balance and preventing falls.

[0179] Figure 16 shows the results according to Figure 15The exemplary simulations performed by the method generated different neural networks, namely the initial architecture, the first-generation 1602, the third-generation 1603, and the final architecture 1604. As shown in Figure 16, the verification configuration is as follows: In this example, there are 500 neurons and 500 synapses, i.e., 500 inverting summing amplifiers with feedback resistors and 500 resistors. They can be freely connected and reconnected. However, each element can only be used once. The goal is for the walker to pass 10 tests. The depth of the neural network and the maximum number of iterations are unlimited. After the search begins, the search process ends after 36 iterations, resulting in a 7-layer neural network that successfully passes the application test. It is particularly noteworthy that the neural network does not necessarily follow a conventional hierarchical structure; many feedforward paths can be found. Secondly, the number of input neurons used is reduced from 24 to 16, meaning that the application does not actually require all the inputs. Third, due to hardware limitations, a single inverting summing amplifier always produces a negative output and its resistance value is limited. Neural networks can connect two neurons in series to obtain a positive output (such as neurons 262 and 238 in generation 36), or connect two neurons in parallel to enhance the impact on the output (such as neurons 120 and 138 in generation 36). In this case, hardware process variations are utilized to the maximum extent to carry information and build useful neural architectures.

[0180] Figure 17 A comparison between embodiments of the present invention and conventional methods is shown. For example... Figure 17 As shown, compared with existing methods, the method proposed in this invention can simultaneously optimize neural architecture and reduce computational errors caused by mapping. Traditional methods (a) typically design neural architectures based on experience, leading to suboptimal and redundant neural architectures in the hardware. After model training, the neural network is directly mapped to the hardware. When the simulated neural network hardware performs inference for these neural networks, large computational errors occur due to process variations and parasitic effects. Using model compression (b), the size and robustness of suboptimal architectures can be optimized based on the hardware. However, mapping errors caused by hardware non-ideals cannot be completely eliminated. Neural architecture search (c) automates the architecture decision-making process, eliminating decisions based on the engineer's experience. Hardware parameters can also be incorporated into the NAS process. However, mapping errors still exist. On-chip learning (d) partially solves the mapping error problem because gradient calculation is performed on the chip, including hardware non-ideals. It has two drawbacks: first, the architecture cannot be optimized; second, training accuracy is limited by the resolution of the data converter, and training still needs to be partially performed in the digital domain.

[0181] The embodiments of the present invention address these two problems as follows: First, neural architecture search directly incorporates hardware into the search loop, thereby directly considering hardware constraints in the neural architecture search. Second, since the inference results used for the search come directly from the hardware, mapping errors do not occur. Third, the search is not limited by the resolution of hardware components because, according to the embodiments, backpropagation-based training is not required or performed.

[0182] In the following text, in other words, the details, effects, and advantages of embodiments of the present invention will be described again. All details described below can be combined with any of the above embodiments, for example, with… Figure 1 Simulation method 100 and / or Figure 2 The electronic components 10 are combined.

[0183] To address the challenges mentioned at the outset, embodiments of this invention provide a method for incorporating analog neural network hardware into the neural architecture search process. This method combines the advantages of neural architecture search in optimizing architecture search with the advantages of on-chip learning in preventing computational errors arising from software-hardware mapping. However, traditional neural architecture search requires a flexible structure to ensure sufficient adaptability of connections between neurons and synaptic circuits. In contrast, on-chip learning tends to employ static circuit structures because inconsistencies in various hardware structures complicate the scheduling of hierarchical gradient computation. This paradoxical situation makes it difficult to implement neural architecture search in hardware. In 2019, a study on weight-agnostic neural networks (WANNs) explored the feasibility of searching for neural network architectures where all connections (weights) share fixed weights for a specific task. This aligns with the characteristic of organisms performing basic activities such as eating, drinking, and moving without prior knowledge, as biological neural networks autonomously incorporate this knowledge without fine-tuning synaptic strengths (such as weights and biases in artificial neural networks). Biological synapses and neurons exhibit similarities to electronic components because their initial synaptic strengths, or the corresponding physical properties of these components, are statistically distributed. Embodiments of the present invention may rely on the discovery that it is feasible to design an electronic system that evolves in a manner similar to a biological neural network, under precisely controlled environmental conditions.

[0184] According to embodiments of the above method, the neural network architecture is optimized for dedicated hardware, where the controller (such as an external controller) always seeks the structure with the fewest connections to achieve the predetermined goal. This characteristic allows the hardware to achieve the goal with minimal power consumption, which is particularly important for edge sensor systems with limited battery life. Since there may be no mapping between software and hardware, there is no loss of accuracy. The result obtained during the search process may be exactly the result of the hardware output. In contrast, existing methods cannot simultaneously address both of these issues well.

[0185] Currently, model leakage has become a critical security issue for neural network hardware, as attackers can generate misleading inputs after analyzing the model. Using this method, the neural network architecture is hardware-customized. This means that each analog neural network hardware can potentially have its own network architecture due to the statistical distribution of electronic component values. This characteristic significantly reduces the risk of using analog neural network hardware. Even if a model leakage occurs in one piece of hardware, it will not jeopardize the use of other hardware.

[0186] For example, the proposed methods can be used to configure analog neural network hardware, which can be used in edge sensor systems for early classification or prediction. These sensor systems can be used wherever sensor systems are needed.

[0187] Analog neural network hardware is not limited to basic artificial neural networks consisting solely of fully connected layers. Such hardware can also be implemented using the proposed approach, employing specialized topologies that can be a hybrid of various layer types, such as fully connected layers, convolutional layers, and reflow layers. For example, analog neural network hardware is not limited to hardware that performs mathematical modeling of biological neurons. It may also include hardware that simulates spike neural networks, i.e., hardware that uses analog electronic components to simulate the electronic behavior of organisms. The proposed approach can also be applied to this type of hardware.

[0188] Although some aspects have been described as features of the apparatus, it is clear that such a description can also be regarded as a description of corresponding features of the method.

[0189] Some or all of the method steps may be performed by (or using) hardware devices, such as microprocessors, programmable computers, or electronic circuits. In some embodiments, one or more of the most important method steps may be performed by such devices.

[0190] As can be seen in the detailed description above, various features are combined in the examples for the purpose of simplifying the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed examples require more features than are expressly recited in each claim. Rather, as reflected in the following claims, the subject matter may not include all features of a single disclosed example. Therefore, the following claims are hereby incorporated into the detailed description, wherein each claim may stand alone as a separate example. While each claim may stand alone as an example, it should be noted that while a dependent claim may refer in the claims to a particular combination with one or more other claims, other examples may also include combinations of the subject matter of a dependent claim with each of the other dependent claims, or combinations of each feature with other dependent or independent claims. Such combinations will be presented herein unless it is stated that a particular combination is not intended to be used. Furthermore, even if a claim does not have a dependent claim that directly becomes an independent claim, the features of that claim may be included in any other independent claim.

[0191] The embodiments described above are merely illustrative of the principles of this disclosure. It will be apparent to those skilled in the art that modifications and variations of the arrangements and details described herein will be readily apparent. Therefore, the intent of this disclosure is limited only by the scope of the pending patent claims and not by the specific details presented herein through the description and explanation of the embodiments.

[0192] References

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Claims

1. A method (10) for configuring an analog neural network, said analog neural network being implemented by a plurality of analog elements of a reconfigurable electronic circuit (12), said method comprising: For each of the multiple configurations (22) of the reconfigurable electronic circuit of the analog neural network, The connections between the analog elements of the reconfigurable electronic circuit are configured (120) according to the corresponding configuration to adapt to the architecture of the analog neural network. The input signal (14) is evaluated (140) using an analog neural network implemented with a corresponding configuration of reconfigurable electronic circuitry to obtain the inference result of the input signal, and The plurality of configurations are evaluated (180) based on the corresponding inference results, thereby selecting one of the configurations as the configuration of the simulated neural network.

2. The method according to claim 1, further comprising: The simulated neural network is configured according to one of the selected configurations.

3. The method according to any one of the preceding claims further includes: For each of the plurality of configurations, a configuration signal (34) is provided to the reconfigurable electronic circuit (520) to configure the reconfigurable electronic circuit according to the corresponding configuration.

4. The method according to any one of the preceding claims, wherein configuring (120) the connections between the analog elements of the reconfigurable electronic circuit comprises: The reconfigurable electronic circuit is configured with switchable connections between multiple neuronal elements and multiple synaptic elements, thereby selecting a set of neurons from the multiple neuronal elements as neurons of the simulated neural network and selecting a set of synapses from the multiple synaptic elements as synapses of the simulated neural network.

5. The method according to any of the preceding claims, further comprising: Determine a set of configurations for the simulated neural network described in (501). For each of the aforementioned set of configurations The connections between the analog elements of the reconfigurable electronic circuit are configured (520) according to the corresponding configuration to adapt to the architecture of the analog neural network. The input signal is processed (540) using an analog neural network implemented with a corresponding configuration of the reconfigurable electronic circuit to obtain an inference result of the input signal. The set of configurations is evaluated based on the corresponding reasoning results (550). If none of the configurations in the set meet the predetermined criteria, another set of configurations is determined (501) for simulating a neural network based on the selected configuration.

6. The method of claim 5, wherein determining the other set of configurations includes a modification of one of the configurations of the simulated neural network, determined from one or more aspects of adding neurons, removing neuronal elements, swapping neuronal elements, adding synaptic elements, removing synaptic elements, or swapping synaptic elements of the simulated neural network.

7. The method according to any of the preceding claims, comprising: The final configuration of the simulated neural network is stored in a non-volatile memory element (52).

8. An electronic component (10) for implementing an analog neural network, the electronic component comprising a reconfigurable electronic circuit (12), the reconfigurable electronic circuit (12) comprising: Multiple (24) resistive elements (S1, S2, S3), Multiple (26) summing elements (N1, N2, N3), and Multiple switchable connectors (32, 321, 322, 323), each switchable connector can be switched to establish a connection between one of the resistive elements and one of the summing elements.

9. The electronic component of claim 8, comprising a first cross switch (321) for providing a switchable connection between each of the outputs of the plurality of resistive elements and each of the inputs of the summing element, and / or A second cross switch (322) is used to provide switchable connections between the respective outputs of the plurality of summing elements and the respective inputs of the resistive elements.

10. The electronic component according to any one of claims 8 or 9, comprising one or more storage elements (52) for storing a switchable connection configuration.

11. The electronic component of claim 10, wherein the one or more storage elements are implemented as a one-time programmable memory.

12. The electronic component according to any one of claims 8 to 11, Among them, multiple resistive elements are nominally equal, and / or Several summing elements are nominally equal.

13. The electronic component according to any one of claims 8 to 12, The resistance values ​​of the plurality of resistive elements are skewed between 5% and 50%, or between 5% and 30%, and / or The summing element is implemented as an operational amplifier, and The offset voltage deviation of the operational amplifier is between 5mV and 100mV, and / or The deviation of the resistance value of the feedback resistor of the operational amplifier is between 5% and 50%, or between 5% and 30%.

14. The electronic component according to any one of claims 8 to 13, implemented as an integrated circuit, and further comprising an input interface (85), wherein the electronic component is configured to receive a configuration signal (34) through the input interface and configure a switchable connection according to the configuration signal.

15. The electronic component according to any one of claims 8 to 14, wherein the plurality of (24) resistive elements (S1, S2, S3) are configured as synaptic weights of the simulated neural network, and the plurality of (26) summing elements (N1, N2, N3) are configured as neurons of the simulated neural network.

16. A means (11) for configuring an analog neural network, the means comprising: The electronic component (10) according to any one of claims 8 to 15, and Processing unit (70), the processing unit being configured to For each of the multiple configurations of the reconfigurable electronic circuit of the analog neural network, Configuration signals (34) are provided to the reconfigurable electronic circuit to configure multiple switchable connections of the reconfigurable electronic circuit according to a corresponding configuration, thereby adapting to the architecture of the analog neural network, and An input signal (14) is provided to the reconfigurable electronic circuit to evaluate the input signal using an analog neural network implemented by a corresponding configuration of the reconfigurable electronic circuit, thereby obtaining an inference result of the input signal.

17. The device according to claim 16 is implemented as an integrated electronic circuit.

18. The apparatus according to any one of claims 16 or 17, wherein the processing unit is further configured to: The multiple configurations are evaluated (180) based on the corresponding reasoning results to select one of the configurations.

19. The apparatus of claim 18, further comprising one or more non-volatile storage elements (52) for storing the configuration of the switchable connection. in, The processing unit is also configured to store one of the selected configurations in the one or more non-volatile memory elements.

20. The apparatus according to any one of claims 16 to 19, wherein the analog neural network is implemented entirely by analog elements.

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