Pixel, display apparatus including same, and electronic device including display apparatus

Abstract

The invention relates to a pixel, a display device including the pixel, and an electronic device including the display device. The pixel includes: a first transistor including a gate connected to a first node, a first terminal connected to a second node, and a second terminal connected to a third node; a second transistor transmitting a data signal to the first node in response to a write gate signal; a third transistor transmitting a sustaining voltage to a third node in response to the compensation gate signal; a fourth transistor transmitting the first power voltage to the second node in response to the transmission signal; a first capacitor connected between the first node and the second node; a second capacitor connected between the second node and a power line transmitting the first power voltage; and a light emitting element including a first terminal connected to the third node and a second terminal receiving a second power voltage.

Description

Technical Field

[0001] The embodiments relate to display devices. More specifically, the embodiments relate to pixels including a plurality of transistors and a plurality of capacitors, display devices including pixels, and electronic devices including display devices. Background Technology

[0002] A display device may include multiple pixels, each displaying a variety of colors. Each pixel may be the smallest unit for displaying a single color, and the display device may display an image containing a combination of colors displayed by the pixels.

[0003] Recently, the demand for high-resolution display devices has been increasing. To increase the resolution of display devices, the area of ​​pixels needs to be reduced. Summary of the Invention

[0004] The implementation provides pixels with a reduced area.

[0005] The implementation provides a display device with high resolution and an electronic device including the display device.

[0006] The pixel according to the embodiment includes: a first transistor including a gate connected to a first node, a first terminal connected to a second node, and a second terminal connected to a third node; a second transistor transmitting a data signal to the first node in response to a write gate signal; a third transistor transmitting a sustaining voltage to the third node in response to a compensation gate signal; a fourth transistor transmitting a first power voltage to the second node in response to a transmit signal; a first capacitor connected between the first node and the second node; a second capacitor connected between the second node and a power line transmitting the first power voltage; and a light-emitting element including a first terminal connected to the third node and a second terminal receiving the second power voltage.

[0007] In the implementation, during the initialization period, the first power voltage can transition from a high level to a low level, the second power voltage can transition from a low level to a high level, the compensation gate signal can transition from a deactivation level to an activation level, and the transmit signal can have an activation level.

[0008] In this implementation, during the initialization period, a first power voltage can be applied to the third node via the fourth transistor and the first transistor.

[0009] In the implementation, during the compensation period after the initialization period, the write gate signal may have an active level, the sustaining voltage may have a high level, the compensation gate signal may transition from the active level to the deactivated level, the transmit signal may transition from the active level to the deactivated level, and the data signal may have a reference voltage.

[0010] In one implementation, during the compensation period, the first capacitor may store the threshold voltage of the first transistor.

[0011] In an implementation, during the addressing period following the compensation period, the write gate signal may include a pulse with an activation level, and the data signal may have a data voltage.

[0012] In this implementation, during the bypass period following the addressing period, the sustaining voltage may be at a low level, and the compensation gate signal may be at an active level.

[0013] In one implementation, during the transmission period following the bypass period, the first power voltage may be at a high level, the second power voltage may be at a low level, and the transmitted signal may be at an active level.

[0014] In the implementation, during the initialization period, the first power voltage can transition from a high level to a low level, the second power voltage can transition from a low level to a high level, the sustaining voltage can have a low level, the compensation gate signal can transition from a deactivation level to an activation level, and the transmit signal can have a deactivation level.

[0015] In this implementation, during the initialization period, the sustaining voltage can be applied to the third node via the third transistor.

[0016] In an implementation, each of the first transistor, the second transistor, the third transistor, and the fourth transistor may be a p-type metal-oxide-semiconductor (PMOS) transistor.

[0017] In an implementation, the first transistor may be a p-type metal-oxide-semiconductor (PMOS) transistor, and at least one of the second, third, and fourth transistors may be an n-type metal-oxide-semiconductor (NMOS) transistor.

[0018] In an embodiment, the display device may further include a fifth transistor that sends an initialization voltage to the second node in response to an initialization gate signal.

[0019] In the implementation, during the initialization period, the first power voltage can transition from a high level to a low level, the second power voltage can transition from a low level to a high level, the compensation gate signal can transition from a deactivation level to an activation level, the transmit signal can have a deactivation level, and the initialization gate signal can have an activation level.

[0020] In the implementation, during the initialization period, the initialization voltage can be applied to the third node through the fifth transistor and the first transistor.

[0021] A display device according to an embodiment includes: a display panel including a plurality of pixels; a gate driver providing a write gate signal, a compensation gate signal, and an transmit signal to each of the pixels; a data driver providing a data signal to each of the pixels; and a power management circuit providing a first power voltage, a second power voltage, and a sustaining voltage to each of the pixels. Each of the pixels may include: a first transistor including a gate connected to a first node, a first terminal connected to a second node, and a second terminal connected to a third node; a second transistor transmitting a data signal to the first node in response to the write gate signal; a third transistor transmitting a sustaining voltage to the third node in response to the compensation gate signal; a fourth transistor transmitting the first power voltage to the second node in response to the transmit signal; a first capacitor connected between the first node and the second node; a second capacitor connected between the second node and a power line transmitting the first power voltage; and a light-emitting element including a first terminal connected to the third node and a second terminal receiving the second power voltage.

[0022] In this implementation, the gate driver can sequentially provide write gate signals to the pixel row, and can also provide a compensation gate signal and a transmit signal to the common ground of the pixel row. The power management circuit can provide a first power voltage to the common ground of the pixel row.

[0023] In one implementation, the gate driver can sequentially provide a write gate signal, a compensation gate signal, and an transmit signal to the pixel row. The power management circuit can sequentially provide a first power voltage to the pixel row.

[0024] In this implementation, the gate driver may also provide an initialization gate signal to each of the pixels. The power management circuitry may also provide an initialization voltage to each of the pixels. Each pixel may further include a fifth transistor that sends an initialization voltage to the second node in response to the initialization gate signal.

[0025] An electronic device according to an embodiment includes: a display panel including a plurality of pixels; a gate driver providing a write gate signal, a compensation gate signal, and an transmit signal to each of the pixels; a data driver providing a data signal to each of the pixels; a power management circuit providing a first power voltage, a second power voltage, and a sustaining voltage to each of the pixels; a controller controlling the gate driver, the data driver, and the power management circuit; and a processor providing the controller with input image data and control signals. Each of the pixels includes: a first transistor including a gate connected to a first node, a first terminal connected to a second node, and a second terminal connected to a third node; a second transistor transmitting a data signal to the first node in response to the write gate signal; a third transistor transmitting a sustaining voltage to the third node in response to the compensation gate signal; a fourth transistor transmitting the first power voltage to the second node in response to the transmit signal; a first capacitor connected between the first node and the second node; a second capacitor connected between the second node and a power line transmitting the first power voltage; and a light-emitting element including a first terminal connected to the third node and a second terminal receiving the second power voltage.

[0026] According to the implementation method, the pixel includes only four or five transistors and two capacitors, which allows the pixel area to be reduced.

[0027] The display device according to the embodiment includes pixels with a small area, which makes it possible to increase the resolution of the display device. Attached Figure Description

[0028] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0030] Figure 2 It is shown Figure 1 A circuit diagram of an example pixel.

[0031] Figure 3 It is shown Figure 2 Timing diagrams of example voltages and signals.

[0032] Figure 4 It is shown Figure 2 Another timing diagram showing examples of voltage and signal.

[0033] Figure 5 It is shown Figure 1 Another circuit diagram of an example of pixels.

[0034] Figure 6 This is a block diagram illustrating a display device according to an embodiment.

[0035] Figure 7 It is shown Figure 6 A circuit diagram of an example pixel.

[0036] Figure 8 This is a block diagram illustrating a display device according to an embodiment.

[0037] Figure 9 It is shown Figure 8 A circuit diagram of an example pixel.

[0038] Figure 10 It is shown Figure 9 Timing diagrams of example voltages and signals.

[0039] Figure 11 This is a block diagram illustrating an electronic device according to an embodiment. Detailed Implementation

[0040] In the following, pixels, display devices, and electronic devices according to embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals will be used for the same elements.

[0041] Figure 1 This is a block diagram illustrating a display device 100 according to an embodiment.

[0042] refer to Figure 1 The display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a power management circuit 140, and a controller 150.

[0043] The display panel 110 may include a plurality of pixels PX. The display panel 110 may include a first pixel row PR[1] to the m-th pixel row PR[m] defined by the pixels PX (m is a natural number greater than 1).

[0044] The gate driver 120 can provide the pixel PX with a first write gate signal GW[1] to the m-th write gate signal GW[m], a compensation gate signal GC, and an transmit signal EM. The gate driver 120 can generate the first write gate signal GW[1] to the m-th write gate signal GW[m], the compensation gate signal GC, and the transmit signal EM based on the gate control signal GCS. The gate control signal GCS may include a gate clock signal, a gate start signal, etc.

[0045] Gate driver 120 can sequentially provide first write gate signals GW[1] to m-th write gate signals GW[m] to the first pixel row PR[1] to the m-th pixel row PR[m]. In other words, gate driver 120 can provide the first write gate signal GW[1] to the first pixel row PR[1] and can provide the m-th write gate signal GW[m] to the m-th pixel row PR[m]. Gate driver 120 can commonly provide compensation gate signal GC and transmit signal EM to the first pixel row PR[1] to the m-th pixel row PR[m].

[0046] Data driver 130 can provide data signal DS to pixel PX. Data driver 130 can generate data signal DS based on output image data IMD2 and data control signal DCS. Data driver 130 can convert digital output image data IMD2 into analog data signal DS. Data control signal DCS may include data clock signal, load signal, output data enable signal, etc.

[0047] The power management circuit 140 can provide a first power voltage ELVDD, a second power voltage ELVSS, and a sustaining voltage VSUS to pixel PX. The power management circuit 140 can generate the first power voltage ELVDD, the second power voltage ELVSS, and the sustaining voltage VSUS based on the power control signal PCS. The power management circuit 140 can provide the first power voltage ELVDD, the second power voltage ELVSS, and the sustaining voltage VSUS to the first pixel row PR[1] to the m-th pixel row PR[m] in a common manner.

[0048] The controller 150 can control the gate driver 120, the data driver 130, and the power management circuit 140. The controller 150 can provide the gate control signal GCS to the gate driver 120, the output image data IMD2 and the data control signal DCS to the data driver 130, and the power control signal PCS to the power management circuit 140. The controller 150 can convert the input image data IMD1 into the output image data IMD2. The controller 150 can generate the gate control signal GCS, the data control signal DCS, and the power control signal PCS based on the control signal CTRL. The control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, a master clock signal, an input data enable signal, etc.

[0049] Figure 2 It is shown Figure 1 A circuit diagram of an example pixel PX.

[0050] refer to Figure 1 and Figure 2Pixel PX can receive write gate signal GW[n] (n is a natural number greater than or equal to 1 and less than or equal to m), compensation gate signal GC, transmit signal EM, data signal DS, first power voltage ELVDD, second power voltage ELVSS, and sustaining voltage VSUS. Write gate signal GW[n] can be one of the first write gate signal GW[1] to the m-th write gate signal GW[m].

[0051] A pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor CST, a second capacitor CHOLD, and a light-emitting element EL.

[0052] The first transistor T1 may include a gate connected to a first node N1, a first terminal connected to a second node N2, and a second terminal connected to a third node N3. The first transistor T1 can generate a drive current corresponding to the voltage difference between the first node N1 and the second node N2.

[0053] The second transistor T2 can transmit a data signal DS to the first node N1 in response to the write gate signal GW[n]. The second transistor T2 may include a gate for receiving the write gate signal GW[n], a first terminal for receiving the data signal DS, and a second terminal connected to the first node N1.

[0054] The third transistor T3 can transmit a sustaining voltage VSUS to the third node N3 in response to the compensation gate signal GC. The third transistor T3 may include a gate for receiving the compensation gate signal GC, a first terminal for receiving the sustaining voltage VSUS, and a second terminal connected to the third node N3.

[0055] The fourth transistor T4 can transmit a first power voltage ELVDD to the second node N2 in response to the transmit signal EM. The fourth transistor T4 may include a gate for receiving the transmit signal EM, a first terminal for receiving the first power voltage ELVDD, and a second terminal connected to the second node N2.

[0056] Each of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can be a p-type metal-oxide-semiconductor (PMOS) transistor. Each of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can be a polycrystalline silicon transistor.

[0057] A first capacitor CST can be connected between a first node N1 and a second node N2. The first capacitor CST may include a first terminal connected to the first node N1 and a second terminal connected to the second node N2. The first capacitor CST can store the voltage difference between the first node N1 and the second node N2.

[0058] A second capacitor, CHOLD, can be connected between the second node N2 and the power line PL that transmits the first power voltage ELVDD. The second capacitor CHOLD may include a first terminal connected to the second node N2 and a second terminal receiving the first power voltage ELVDD. The second capacitor CHOLD can store the voltage of the second node N2.

[0059] The light-emitting element EL may include a first terminal (e.g., anode) connected to the third node N3 and a second terminal (e.g., cathode) receiving a second electrical voltage ELVSS. The light-emitting element EL may emit light with a brightness corresponding to the drive current generated by the first transistor T1.

[0060] The pixel PX according to the embodiment includes only four transistors and two capacitors, which allows for a reduction in the area of ​​the pixel PX. Furthermore, the display device 100 according to the embodiment includes pixels PX with a small area, which allows for an increase in the resolution of the display device 100.

[0061] Figure 3 It is shown Figure 2 Timing diagrams for example voltages ELVDD, ELVSS, and VSUS, and signals GW[n], GC, EM, and DS.

[0062] refer to Figure 2 and Figure 3 The frame period corresponding to an image frame can include an initialization period P1, a compensation period P2, an addressing period P3, a bypass period P4, and a transmission period P5. The initialization period P1, compensation period P2, addressing period P3, bypass period P4, and transmission period P5 can be executed sequentially.

[0063] The first power voltage, ELVDD, can transition from high to low during the initialization period P1, remain low during the compensation period P2, and remain high during the addressing period P3, bypass period P4, and transmission period P5. The second power voltage, ELVSS, can transition from low to high during the initialization period P1, remain high during the compensation period P2 and addressing period P3, and remain low during the bypass period P4 and transmission period P5.

[0064] The write gate signal GW[n] can have a deactivation level in the initialization period P1, an activation level in the compensation period P2, include a pulse with an activation level in the addressing period P3, and a deactivation level in the bypass period P4 and the transmit period P5. The data signal DS can have a reference voltage VREF in the initialization period P1, the compensation period P2, the bypass period P4, and the transmit period P5, and can have a data voltage VDAT in the addressing period P3.

[0065] The sustaining voltage VSUS can be low during initialization period P1, high during compensation period P2 and addressing period P3, and low during bypass period P4 and transmit period P5. The compensation gate signal GC can transition from deactivation level to activation level during initialization period P1, from activation level to deactivation level during compensation period P2, be deactivation level during addressing period P3, be activation level during bypass period P4, and be deactivation level during transmit period P5.

[0066] The transmit signal EM can have an active level during the initialization period P1, can transition from an active level to a deactivated level during the compensation period P2, can have a deactivated level during the addressing period P3, and can have an active level during the bypass period P4 and the transmit period P5.

[0067] During the initialization period P1, the fourth transistor T4 can be turned on in response to the emitter signal EM with an activation level, and the first power voltage ELVDD can be applied to the third node N3 through the fourth transistor T4 and the first transistor T1. Therefore, during the initialization period P1, the first terminal of the light-emitting element EL can be initialized by the first power voltage ELVDD.

[0068] During compensation period P2, the second transistor T2 can be turned on in response to the write gate signal GW[n] with an active level, and the reference voltage VREF can be applied to the first node N1 through the second transistor T2. During period P2-1, in which the compensation gate signal GC has an active level within compensation period P2, the third transistor T3 can be turned on in response to the compensation gate signal GC with an active level, and the high-level sustaining voltage VSUS can be applied to the third node N3 through the third transistor T3. During period P2-1, in which the transmit signal EM has an active level within compensation period P2, the fourth transistor T4 can be turned on in response to the active-level transmit signal EM, and the low-level first power voltage ELVDD can be applied to the second node N2 through the fourth transistor T4. During the period P2-2, in which the compensation gate signal GC and the emitter signal EM have deactivation levels within the compensation period P2, current can flow from the third node N3 to the second node N2 through the first transistor T1, and a voltage corresponding to the value VREF-VTH can be applied to the second node N2. This value VREF-VTH is obtained by subtracting the threshold voltage VTH of the first transistor T1 from the reference voltage VREF. Therefore, during the compensation period P2, the first capacitor CST can store the threshold voltage VTH of the first transistor T1.

[0069] During addressing period P3, the second transistor T2 can be turned on in response to a pulse with an activation level for the write gate signal GW[n], and the data voltage VDAT can be applied to the first node N1 through the second transistor T2. Therefore, during addressing period P3, the first capacitor CST can store a voltage corresponding to the value VDAT-VREF+VTH, which is obtained by subtracting the value VREF-VTH from the data voltage VDAT, wherein the value VREF-VTH is obtained by subtracting the threshold voltage VTH of the first transistor T1 from the reference voltage VREF.

[0070] During the bypass period P4, the third transistor T3 can be turned on in response to the compensation gate signal GC with an activation level, and a sustaining voltage VSUS with a low level can be applied to the third node N3 through the third transistor T3. Therefore, during the bypass period P4, the charge stored in the first terminal of the light-emitting element EL through the parasitic capacitance of the light-emitting element EL can be discharged to the line through which the sustaining voltage VSUS is transmitted via the third transistor T3.

[0071] During the emission period P5, the fourth transistor T4 can be turned on in response to the emission signal EM with an activation level, and the drive current generated by the first transistor T1 can flow through the fourth transistor T4 and the first transistor T1 to the light-emitting element EL. The light-emitting element EL can emit light with a brightness corresponding to the magnitude of the drive current. The magnitude of the drive current can correspond to the value VDAT-VREF, which is obtained by subtracting the threshold voltage VTH of the first transistor T1 from the voltage VDAT-VREF+VTH stored in the first capacitor CST connected between the gate and the first terminal of the first transistor T1. Therefore, during the emission period P5, the light-emitting element EL can emit light with a brightness corresponding to the data voltage VDAT.

[0072] Figure 4 It is shown Figure 2 Another timing diagram of the voltages ELVDD, ELVSS, and VSUS, and the signals GW[n], GC, EM, and DS.

[0073] References omitted Figure 2 and Figure 4 In the described operation steps of pixel PX, those that are related to the reference Figure 2 and Figure 3 The operation steps described are basically the same or similar to those of the pixel PX.

[0074] refer to Figure 2 and Figure 4The transmitted signal EM can have a deactivation level during the initialization period P1, the compensation period P2, and the addressing period P3, and can have an activation level during the bypass period P4 and the transmission period P5.

[0075] During the initialization period P1, the third transistor T3 can be turned on in response to the compensation gate signal GC with an activation level, and a sustaining voltage VSUS with a low level can be applied to the third node N3 through the third transistor T3. Therefore, during the initialization period P1, the first terminal of the light-emitting element EL can be initialized by the sustaining voltage VSUS with a low level.

[0076] During compensation period P2, the second transistor T2 can be turned on in response to a write gate signal GW[n] with an activation level, and the reference voltage VREF can be applied to the first node N1 through the second transistor T2. During compensation period P2, the third transistor T3 can be turned on in response to a compensation gate signal GC with an activation level, and a sustaining voltage VSUS with a high level can be applied to the third node N3 through the third transistor T3. During compensation period P2, current can flow from the third node N3 to the second node N2 through the first transistor T1, and a voltage corresponding to the value VREF-VTH can be applied to the second node N2, which is obtained by subtracting the threshold voltage VTH of the first transistor T1 from the reference voltage VREF. Therefore, during compensation period P2, the first capacitor CST can store the threshold voltage VTH of the first transistor T1.

[0077] Figure 5 It is shown Figure 1 Another circuit diagram of an example of pixel PX.

[0078] References omitted Figure 5 Of the components of the described pixel PX, those that are related to the reference Figure 2 The description of the components of the pixel PX is substantially the same as or similar to those of the components described.

[0079] refer to Figure 5 The first transistor T1 can be a PMOS transistor, and at least one of the second transistor T2, the third transistor T3, and the fourth transistor T4 can be an NMOS transistor. In an embodiment, as shown... Figure 5 As shown, each of the second transistor T2, the third transistor T3, and the fourth transistor T4 can be an NMOS transistor. The first transistor T1 can be a polysilicon transistor, and each of the second transistor T2, the third transistor T3, and the fourth transistor T4 can be an oxide semiconductor transistor.

[0080] Figure 6 This is a block diagram illustrating a display device 101 according to an embodiment.

[0081] References omitted Figure 6 Of the components of the described display device 101, those that are related to the reference Figure 1 The description of the components of the display device 100 is substantially the same as or similar to those of the components described.

[0082] refer to Figure 6 The display device 101 may include a display panel 110, a gate driver 121, a data driver 130, a power management circuit 141, and a controller 150.

[0083] Gate driver 121 can provide pixel PX with first write gate signals GW[1] to m-th write gate signals GW[m], first compensation gate signals GC[1] to m-th compensation gate signals GC[m], and first transmit signals EM[1] to m-th transmit signals EM[m]. Gate driver 121 can generate first write gate signals GW[1] to m-th write gate signals GW[m], first compensation gate signals GC[1] to m-th compensation gate signals GC[m], and first transmit signals EM[1] to m-th transmit signals EM[m] based on gate control signal GCS.

[0084] Gate driver 121 can sequentially provide first compensation gate signals GC[1] to m-th compensation gate signals GC[m] to the first pixel row PR[1] to the m-th pixel row PR[m]. In other words, gate driver 121 can provide first compensation gate signal GC[1] to the first pixel row PR[1] and can provide m-th compensation gate signal GC[m] to the m-th pixel row PR[m]. Gate driver 121 can sequentially provide first transmission signals EM[1] to m-th transmission signals EM[m] to the first pixel row PR[1] to the m-th pixel row PR[m]. In other words, gate driver 121 can provide first transmission signal EM[1] to the first pixel row PR[1] and can provide m-th transmission signal EM[m] to the m-th pixel row PR[m].

[0085] The power management circuit 141 can provide a first power voltage ELVDD[1] to the m-th first power voltage ELVDD[m], a second power voltage ELVSS, and a sustaining voltage VSUS to the pixel PX. The power management circuit 141 can generate the first power voltage ELVDD[1] to the m-th first power voltage ELVDD[m], the second power voltage ELVSS, and the sustaining voltage VSUS based on the power control signal PCS. The power management circuit 141 can sequentially provide the first power voltage ELVDD[1] to the m-th first power voltage ELVDD[m] to the first pixel row PR[1] to the m-th pixel row PR[m]. In other words, the power management circuit 141 can provide the first power voltage ELVDD[1] to the first pixel row PR[1], and can provide the m-th first power voltage ELVDD[m] to the m-th pixel row PR[m].

[0086] Figure 7 It is shown Figure 6 A circuit diagram of an example pixel PX.

[0087] References omitted Figure 7 Among the components of the described pixel PX, those that are related to the reference Figure 2 The components described for pixel PX are substantially the same as or similar to those of the components described.

[0088] refer to Figure 6 and Figure 7 Pixel PX can receive a write gate signal GW[n], a compensation gate signal GC[n], a transmit signal EM[n], a data signal DS, a first power voltage ELVDD[n], a second power voltage ELVSS, and a sustaining voltage VSUS. The compensation gate signal GC[n] can be one of the first compensation gate signal GC[1] to the m-th compensation gate signal GC[m], the transmit signal EM[n] can be one of the first transmit signal EM[1] to the m-th transmit signal EM[m], and the first power voltage ELVDD[n] can be one of the first power voltage ELVDD[1] to the m-th power voltage ELVDD[m].

[0089] The third transistor T3 can transmit a sustaining voltage VSUS to the third node N3 in response to the compensation gate signal GC[n]. The third transistor T3 may include a gate for receiving the compensation gate signal GC[n], a first terminal for receiving the sustaining voltage VSUS, and a second terminal connected to the third node N3.

[0090] The fourth transistor T4 can transmit a first power voltage ELVDD[n] to the second node N2 in response to the transmit signal EM[n]. The fourth transistor T4 may include a gate for receiving the transmit signal EM[n], a first terminal for receiving the first power voltage ELVDD[n], and a second terminal connected to the second node N2.

[0091] Figure 8 This is a block diagram illustrating a display device 102 according to an embodiment.

[0092] References omitted Figure 8 Of the components of the described display device 102, those that are related to the reference Figure 1 The components and / or references of the described display device 100 Figure 6 The description of the components of the display device 101 is substantially the same as or similar to those of the components described.

[0093] refer to Figure 8 The display device 102 may include a display panel 110, a gate driver 122, a data driver 130, a power management circuit 142, and a controller 150.

[0094] The gate driver 122 can provide the pixel PX with a first write gate signal GW[1] to the m-th write gate signal GW[m], a first compensation gate signal GC[1] to the m-th compensation gate signal GC[m], a first initialization gate signal GI[1] to the m-th initialization gate signal GI[m], and a first transmit signal EM[1] to the m-th transmit signal EM[m]. The gate driver 122 can generate the first write gate signal GW[1] to the m-th write gate signal GW[m], the first compensation gate signal GC[1] to the m-th compensation gate signal GC[m], the first initialization gate signal GI[1] to the m-th initialization gate signal GI[m], and the first transmit signal EM[1] to the m-th transmit signal EM[m] based on the gate control signal GCS.

[0095] The gate driver 122 can sequentially provide the first initialization gate signal GI[1] to the m-th initialization gate signal GI[m] to the first pixel row PR[1] to the m-th pixel row PR[m]. In other words, the gate driver 122 can provide the first initialization gate signal GI[1] to the first pixel row PR[1] and can provide the m-th initialization gate signal GI[m] to the m-th pixel row PR[m].

[0096] The power management circuit 142 can provide a first power voltage ELVDD, a second power voltage ELVSS, a sustaining voltage VSUS, and an initialization voltage VINT to pixel PX. The power management circuit 142 can generate the first power voltage ELVDD, the second power voltage ELVSS, the sustaining voltage VSUS, and the initialization voltage VINT based on the power control signal PCS. The power management circuit 142 can provide the initialization voltage VINT to the first pixel row PR[1] to the m-th pixel row PR[m] in common.

[0097] Figure 9 It is shown Figure 8 A circuit diagram of an example pixel PX.

[0098] References omitted Figure 9 Of the components of the described pixel PX, those that are related to the reference Figure 2 The described pixel PX components and / or references Figure 7 The description of the components of the pixel PX is substantially the same as or similar to those of the components described.

[0099] refer to Figure 8 and Figure 9 Pixel PX can receive the write gate signal GW[n], the compensation gate signal GC[n], the initialization gate signal GI[n], the transmit signal EM[n], the data signal DS, the first power voltage ELVDD, the second power voltage ELVSS, the sustaining voltage VSUS, and the initialization voltage VINT. The initialization gate signal GI[n] can be one of the first initialization gate signal GI[1] to the m-th initialization gate signal GI[m].

[0100] A pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor CST, a second capacitor CHOLD, and a light-emitting element EL.

[0101] The fifth transistor T5 can transmit an initialization voltage VINT to the second node N2 in response to the initialization gate signal GI[n]. The fifth transistor T5 may include a gate for receiving the initialization gate signal GI[n], a first terminal for receiving the initialization voltage VINT, and a second terminal connected to the second node N2.

[0102] The pixel PX according to the embodiment includes only five transistors and two capacitors, which allows for a reduction in the area of ​​the pixel PX. Furthermore, the display device 102 according to the embodiment includes pixels PX with a small area, which allows for an increase in the resolution of the display device 102.

[0103] Figure 10 It is shown Figure 9The timing diagrams are examples of voltages ELVDD, ELVSS, VSUS, and VINT, as well as signals GW[n], GC[n], GI[n], EM[n], and DS.

[0104] References omitted Figure 9 and Figure 10 In the described operation steps of pixel PX, those that are related to the reference Figure 2 and Figure 3 The described operation steps for pixel PX and / or reference Figure 2 and Figure 4 The operation steps described are basically the same or similar to those of the pixel PX.

[0105] The initialization voltage VINT can be low during the initialization period P1, compensation period P2, addressing period P3, bypass period P4, and transmit period P5. In other words, the initialization voltage VINT can be a DC voltage. The initialization gate signal GI[n] can be active during the initialization period P1 and deactivated during the compensation period P2, addressing period P3, bypass period P4, and transmit period P5.

[0106] During the initialization period P1, the fifth transistor T5 can be turned on in response to the initialization gate signal GI[n] with an activation level, and the initialization voltage VINT can be applied to the third node N3 through the fifth transistor T5 and the first transistor T1. Therefore, during the initialization period P1, the first terminal of the light-emitting element EL can be initialized by the initialization voltage VINT.

[0107] Figure 11 This is a block diagram illustrating an electronic device 1000 according to an embodiment.

[0108] refer to Figure 11 The electronic device 1000 can output various information through the display module 1040 within the operating system. When the processor 1010 executes an application stored in the memory 1020, the display module 1040 can provide application information to the user through the display panel 1041. In other words, the processor 1010 can control the display module 1040. In this embodiment, the processor 1010 can provide information to the display module 1040. Figure 1 , Figure 6 and Figure 8 Input image data IMD1 and Figure 1 , Figure 6 and Figure 8 The control signal CTRL.

[0109] Processor 1010 can obtain external input through input module 1030 or sensor module 1061 and can execute applications corresponding to the external input. For example, when a user selects the camera icon displayed on display panel 1041, processor 1010 can obtain user input through input sensor 1061-2 and can activate camera module 1071. Processor 1010 can send image data corresponding to the captured image obtained by camera module 1071 to display module 1040. Display module 1040 can display the image corresponding to the captured image through display panel 1041. Some components of electronic device 1000 can be integrated and configured as one component, or one component can be configured as two or more components.

[0110] Electronic device 1000 can communicate with external electronic device 1002 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). In embodiments, electronic device 1000 may include a processor 1010, a memory 1020, an input module 1030, a display module 1040, a power module 1050, an internal module 1060, and an external module 1070. In embodiments, electronic device 1000 may omit at least one of the components described above, or may add one or more other components. In embodiments, some of the components described above (e.g., sensor module 1061, antenna module 1062, or sound output module 1063) may be integrated into another component (e.g., display module 1040).

[0111] The processor 1010 can execute software to control at least one other component (e.g., hardware or software component) connected to the electronic device 1000, and can perform various data processing or calculations. In an embodiment, as at least part of data processing or calculation, the processor 1010 can store commands or data received from another component (e.g., input module 1030, sensor module 1061, or communication module 1073) in volatile memory 1021, can process commands or data stored in volatile memory 1021, and can store result data in non-volatile memory 1022.

[0112] Processor 1010 may include a main processor 1011 and a coprocessor 1012. Main processor 1011 may include one or more of a central processing unit (CPU) 1011-1 and an application processor (AP). Main processor 1011 may also include one or more of a graphics processing unit (GPU) 1011-2, a communication processor (CP), and an image signal processor (ISP). At least two of the processing units and processors described above may be implemented as integrated components (e.g., a single chip), or each may be implemented as a separate component (e.g., multiple chips).

[0113] The coprocessor 1012 may include a controller 1012-1. The controller 1012-1 may include interface conversion circuitry and timing control circuitry. The controller 1012-1 can receive image signals from the main processor 1011, convert the data format of the image signals to suit the interface specifications of the display module 1040, and output image data. The controller 1012-1 can output various control signals required to drive the display module 1040.

[0114] The coprocessor 1012 may also include a data conversion circuit 1012-2, a gamma correction circuit 1012-3, a rendering circuit 1012-4, etc. The data conversion circuit 1012-2 can receive image data from the controller 1012-1 and can compensate the image data to display an image at a desired brightness according to the characteristics of the electronic device 1000 or user settings, or it can convert the image data to reduce power consumption or compensate for afterimages. The gamma correction circuit 1012-3 can convert image data or a gamma reference voltage so that the image displayed on the electronic device 1000 has desired gamma characteristics. The rendering circuit 1012-4 can receive image data from the controller 1012-1 and can render the image data by taking into account the pixel arrangement of the display panel 1041 applied to the electronic device 1000. At least one of the data conversion circuit 1012-2, the gamma correction circuit 1012-3, and the rendering circuit 1012-4 can be integrated into another component (e.g., the main processor 1011 or the controller 1012-1). At least one of the data conversion circuit 1012-2, the gamma correction circuit 1012-3, and the rendering circuit 1012-4 can be integrated into the data driver 1043, which will be described below.

[0115] The memory 1020 may store various data used by at least one component of the electronic device 1000 (e.g., processor 1010 or sensor module 1061), as well as input or output data for commands in connection therewith. The memory 1020 may include at least one of volatile memory 1021 and non-volatile memory 1022.

[0116] The input module 1030 can receive commands or data from outside the electronic device 1000 (e.g., from a user or external electronic device 1002) to be used in components of the electronic device 1000 (e.g., processor 1010, sensor module 1061, or voice output module 1063).

[0117] Input module 1030 may include a first input module 1031 through which commands or data are input from a user, and a second input module 1032 through which commands or data are input from an external electronic device 1002. The first input module 1031 may include a microphone, mouse, keyboard, keys (e.g., buttons), or pen (e.g., a passive or active pen). The second input module 1032 may support a specified protocol that can be connected to the external electronic device 1002 via wired or wireless connection. In embodiments, the second input module 1032 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, an SD card interface, or an audio interface. The second input module 1032 may include a connector that can be physically connected to the external electronic device 1002, such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0118] Display module 1040 can provide visual information to a user. Display module 1040 may include display panel 1041, gate driver 1042, and data driver 1043. Display module 1040 may also include a window, chassis, and bracket to protect display panel 1041. Display module 1040 can be connected to... Figure 1 Display device 100 Figure 6 Display device 101 and Figure 8 The display device 102 corresponds to the display panel 1041. Figure 1 , Figure 6 and Figure 8 Corresponding to the display panel 110, the gate driver 1042 can be connected to... Figure 1 Gate driver 120 Figure 6 Gate driver 121 and Figure 8 The gate driver 122 corresponds to the data driver 1043, and the data driver 1043 can be connected to the gate driver 122. Figure 1 , Figure 6 and Figure 8 The data drive 130 is compatible.

[0119] Power module 1050 can supply power to components of electronic device 1000. Power module 1050 may include a battery that can be charged with a power voltage. The battery may include a non-rechargeable primary battery, a rechargeable storage battery, or a fuel cell. Power module 1050 may include power management circuitry 1051. Power management circuitry 1051 can provide optimized power to each of the modules described above and below. Power management circuitry 1051 can interact with... Figure 1 Power management circuit 140 Figure 6 The power management circuit 141 and Figure 8 The power management circuit 142 corresponds to this. The power module 1050 may include a wireless power transmitting / receiving component electrically connected to the battery. The wireless power transmitting / receiving component may include multiple coil-shaped antenna radiators.

[0120] The electronic device 1000 may also include an internal module 1060 and an external module 1070. The internal module 1060 may include a sensor module 1061, an antenna module 1062, and a sound output module 1063. The external module 1070 may include a camera module 1071, an optical module 1072, and a communication module 1073.

[0121] Sensor module 1061 can detect input from the user's body or from the pen in the first input module 1031, and can generate an electrical signal or data value corresponding to the input. Sensor module 1061 may include at least one of fingerprint sensor 1061-1, input sensor 1061-2, and digitizer 1061-3.

[0122] The processor 1010 can output commands or data to the display module 1040, the sound output module 1063, the camera module 1071, or the optical module 1072 based on input data received from the input module 1030. For example, the processor 1010 can generate image data and output the image data to the display module 1040 in response to input data applied by a mouse or active pen, or it can generate command data in response to input data to output command data to the camera module 1071 or the optical module 1072. When no input data is received from the input module 1030 for a certain period of time, the processor 1010 can switch the operating mode of the electronic device 1000 to a low-power mode or a sleep mode to reduce the power consumption of the electronic device 1000.

[0123] The processor 1010 can output commands or data to the display module 1040, the sound output module 1063, the camera module 1071, or the optical module 1072 based on the sensing data received from the sensor module 1061. For example, the processor 1010 can compare the authentication data authorized by the fingerprint sensor 1061-1 with the authentication data stored in the memory 1020, and then execute an application based on the comparison result. The processor 1010 can execute commands or output corresponding image data to the display module 1040 based on the sensing data detected by the input sensor 1061-2 or the digitizer 1061-3. When the sensor module 1061 includes a temperature sensor, the processor 1010 can receive temperature data measured from the sensor module 1061, and can also perform brightness correction of image data, etc., based on the temperature data.

[0124] The display device according to the embodiments (e.g., display device 100, display device 101, or display device 102) can be applied to display devices included in computers, laptops, mobile phones, smartphones, smartboards, smartwatches, PMPs, PDAs, MP3 players, etc.

[0125] Although pixels, display devices, and electronic devices according to embodiments have been described with reference to the accompanying drawings, the embodiments shown are examples and can be modified and altered by those skilled in the art without departing from the spirit of the technology described in the appended claims.

Claims

1. Pixel, including: The first transistor includes a gate connected to a first node, a first terminal connected to a second node, and a second terminal connected to a third node; The second transistor transmits a data signal to the first node in response to a write gate signal; The third transistor transmits a sustaining voltage to the third node in response to a compensation gate signal; The fourth transistor transmits a first electrical voltage to the second node in response to a transmitted signal; A first capacitor is connected between the first node and the second node; A second capacitor is connected between the second node and the power line that transmits the first power voltage; as well as The light-emitting element includes a first terminal connected to the third node and a second terminal receiving a second electrical voltage.

2. The pixel according to claim 1, wherein, During the initialization period, the first power voltage transitions from a high level to a low level, the second power voltage transitions from a low level to a high level, the compensation gate signal transitions from a deactivation level to an activation level, and the transmit signal has an activation level.

3. The pixel according to claim 2, wherein, During the initialization period, the first power voltage is applied to the third node through the fourth transistor and the first transistor.

4. The pixel according to claim 2, wherein, During the compensation period following the initialization period, the write gate signal has an active level, the sustain voltage has a high level, the compensation gate signal transitions from the active level to the deactivated level, the transmit signal transitions from the active level to the deactivated level, and the data signal has a reference voltage.

5. The pixel according to claim 4, wherein, During the compensation period, the first capacitor stores the threshold voltage of the first transistor.

6. The pixel according to claim 4, wherein, During the addressing period following the compensation period, the write gate signal includes a pulse having the activation level, and the data signal has a data voltage.

7. The pixel according to claim 6, wherein, During the bypass period following the addressing period, the sustaining voltage has a low level, and the compensation gate signal has the activation level.

8. The pixel according to claim 7, wherein, During the transmission period following the bypass period, the first power voltage has the high level, the second power voltage has the low level, and the transmission signal has the activation level.

9. The pixel according to claim 1, wherein, During the initialization period, the first power voltage transitions from a high level to a low level, the second power voltage transitions from a low level to a high level, the sustaining voltage has a low level, the compensation gate signal transitions from a deactivated level to an activated level, and the transmit signal has a deactivated level.

10. The pixel according to claim 9, wherein, During the initialization period, the sustaining voltage is applied to the third node via the third transistor.

11. The pixel according to claim 1, wherein, Each of the first transistor, the second transistor, the third transistor, and the fourth transistor is a p-type metal-oxide-semiconductor transistor.

12. The pixel according to claim 1, wherein, The first transistor is a p-type metal-oxide-semiconductor transistor, and Wherein, at least one of the second transistor, the third transistor, and the fourth transistor is an n-type metal-oxide-semiconductor transistor.

13. The pixel according to claim 1, further comprising: The fifth transistor transmits an initialization voltage to the second node in response to the initialization gate signal.

14. The pixel according to claim 13, wherein, During the initialization period, the first power voltage transitions from a high level to a low level, the second power voltage transitions from a low level to a high level, the compensation gate signal transitions from a deactivated level to an activated level, the transmit signal has a deactivated level, and the initialization gate signal has an activated level.

15. The pixel according to claim 14, wherein, During the initialization period, the initialization voltage is applied to the third node through the fifth transistor and the first transistor.

16. A display device, including: The display panel includes multiple pixels; A gate driver provides a write gate signal, a compensation gate signal, and an transmit signal to each of the plurality of pixels; A data driver that provides a data signal to each of the plurality of pixels; as well as The power management circuit provides a first power voltage, a second power voltage, and a sustaining voltage to each of the plurality of pixels. Each of the plurality of pixels includes: The first transistor includes a gate connected to a first node, a first terminal connected to a second node, and a second terminal connected to a third node; The second transistor transmits the data signal to the first node in response to the write gate signal; The third transistor transmits the sustaining voltage to the third node in response to the compensation gate signal; The fourth transistor transmits the first power voltage to the second node in response to the transmitted signal; A first capacitor is connected between the first node and the second node; A second capacitor is connected between the second node and the power line transmitting the first power voltage; and The light-emitting element includes a first terminal connected to the third node and a second terminal receiving the second electrical voltage.

17. The display device according to claim 16, wherein, The gate driver sequentially provides the write gate signal to the pixel row, and commonly provides the compensation gate signal and the transmit signal to the pixel row. The power management circuit provides the first power voltage to the common ground of the pixel row.

18. The display device according to claim 16, wherein, The gate driver sequentially provides the write gate signal, the compensation gate signal, and the transmit signal to the pixel row, and The power management circuit sequentially provides the first power voltage to the pixel row.

19. The display device according to claim 16, wherein, The gate driver also provides an initialization gate signal to each of the plurality of pixels. The power management circuit also provides an initialization voltage to each of the plurality of pixels, and Each of the plurality of pixels further includes a fifth transistor that transmits the initialization voltage to the second node in response to the initialization gate signal.

20. Electronic devices, including: The display panel includes multiple pixels; A gate driver provides a write gate signal, a compensation gate signal, and an transmit signal to each of the plurality of pixels; A data driver that provides a data signal to each of the plurality of pixels; A power management circuit provides a first power voltage, a second power voltage, and a sustaining voltage to each of the plurality of pixels; The controller controls the gate driver, the data driver, and the power management circuitry. as well as The processor provides input image data and control signals to the controller; Each of the plurality of pixels includes: The first transistor includes a gate connected to a first node, a first terminal connected to a second node, and a second terminal connected to a third node; The second transistor transmits the data signal to the first node in response to the write gate signal; The third transistor transmits the sustaining voltage to the third node in response to the compensation gate signal; The fourth transistor transmits the first power voltage to the second node in response to the transmitted signal; A first capacitor is connected between the first node and the second node; A second capacitor is connected between the second node and the power line transmitting the first power voltage; and The light-emitting element includes a first terminal connected to the third node and a second terminal receiving the second electrical voltage.

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