Transistor splicing circuit

Abstract

The invention provides a transistor splicing circuit. The transistor splicing circuit comprises a first transistor, a second transistor, a level shifter and an alternating current signal enhancement circuit. The level shifter is used for receiving a first input signal of a pair of differential input signals and shifting the first input signal to an offset bias level to generate an offset input signal to at least one of the gate of the first transistor and the gate of the second transistor. In addition, the AC signal enhancement circuit is configured to enhance the AC signal of the offset input signal according to a voltage difference between the first input signal and a second input signal of the pair of differential input signals. In particular, one of the first transistor and the second transistor is an N-type transistor and the other is a P-type transistor.

Description

Technical Field

[0001] This invention relates to amplifiers or source followers, and more particularly to a transistor stacked circuit (e.g., an inverter-type amplifier or source follower). Background Technology

[0002] Amplifiers operating at low supply voltages can utilize multiple transistors at their inputs to increase transconductance. However, these transistors may have optimal operating points at different bias levels. To ensure overall circuit performance, techniques can adjust the input signal bias level using level shifters to ensure the amplifier's input transistors operate at their optimal bias levels. However, these transistors typically possess parasitic capacitance, which attenuates the input signal during bias level adjustments, leading to a decrease in the amplifier's overall bandwidth and performance.

[0003] Therefore, a novel architecture is needed to address the above problems with little or no side effects. Summary of the Invention

[0004] The purpose of this invention is to provide a transistor stacking circuit (e.g., an inverter amplifier or a source follower) to enhance the magnitude of an input signal or reduce the attenuation of the input signal during the adjustment of the bias level without significantly increasing additional costs.

[0005] At least one embodiment of the present invention provides a transistor stacking circuit. The transistor stacking circuit includes a first transistor, a second transistor, a level shifter, and an AC signal enhancement circuit, wherein the second transistor is coupled to the first transistor, the level shifter is coupled to a gate of the first transistor and a gate of the second transistor, and the AC signal enhancement circuit is coupled to the gate of the first transistor and the gate of the second transistor. The level shifter is used to receive a first input signal of a pair of differential input signals and shift an initial bias level of the first input signal to an offset bias level to generate an offset input signal to at least one of the gates of the first transistor and the gate of the second transistor. Additionally, the AC signal enhancement circuit is used to enhance the offset input signal as an AC signal based on a voltage difference between the first input signal and a second input signal of the pair of differential input signals. Specifically, one of the first transistor and the second transistor is an N-type transistor, and the other of the first transistor and the second transistor is a P-type transistor.

[0006] The transistor stacking circuit provided by the embodiments of the present invention can compensate for the attenuation of the AC signal of the offset input signal using an AC signal enhancement circuit, thereby ensuring the overall performance of the transistor stacking circuit. Furthermore, the embodiments of the present invention do not significantly increase additional costs. Therefore, the present invention can solve the problems of related technologies without or with minimal side effects. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of an inverter-type amplifier according to an embodiment of the present invention.

[0008] Figure 2 This is a schematic diagram of a source follower according to an embodiment of the present invention.

[0009] Figure 3 This is a schematic diagram of a level offset device according to an embodiment of the present invention.

[0010] Figure 4 This is a schematic diagram of a level offset device according to another embodiment of the present invention.

[0011] Figure 5 This is a schematic diagram of a partial circuit of a source follower according to an embodiment of the present invention.

[0012] Figure 6 This is a schematic diagram of a partial circuit of a source follower according to another embodiment of the present invention.

[0013] Symbol Explanation

[0014] 10: Inverter type amplifier

[0015] 111, 112: Level offset

[0016] 121, 122: AC signal enhancement circuit

[0017] VIP, VIN, VOP, VON: Signals

[0018] V1, V2: Nodes

[0019] C1, C2, CP1, CP2: Capacitors

[0020] MP1, MP2, MN1, MN2: Transistors

[0021] SW1~SW8: Switches

[0022] φ1, φ2: Phase

[0023] np1, np2, nn1, nn2: Nodes

[0024] 20: Source Follower

[0025] MP3, MP4, MN3, MN4: Transistors

[0026] 311, 312: Level offset

[0027] VBP, VBN: Bias source

[0028] SW31~SW38: Switches

[0029] C31~C34: Capacitors

[0030] 411, 412: Level offset

[0031] MP41, MP42, MN41, MN42: Transistors

[0032] R41, R42: Resistors

[0033] C41, C42: Capacitors

[0034] VDDH: Voltage supply source

[0035] VSSN: Voltage supply source

[0036] VB1, VB2: Bias voltage

[0037] 50: Source follower

[0038] MN51, MP51: Transistors

[0039] 511, 512: Level offset

[0040] 521, 522: AC signal enhancement circuits

[0041] CB1, CB2, C51, C52: Capacitors

[0042] SW51~SW58: Switches

[0043] nk51, nk52, nk53: Nodes

[0044] 60: Source Follower

[0045] MN61~MN63, MP61~MP63: Transistors

[0046] 611N~613N, 611P~613P: Level offset

[0047] 621, 622: AC signal enhancement circuits

[0048] C61, C62: Capacitors

[0049] SW61~SW68: Switches

[0050] nk61, nk62, nk63: Nodes Detailed Implementation

[0051] Figure 1 This is a schematic diagram of a transistor stacked circuit, such as an inverter-type amplifier 10, according to an embodiment of the present invention. Figure 1 As shown, the inverter-type amplifier 10 may include: a first transistor, such as transistors MP1 and MP2; a second transistor, such as transistors MN1 and MN2; level shifters 111 and 112 (e.g., DC level shifting circuitry); and AC signal enhancement circuitry 121 and 122. In this embodiment, transistor MN1 is coupled to transistor MP1, and level shifter 111 is coupled to the gate of transistor MP1 (e.g., DC level shifting circuitry). Figure 1 The node np1 shown) and the gate of transistor MN1 (e.g. Figure 1 The node np2 shown, and the AC signal enhancement circuit 121 are coupled to the gates of transistor MP1 and transistor MN1. Additionally, transistor MN2 is coupled to transistor MP2, and level offset 112 is coupled to the gate of transistor MP2 (e.g., MN1). Figure 1 The node nn1 shown) and the gate of transistor MN2 (e.g. Figure 1The node nn2 shown, and the AC signal enhancement circuit 122 are coupled to the gates of transistor MP2 and transistor MN2. Since the inverter amplifier 10 is a differential circuit, the architecture of the left half of the inverter amplifier 10 is symmetrical to the architecture and operation of its right half. For simplicity, only the left half of the inverter amplifier 10 will be described below, and the rest can be deduced similarly. The level offsetter 111 is used to receive a first input signal (such as signal VIN) of a pair of differential input signals and offset the initial bias level of signal VIN to an offset bias level to generate an offset input signal to at least one of the gates of transistor MP1 and transistor MN1. Additionally, the AC signal enhancement circuit 121 is used to enhance the AC signal of the offset input signal based on the voltage difference between signal VIN and a second input signal (such as signal VIP) of the pair of differential input signals. In this embodiment, transistors MP1 and MP2 are P-type transistors, and transistors MN1 and MN2 are N-type transistors. It should be noted that transistors MP1 and MP2 are coupled to a node V1, wherein node V1 is coupled to a reference voltage source (e.g., a supply voltage source VDDH) or a supply current source (e.g., a supply current source coupled between the supply voltage source VDDH and node V1). Similarly, transistors MN1 and MN2 are coupled to a node V2, wherein node V2 is coupled to a reference voltage source (e.g., a supply voltage source VSSN) or a supply current source (e.g., a supply current source coupled between node V1 and the supply voltage source VSSN). In this embodiment, the voltage level of the supply voltage source VDDH may be higher than the voltage level of the supply voltage source VSSN, but the present invention is not limited thereto.

[0052] In this embodiment, the gate of transistor MP1 is used to receive the offset input signal, and the gate of transistor MN1 is used to receive the signal VIN. Specifically, level offsetter 111 can receive the signal VIN at node np2, which is coupled to the gate of transistor MN1, and offset the initial bias level of signal VIN (e.g., the bias level applicable to transistor MN1) to the bias level applicable to transistor MP1, thereby generating the offset input signal at node np1, which is coupled to the gate of transistor MP1. In this way, transistors MP1 / MP2 and MN1 / MN2 can operate at appropriate bias levels to generate a pair of differential output signals, such as signals {VOP, VON}. However, since the gates of transistors MP1 and MP2 (e.g., nodes np1 and nn1) have parasitic capacitors CP1 and CP2, respectively, the present invention utilizes AC signal enhancement circuits 121 and 122 to enhance the AC signals at nodes np1 and nn1.

[0053] In this embodiment, the AC signal enhancement circuit 121 may include a capacitor C1, wherein the capacitor C1 is used to sample the voltage difference between signals VIN and VIP. Specifically, in a first phase (e.g., phase φ1) of a control clock, the first terminal of capacitor C1 (e.g., at...) Figure 1 The upper end of the capacitor C1 is used to receive the signal VIN, and the second end of capacitor C1 (e.g., capacitor C1 in...) Figure 1 The lower end of the capacitor C1 is used to receive the signal VIP. In a second phase (e.g., phase φ2) of the control clock, the first end of the capacitor C1 is coupled to the gate of the transistor MP1 (e.g., coupled to node np1), and the second end of the capacitor C1 is coupled to the gate of the transistor MN1 (e.g., coupled to node np2). Specifically, the AC signal enhancement circuit 121 also includes switches SW1, SW2, SW3, and SW4, wherein switch SW1 is coupled to the first end of the capacitor C1 and is used to receive the signal VIN, switch SW2 is coupled between the first end of the capacitor C1 and the gate of the transistor MP1 (e.g., node np1), switch SW3 is coupled to the second end of the capacitor C1 and is used to receive the signal VIP, and switch SW4 is coupled between the second end of the capacitor C1 and the gate of the transistor MN1 (e.g., node np2). In the first phase of the control clock, switches SW1 and SW3 are turned on (conducted) (in Figure 1 (The labels "SW1(φ1)" and "SW3(φ1)" are provided for clarity) while switches SW2 and SW4 are closed (open), allowing the voltage difference between signals VIN and VIP to be sampled across capacitor C1. In this second phase of the control clock, switches SW1 and SW3 are closed while switches SW2 and SW4 are open (in...) Figure 1 (The labels “SW2(φ2)” and “SW4(φ2)” are provided for clarity) so that the AC signal of the offset input signal on the gate of transistor MP1 is amplified based on the voltage difference on capacitor C1. The capacitor C2 in AC signal enhancement circuit 122, and switches SW5, SW6, SW7, and SW8, can be deduced similarly, and will not be elaborated upon here for simplicity.

[0054] In some embodiments, the inverter amplifier 10 may utilize a control signal generator to generate two non-overlapping control signals according to the control clock, wherein the two non-overlapping control signals may represent phases φ1 and φ2 respectively, but the invention is not limited thereto.

[0055] It should be noted that, Figure 1In some embodiments, the initial bias levels of signals VIN and VIP are bias levels applicable to transistor MN1 (e.g., the common-mode voltage of signals VIN and VIP is at the optimal operating level of transistor MN1), but the invention is not limited thereto. In some embodiments, the initial bias levels of input signals VIN and VIP are bias levels applicable to transistor MP1 (e.g., the common-mode voltage of signals VIN and VIP is at the optimal operating level of transistor MP1). In this case, level offsetter 111 can receive signal VIN at node np1 coupled to the gate of transistor MP1 and offset the initial bias level of signal VIN (e.g., the bias level applicable to transistor MP1) to the bias level applicable to transistor MN1, so as to generate the offset input signal at node np2 coupled to the gate of transistor MN1, wherein switch SW1 is used to receive signal VIN and switch SW3 is used to receive signal VIP to ensure that the polarity of the voltage difference across capacitor C1 can be used to enhance the AC signal of the offset input signal.

[0056] In this embodiment, transistors MP1 and MP2 are P-type transistors, while transistors MN1 and MN2 are N-type transistors. The drain of transistor MP1 is coupled to the drain of transistor MN1, and the drain of transistor MP2 is coupled to the drain of transistor MN2.

[0057] Figure 2 This is a schematic diagram of a transistor stacked circuit, such as a source follower 20, according to an embodiment of the present invention. Compared to Figure 1 In the inverter-type amplifier 10 shown, transistors MP1, MP2, MN1, and MN2 are replaced with transistors MN3, MN4, MP3, and MP4, respectively, while the rest remain the same. In particular, transistors MN and MN4 are N-type transistors, while transistors MP3 and MP4 are P-type transistors, wherein the source of transistor MN3 is coupled to the source of transistor MP3, and the source of transistor MN4 is coupled to the source of transistor MP4.

[0058] Figure 3 This is a schematic diagram of level shifters 311 and 312 according to an embodiment of the present invention, wherein level shifters 311 and 312 can respectively serve as Figure 1 and Figure 2 Examples of level offsetters 111 and 112 are shown. For simplicity, all subsequent examples will use the same characters. Figure 1 The inverter-type amplifier 10 shown is used for illustration, while... Figure 2 The level shifters 311 and 312 implemented in the source follower 20 shown can be deduced similarly. For example... Figure 3As shown, the level offsetter 311 may include capacitors C31 and C32 and switches SW31, SW32, SW33, and SW34, wherein capacitor C32 is coupled between the gate of transistor MP1 (e.g., node np1) and the gate of transistor MN1 (e.g., node np2). Furthermore, in this first phase of the control clock, switches SW31 and SW33 are turned on (in...). Figure 3 (The labels “SW31(φ1)” and “SW33(φ1)” are used for clarity) while switches SW32 and SW34 are closed, such that capacitor C31 is coupled between a first bias source, such as bias source VBP, and a second bias source, such as bias source VBN. Bias source VBP provides the bias levels for transistors MP1 and MP2, while bias source VBN provides the bias levels for transistors MN1 and MN2. In the second phase of the control clock, switches SW31 and SW33 are closed while switches SW32 and SW34 are open (in...) Figure 3 (The designations “SW32(φ2)” and “SW34(φ2)” are used for clarity) to couple capacitor C31 between the gate of transistor MP1 (e.g., node np1) and the gate of transistor MN1 (e.g., node np2). The operation of level offsetters 312 coupled to nodes nn1 and nn2 (e.g., capacitors C33 and C34 therein and switches SW35, SW36, SW37 and SW38) can be deduced similarly, and will not be elaborated here for simplicity.

[0059] Without the AC signal enhancement circuit 121, the magnitude of the AC signal at node np1 is attenuated due to the charge-sharing effect of capacitors C31, C32, and CP1. Assuming that capacitors C31 and C32 each have a capacitance of 2×C and the parasitic capacitor CP1 has a capacitance of 1×C, when signal VIN = Vcm - dV and signal VIP = Vcm + dV (Vcm represents the common-mode voltage of signals VIN and VIP, and dV represents the AC signal of signals VIN and VIP), the magnitude of the AC signal at node np1 is attenuated to ((4 / 5)×dV). Conversely, with the AC signal enhancement circuit 121 implemented, since capacitor C1 can sample the voltage difference between signals VIN and VIP (i.e., the AC signal of signals VIN and VIP), the signal attenuation caused by the charge-sharing effect can be compensated. Assuming that capacitors C1, C31, and C32 each have a capacitance of 2×C, while the parasitic capacitor CP1 has a capacitance of 1×C, when signal VIN = Vcm - dV and signal VIP = Vcm + dV, the magnitude of the AC signal at node np1 is ((5 / 4)×dV). Therefore, AC signal enhancement circuit 121 can effectively prevent the attenuation of the AC signal at node np1. The effect of AC signal enhancement circuit 122 can be deduced similarly, and will not be elaborated here for the sake of simplicity.

[0060] Figure 4 This is a schematic diagram of level offsetters 411 and 412 according to another embodiment of the present invention, wherein level offsetters 411 and 412 can respectively serve as Figure 1 and Figure 2 Examples of level offsetters 111 and 112 are shown. For simplicity, all subsequent examples will use the same characters. Figure 1 The inverter-type amplifier 10 shown is used for illustration, while... Figure 2 The level offsetters 411 and 412 implemented in the source follower 20 shown can be deduced similarly. For example... Figure 4 As shown, the level offsetter 411 may include a capacitor C41, a resistor R41, a first current source such as a transistor MP41 controlled by a bias voltage VB1, and a second current source such as a transistor MN41 controlled by a bias voltage VB2. The capacitor C41 is coupled between the gate of transistor MP1 (e.g., node np1) and the gate of transistor MN1 (e.g., node np2), while the resistor is coupled between the gate of transistor MP1 (e.g., node np1) and the gate of transistor MN1 (e.g., node np2). Additionally, transistor MP41 is coupled between a first reference voltage source such as a supply voltage source VDDH and the gate of transistor MP1 (e.g., node np1), and transistor MN41 is coupled between a second reference voltage source such as a supply voltage source VSSN and the gate of transistor MN1 (e.g., node np2). Therefore, the voltage difference generated by the currents of transistors MP41 and MN41 through resistor R41 represents the offset applied by level offset 411 to the input signal VIN, while capacitor C41 transmits the AC signal of the input signal VIN. In some embodiments, transistors MP41 or MN41 may be implemented using multiple transistors connected in series, but the invention is not limited thereto. Furthermore, the operation of level offset 412 coupled to nodes nn1 and nn2 (e.g., capacitor C42, resistor R42, and transistors MP42 and MN42 therein) can be deduced similarly, and will not be elaborated here for simplicity.

[0061] Figure 5 This is a partial circuit (e.g., the left half circuit) of a source follower 50 according to an embodiment of the present invention. Figure 5 As shown, the source follower 50 may include transistors MN51 and MP51, level shifters 511 and 512, and AC signal enhancement circuitry 521 and 522. In some embodiments, each of level shifters 511 and 512 may be used Figure 3 The level offset 311 shown is used for implementation. For example, when level offset 511 is implemented using level offset 311, Figure 5The capacitor CB1 shown can represent capacitor C32 in level offsetter 311. When level offsetter 512 is implemented using level offsetter 311, Figure 5 The capacitor CB2 shown may represent capacitor C32 in level offsetter 311. In some embodiments, each of level offsetters 511 and 512 may be used. Figure 4 The level offset 411 shown is used for implementation. For example, when level offset 511 is implemented using level offset 411, Figure 5 The capacitor CB1 shown can represent capacitor C41 in level offsetter 411. When level offsetter 512 is implemented using level offsetter 411, Figure 5 The capacitor CB2 shown represents capacitor C41 in level offsetter 411. For simplicity, level offsetters 511 and 512 are not shown in full. Figure 5 Those skilled in the art should be able to determine the correct use of capacitors CB1 and CB2 based on their properties. Figure 5 The positional understanding of how the level offset 311 or 411 architecture is implemented in this embodiment will not be elaborated here for the sake of simplicity.

[0062] In this embodiment, the level offset 511 (e.g., the capacitor CB1 therein) is coupled to an intermediate node such as node nk51 and the gate of transistor MN51 (e.g. Figure 5 The intermediate nodes, such as node nk52, are connected between each other, while level offset 512 (e.g., capacitor CB2 within it) is coupled to the gate of the intermediate node, such as node nk51, and transistor MP51 (e.g., ...). Figure 5 Between nodes nk53 shown. Level offsetter 511 is used to receive signal VIN from node nk51 and offset the initial bias level of signal VIN to a first bias level (e.g., the voltage level applicable to transistor MN51) to generate a first offset input signal to the gate of transistor MN51 (e.g., node nk52), while level offsetter 512 is used to receive signal VIN from node nk51 and offset the initial bias level of signal VIN to a second bias level (e.g., the voltage level applicable to transistor MP51) to generate a second offset input signal to the gate of transistor MP51 (e.g., node nk53).

[0063] In this embodiment, AC signal enhancement circuit 521 is coupled between the gate (e.g., node nk52) and node nk51 of transistor MN51, while AC signal enhancement circuit 522 is coupled between the gate (e.g., node nk53) and node nk51 of transistor MP51. AC signal enhancement circuit 521 is a first AC signal used to enhance the first offset input signal at the gate (e.g., node nk52) of transistor MN51 based on the voltage difference between signal VIN and signal VIP, and AC signal enhancement circuit 522 is a second AC signal used to enhance the second offset input signal at the gate of transistor MP51 based on the voltage difference between signal VIN and signal VIP.

[0064] like Figure 5 As shown, AC signal enhancement circuit 521 may include capacitor C51 and switches SW51, SW52, SW53, and SW54, while AC signal enhancement circuit 522 may include capacitor C52 and switches SW55, SW56, SW57, and SW58. In this first phase of the control clock, switches SW51, SW53, SW55, and SW57 are turned on (in...). Figure 5 (The symbols “SW51(φ1)”, “SW53(φ1)”, “SW55(φ1)”, and “SW57(φ1)” are used for clarity) while switches SW52, SW54, SW56, and SW58 are closed, so that the voltage difference between the sampled signal VIN and the signal VIP of each of capacitors C51 and C52 is achieved. In this second phase of the control clock, switches SW51, SW53, SW55, and SW57 are closed while switches SW52, SW54, SW56, and SW58 are opened (in...) Figure 5 (The labels “SW52(φ2)”, “SW54(φ2)”, “SW56(φ2)”, and “SW58(φ2)” are used for ease of understanding) so that capacitor C51 is coupled between the gate of transistor MN51 and node nk51, and capacitor C52 is coupled between the gate of transistor MP51 and node nk51, to respectively amplify the first AC signal of the first offset input signal on the gate of transistor MN51 and the second AC signal of the second offset input signal on the gate of transistor MP51.

[0065] In this embodiment, transistor MN51 is an N-type transistor and transistor MP51 is a P-type transistor. In some embodiments, transistor MN51 can be replaced by a P-type transistor and transistor MP51 can be replaced by an N-type transistor to... Figure 5 The source follower 50 shown is changed to an inverter type amplifier.

[0066] Figure 6This is a schematic diagram of a partial circuit (e.g., the left half) of a source follower 60 according to another embodiment of the present invention. Figure 6 As shown, the source follower 60 may include transistors MN61, MN62, MN63, MP61, MP62, and MP63, level offsets 611N, 612N, 613N, 611P, 612P, and 613P, and AC signal enhancement circuits 621 and 622. In this embodiment, level offsets 611N, 612N, and 613N can offset the signal VIN to the bias levels applicable to the gates of transistors MN61, MN62, and MN63, respectively, while level offsets 611P, 612P, and 613P can offset the signal VIN to the bias levels applicable to the gates of transistors MP61, MP62, and MP63, respectively. In some embodiments, each of the level offsets 611N, 612N, 613N, 611P, 612P, and 613P may be used... Figure 3 The level offset 311 shown is used for implementation. In some embodiments, each of the level offsets 611N, 612N, 613N, 611P, 612P, and 613P can be used. Figure 4 The level offset 411 shown is used for implementation. Those skilled in the art should be able to [implement this based on...] Figure 6 The architecture shown shows how to Figure 3 The level offset 311 shown or Figure 4 The level offset 411 shown is implemented in level offsets 611N, 612N, 613N, 611P, 612P and 613P, and will not be described in detail here for the sake of simplicity.

[0067] In this embodiment, the level offset 611N is coupled to an intermediate node such as node nk61 and the gate of transistor MN61 (e.g. Figure 6 Between nodes nk62 (as shown), level offsetter 612N is coupled between the output of level offsetter 611N and the gate of transistor MN62, while level offsetter 613N is coupled between the source of transistor MN62 and the gate of transistor MN63. Additionally, level offsetter 611P is coupled between intermediate nodes such as node nk61 and the gate of transistor MP61 (e.g., Figure 6Between nodes nk63 shown, level offsetter 612P is coupled between the output of level offsetter 611P and the gate of transistor MP62, while level offsetter 613P is coupled between the source of transistor MP62 and the gate of transistor MP63. Level offsetter 611N is used to receive signal VIN from node nk51 and offset the initial bias level of signal VIN to a first bias level (e.g., the voltage level applicable to transistor MN61) to generate a first offset input signal to the gate of transistor MN61 (e.g., node nk62). Level offsetter 612N can offset this first offset input signal to the voltage level applicable to the gate of transistor MN62, while level offsetter 613N can offset the signal at the source of transistor MN62 to the voltage level applicable to the gate of transistor MN63. Additionally, level offsetter 611P is used to receive signal VIN from node nk61 and offset the initial bias level of signal VIN to a second bias level (e.g., a voltage level suitable for transistor MP61) to generate a second offset input signal to the gate of transistor MP61 (e.g., node nk63). Level offsetter 612P can offset the second offset input signal to a voltage level suitable for the gate of transistor MP62, while level offsetter 613P can offset the signal at the source of transistor MP62 to a voltage level suitable for the gate of transistor MP63.

[0068] In this embodiment, AC signal enhancement circuit 621 is coupled between the gate (e.g., node nk62) and node nk61 of transistor MN61, while AC signal enhancement circuit 622 is coupled between the gate (e.g., node nk63) and node nk61 of transistor MP61. AC signal enhancement circuit 621 is a first AC signal used to enhance the first offset input signal at the gate (e.g., node nk62) of transistor MN61 based on the voltage difference between signal VIN and signal VIP, and AC signal enhancement circuit 622 is a second AC signal used to enhance the second offset input signal at the gate of transistor MP61 based on the voltage difference between signal VIN and signal VIP.

[0069] like Figure 5 As shown, AC signal enhancement circuit 621 may include capacitor C61 and switches SW61, SW62, SW63, and SW64, while AC signal enhancement circuit 622 may include capacitor C62 and switches SW65, SW66, SW67, and SW68. In this first phase of the control clock, switches SW61, SW63, SW65, and SW67 are turned on (in...). Figure 5(The labels “SW61(φ1)”, “SW63(φ1)”, “SW65(φ1)”, and “SW67(φ1)” are used for clarity.) Switches SW62, SW64, SW66, and SW68 are closed, so that the voltage difference between the sampled signal VIN and the signal VIP of each of capacitors C61 and C62 is achieved. In this second phase of the control clock, switches SW61, SW63, SW65, and SW67 are closed, while switches SW62, SW64, SW66, and SW68 are opened (in...). Figure 5 (The labels “SW62(φ2)”, “SW64(φ2)”, “SW66(φ2)”, and “SW68(φ2)” are used for ease of understanding) so that capacitor C61 is coupled between the gate of transistor MN61 and node nk61, and capacitor C62 is coupled between the gate of transistor MP61 and node nk61, to respectively amplify the first AC signal of the first offset input signal on the gate of transistor MN61 and the second AC signal of the second offset input signal on the gate of transistor MP61.

[0070] In this embodiment, transistors MN61, MN62, and MN63 are N-type transistors, while transistors MP61, MP62, and MP63 are P-type transistors. In some embodiments, transistors MN61, MN62, and MN63 can be replaced with P-type transistors, while transistors MP61, MP62, and MP63 can be replaced with N-type transistors, in order to... Figure 5 The source follower 50 shown is changed to an inverter type amplifier.

[0071] In summary, the transistor stacked circuit (e.g., an inverter amplifier or source follower) provided by embodiments of the present invention solves the signal attenuation problem by sampling the AC signal in the differential signal through a capacitor and using the charge on this capacitor to compensate for the AC signal in the offset input signal. The architecture of the present invention can be combined with various types of level shifters. Furthermore, embodiments of the present invention do not significantly increase additional costs. Therefore, the present invention solves the problems of related technologies without or with minimal side effects.

[0072] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A transistor stacked circuit, comprising: The first transistor; A second transistor is coupled to the first transistor; A level offset, coupled to a gate of the first transistor and a gate of the second transistor, is used to receive a first input signal of a pair of differential input signals and offset an initial bias level of the first input signal to an offset bias level to generate an offset input signal to at least one of the gates of the first transistor and the gate of the second transistor. An AC signal enhancement circuit, coupled to the gate of the first transistor and the gate of the second transistor, is used to enhance an AC signal of the offset input signal based on a voltage difference between the first input signal and a second input signal of the pair of differential input signals. One of the first transistor and the second transistor is an N-type transistor, and the other of the first transistor and the second transistor is a P-type transistor.

2. The transistor stacked circuit of claim 1, wherein a drain of the first transistor is coupled to a drain of the second transistor.

3. The transistor stacked circuit as claimed in claim 1, wherein a source of the first transistor is coupled to a source of the second transistor.

4. The transistor stacked circuit of claim 1, wherein the gate of the first transistor is used to receive the offset input signal, and the gate of the second transistor is used to receive the first input signal.

5. The transistor stacked circuit of claim 4, wherein the AC signal enhancement circuit comprises: A capacitor is used to sample the voltage difference between the first input signal and the second input signal; in: In a first phase of a control clock, a first terminal of the capacitor is used to receive the first input signal, and a second terminal of the capacitor is used to receive the second input signal; as well as In a second phase of the control clock, the first terminal of the capacitor is coupled to the gate of the first transistor, and the second terminal of the capacitor is coupled to the gate of the second transistor.

6. The transistor stacked circuit of claim 5, wherein the AC signal enhancement circuit further comprises: A first switch is coupled to the first terminal of the capacitor to receive the first input signal; A second switch is coupled between the first terminal of the capacitor and the gate of the first transistor; A third switch, coupled to the second terminal of the capacitor, is used to receive the second input signal; as well as A fourth switch is coupled between the second terminal of the capacitor and the gate of the second transistor; in: In the first phase of the control clock, the first switch and the third switch are turned on while the second switch and the fourth switch are turned off, so that the voltage difference between the first input signal and the second input signal is sampled on the capacitor. as well as In the second phase of the control clock, the first and third switches are turned off while the second and fourth switches are turned on, so that the AC signal of the offset input signal on the gate of the first transistor is amplified according to the voltage difference on the capacitor.

7. The transistor stacked circuit of claim 1, wherein the level offset comprises: A first capacitor is coupled between the gate of the first transistor and the gate of the second transistor; A second capacitor, wherein: In a first phase of a control clock, the second capacitor is coupled between a first bias source and a second bias source; as well as In a second phase of the control clock, the second capacitor is coupled between the gate of the first transistor and the gate of the second transistor.

8. The transistor stacked circuit of claim 1, wherein the level offset comprises: A capacitor is coupled between the gate of the first transistor and the gate of the second transistor; A resistor is coupled between the gate of the first transistor and the gate of the second transistor; A first current source is coupled between a first reference voltage source and the gate of the first transistor; as well as A second current source is coupled between a second reference voltage source and the gate of the second transistor.

9. The transistor stacked circuit as claimed in claim 1, wherein: This level offset includes: A first level offset is coupled between an intermediate node and the gate of the first transistor to receive the first input signal from the intermediate node and offset the initial bias level of the first input signal to a first bias level to generate a first offset input signal to the gate of the first transistor. as well as A second level offset is coupled between the intermediate node and the gate of the second transistor to receive the first input signal from the intermediate node and offset the initial bias level of the first input signal to a second bias level to generate a second offset input signal to the gate of the second transistor. as well as The AC signal enhancement circuit includes: A first AC signal enhancement circuit is coupled between the gate and the intermediate node of the first transistor to enhance a first AC signal of the first offset input signal on the gate of the first transistor based on the voltage difference between the first input signal and the second input signal. as well as A second AC signal enhancement circuit is coupled between the gate and the intermediate node of the second transistor to enhance a second AC signal of the second offset input signal on the gate of the second transistor based on the voltage difference between the first input signal and the second input signal.

10. The transistor stacked circuit of claim 9, wherein the first AC signal enhancement circuit and the second AC signal enhancement circuit each include a first capacitor and a second capacitor; in a first phase of a control clock, each of the first capacitor and the second capacitor is used to sample the voltage difference between the first input signal and the second input signal; and in a second phase of the control clock, the first capacitor is coupled between the gate of the first transistor and the intermediate node, and the second capacitor is coupled between the gate of the second transistor and the intermediate node, to respectively enhance the first AC signal of the first offset input signal on the gate of the first transistor and the second AC signal of the second offset input signal on the gate of the second transistor.

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