A bidirectional directionless-controlled level shifter circuit

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to a bidirectional directionless level shift circuit. The bidirectional directionless level shift circuit comprises a first driving module, a first level detection module, an internal direction control circuit and a second driving module. The first driving module comprises a PMOS tube P1 and an NMOS tube N1. The first level detection module comprises a comparator CMP1. The internal direction control circuit is used for inputting signals A, B and C at an input end and outputting enable signals EN_A and EN_B at an output end. The second driving module comprises a PMOS tube P2 and an operational amplifier OPA1. The second level detection module comprises comparators CMP2-CMP3. The bidirectional directionless level shift is realized by the way that the input low level of one port is lower than the output low level plus the latch port behavior. The port conflict problem when both the two ports are used as inputs is solved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a bidirectional level shifting circuit without directional control. Background Technology

[0002] like Figure 1 and Figure 2 As shown, the existing technical solution achieves bidirectional level shifting by using two level shifting units and direction control selection. This existing technical solution achieves bidirectional signal transmission through DIR direction selection. When the DIR direction selection signal is logic "0", level shifting unit 1 is enabled, and level shifting unit 2 is disabled, allowing the signal to be transmitted from port A to port B. When the DIR direction selection signal is logic "1", level shifting unit 2 is enabled, and level shifting unit 1 is disabled, allowing the signal to be transmitted from port B to port A. When port A receives a logic "0", Buffer1 outputs logic "0" and inv4 outputs logic "1", causing N1 to turn off and N2 to turn on. This pulls the voltage at port B low, which in turn turns on PM1. The turn on of PM1 pulls the gate of PM2 high, causing PM2 to turn off. The turn off of PM2 further accelerates the pull-down of the voltage at port B, thus forming a positive feedback loop that quickly pulls the voltage at port B low. This ensures that the logic "0" from port A is transmitted to port B. When port A receives a logic "1", Buffer1 outputs logic "1", and inv4... Outputting logic "0" turns NM1 on and off, and turns NM2 off. This pulls the voltage at the drain of NM1 low, which in turn turns on PM2. The turning on of PM2 pulls the gate of PM1 high, turning PM1 off. The turning off of PM1 further accelerates the pull-down of the drain of NM1, quickly turning PM2 on and rapidly pulling port B high to logic "1". Thus, logic "1" from port A is transmitted to logic "1" from port B. Since ports A and B are in different voltage domains, this achieves level shifting. Similarly, the principle of level shifting from port B to port A is the same as that from port A to port B, and will not be described further here.

[0003] Therefore, the existing technical solutions have the following technical defects:

[0004] 1) Port direction control requires an additional direction selection signal;

[0005] 2) Unable to handle signal conflicts at the port. Summary of the Invention

[0006] The purpose of this invention is to provide a bidirectional, undirected level shifting circuit. This invention utilizes the input low level of one port being lower than the output low level, along with latching port behavior, to achieve undirected bidirectional level shifting; and solves the port conflict problem when both ports are used as inputs.

[0007] To solve the above-mentioned technical problems, the present invention provides a bidirectional, directionless level shifting circuit, comprising:

[0008] The first driving module includes a PMOS transistor P1 and an NMOS transistor N1; the gate terminal of the PMOS transistor P1 is connected to a bias voltage VBIAS, the source terminal of the PMOS transistor P1 is connected to a power supply VCC1, the drain terminal of the PMOS transistor P1 is connected to port A and the drain terminal of the NMOS transistor N1, the gate terminal of the NMOS transistor N1 is connected to an enable signal EN_A, and the source terminal of the NMOS transistor N1 is grounded.

[0009] The first level detection module includes a comparator CMP1; the non-inverting input of the comparator CMP1 is connected to port A, the inverting input of the comparator CMP1 is connected to a reference voltage VREF1, and the output of the comparator CMP1 outputs signal A.

[0010] The internal direction control circuit has input terminals for input signals A, B and C, and output terminals for output enable signals EN_A and EN_B.

[0011] The second driving module includes a PMOS transistor P2 and an operational amplifier OPA1. The gate terminal of the PMOS transistor P2 is connected to a bias voltage VBIAS, the source terminal of the PMOS transistor P2 is connected to a power supply VCC2, the drain terminal of the PMOS transistor P2 is connected to the output terminal and port B of the operational amplifier OPA1, the non-inverting input terminal of the operational amplifier OPA1 is connected to a reference voltage VREF2, the inverting input terminal of the operational amplifier OPA1 is connected to its output terminal, and the control terminal of the operational amplifier OPA1 is connected to the enable signal EN_B.

[0012] The second level detection module includes comparators CMP2~CMP3; the non-inverting input terminals of the comparators CMP2~CMP3 are connected to port B, the inverting input terminals of the comparators CMP2~CMP3 are respectively connected to reference voltages VREF3~VREF4, and the output terminals of the comparators CMP2~CMP3 output the signal B and the signal C respectively.

[0013] The internal direction control circuit includes:

[0014] Latch module one has its input terminals used to input signals A, B and C, and its output terminal used to output latch signal Q1.

[0015] Latch module 2 has its input terminals used for input signals A and C, and its output terminal used for outputting latch signal Q2;

[0016] Latch module three has its input terminals used for input signals A, C and latch signals Q1~Q2, and its output terminal used for output latch signal Q3;

[0017] Enable module 1 has its input terminals used for input signals A, B and latch signals Q1~Q2, and its output terminal used for outputting the enable signal EN_B;

[0018] Enable module 2 has its input terminals used for input signal B and latch signals Q1 and Q3, and its output terminal used for outputting enable signal EN_A.

[0019] Preferably, the latching module includes: NAND gates NAND1~NAND3 and buffers BUF1~BUF3; the two inputs of NAND gate NAND1 are respectively input to signal A and signal C, the output of NAND gate NAND1 is connected to one input of NAND gate NAND2 through buffer BUF1, the other input of NAND gate NAND2 is input to latch signal Q1, the output of NAND gate NAND2 is connected to one input of NAND gate NAND3, the signal B is connected to the other input of NAND gate NAND3 through buffers BUF2~BUF3, and the output of NAND gate NAND3 outputs latch signal Q1.

[0020] Preferably, the latch module two includes: NAND gates NAND4~NAND7, buffers BUF4~BUF5, and NOT gate NOT1; the input of NOT gate NOT1 is connected to signal A, the output of NOT gate NOT1 is connected to one input of NAND gate NAND4, the other input of NAND gate NAND4 is connected to signal C, the output of NAND gate NAND4 is connected to the input of buffer BUF4, the output of buffer BUF4 is connected to one input of NAND gate NAND5, the output of NAND gate NAND5 outputs latch signal Q2 and is connected to one input of NAND gate NAND7, signals A and C are respectively connected to the two inputs of NAND gate NAND6, the output of NAND gate NAND6 is connected to the input of buffer BUF5, the output of buffer BUF5 is connected to the other input of NAND gate NAND7, and the output of NAND gate NAND7 is connected to the other input of NAND gate NAND5.

[0021] Preferably, the latch module three includes: OR gates OR1~OR3, NOT gate NOT2, NOR gate NOR1, buffers BUF6~BUF7, and NAND gates NAND8~NAND9; the two inputs of OR gate OR1 are respectively connected to latch signals Q1~Q2, the input of NOT gate NOT2 is connected to signal A, the input of buffer BUF6 is connected to signal C, the outputs of OR gate OR1, NOT gate NOT2, and buffer BUF6 are respectively connected to the three inputs of OR gate OR2, and the output of OR gate OR2 is connected to one of the NAND gates NAND8. At the input terminals, the output terminal of the NAND gate NAND8 outputs a latch signal Q3 and connects to one input terminal of the NAND gate NAND9. The output terminal of the NAND gate NAND9 is connected to the other input terminal of the NAND gate NAND8. The latch signal Q1 is connected to the input terminal of the buffer BUF7. The latch signal Q2 and the signal C are respectively connected to the two input terminals of the OR gate OR3. The output terminals of the buffer BUF7 and the OR gate OR3 are respectively connected to the two input terminals of the NOR gate NOR1. The output terminal of the NOR gate NOR1 is connected to the other input terminal of the NAND gate NAND9.

[0022] Preferably, the enabling module one includes: NOT3~NOT5 and NAND10~NAND13; the input terminal of NOT3 is connected to signal A, the output terminal of NOT3 and the latch signal Q1 are respectively connected to the two input terminals of NAND10, the input terminal of NOT4 is connected to signal B, the output terminal of NOT4 and the latch signal Q1 are respectively connected to the two input terminals of NAND11, signal A is connected to the input terminal of NOT5, the output terminal of NOT5 and the latch signal Q2 are respectively connected to the two input terminals of NAND12, the output terminals of NAND10~NAND12 are respectively connected to the three input terminals of NAND13, and the output terminal of NAND13 outputs the enabling signal EN_B.

[0023] Preferably, the second enabling module includes: NOT6~NOT7, BUF8, and NAND14~NAND15; the input of NOT6 is connected to signal B, the output of NOT6 and latch signal Q1 are respectively connected to the two inputs of NAND14, the latch signal Q3 is connected to the input of NOT7, the output of NOT7 is connected to the input of BUF8, the outputs of NAND14 and BUF8 are respectively connected to the two inputs of NAND15, and the output of NAND15 outputs an enabling signal EN_A.

[0024] Preferably, it also includes a VREF1 generation circuit, which includes a resistor string Rf1. One end of the resistor string Rf1 is connected to the power supply VCC1, and the other end is grounded. The reference voltage VREF1 is generated by voltage division through the resistor string Rf1.

[0025] Preferably, it further includes a VBIAS generation circuit, which includes: PMOS transistors P3~P13, NMOS transistors N2~N5, transistors Q1~Q3, resistors R1~R3, operational amplifier OPA2, and capacitor C1; the source and substrate terminals of PMOS transistor P3, and the substrate terminals of PMOS transistors P4~P8 are all connected to power supply VCC2; the gate terminals of PMOS transistors P3~P8 are connected to and grounded by resistor R1; the drain terminal of PMOS transistor P3 is connected to the source terminal of PMOS transistor P4; the PMOS transistor... The drain of S-channel MOSFET P4 is connected to the source of PMOS transistor P5. The drain of PMOS transistor P5 is connected to the source of PMOS transistor P6. The drain of PMOS transistor P6 is connected to the source of PMOS transistor P7. The drain of PMOS transistor P7 is connected to the source of PMOS transistor P8. The drain of PMOS transistor P8 is connected to the drain of NMOS transistor N2 and the gate of NMOS transistor N3. The gate of NMOS transistor N2 is connected to the bandgap reference voltage BG_VREF. The sources of NMOS transistors N2-N3 are connected to the base voltages of transistors Q1-Q3. The collector and drain terminals of NMOS transistors N4-N5 are connected to ground. The drain terminal of NMOS transistor N3 is connected to the gate terminal of PMOS transistors P9-P12. The source terminals of PMOS transistors P9-P13 are connected to power supply VCC2. The drain terminal of PMOS transistor P9 is connected to the emitter terminal of transistor Q1 and the inverting input terminal of operational amplifier OPA2. The non-inverting input terminal of operational amplifier OPA2 is connected to one end of resistor R2 and the drain terminal of PMOS transistor P10. The other end of resistor R2 is connected to the emitter terminal of transistor Q2. The operational amplifier O... The output terminal of PA2 is connected to one end of capacitor C1 to generate a bias voltage VB1. The other end of capacitor C1 is connected to power supply VCC2. The drain terminal of PMOS transistor P11 is connected to one end of resistor R3 to generate a bandgap reference voltage BG_VREF. The other end of resistor R3 is connected to the emitter of transistor Q3. The drain terminal of PMOS transistor P12 is connected to the drain and gate terminals of NMOS transistor N4 and NMOS transistor N5. The drain terminal of NMOS transistor N5 is connected to the drain and gate terminals of PMOS transistor P13 to generate a bias voltage VBIAS.

[0026] Preferably, the system further includes a VREF2~VREF4 generation circuit, which comprises: an operational amplifier OPA3, an NMOS transistor N6, a capacitor C2, and a resistor string Rf2; the inverting input terminal of the operational amplifier OPA3 is connected to a bandgap reference voltage BG_VREF and a grounded capacitor C2; the non-inverting input terminal of the operational amplifier OPA3 is connected to the grounded resistor string Rf2 and the source terminal of the NMOS transistor N6; the output terminal of the operational amplifier OPA3 is connected to the gate terminal of the NMOS transistor N6; and the drain terminal of the NMOS transistor N6 is connected to a power supply VCC2. The reference voltages VREF2~VREF4 are generated by voltage division through the resistor string Rf2.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] This invention sets VREF1=1.0V, VREF2=0.5V, VREF3=0.4V, and VREF4=1.5V.

[0029] When the input to port A is higher than 1.0V (input H), port B outputs VCC2 (output H); when the input to port A is lower than 1.0V (input L), port B outputs 0.5V (output L); when the input to port B is higher than 1.5V (input H), port A outputs VCC1 (output H); when the input to port B is lower than 1.5V (input L), port A outputs 0V (output L); when the input to port A is lower than 1.0V (input L) and the input to port B is lower than 0.4V (input L), the input to port A is released, and port A outputs 0V (output L).

[0030] When the input of port B is lower than 0.4V (input L) and the input of port A is lower than 1.0V (input L), the input of port B is released, and port B outputs 0.5V (output L). This invention utilizes the method of a port's input low level being lower than its output low level plus latching port behavior to achieve bidirectional level shifting without direction control; it solves the port conflict problem when both ports are used as inputs. Attached Figure Description

[0031] Figure 1 This is a circuit diagram of a bidirectional level shifter circuit based on existing technology.

[0032] Figure 2 yes Figure 1 The circuit diagram of the two level shifting units in the circuit.

[0033] Figure 3 This is a circuit diagram of a bidirectional, directionless level shifting circuit provided by the present invention.

[0034] Figure 4 This is a circuit diagram of latch module one provided by the present invention.

[0035] Figure 5 This is a circuit diagram of latch module two provided by the present invention.

[0036] Figure 6 This is a circuit diagram of latch module three provided by the present invention.

[0037] Figure 7 This is a circuit diagram of the enable module one provided by the present invention.

[0038] Figure 8 This is a circuit diagram of the enabling module two provided by the present invention.

[0039] Figure 9 This is a circuit diagram of the VREF1 generation circuit provided by the present invention.

[0040] Figure 10 This is a circuit diagram of the VBIAS generation circuit and the VREF2~VREF4 generation circuit provided by the present invention. Detailed Implementation

[0041] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0042] like Figure 3 As shown, this embodiment of the invention provides a bidirectional, directionless level shifting circuit, comprising:

[0043] The first driving module includes a PMOS transistor P1 and an NMOS transistor N1; the gate terminal of the PMOS transistor P1 is connected to a bias voltage VBIAS, the source terminal of the PMOS transistor P1 is connected to a power supply VCC1, the drain terminal of the PMOS transistor P1 is connected to port A and the drain terminal of the NMOS transistor N1, the gate terminal of the NMOS transistor N1 is connected to an enable signal EN_A, and the source terminal of the NMOS transistor N1 is grounded.

[0044] The first level detection module includes a comparator CMP1; the non-inverting input of the comparator CMP1 is connected to port A, the inverting input of the comparator CMP1 is connected to a reference voltage VREF1, and the output of the comparator CMP1 outputs signal A.

[0045] The internal direction control circuit has input terminals for input signals A, B and C, and output terminals for output enable signals EN_A and EN_B.

[0046] The second driving module includes a PMOS transistor P2 and an operational amplifier OPA1; the gate terminal of the PMOS transistor P2 is connected to a bias voltage VBIAS, the source terminal of the PMOS transistor P2 is connected to a power supply VCC2, the drain terminal of the PMOS transistor P2 is connected to the output terminal of the operational amplifier OPA1 and port B, the non-inverting input terminal of the operational amplifier OPA1 is connected to a reference voltage VREF2, the inverting input terminal of the operational amplifier OPA1 is connected to its output terminal, and the control terminal of the operational amplifier OPA1 is connected to the enable signal EN_B;

[0047] The second level detection module includes comparators CMP2 to CMP3; the non-inverting input terminals of the comparators CMP2 to CMP3 are connected to port B, the inverting input terminals of the comparators CMP2 to CMP3 are respectively connected to reference voltages VREF3 to VREF4, and the output terminals of the comparators CMP2 to CMP3 respectively output the signal B and the signal C.

[0048] Figure 1 In which VREF3 < VREF2 < VREF4, and VREF3, VREF2, and VREF4 are 0.4V, 0.5V, and 1.5V respectively.

[0049] As Figures 4-8 shown, the internal direction control circuit includes:

[0050] A latch module one, whose input terminal is used to input signals A, B, and C, and whose output terminal is used to output a latch signal Q1;

[0051] A latch module two, whose input terminal is used to input signals A and C, and whose output terminal is used to output a latch signal Q2;

[0052] A latch module three, whose input terminal is used to input signals A, C, and latch signals Q1 to Q2, and whose output terminal is used to output a latch signal Q3;

[0053] An enable module one, whose input terminal is used to input signals A, B, and latch signals Q1 to Q2, and whose output terminal is used to output an enable signal EN_B;

[0054] An enable module two, whose input terminal is used to input signal B and latch signals Q1 and Q3, and whose output terminal is used to output an enable signal EN_A.

[0055] Continue to refer to Figure 4The latching module includes: NAND gates NAND1~NAND3 and buffers BUF1~BUF3; the two inputs of NAND gate NAND1 are respectively input to signal A and signal C, the output of NAND gate NAND1 is connected to one input of NAND gate NAND2 through buffer BUF1, the other input of NAND gate NAND2 is input to latch signal Q1, the output of NAND gate NAND2 is connected to one input of NAND gate NAND3, the signal B is connected to the other input of NAND gate NAND3 through buffers BUF2~BUF3, and the output of NAND gate NAND3 outputs latch signal Q1.

[0056] Continue reading Figure 5 The latch module 2 includes: NAND gates NAND4~NAND7, buffers BUF4~BUF5, and NOT gate NOT1; the input of NOT gate NOT1 is connected to signal A, the output of NOT gate NOT1 is connected to one input of NAND gate NAND4, the other input of NAND gate NAND4 is connected to signal C, the output of NAND gate NAND4 is connected to the input of buffer BUF4, the output of buffer BUF4 is connected to one input of NAND gate NAND5, the output of NAND gate NAND5 outputs latch signal Q2 and is connected to one input of NAND gate NAND7, signals A and C are respectively connected to the two inputs of NAND gate NAND6, the output of NAND gate NAND6 is connected to the input of buffer BUF5, the output of buffer BUF5 is connected to the other input of NAND gate NAND7, and the output of NAND gate NAND7 is connected to the other input of NAND gate NAND5.

[0057] Continue reading Figure 6The latch module three includes: OR gates OR1~OR3, NOT gate NOT2, NOR gate NOR1, buffers BUF6~BUF7, and NAND gates NAND8~NAND9. The two inputs of OR gate OR1 are connected to latch signals Q1~Q2, the input of NOT gate NOT2 is connected to signal A, and the input of buffer BUF6 is connected to signal C. The outputs of OR gate OR1, NOT gate NOT2, and buffer BUF6 are connected to the three inputs of OR gate OR2, and the output of OR gate OR2 is connected to one input of NAND gate NAND8. The output of NAND gate NAND8 outputs a latch signal Q3 and is connected to one input of NAND gate NAND9. The output of NAND gate NAND9 is connected to the other input of NAND gate NAND8. The latch signal Q1 is connected to the input of buffer BUF7. The latch signal Q2 and the signal C are respectively connected to the two inputs of OR gate OR3. The outputs of buffer BUF7 and OR gate OR3 are respectively connected to the two inputs of NOR gate NOR1. The output of NOR gate NOR1 is connected to the other input of NAND gate NAND9.

[0058] Continue reading Figure 7 The enabling module includes: NOT3~NOT5 and NAND10~NAND13; the input of NOT3 is connected to signal A, the output of NOT3 and the latch signal Q1 are respectively connected to the two inputs of NAND10, the input of NOT4 is connected to signal B, the output of NOT4 and the latch signal Q1 are respectively connected to the two inputs of NAND11, signal A is connected to the input of NOT5, the output of NOT5 and the latch signal Q2 are respectively connected to the two inputs of NAND12, the outputs of NAND10~NAND12 are respectively connected to the three inputs of NAND13, and the output of NAND13 outputs the enable signal EN_B.

[0059] Continue reading Figure 8 The second enabling module includes: NOT6~NOT7, BUF8, and NAND14~NAND15; the input of NOT6 is connected to signal B, the output of NOT6 and latch signal Q1 are respectively connected to the two inputs of NAND14, the latch signal Q3 is connected to the input of NOT7, the output of NOT7 is connected to the input of BUF8, the outputs of NAND14 and BUF8 are respectively connected to the two inputs of NAND15, and the output of NAND15 outputs the enable signal EN_A.

[0060] The principle of the above-mentioned bidirectional level shift without direction control is as follows:

[0061] First, it should be noted that latch modules 1, 2, and 3 in the internal direction control circuit adopt an RS flip-flop structure. Latch module 1 latches the behavior of port B; latch module 2 latches the behavior of ports A and B; and latch module 3 latches the behavior of latch signals Q1 and Q2 with ports A and B. The behaviors are described below:

[0062] Latch signal Q1: When port B < 0.4V, latch "H"; when port A > 1.0V and port B > 1.5V, latch "L"; otherwise, it remains in hold state.

[0063] Latch signal Q2: When port A < 1.0V and port B > 1.5V, latch "H"; when port A > 1.0V and port B > 1.5V, latch "L"; otherwise, it remains in hold state.

[0064] Latch signal Q3: When latch signals Q1 and Q2 are "L" and port A > 1.0V and port B < 1.5V, latch "H"; when latch signal Q1 is "H" or latch signal Q2 is "H" or port B > 1.5V, latch "L"; otherwise, it is in hold state.

[0065] Having understood the working mechanisms of the three latching modules mentioned above, the working principle of the undirected level shifter will now be formally introduced:

[0066] Normal operating mode includes the following process ("H" refers to logic "1", and "L" refers to logic "0"):

[0067] Process 1: When ports A and B are not in operation: Ports A and B are pulled up to "H"; Since P1 and P2 are equivalent to weak pull-up resistors, when ports A and B are not in operation, ports A and B are pulled up. At this time, the latching of Q1 by latch module 1 is "L", the latching of Q2 by latch module 2 is "L", and the latching of Q3 by latch module 3 is "L". It can be deduced that the output of EN_B of enable module 1 is "L". The operational amplifier OPA1 of port B (as a follower) is not enabled, and port B is pulled up by P2; it can be deduced that the output of EN_A is "L". The driver transistor N1 of port A is not enabled, and port A is pulled up by P1.

[0068] Process 2: Input “H” at port A: equivalent to process 1.

[0069] Process 3: Input “H” at port B: equivalent to process 1.

[0070] Process 4: Port A inputs "L": Port B outputs 0.5V; Q1 of latch module 1 latches "L", Q2 of latch module 2 latches "H", and Q3 of latch module 3 latches "L", which results in EN_B of enable module 1 being "H". The OPA1 follower of port B is enabled, outputting 0.5V. At this time, Q1, Q2, and Q3 continue to maintain the previous state, EN_A is "L", and the driver transistor N1 of port A is not enabled.

[0071] Process 5: Port B inputs "L" (greater than 0.4V, less than 1.5V): Port A outputs 0V; Q1 of latch module 1 holds "L", Q2 of latch module 2 holds "L", Q3 of latch module 3 latches "H", enabling module 2 can get EN_A as "H", enabling module 1's EN_B is "L", the op-amp of port B is not enabled, the driver transistor N1 of port A is enabled, port A outputs "L", at this time Q1, Q2, Q3 maintain the previous state.

[0072] Process 6: Port B inputs "L" (less than 0.4V): Port A outputs 0V; Q1 of latch module 1 latches "H", Q2 of latch module 2 holds "L", and Q3 of latch module 3 latches "L", resulting in EN_A of enable module 2 being "H" and EN_B of enable module 1 being "H". At this time, N1, the driver transistor of port A, is enabled, and port A outputs 0V; OPA1, the follower of port B, is enabled. At this time, OPA1 acts as a comparator, and the input drive of port B is strong, forcibly pulling it low. At this time, Q1, Q2, and Q3 remain in the previous state.

[0073] Process 7: Input "L" to port A first, then input "L" to port B (<0.4V): This is equivalent to continuing to input "L" to port B after process 4; latch module 1's Q1 latches "H", latch module 2's Q2 holds "L", and latch module 3's Q3 latches "L", which results in enable module 2's EN_A being "H" and enable module 1's EN_B being "H", enabling the driver transistor N1 of port A and the follower OPA1 of port B.

[0074] Process 8: Input "L" (<0.4V) to port B first, then input "L" to port A: This is equivalent to continuing to input "L" to port A after process 6; Since port A in process 6 is the output "L", it is equivalent to inputting "L" to port A. This process is equivalent to process 6. Q1 of latch module 1 holds "H", Q2 of latch module 2 holds "L", and Q3 of latch module 3 holds "L".

[0075] Procedure 9: Release “L” input to port A after procedure 7: Port A outputs “L”.

[0076] The end state of process 7 is that Q1 of latch module 1 latches "H", Q2 of latch module 2 holds "L", and Q3 of latch module 3 latches "L". The driver transistor N1 of port A is enabled, and the follower OPA1 of port B is enabled. At this time, the input "L" of port A is released, and port A is pulled down by the driver transistor N1 of port A. At this time, Q1 holds "H", Q2 holds "L", and Q3 holds "L".

[0077] Process 10: Release “L” on port B after process 8: Port B outputs 0.5V.

[0078] When process 8 ends, Q1 of latch module 1 remains "H", Q2 of latch module 2 remains "L", and Q3 of latch module 3 remains "L". At this time, EN_B of enable module 1 outputs logic "1", which releases port B and enables OPA of port B, outputting 0.5V.

[0079] Process 11: Release port B after process 7: Port B outputs 0.5V.

[0080] The end state of process 7 is that Q1 holds "H", Q2 holds "L", Q3 holds "L", the driver transistor N1 of port A is enabled, and the follower OPA1 of port B is enabled. At this time, the "L" input of port B is released, and OPA1 of port B works, outputting 0.5V.

[0081] like Figure 9 As shown, it also includes a VREF1 generation circuit, which includes a resistor string Rf1. One end of the resistor string Rf1 is connected to the power supply VCC1, and the other end is grounded. The reference voltage VREF1 is generated by voltage division through the resistor string Rf1.

[0082] like Figure 10As shown, it also includes a VBIAS generation circuit, which includes: PMOS transistors P3~P13, NMOS transistors N2~N5, transistors Q1~Q3, resistors R1~R3, operational amplifier OPA2, and capacitor C1; the source and substrate terminals of PMOS transistor P3, and the substrate terminals of PMOS transistors P4~P8 are all connected to power supply VCC2; the gate terminals of PMOS transistors P3~P8 are connected to and grounded by resistor R1; the drain terminal of PMOS transistor P3 is connected to the source terminal of PMOS transistor P4; the PMOS... The drain of transistor P4 is connected to the source of PMOS transistor P5. The drain of PMOS transistor P5 is connected to the source of PMOS transistor P6. The drain of PMOS transistor P6 is connected to the source of PMOS transistor P7. The drain of PMOS transistor P7 is connected to the source of PMOS transistor P8. The drain of PMOS transistor P8 is connected to the drain of NMOS transistor N2 and the gate of NMOS transistor N3. The gate of NMOS transistor N2 is connected to the bandgap reference voltage BG_VREF. The sources of NMOS transistors N2-N3 are connected to the bases of transistors Q1-Q3. The collector and the source terminals of NMOS transistors N4-N5 are grounded. The drain terminal of NMOS transistor N3 is connected to the gate terminal of PMOS transistors P9-P12. The source terminals of PMOS transistors P9-P13 are connected to power supply VCC2. The drain terminal of PMOS transistor P9 is connected to the emitter of transistor Q1 and the inverting input terminal of operational amplifier OPA2. The non-inverting input terminal of operational amplifier OPA2 is connected to one end of resistor R2 and the drain terminal of PMOS transistor P10. The other end of resistor R2 is connected to the emitter of transistor Q2. The operational amplifier O... The output terminal of PA2 is connected to one end of capacitor C1 to generate a bias voltage VB1. The other end of capacitor C1 is connected to power supply VCC2. The drain terminal of PMOS transistor P11 is connected to one end of resistor R3 to generate a bandgap reference voltage BG_VREF. The other end of resistor R3 is connected to the emitter of transistor Q3. The drain terminal of PMOS transistor P12 is connected to the drain and gate terminals of NMOS transistor N4 and NMOS transistor N5. The drain terminal of NMOS transistor N5 is connected to the drain and gate terminals of PMOS transistor P13 to generate a bias voltage VBIAS.

[0083] Continue reading Figure 10It also includes VREF2~VREF4 generation circuits, which include: operational amplifier OPA3, NMOS transistor N6, capacitor C2, and resistor string Rf2; the non-inverting input terminal of operational amplifier OPA3 is connected to the bandgap reference voltage BG_VREF and the grounded capacitor C2, the inverting input terminal of operational amplifier OPA3 is connected to the grounded resistor string Rf2 and the source terminal of NMOS transistor N6, the output terminal of operational amplifier OPA3 is connected to the gate terminal of NMOS transistor N6, and the drain terminal of NMOS transistor N6 is connected to the power supply VCC2. The reference voltages VREF2~VREF4 are generated by voltage division through the resistor string Rf2.

[0084] Figure 10 P3~P8, R1, N2, and N3 form the startup circuit for the bandgap reference. When VCC2 is powered on, if the circuit is in a degenerate state (i.e., the gate of P9 is VCC2), BG_VREF is 0V. At this time, N3 turns on, pulling the gate of P9 low. When the bandgap reference circuit is working normally, BG_VREF outputs normally. Then, N2 turns on, turning off N3, thus shutting down the startup circuit.

[0085] Figure 10 P9, P10, OPA2, R2, Q1, Q2, P11, R3, and Q3 form a bandgap reference circuit, and the output reference voltage is: .

[0086] Figure 10 OPA3, N6, and Rf2 form an LDO structure used to generate VREF4, VREF2, and VREF3. C2 is connected across the output of the bandgap reference and the input of the LDO to filter out high-frequency noise, suppress oscillations, and buffer transient currents.

[0087] Figure 10 P12, N4, N5, and P13 are bias modules used to generate the VBIAS bias voltage. They are connected to... Figure 3 The gate terminals P1 and P2 in the middle serve as weak pull-up terminals.

[0088] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A bidirectional directionless-controlled level shifter circuit, characterized by, The application relates to a level shifter, which comprises: a first driving module comprising a PMOS tube P1 and an NMOS tube N1; the gate end of the PMOS tube P1 is connected with a bias voltage VBIAS, the source end of the PMOS tube P1 is connected with a power supply VCC1, the drain end of the PMOS tube P1 is connected with a port A and the drain end of the NMOS tube N1, the gate end of the NMOS tube N1 is connected with an enable signal EN_A, and the source end of the NMOS tube N1 is grounded; a first level detection module comprising a comparator CMP1; the non-inverting input end of the comparator CMP1 is connected with the port A, the inverting input end of the comparator CMP1 is connected with a reference voltage VREF1, and the output end of the comparator CMP1 outputs a signal A; an internal direction control circuit, which has input ends for inputting signals A, B and C and output ends for outputting enable signals EN_A and EN_B; a second driving module comprising a PMOS tube P2 and an operational amplifier OPA1; the gate end of the PMOS tube P2 is connected with the bias voltage VBIAS, the source end of the PMOS tube P2 is connected with the power supply VCC2, the drain end of the PMOS tube P2 is connected with the output end of the operational amplifier OPA1 and the port B, the non-inverting input end of the operational amplifier OPA1 is connected with the reference voltage VREF2, the inverting input end of the operational amplifier OPA1 is connected with the output end thereof, and the control end of the operational amplifier OPA1 is connected with the enable signal EN_B; a second level detection module comprising comparators CMP2-CMP3; the non-inverting input ends of the comparators CMP2-CMP3 are connected with the port B, the inverting input ends of the comparators CMP2-CMP3 are respectively connected with reference voltages VREF3-VREF4, and the output ends of the comparators CMP2-CMP3 respectively output the signals B and C; the internal direction control circuit comprises: a first latch module, which has input ends for inputting the signals A, B and C and an output end for outputting a latch signal Q1; a second latch module, which has input ends for inputting the signals A and C and an output end for outputting a latch signal Q2; a third latch module, which has input ends for inputting the signals A, C and the latch signals Q1-Q2 and an output end for outputting a latch signal Q3; a first enable module, which has input ends for inputting the signals A, B and the latch signals Q1-Q2 and an output end for outputting the enable signal EN_B; a second enable module, which has input ends for inputting the signal B and the latch signals Q1 and Q3 and an output end for outputting the enable signal EN_A.

2. A bidirectional, directionally-neutral level-shifting circuit as claimed in claim 1, characterized in that, The latch module one comprises NAND gates NAND1-NAND3 and buffers BUF1-BUF3; two inputs of the NAND gate NAND1 input signals A and C respectively, an output of the NAND gate NAND1 is connected to an input of the NAND gate NAND2 through the buffer BUF1, another input of the NAND gate NAND2 inputs a latch signal Q1, an output of the NAND gate NAND2 is connected to an input of the NAND gate NAND3, the signal B is connected to another input of the NAND gate NAND3 through the buffers BUF2-BUF3, and an output of the NAND gate NAND3 outputs the latch signal Q1.

3. A bidirectional, directionally-neutral level-shifting circuit as defined in claim 1, wherein, The latch module two comprises NAND gates NAND4-NAND7, buffers BUF4-BUF5 and a NOT gate NOT1; an input of the NOT gate NOT1 is connected to the signal A, an output of the NOT gate NOT1 is connected to an input of the NAND gate NAND4, another input of the NAND gate NAND4 is connected to the signal C, an output of the NAND gate NAND4 is connected to an input of the buffer BUF4, an output of the buffer BUF4 is connected to an input of the NAND gate NAND5, an output of the NAND gate NAND5 outputs a latch signal Q2 and is connected to an input of the NAND gate NAND7, the signals A and C are connected to two inputs of the NAND gate NAND6 respectively, an output of the NAND gate NAND6 is connected to an input of the buffer BUF5, an output of the buffer BUF5 is connected to another input of the NAND gate NAND7, and an output of the NAND gate NAND7 is connected to another input of the NAND gate NAND5.

4. A bidirectional, directionally-neutral level-shifting circuit as defined in claim 1, wherein, The latch module three comprises OR gates OR1-OR3, a NOT gate NOT2, a NOR gate NOR1, buffers BUF6-BUF7 and NAND gates NAND8-NAND9; two inputs of the OR gate OR1 are connected to the latch signals Q1-Q2 respectively, an input of the NOT gate NOT2 is connected to the signal A, an input of the buffer BUF6 is connected to the signal C, outputs of the OR gate OR1, the NOT gate NOT2 and the buffer BUF6 are connected to three inputs of the OR gate OR2 respectively, an output of the OR gate OR2 is connected to an input of the NAND gate NAND8, an output of the NAND gate NAND8 outputs a latch signal Q3 and is connected to an input of the NAND gate NAND9, an output of the NAND gate NAND9 is connected to another input of the NAND gate NAND8, the latch signal Q1 is connected to an input of the buffer BUF7, the latch signal Q2 and the signal C are connected to two inputs of the OR gate OR3 respectively, outputs of the buffer BUF7 and the OR gate OR3 are connected to two inputs of the NOR gate NOR1 respectively, an output of the NOR gate NOR1 is connected to another input of the NAND gate NAND9.

5. A bidirectional, directionally-neutral level-shifting circuit as defined in claim 1, wherein, The enable module one includes NOT gates NOT3~NOT5 and NAND gates NAND10~NAND13; an input end of the NOT gate NOT3 is connected to a signal A, an output end of the NOT gate NOT3 and the latch signal Q1 are connected to two input ends of the NAND gate NAND10 respectively, an input end of the NOT gate NOT4 is connected to a signal B, an output end of the NOT gate NOT4 and the latch signal Q1 are connected to two input ends of the NAND gate NAND11 respectively, the signal A is connected to an input end of the NOT gate NOT5, an output end of the NOT gate NOT5 and the latch signal Q2 are connected to two input ends of the NAND gate NAND12 respectively, output ends of the NAND gates NAND10~NAND12 are connected to three input ends of the NAND gate NAND13 respectively, and an output end of the NAND gate NAND13 outputs an enable signal EN_B.

6. A bidirectional, directionally-neutral level-shifting circuit as defined in claim 1, wherein, The enable module two includes NOT gates NOT6~NOT7, a buffer BUF8 and NAND gates NAND14~NAND15; an input end of the NOT gate NOT6 is connected to the signal B, an output end of the NOT gate NOT6 and the latch signal Q1 are connected to two input ends of the NAND gate NAND14 respectively, the latch signal Q3 is connected to an input end of the NOT gate NOT7, an output end of the NOT gate NOT7 is connected to an input end of the buffer BUF8, output ends of the NAND gate NAND14 and the buffer BUF8 are connected to two input ends of the NAND gate NAND15 respectively, and an output end of the NAND gate NAND15 outputs an enable signal EN_A.

7. A bidirectional, directionally-neutral level-shifting circuit as defined in claim 1, wherein, The VREF1 generating circuit includes a resistance string Rf1, one end of the resistance string Rf1 is connected to a power supply VCC1, the other end is grounded, and the reference voltage VREF1 is generated by voltage division through the resistance string Rf1.

8. A bidirectional, directionally-neutral level-shifting circuit as defined in claim 1, wherein, The VBIAS generating circuit comprises PMOS tubes P3-P13, NMOS tubes N2-N5, transistors Q1-Q3, resistors R1-R3, an operational amplifier OPA2 and a capacitor C1; the source end and substrate end of the PMOS tube P3 and the substrate ends of the PMOS tubes P4-P8 are connected to a power supply VCC2, the gate ends of the PMOS tubes P3-P8 are connected to the resistor R1 grounded, the drain end of the PMOS tube P3 is connected to the source end of the PMOS tube P4, the drain end of the PMOS tube P4 is connected to the source end of the PMOS tube P5, the drain end of the PMOS tube P5 is connected to the source end of the PMOS tube P6, the drain end of the PMOS tube P6 is connected to the source end of the PMOS tube P7, the drain end of the PMOS tube P7 is connected to the source end of the PMOS tube P8, the drain end of the PMOS tube P8 is connected to the drain end of the NMOS tube N2 and the gate end of the NMOS tube N3, the gate end of the NMOS tube N2 is connected to a bandgap reference voltage BG_VREF, the source ends of the NMOS tubes N2-N3 are connected to the bases and collectors of the transistors Q1-Q3 and the source ends of the NMOS tubes N4-N5 and grounded, the drain end of the NMOS tube N3 is connected to the gate ends of the PMOS tubes P9-P12, the source ends of the PMOS tubes P9-P13 are connected to the power supply VCC2, the drain end of the PMOS tube P9 is connected to the emitter of the transistor Q1 and the inverting input end of the operational amplifier OPA2, the non-inverting input end of the operational amplifier OPA2 is connected to one end of the resistor R2 and the drain end of the PMOS tube P10, the other end of the resistor R2 is connected to the emitter of the transistor Q2, the output end of the operational amplifier OPA2 is connected to one end of the capacitor C1 and generates a bias voltage VB1, the other end of the capacitor C1 is connected to the power supply VCC2, the drain end of the PMOS tube P11 is connected to one end of the resistor R3 and generates a bandgap reference voltage BG_VREF, the other end of the resistor R3 is connected to the emitter of the transistor Q3, the drain end of the PMOS tube P12 is connected to the drain end and gate end of the NMOS tube N4 and the gate end of the NMOS tube N5, the drain end of the NMOS tube N5 is connected to the drain end and gate end of the PMOS tube P13 and generates the bias voltage VBIAS.

9. A bidirectional, directionally-neutral level-shifting circuit as defined in claim 8, wherein, The VREF2-VREF4 generating circuit comprises an operational amplifier OPA3, an NMOS tube N6, a capacitor C2 and a resistor string Rf2; the inverting input end of the operational amplifier OPA3 is connected to the bandgap reference voltage BG_VREF and the capacitor C2 grounded, the non-inverting input end of the operational amplifier OPA3 is connected to the resistor string Rf2 and the source end of the NMOS tube N6 grounded, the output end of the operational amplifier OPA3 is connected to the gate end of the NMOS tube N6, the drain end of the NMOS tube N6 is connected to the power supply VCC2, the resistor string Rf2 divides the voltage to generate the reference voltages VREF2-VREF4.

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