Data synchronization transmission methods, electronic devices and computer-readable storage media

Abstract

This application relates to the field of data transmission technology, and in particular to a data synchronization transmission method, electronic device, and computer-readable storage medium. The method includes: acquiring raw bit data and generating a base clock signal adapted to the transmission requirements of the raw bit data; down-clocking the base clock signal to obtain synchronization clock information; fusing and encoding the raw bit data and the synchronization clock information to generate an encoded signal containing a clock region and a data region; sending the encoded signal to a receiving end through a single-line transmission link, enabling the receiving end to extract the synchronization clock information based on a preset difference filter, restoring the extracted synchronization clock information to a target clock signal with the same frequency as the base clock signal, and parsing the data region of the encoded signal based on the target clock signal to obtain target bit data consistent with the raw bit data, thereby achieving efficient synchronous transmission of bit data in a single-line environment.

Description

Technical Field

[0001] This application relates to the field of data transmission technology, and in particular to a data synchronization transmission method, electronic device, and computer-readable storage medium. Background Technology

[0002] As industrial automation and IoT devices rapidly evolve towards high-density integration and miniaturization, wiring space for devices such as intelligent sensor clusters, distributed data acquisition terminals, and PLCs (Programmable Logic Controllers) is becoming increasingly scarce. Furthermore, industrial scenarios are increasingly demanding simplified wiring, cost control, and ease of installation. Single-wire transmission technology, due to its ability to significantly reduce the number of lines, lower hardware complexity, and reduce wiring costs, has become the core preferred direction for data communication in such scenarios. It is particularly suitable for scenarios such as sensor-controller interconnection and short-distance data interaction between device modules. For example, digital isolator chips—traditional digital isolators require an independent isolation channel for each data bit, resulting in large chip size, numerous pins, and cumbersome wiring, contradicting the development trend of miniaturization and low cost.

[0003] Synchronous transmission of bit data is a fundamental requirement of industrial electronic systems. Current mainstream processing methods have significant limitations: First, using multiple data lines to transmit data bits in parallel, along with an independent clock line to provide a synchronization reference, while ensuring transmission speed, requires a large amount of wiring resources. This is difficult to adapt to scenarios such as robotic arm end effectors, high-density integrated modules, and digital isolator chips, and increases the complexity and failure rate of industrial field wiring. Second, using a single signal line to transmit only a single bit of data, splicing multiple bits of information through multiple transmissions (such as the traditional single-bus solution), although simplifying wiring, only 1 bit of data can be transmitted at a time, resulting in extremely low transmission efficiency. Furthermore, it suffers from high latency and weak anti-interference capabilities due to the influence of equipment filtering mechanisms and scanning cycles. It cannot meet the medium-speed data interaction requirements in industrial scenarios, severely restricting the performance improvement of devices such as intelligent sensors, distributed acquisition systems, and digital isolator chips. It also fails to meet the core requirements of industrial scenarios for "simple wiring, stable speed, and accurate synchronization" of bit data. Therefore, there is an urgent need for a technical solution that can efficiently and synchronously transmit bit data in a single-line environment. Summary of the Invention

[0004] The main objective of this application is to provide a data synchronization transmission method, electronic device, and computer-readable storage medium, which aim to efficiently and synchronously transmit bit data in a single-line environment.

[0005] To achieve the above objectives, this application provides a data synchronization transmission method applied to the sending end of a data synchronization transmission system. The data synchronization transmission method includes:

[0006] Obtain the raw bit data and generate a base clock signal that matches the transmission requirements of the raw bit data;

[0007] The basic clock signal is down-frequency processed to obtain synchronous clock information. The original bit data and synchronous clock information are fused and encoded to generate an encoded signal containing a clock area and a data area. The number of pulse duration cycles in the clock area and the number of pulse duration cycles in the data area have a preset difference.

[0008] The encoded signal is sent to the receiving end through a single-line transmission link, so that the receiving end can extract the synchronization clock information based on the preset difference filter, restore the extracted synchronization clock information to the target clock signal with the same frequency as the basic clock signal, and analyze the data area of ​​the encoded signal based on the target clock signal to obtain the target bit data that is consistent with the original bit data.

[0009] To achieve the above objectives, this application provides a data synchronization transmission method, applied at the receiving end of a data synchronization transmission system, the data synchronization transmission method comprising:

[0010] The encoded signal is received by the transmitter through a single-line transmission link. The encoded signal includes a clock area and a data area. The number of pulse duration cycles in the clock area and the number of pulse duration cycles in the data area have a preset difference.

[0011] Based on the preset differences, narrow pulses in the data area of ​​the encoded signal are filtered by narrow pulse filtering to extract the synchronization clock information of the clock area.

[0012] The extracted synchronization clock information is restored to the target clock signal that is in the same frequency as the basic clock signal of the transmitting end;

[0013] Based on the target clock signal, the data area of ​​the encoded signal is analyzed to obtain target bit data that is consistent with the original bit data of the transmitting end.

[0014] In addition, to achieve the above objectives, this application also provides an electronic device, which includes a memory, a processor, and a data synchronization transmission program stored in the memory and executable on the processor. When the data synchronization transmission program is executed by the processor, it implements the steps of the above-described data synchronization transmission method.

[0015] In addition, to achieve the above objectives, this application also provides a computer-readable storage medium storing a data synchronization transmission program, which, when executed by a processor, implements the steps of the data synchronization transmission method described above.

[0016] This application provides a data synchronization transmission method applied to the transmitting end of a data synchronization transmission system. By acquiring raw bit data, a base clock signal adapted to the transmission requirements of the raw bit data is generated, providing a precise timing reference for the entire encoding, transmission, and decoding process. This ensures timing consistency at each stage from the source, avoiding data distortion or bandwidth waste caused by clock mismatch with transmission requirements. The base clock signal is down-frequency processed to obtain synchronization clock information. The raw bit data and the synchronization clock information are then fused and encoded to generate an encoded signal containing a clock region and a data region. The pulse duration of the clock region differs from that of the data region by a preset difference. This difference provides a unique and distinguishable signal identifier for the receiving end, ensuring precise separation of the clock and data regions and fundamentally preventing interference between the two types of signals, thus providing a basis for subsequent timing... Clock recovery and data parsing establish a reliable foundation. By sending coded signals to the receiving end through a single-line transmission link, compared to the traditional multi-data-line + clock-line transmission method, the number of wires is significantly reduced, the wiring complexity is lowered, and hardware space is saved. The receiving end extracts synchronous clock information based on preset difference filtering, effectively avoiding extraction errors caused by signal confusion. The extracted synchronous clock information is restored to the target clock signal with the same frequency as the basic clock signal, achieving complete timing synchronization between the receiving end and the transmitting end. This provides a precise timing reference consistent with the transmitting end for data parsing. The data area of ​​the coded signal is parsed based on the target clock signal. By synchronously sampling each data bit, it is ensured that the target bit data is completely consistent with the original bit data, without bit errors, misalignments, or loss. Ultimately, efficient synchronous transmission of multi-bit data in a single-line environment is achieved, breaking through the application boundaries of traditional single-line technology that cannot achieve synchronous transmission. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating the first embodiment of the data synchronization transmission method of this application;

[0018] Figure 2 This is a schematic diagram of the equipment structure of the data synchronization transmission system involved in this application;

[0019] Figure 3 This is a schematic diagram of the signal timing and circuit connection relationship of the data synchronization transmission system involved in this application;

[0020] Figure 4 This is a flowchart illustrating the second embodiment of the data synchronization transmission method of this application;

[0021] Figure 5 This is a schematic diagram of the structure of the electronic device involved in the embodiments of this application.

[0022] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] This application provides a data synchronization transmission method, referring to... Figure 1 As shown, Figure 1 This is a flowchart illustrating the first embodiment of the data synchronization transmission method of this application.

[0024] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0025] In industrial settings, devices such as digital isolators and integrated modules urgently require simplified cabling and space optimization. Current multi-bit synchronous transmission methods either rely on multiple data lines plus independent clock lines, resulting in complex cabling and significant space consumption; or they use a single bus to transmit and splice data multiple times, leading to low efficiency and high latency, neither of which is suitable for single-wire environments. This issue hinders the miniaturization and performance improvement of these devices.

[0026] This application provides a data synchronization transmission method, an electronic device, and a computer-readable storage medium, enabling efficient synchronous transmission of multi-bit data in a single-wire environment.

[0027] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, mobile phone, database system, etc., or a device capable of performing the above functions, such as an electronic device. The following description uses an electronic device as an example to illustrate this embodiment and the subsequent embodiments.

[0028] The data synchronization transmission method of this application is applied to the sending end of a data synchronization transmission system. The data synchronization transmission method includes the following implementation steps S10 to S30.

[0029] Step S10: Obtain the raw bit data and generate a basic clock signal that matches the transmission requirements of the raw bit data;

[0030] Optionally, as an example, the application scenarios of this application include, but are not limited to: electronic devices or chip-to-chip communication scenarios where wiring space is limited and the requirements for connection simplicity are high, such as digital isolators, implantable medical devices, miniaturized wireless communication modules, high-density integrated electronic systems, etc., and are especially suitable for various application scenarios that require multi-bit data synchronous interaction in a single-line transmission link.

[0031] Optionally, in the digital isolator scenario, compared with the traditional 6-channel transmission scheme, this application only requires 1 isolation channel, which greatly reduces the number of chip pins and wiring density, reduces electromagnetic interference between lines, and improves the stability of the isolation system; in implantable medical devices, the simplified wiring design can reduce the size of the device, reduce power consumption, and adapt to the small installation space inside the body.

[0032] Optionally, the data synchronization transmission system includes a transmitter and a receiver, adapting to cabling-constrained scenarios such as digital isolators, and achieving multi-bit data synchronous transmission through a single-wire transmission link. The transmitter includes a clock generation circuit and a clock data encoding circuit. It acquires multi-bit raw data, generates a basic clock signal adapted to the transmission requirements, down-clocks the basic clock signal to obtain synchronization clock information, encodes the synchronization clock information into a clock region, and encodes the raw data into a data region according to preset rules. Each data bit has a low level in the first cycle, and the high / low level in subsequent cycles depends on the data value. The clock region and data region are concatenated to generate a single-bit serial code stream, which is transmitted through a single wire. The receiver includes a narrow pulse filtering circuit, a frequency multiplier circuit, and a clock data decoding circuit. After receiving the encoded signal, it filters the narrow pulse based on the pulse period difference to extract the synchronization clock information, multiplies the frequency to restore the target clock signal at the same frequency as the basic clock, and then analyzes the data region based on the target clock signal to reconstruct the original multi-bit data. This system eliminates the need for multiple data lines and independent clock lines, reducing hardware footprint and achieving efficient synchronous transmission of multi-bit data in a single-wire environment.

[0033] like Figure 2 As shown, Figure 2This is a schematic diagram of the equipment structure of the data synchronization transmission system involved in this application. The transmitting circuit 1, as the transmitting end of the data synchronization transmission system, internally includes: first, a clock generation circuit 11, whose output is connected to the clock input of the clock data encoding circuit 12; second, a clock data encoding circuit 12, whose data input is connected to the input signal 13 (multi-bit raw data interface), and whose output is connected to the single-wire transmission link 2; the single-wire transmission link 2 connects the transmitting circuit 1 and the receiving circuit 3, and is used to transmit encoded signals; the receiving circuit 3, as the receiving end of the data synchronization transmission system, internally includes: 1. a narrow pulse filter circuit 31, whose input is connected to the single-wire transmission link 2, and whose output is connected to the input of the frequency multiplier circuit 32; 2. the frequency multiplier circuit 32, whose output is connected to the clock input of the clock data decoding circuit 33; 3. the clock data decoding circuit 33, whose data input is connected to the single-wire transmission link 2, and whose output is connected to the output signal 34 (restored multi-bit data interface). Furthermore, the transmitting circuit 1 includes a clock generation circuit 11, a clock data encoding circuit 12, and an input signal 13. The clock generation circuit 11 provides a basic clock signal to the clock data encoding circuit 12, and the input signal 13 inputs multi-bit raw data to the clock data encoding circuit 12. The encoded signal generated by the clock data encoding circuit 12 is transmitted to the receiving circuit 3 via a single-wire transmission link 2. The receiving circuit 3 includes a narrow pulse filter circuit 31, a frequency multiplier circuit 32, a clock data decoding circuit 33, and an output signal 34. The single-wire transmission link 2 synchronously inputs the encoded signal to the narrow pulse filter circuit 31 and the clock data decoding circuit 33. After the narrow pulse filter circuit 31 extracts the synchronous clock information, it is restored to the target clock signal by the frequency multiplier circuit 32 and input to the clock data decoding circuit 33. Finally, the target data parsed by the clock data decoding circuit 33 is output through the output signal 34. This structure integrates clock and data transmission via a single wire, significantly reducing the number of wires and hardware space occupied, reducing interference between lines, and accurately restoring the synchronous clock to ensure data transmission without misalignment or loss. It is suitable for the efficient synchronous transmission requirements of space-constrained scenarios such as digital isolators.

[0034] like Figure 3 As shown, Figure 3This diagram illustrates the signal timing and circuit connections of the data synchronization transmission system involved in this application. It includes two parts: circuit modules and corresponding signal waveforms. The relationships and details of each part are as follows: The clock generation circuit outputs a high-frequency pulse sequence as the basic clock signal (corresponding to the top waveform in the diagram, alternating between high and low levels, with the duration of each cycle matching the transmission rate). Its output is directly connected to the clock input of the clock data encoding circuit. After receiving the basic clock signal, the clock data encoding circuit down-encodes it into a clock region (specifically, a 0-3 cycle segment, with the first cycle being low and the next three cycles being high, labeled "CLK" for clear identification). Simultaneously, it encodes the original bit data "1, 1, 0, 1, 0, 1" into a data region according to the rule that each bit occupies two cycles (the first cycle is fixed at low level, and the next cycle is determined by the bit value). The clock region and data region are then merged to generate a serial encoded signal (corresponding to the second waveform segment in the diagram, 0...). -3 cycles constitute the clock region, and cycles 4-15 constitute the data region (the number of pulse cycles in the clock and data regions meets a preset difference). Its output is unidirectionally connected to a single-wire transmission link. The narrow pulse filter circuit receives the serial encoded signal through the single-wire transmission link and, based on the preset difference, filters out the preset critical number of cycles to distinguish between long and short pulses. It filters the short-cycle pulses that occupy 2 cycles in the data region and retains the long-cycle pulses that occupy 4 cycles in the clock region (corresponding to the third waveform in the figure, only the long-cycle pulse sequence of cycles 0-3 is retained). Its output is connected to the input of the frequency multiplier circuit. After receiving the long-cycle pulse, the frequency multiplier circuit performs a frequency upsampling operation according to the preset downsampling ratio and frequency multiplication matching rule to recover the target clock signal with the same frequency as the output of the clock generation circuit (corresponding to the bottom waveform in the figure, the frequency is consistent with the basic clock signal, and the timing is without deviation). Its output is connected to the clock input of the clock data decoding circuit, providing a precise timing reference for bit splitting, level sampling, and bit value mapping in the data region.

[0035] Optionally, the raw bit data refers to the multi-bit digital information to be transmitted; the transmission requirements include, but are not limited to, parameters such as data bit width and transmission rate; the basic clock signal refers to the oscillation signal that provides a timing reference for data transmission, and its frequency is adapted to the transmission rate; the preset adaptation conditions refer to the preset range that the transmission parameters need to meet, and in this embodiment, the rate range is 1Mbps-100Mbps.

[0036] Optionally, this embodiment is applied to wiring-constrained scenarios such as digital isolators. Existing technologies require transmitting clock and data through at least two separate lines, resulting in high wiring costs and susceptibility to interference. This embodiment first acquires initial multi-bit data, obtains the data's bit width and transmission rate parameters, and determines whether the parameters meet preset adaptation conditions. If they do, the data is identified as the original bit data. Then, a basic clock signal is generated based on the transmission rate parameters. The adaptation ratio between the basic clock signal frequency and the transmission rate is set according to the actual scenario. Subsequently, the basic clock signal is down-clocked, and timing features are extracted and encoded into a clock region. The original bit data is encoded into a data region, ensuring a preset difference in the number of pulse cycles between the two regions. After splicing, the data is transmitted through a single-line transmission link.

[0037] Optionally, the preset adaptation conditions have a rate range of 50Mbps-200Mbps. After collecting the initial data, the corresponding basic clock signal frequency is matched by means including but not limited to parameter lookup table method and dynamic calculation method. The adaptation ratio of basic clock signal frequency to transmission rate is 2:1. The basic clock signal is processed according to the preset down-frequency ratio to ensure that the difference in the number of pulse cycles between the clock area and the data area meets the subsequent identification requirements. Then, the original bit data is encoded into a data area according to the preset rules. The clock area and the data area are spliced ​​together to generate an encoded signal and sent through a single line.

[0038] This embodiment reduces the number of lines and hardware space occupied by single-line fusion transmission of clock and data, reduces interference between lines, and ensures that the basic clock signal is precisely matched with the transmission requirements, thus guaranteeing the stability and accuracy of data synchronous transmission.

[0039] Step S20: The basic clock signal is down-clocked to obtain synchronous clock information. The original bit data and synchronous clock information are fused and encoded to generate an encoded signal containing a clock area and a data area. The number of pulse duration cycles in the clock area and the number of pulse duration cycles in the data area have a preset difference.

[0040] Optionally, the synchronous clock information refers to the timing reference signal after the base clock signal has been down-clocked; the preset difference refers to the preset difference in the number of pulse duration cycles between the clock region and the data region, used to distinguish between the two types of signals; the clock region refers to the segment in the encoded signal that carries the synchronous clock, and the data region refers to the segment that carries the original bit data. Existing technologies require an independent isolation channel for each data bit. In this embodiment, the base clock signal is first down-clocked according to a preset down-clocking ratio to obtain the synchronous clock information; its timing characteristics are extracted and encoded into a clock region, which occupies 4 cycles, with the first cycle being low and the next 3 cycles being high; the original bit data is encoded into a data region according to the rule that each bit occupies 2 cycles, with the first cycle fixed at low level and the next cycle determined by the data value, so that the number of pulse cycles in the two regions meets the preset difference; after splicing, an encoded signal is generated and transmitted via a single wire.

[0041] Optionally, in the data area, cycles 4-5 correspond to the first bit "1" of the original bit data, cycles 6-7 correspond to the second bit "1", cycles 8-9 correspond to the third bit "0", cycles 10-11 correspond to the fourth bit "1", cycles 12-13 correspond to the fifth bit "0", and cycles 14-15 correspond to the sixth bit "1". The encoding logic of each bit strictly follows the rule of "low level in the first cycle and changes with the bit value in the next cycle".

[0042] Optionally, the preset difference is set to 3 cycles according to the transmission requirements, and the preset down-frequency ratio is determined by a method including but not limited to parameter lookup table. The clock area occupies 6 cycles, and each data bit in the data area occupies 3 cycles. During encoding, the first two cycles of the clock area are low level and the subsequent cycles are high level. The first two cycles of the data area are fixed at low level, and the level of the third cycle is determined according to the data value. The encoded signal is generated after splicing.

[0043] This embodiment adapts to different transmission scenarios by flexibly configuring periodic parameters and encoding rules. It eliminates the need for multiple isolation channels and independent clock lines, reducing hardware footprint and wiring complexity. At the same time, it ensures the fusion of clock and data transmission, providing a reliable foundation for accurate signal separation at the receiving end.

[0044] Step S30: Send the encoded signal to the receiving end through a single-line transmission link, so that the receiving end can extract the synchronization clock information based on the preset difference filter, restore the extracted synchronization clock information to the target clock signal with the same frequency as the basic clock signal, and parse the data area of ​​the encoded signal based on the target clock signal to obtain the target bit data that is consistent with the original bit data.

[0045] Optionally, the target clock signal refers to a synchronous reference signal that is at the same frequency as the base clock of the transmitting end; the preset difference refers to the preset difference in the number of pulse duration cycles between the clock area and the data area, which is used to distinguish between the two types of signals.

[0046] Optionally, existing technologies require multi-channel transmission of multi-bit data and clock. This embodiment receives the encoded signal through a single-line transmission link, obtains a preset critical period number based on preset differences, detects and compares the duration of each pulse in the encoded signal, filters short-period pulses, retains long-period pulses and verifies timing patterns, and extracts synchronization clock information. The target frequency multiplication factor is calculated according to a preset down-conversion ratio and frequency multiplication matching rule. The synchronization clock information is up-converted and the frequency error is verified to obtain the target clock signal. The preset encoding rule is called to generate parsing parameters, the data area is split into bit encoding units, the level state is sampled and mapped to bit values, and after verification, the data is spliced ​​to form the target bit data.

[0047] Optionally, the preset difference is set to 3 cycles, the preset critical cycle number is set to 4 cycles according to the transmission requirements, and the frequency multiplication factor is determined by methods including but not limited to dynamic calculation. After receiving the encoded signal, the header pulse sequence is extracted and compared with the preset clock zone start identifier to detect whether the level transition conforms to the transition rule to confirm the encoded signal. During parsing, the data area is split into bits and periods, the level status is detected based on the level sampling threshold, the data is converted into bit values ​​according to the mapping relationship, the total number of bits and the start / end identifier are checked according to the data verification format, and the target bit data is obtained after splicing.

[0048] This embodiment accurately separates clock and data by using pulse period differences, eliminating the need for multiple channels and independent clock lines, reducing hardware footprint and wiring complexity, adapting to space-constrained scenarios, and ensuring the accuracy and stability of multi-bit data synchronous transmission.

[0049] This embodiment acquires raw bit data and generates a base clock signal that matches the transmission requirements of the raw bit data. This provides a precise timing reference for the entire encoding, transmission, and decoding process, ensuring timing consistency at each stage from the source and avoiding data distortion or bandwidth waste caused by mismatch between the clock and transmission requirements. The base clock signal is down-clocked to obtain synchronization clock information. The raw bit data and the synchronization clock information are then fused and encoded to generate an encoded signal containing a clock region and a data region. The number of pulse duration cycles in the clock region and the number of pulse duration cycles in the data region have a preset difference. This difference provides a unique and distinguishable signal identifier for the receiving end, ensuring that the clock region and the data region can be accurately separated. This fundamentally avoids mutual interference between the two types of signals and lays a reliable foundation for subsequent clock recovery and data parsing. By sending coded signals to the receiving end via a single-wire transmission link, compared to the traditional multi-data-line + clock-line transmission method, the number of wires is significantly reduced, the wiring complexity is lowered, and hardware space is saved. The receiving end extracts the synchronization clock information based on a preset difference filter, effectively avoiding extraction errors caused by signal confusion. The extracted synchronization clock information is restored to the target clock signal with the same frequency as the base clock signal, achieving complete timing synchronization between the receiving and transmitting ends. This provides a precise timing reference consistent with the transmitting end for data parsing. The data area of ​​the coded signal is parsed based on the target clock signal. By synchronously sampling each data bit, it is ensured that the target bit data is completely consistent with the original bit data, without bit errors, misalignments, or loss. Ultimately, efficient synchronous transmission of bit data is achieved in a single-wire environment, breaking through the application boundaries of traditional single-wire technology that cannot achieve synchronous transmission.

[0050] Furthermore, based on the above, a second embodiment of the data synchronization transmission method of this embodiment is proposed, such as... Figure 4 As shown, Figure 4This is a flowchart illustrating the second embodiment of the data synchronization transmission method of this application. In some feasible embodiments, step S10 above includes the following implementation steps S201-S204.

[0051] Step S201: Acquire initial bit data and obtain the bit width and transmission rate parameters of the initial bit data;

[0052] Step S202: Determine whether the bit width and transmission rate parameters meet the preset transmission adaptation conditions;

[0053] Step S203: When it is determined that the preset transmission adaptation conditions are met, the initial bit data is used as the original bit data;

[0054] Step S204: Generate a basic clock signal based on the transmission rate parameter, wherein the frequency of the basic clock signal is adapted to the transmission rate parameter.

[0055] Optionally, the preset difference refers to the preset difference in the number of pulse duration cycles between the clock area and the data area, used to distinguish between the two types of signals; the synchronous clock information refers to the timing reference signal after the base clock signal has been down-processed; and the encoded signal refers to the serial code stream signal that merges the clock area and the data area.

[0056] Optionally, in the digital isolator scenario, existing technologies require configuring an independent isolation channel for each data bit. In this embodiment, a preset down-frequency ratio is first determined based on the base clock signal frequency and the original bit data width. The base clock signal is down-frequencyed according to the ratio to obtain synchronous clock information. The timing characteristics of the synchronous clock information are extracted and encoded into a clock region (cycles 0-3, with the first cycle being low and the last 3 cycles being high). The original bit data "1, 1, 0, 1, 0, 1" is encoded into a data region, with each cycle occupying 2 cycles. The first cycle is fixed at a low level, and the next cycle is set to high or low level according to the bit value, so that the number of pulse cycles in the two regions meets the preset difference. After splicing, an encoded signal is generated and transmitted through a single wire.

[0057] Optionally, the preset down-frequency ratio is determined by a method including but not limited to parameter lookup table. The clock zone is set to 0-5 cycles (low level for the first 2 cycles and high level for the last 4 cycles), and each bit in the data zone occupies 3 cycles. During encoding, the data zone is fixed at a low level for the first 2 cycles and at a fixed level according to the bit value for the third cycle. The preset difference in the number of pulse cycles between the clock zone and the data zone is set to 3 cycles. After splicing to generate the encoded signal, it is transmitted through a single wire.

[0058] This embodiment flexibly configures encoding parameters to adapt to different isolator channel requirements, eliminating the need for multiple isolation channels, reducing hardware footprint and wiring complexity, while ensuring the fusion of clock and data transmission, providing a reliable foundation for accurate signal separation at the receiving end.

[0059] Furthermore, based on the above, in some feasible embodiments, step S20 includes the following implementation steps C301-C304.

[0060] Step C301: Based on the frequency of the base clock signal, the bit width of the original bit data, and the preset down-frequency and multiplication matching rules, obtain the preset down-frequency ratio, down-frequency the base clock signal according to the preset down-frequency ratio, and obtain the synchronization clock information.

[0061] Step C302: Extract the timing features of the synchronization clock information and encode the timing features into the clock region of the encoded signal;

[0062] Step C303: According to the preset encoding rules, each bit value of the original bit data is sequentially encoded into the data area of ​​the encoded signal, so that the number of pulse duration cycles in the clock area and the number of pulse duration cycles in the data area meet the preset difference.

[0063] Step C304: Combine the clock area and the data area to generate a complete coded signal.

[0064] Optionally, the preset down-frequency and multiplication matching rules refer to the pre-set adaptation standards, including but not limited to the correspondence between the base clock frequency, data bit width and down-frequency ratio; the preset down-frequency ratio refers to the clock down-frequency coefficient determined based on the matching rules; and the preset encoding rules refer to the rules that specify the mapping relationship between data bits and level states.

[0065] Optionally, in a digital isolator scenario, existing technologies require six isolation channels to transmit six signals. In this embodiment, the frequency of the basic clock signal and the bit width of the original bit data "1, 1, 0, 1, 0, 1" are first obtained. A preset down-frequency ratio is determined by combining preset down-frequency and multiplication matching rules. The basic clock signal is down-frequencyd according to this ratio to obtain synchronous clock information. Its timing characteristics are extracted and encoded into a clock region of 0-3 cycles, with the first cycle being low and the next three cycles being high. According to the preset encoding rules, each bit value is encoded into a data region, with each bit occupying two cycles. The first cycle is fixed at a low level, and the next cycle is determined by the bit value to determine the high or low level, so that the number of pulse cycles of the clock region and the data region meet the preset difference. The clock region and the data region are spliced ​​together to generate a complete encoded signal.

[0066] Optionally, the preset down-clock ratio is determined by a parameter lookup table. The preset calculation table stores the down-clock ratio corresponding to different base clock frequencies (1MHz-100MHz) and data bit widths (1-16 bits). The table is directly matched based on the actual collected parameters to ensure that the number of pulse cycles in the clock area and data area after down-clocking meets the preset difference.

[0067] This embodiment achieves multi-bit synchronous transmission through a single isolation channel, reducing hardware footprint and wiring complexity, while ensuring the recognizability of the encoded signal and adapting to space-constrained scenarios such as isolators.

[0068] Furthermore, based on the above, in some feasible embodiments, the data synchronization transmission method is applied to the receiving end of the data synchronization transmission system, and the data synchronization transmission method further includes the following implementation steps D40 to D70.

[0069] Step D40: Receive the encoded signal sent by the transmitter through a single-wire transmission link. The encoded signal includes a clock area and a data area. There is a preset difference between the number of pulse duration cycles in the clock area and the number of pulse duration cycles in the data area.

[0070] Optionally, the preset difference refers to the preset difference in the number of pulse duration cycles between the clock area and the data area, which is used to distinguish between the two types of signals. In this embodiment, it is set to 2 cycles.

[0071] Optionally, the single-line transmission link synchronously inputs the encoded signal into the narrow pulse filter circuit and clock data decoding circuit at the receiving end. The narrow pulse filter circuit focuses on extracting the synchronous clock information, while the clock data decoding circuit synchronously buffers the encoded signal and starts parsing immediately after the target clock signal is recovered, ensuring timing synchronization.

[0072] Optionally, existing technologies require six isolation channels to transmit six signals. In this embodiment, the encoded signal is received through a single-wire transmission link. The encoded signal includes a clock region of 0-3 cycles (occupying 4 cycles, with the first cycle being low and the last 3 cycles being high) and a data region of 4-15 cycles (each bit occupies 2 cycles, with the first cycle being fixed at a low level). Based on a preset difference, a preset critical cycle number of 3 cycles is set. The duration of each pulse is detected by a narrow pulse filter circuit, filtering out short pulses with less than 3 cycles and retaining long-cycle pulses in the clock region to extract the synchronization clock information. The synchronization clock information is up-frequency processed by a 16-fold frequency multiplier, and the frequency error after up-frequency processing is calculated. After confirming that the error is within the preset allowable range of ±0.1%, it is determined as the target clock signal. Based on the target clock signal, the data region is divided into 6 bit encoding units. The level state of each unit is sampled, and the mapping relationship between high level and bit value 1 and low level and bit value 0 is converted. After verifying that the total number of bits is 6 and the start / end markers are complete, the target bit data "1, 1, 0, 1, 0, 1" is formed by splicing them in time sequence.

[0073] Optionally, the preset difference is set to 3 cycles, the clock region of the encoded signal occupies 6 cycles (low level for the first 2 cycles and high level for the next 4 cycles), and each bit in the data region occupies 3 cycles (fixed low level for the first 2 cycles). After receiving the encoded signal through a single-wire transmission link, the preset critical cycle number is determined to be 4 cycles based on the preset difference. The duration of each pulse cycle is detected and compared, and short-cycle pulses are filtered to extract the synchronization clock information. The frequency is increased by a 24-fold factor and the frequency error is checked to obtain the target clock signal. The data region is split into bit encoding units, the level state of the third cycle is sampled and converted into bit values, and after verification, they are spliced ​​together to form the target bit data.

[0074] This embodiment requires only one isolation channel to achieve multi-bit synchronous transmission, which greatly reduces hardware footprint and wiring complexity. At the same time, through clear periodic parameters and error control, it ensures transmission accuracy and is suitable for space-constrained scenarios such as digital isolators.

[0075] Step D50: Based on the preset difference, filter the narrow pulses in the data area of ​​the encoded signal through narrow pulse filtering to extract the synchronization clock information of the clock area;

[0076] Optionally, the narrow pulse filter circuit achieves pulse period selection by combining capacitor charging delay with logic gate discrimination. The capacitor charging time is matched with the preset critical number of cycles. Short-cycle pulses cannot charge the capacitor to the preset voltage threshold, so the logic gate does not conduct, thereby achieving narrow pulse filtering; long-cycle pulses can charge the capacitor to the threshold, so the logic gate conducts and outputs a pulse signal.

[0077] Optionally, the preset difference refers to the preset difference in the number of pulse duration cycles between the clock region and the data region, used to distinguish between the two types of signals. In this embodiment, it is set to 2 cycles. Narrow pulse filtering refers to the processing method of filtering short-period pulses by selecting the pulse period, including but not limited to capacitor delay filtering, threshold comparison filtering, etc. Existing technology requires 6 isolation channels to transmit 6 signals. In this embodiment, the encoded signal includes a clock region (0-3 cycles, occupying 4 cycles) and a data region (4-15 cycles, each bit occupies 2 cycles). Based on the preset difference, the preset critical period number is set to 3 cycles. The number of duration cycles of each pulse in the encoded signal is detected one by one by the narrow pulse filtering circuit and compared with the preset critical period number. Narrow pulses in the data region with a duration cycle number of less than 3 cycles are filtered out, and long-period pulses in the clock region are retained. After verifying that the retained long-period pulse sequence conforms to the preset timing rule of the down-frequency clock at the transmitting end, it is used as the synchronization clock information.

[0078] Optionally, the preset difference is set to 3 cycles, the clock region of the encoded signal occupies 6 cycles, and each bit of the data region occupies 3 cycles; based on the preset difference, the preset critical cycle number is determined to be 4 cycles, and the duration of each pulse is detected and compared by a narrow pulse filter circuit; after filtering short-cycle pulses, the timing pattern of the remaining long-cycle pulse sequence is verified; after confirmation, it is extracted as synchronous clock information, wherein the narrow pulse filter circuit realizes pulse period discrimination through methods including but not limited to logic gate circuits.

[0079] This embodiment achieves multi-bit synchronous transmission by precisely selecting clock and data pulses, requiring only one isolation channel. This reduces hardware footprint and wiring complexity, provides a reliable foundation for subsequent clock recovery, and is suitable for space-constrained scenarios such as digital isolators.

[0080] Step D60: Restore the extracted synchronization clock information to the target clock signal that is in the same frequency as the base clock signal of the transmitting end;

[0081] Optionally, the target clock signal refers to the synchronization reference signal that is in the same frequency as the transmitting end's base clock after recovery; the preset down-frequency and multiplication matching rule refers to the adaptation standard that associates the down-frequency ratio with the multiplication factor, including but not limited to frequency correspondence tables, dynamic calculation logic, etc. Existing technologies require six isolation channels to transmit six signals. In this embodiment, the synchronization clock information is obtained after narrow pulse filtering; based on the synchronization clock information frequency, the preset down-frequency ratio, and the preset down-frequency and multiplication matching rule, the target multiplication factor is determined through methods including but not limited to parameter lookup tables; the synchronization clock information is up-frequencyed according to this factor to obtain the initial recovered clock; the frequency error between the initial recovered clock and the transmitting end's base clock signal is calculated, and after confirming that the error is within a preset allowable range of ±0.1%, it is determined as the target clock signal.

[0082] Optionally, the frequency multiplier circuit uses a phase-locked loop circuit to perform frequency upscaling. The phase-locked loop circuit includes a phase detector, a loop filter, and a voltage-controlled oscillator. The phase detector compares the phase difference between the synchronous clock information and the output signal of the voltage-controlled oscillator. The loop filter outputs a control voltage to adjust the voltage-controlled oscillator until it outputs a target clock signal with the same frequency as the base clock signal.

[0083] Optionally, the preset frequency reduction and frequency multiplication matching rules are implemented through methods including but not limited to algorithm modeling; after obtaining the synchronous clock information, the target frequency multiplication factor is derived in reverse by combining the preset frequency reduction ratio of the transmitting end; the synchronous clock information is up-processed by the phase-locked loop circuit to generate the initial recovery clock; the frequency deviation is corrected by the high-frequency oscillation calibration circuit, and the target clock signal is determined after verifying that the error meets the preset allowable range.

[0084] This embodiment achieves accurate clock signal recovery through the collaboration of hardware circuits and adaptation rules, providing a reliable timing reference for data parsing. It only requires one isolation channel to achieve multi-bit synchronous transmission, reducing hardware footprint and wiring complexity, and is suitable for space-constrained scenarios such as digital isolators.

[0085] Step D70: Based on the target clock signal, analyze the data area of ​​the encoded signal to obtain target bit data that is consistent with the original bit data of the transmitting end.

[0086] Optionally, the target bit data refers to the output data that is consistent with the original bit data of the transmitting end after parsing; the preset data area encoding rule refers to the rule that specifies the mapping relationship between bit values ​​and level states, including but not limited to bit period ratio and level definition standard.

[0087] Optionally, existing technologies require 6 isolation channels to transmit 6 signals. In this embodiment, after obtaining the target clock signal, a preset data area encoding rule is called to generate parsing control parameters such as bit splitting period and level sampling threshold. The data area (4-15 cycles) of the encoded signal is split into 6 bit encoding units according to the bit splitting period, with each unit occupying 2 cycles. The level state of the second cycle of each unit is detected based on the level sampling threshold, and the mapping relationship between high level and bit value 1 and low level and bit value 0 is converted. After verifying that the total number of bits is 6 and the start / end identifier is complete, the target bit data "1, 1, 0, 1, 0, 1" is formed by splicing them in time sequence.

[0088] Optionally, the cache file temporarily stores bit values ​​in the split timing order, using a first-in-first-out storage rule. Each bit value corresponds to a unique timing index. During verification, the start / end identifier is matched by the index to ensure that the splicing order is consistent with the transmission order of the original bit data.

[0089] Optionally, the preset data area encoding rules are determined by means of, but not limited to, a parameter configuration table. Each bit in the data area occupies 3 cycles, with the first 2 cycles fixed at a low level. After acquiring the target clock signal, the data area is split into 3-cycle bit splits. The level state of the third cycle is sampled and converted into a bit value. The total number of bits and the start / end marker are checked according to the preset data verification format. After passing the verification, the bits are concatenated to form the target bit data.

[0090] This embodiment achieves accurate restoration of multi-bit data through precise timing splitting and level mapping. Only one isolation channel is needed to complete the synchronous transmission of multi-bit data, reducing hardware occupation and wiring complexity, and adapting to space-constrained scenarios such as digital isolators.

[0091] This embodiment requires only one isolation channel to achieve multi-bit synchronous transmission, which greatly reduces hardware footprint and wiring complexity. At the same time, it ensures transmission accuracy through precise clock recovery and data parsing, and is suitable for space-constrained scenarios such as digital isolators.

[0092] Furthermore, based on the content of any of the above embodiments, in some feasible embodiments, step D40 includes the following implementation steps E501-E504.

[0093] Step E501: Receive the serial code stream signal through a single-wire transmission link and extract the header pulse sequence of the serial code stream signal;

[0094] Step E502: Compare the head pulse sequence with the preset clock zone start marker and check the consistency of the comparison;

[0095] Step E503: When a match is detected, check whether the level transition at the end of the head pulse sequence conforms to the preset transition rule between the end of the clock area and the beginning of the data area.

[0096] Step E504: When a preset transition rule is detected, the serial bit stream signal is determined as an encoded signal.

[0097] Optionally, the clock zone start identifier refers to a pre-defined pulse characteristic used to identify the start of the clock zone, including but not limited to a combination of levels with a specific number of cycles; the preset transition rule refers to the level transition standard between the end of the clock zone and the start of the data zone, which in this embodiment is set to "a single transition from high level to low level".

[0098] Optionally, existing technologies require six isolation channels to transmit six signals. In this embodiment, the serial code stream signal is received through a single-wire transmission link; the header pulse sequence (a combination of pulses in the first four cycles) of the signal is extracted; the header pulse sequence is compared with a preset clock zone start marker (low level in the first cycle and high level in the last three cycles) to detect consistency; if the comparison is consistent, it is detected whether the level transition at the end of the header pulse sequence conforms to a preset transition rule; if it conforms to the rule, the serial code stream signal is determined as an encoded signal, which includes a clock zone of 0-3 cycles and a data zone of 4-15 cycles.

[0099] Optionally, the clock zone start identifier is set to "low level for the first 2 cycles and high level for the next 4 cycles", and the preset transition rule is set to "single transition from low level to high level". After receiving the serial code stream signal through a single-wire transmission link, the header pulse sequence of the first 6 cycles is extracted. It is compared with the preset clock zone start identifier to detect consistency. If the comparison is consistent, it is detected whether the level transition at the end of the header pulse sequence conforms to the preset transition rule. If it conforms to the rule, the serial code stream signal is determined as the encoded signal, which includes a clock zone of 0-5 cycles and a data zone of 6-23 cycles.

[0100] This embodiment accurately identifies the encoded signal through dual verification, avoiding misjudgment of non-target code streams, and provides reliable input for subsequent narrow pulse filtering and clock extraction. It only requires one isolation channel to achieve multi-bit synchronous transmission, reducing hardware footprint and wiring complexity, and is suitable for space-constrained scenarios such as digital isolators.

[0101] Furthermore, based on the content of any of the above embodiments, in some feasible embodiments, step D50 includes the following implementation steps F501 to F505.

[0102] Step F501: Based on the preset difference, obtain the preset critical period number that distinguishes the periodic pulse of the clock area from the short periodic pulse of the data area;

[0103] Step F502: Detect the duration of each pulse in the encoded signal one by one and compare it with the preset critical number of cycles;

[0104] Step F503: Filter out short-cycle pulses with a duration of less than a preset critical number of cycles, and retain long-cycle pulses with a duration of more than a preset critical number of cycles.

[0105] Step F504: Verify whether the retained long-period pulse sequence conforms to the preset timing pattern of the down-frequency clock at the transmitting end;

[0106] Step F505: When a preset timing pattern is detected, the long-period pulse sequence is used as the synchronization clock information.

[0107] Optionally, the preset critical cycle number refers to the threshold for distinguishing between long-cycle pulses in the clock region and short-cycle pulses in the data region. In this embodiment, it is set to 3 cycles. The preset timing rule refers to the level change rule of the down-frequency clock at the transmitting end, including but not limited to the proportion of high and low level durations. In this embodiment, it is "low level for the first cycle and high level for the next 3 cycles".

[0108] Optionally, existing technologies require 6 isolation channels to transmit 6 signals. In this embodiment, a preset critical period number is obtained based on a preset difference (the difference between the number of pulse cycles in the clock area and the data area is 2). The duration of each pulse in the encoded signal is detected one by one by a narrow pulse filter circuit and compared with the preset critical period number. Short pulses in the data area with a duration of less than 3 cycles are filtered out, and long pulses in the clock area with a duration of more than 3 cycles are retained. It is verified whether the retained long period pulse sequence conforms to the preset timing rule. If it is found to conform, the long period pulse sequence is used as the synchronization clock information.

[0109] Optionally, the preset difference is set to 3 cycles, the preset critical cycle number is set to 4 cycles, and the preset timing rule is set to "low level for the first 2 cycles and high level for the next 4 cycles". The preset critical cycle number is determined based on the preset difference. The duration of each pulse in the encoded signal is detected and compared by a narrow pulse filter circuit. After filtering short-cycle pulses, it is verified whether the remaining long-cycle pulse sequence conforms to the preset timing rule. After confirmation, it is extracted as synchronous clock information. The narrow pulse filter circuit achieves pulse cycle screening by means including but not limited to capacitor charging delay combined with logic gate discrimination.

[0110] This embodiment ensures the accuracy of synchronous clock information extraction through precise periodic screening and timing verification, providing reliable input for subsequent clock recovery. It only requires one isolation channel to achieve multi-bit synchronous transmission, reducing hardware footprint and wiring complexity, and is suitable for space-constrained scenarios such as digital isolators.

[0111] Furthermore, based on the content of any of the above embodiments, in some feasible embodiments, step D60 includes steps G601-G604.

[0112] Step G601: Calculate the target multiplication factor based on the frequency of the synchronous clock information, the preset down-frequency ratio, and the preset down-frequency and multiplication matching rules;

[0113] Step G602: Align the frequency of the synchronization clock information with the base clock signal at the transmitting end according to the target multiplication factor to obtain the initial recovery clock;

[0114] Step G603: Calculate the frequency error between the initial recovery clock and the base clock signal, and determine whether the frequency error is within the preset allowable range;

[0115] Step G604: When it is detected that the signal is within the preset allowable range, the initial recovery clock is determined as the target clock signal.

[0116] Optionally, the target frequency multiplication factor refers to the coefficient used to upscale the synchronization clock information to the frequency of the base clock signal; the initial recovery clock refers to the clock signal initially obtained after frequency multiplication; and the preset allowable range refers to the acceptable range of frequency error, which is set to ±0.1% in this embodiment.

[0117] Optionally, existing technologies require six isolation channels to transmit six signals. In this embodiment, the frequency of the synchronization clock information, the preset down-frequency ratio, and the preset down-frequency and multiplication matching rules are obtained. The target multiplication factor of 16 is calculated through algorithms including but not limited to proportional calculation. The frequency of the synchronization clock information is aligned with the base clock signal of the transmitting end according to this factor to obtain the initial recovery clock. The frequency error between the initial recovery clock and the base clock signal is calculated, and it is determined whether the frequency error is within the preset allowable range. When it is detected that it is within the preset allowable range, the initial recovery clock is determined as the target clock signal.

[0118] Optionally, the preset frequency reduction and frequency multiplication matching rules are implemented through methods including but not limited to dynamic calculation, with the preset allowable range set to ±0.2%; after obtaining the synchronization clock information, the target frequency multiplication factor of 24 is derived in reverse by combining the preset frequency reduction ratio of the transmitting end; the synchronization clock information is up-processed through a phase-locked loop circuit to generate an initial recovery clock; the frequency error between the initial recovery clock and the basic clock signal is calculated, and the target clock signal is determined after verifying that the error meets the preset allowable range.

[0119] Optionally, the target frequency multiplication factor has a fixed correspondence with the preset frequency reduction ratio of the transmitter. For example, when the transmitter reduces the frequency by 4 times, the frequency multiplication factor is set to 4; when the frequency is reduced by 8 times, the frequency multiplication factor is set to 8. It can also be set to an integer multiple of the frequency reduction ratio according to the actual transmission requirements to ensure accurate recovery of the clock signal.

[0120] This embodiment achieves accurate clock signal recovery by precisely matching the frequency multiplication factor and coordinating with hardware circuitry, providing a reliable timing reference for data parsing. It only requires one isolation channel to achieve multi-bit synchronous transmission, reducing hardware footprint and wiring complexity.

[0121] Furthermore, based on the content of any of the above embodiments, in some feasible embodiments, step D70 includes steps K701-K705.

[0122] Step K701: Call the preset data area encoding rules, combine them with the timing reference of the target clock signal, and generate parsing control parameters. The parsing control parameters include at least the bit splitting period, level sampling threshold, and data verification format.

[0123] Step K702: Serially split the data area of ​​the encoded signal according to the bit splitting period to obtain continuous bit encoding units. Based on the level sampling threshold and according to the level standard of the preset data area encoding rule, perform level sampling detection on each bit encoding unit and output a high / low level state signal that matches the preset data area encoding rule.

[0124] Step K703: Based on the mapping relationship between high / low level status signals and bit values ​​in the preset data area encoding rules, the high / low level status signals of each bit encoding unit are matched one-to-one and converted into corresponding bit values. All bit values ​​are temporarily stored in the cache file according to the split timing order.

[0125] Step K704: According to the data verification format, verify whether the total number of bits and the start / end markers of the temporarily stored bit values ​​meet the preset bit value verification conditions.

[0126] Step K705: When all the bit values ​​that meet the preset bit value verification conditions are detected, the verified bit values ​​are spliced ​​together in the split timing sequence to form the target bit data.

[0127] Optionally, the parsing control parameters refer to the core configuration information of the decoding process, including but not limited to the bit splitting period, level sampling threshold, and data verification format; the preset data area encoding rules refer to the standards that specify the data encoding logic, including but not limited to the mapping relationship between level and bit value, and the proportion of data area period.

[0128] Optionally, existing technologies require 6 isolation channels to transmit 6 signals. In this embodiment, after obtaining the target clock signal, the preset data area encoding rules are called, and analytical control parameters are generated in combination with the timing reference. The data area of ​​the 4th to 15th cycles of the encoded signal is serially split according to the bit splitting period of 2 cycles to obtain 6 bit encoding units. The first cycle of each unit is fixed to a low level. The level state of the second cycle of each unit is detected based on the level sampling threshold, and a high / low level state signal is output. According to the mapping relationship that high level corresponds to bit value 1 and low level corresponds to bit value 0, the signal is converted and temporarily stored in a cache file. After verifying that the total number of bits is 6 and the start / end identifier is complete according to the data verification format, the target bit data "1, 1, 0, 1, 0, 1" is formed by splicing them in the timing sequence.

[0129] Optionally, the preset data area encoding rules are determined by means of, but not limited to, a parameter configuration table. Each bit in the data area occupies 3 cycles, with the first 2 cycles fixed at a low level. After acquiring the target clock signal, the data area is split into 3-cycle bit splits. The level state of the third cycle is sampled and converted into a bit value. The total number of bits and the start / end marker are checked according to the preset data verification format. After passing the verification, the bits are concatenated to form the target bit data.

[0130] This embodiment achieves accurate restoration of multi-bit data through a standardized parsing process and precise verification. Synchronous transmission can be completed with only one isolation channel, reducing hardware footprint and wiring complexity, and is suitable for space-constrained scenarios such as digital isolators.

[0131] In addition, this application also provides an electronic device. Please refer to... Figure 5 , Figure 5This is a schematic diagram of the structure of the electronic device involved in the embodiments of this application.

[0132] This application provides an electronic device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the data synchronization transmission method in Embodiment 1 above.

[0133] The following is for reference. Figure 5 , Figure 5 This is a schematic diagram of the structure of an electronic device involved in the embodiments of this application, illustrating a structural schematic diagram of an electronic device suitable for implementing the embodiments of this application. The electronic devices in the embodiments of this application may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (such as in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 5 The electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0134] like Figure 5As shown, the electronic device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the electronic device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005, and an input / output (I / O) interface 1006 is also connected to the bus 1005. Typically, devices that can be connected to the I / O interface 1006 include: an input device 1007 for acquiring device operation data; an output device for outputting control commands (including but not limited to a cluster scheduling control module, a data acquisition task allocation module, etc.); an output device 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1003 including, for example, magnetic tape, a hard disk, etc.; and a communication device 1009. Communication device 1009 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although electronic devices with various devices are shown in the figures, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0135] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0136] The electronic device provided in this application, employing the data synchronization transmission method described in the above embodiments, can solve the technical problem of the inability to achieve efficient synchronous transmission of bit data in a single-line environment. Compared with the prior art, the beneficial effects of the electronic device provided in this application are the same as those of the data synchronization transmission method provided in the above embodiments, and other technical features of this electronic device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0137] Furthermore, this application provides a computer-readable storage medium. This computer-readable storage medium stores a data synchronization transmission program, which, when executed by a processor, implements the steps of the data synchronization transmission method described above.

[0138] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0139] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0140] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0141] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A data synchronization transmission method, characterized in that, The data synchronization transmission method, applied to the sending end of a data synchronization transmission system, includes: Acquire initial bit data and obtain the bit width and transmission rate parameters of the initial bit data; Determine whether the bit width and the transmission rate parameters meet the preset transmission adaptation conditions; When it is determined that the preset transmission adaptation conditions are met, the initial bit data is used as the original bit data; A basic clock signal is generated based on the transmission rate parameters, wherein the frequency of the basic clock signal is adapted to the transmission rate parameters; Based on the frequency of the base clock signal, the bit width of the original bit data, and the preset frequency reduction and multiplication matching rules, a preset frequency reduction ratio is obtained, and the base clock signal is reduced according to the preset frequency reduction ratio to obtain synchronization clock information. The timing characteristics of the synchronization clock information are extracted, and the timing characteristics are encoded into a clock region of an encoded signal. The clock region occupies 4 cycles, with the first cycle being low and the last 3 cycles being high. According to the preset encoding rules, each bit value of the original bit data is sequentially encoded into the data area of ​​the encoded signal. Each bit of the data area occupies 2 cycles. The first cycle is fixed at a low level, and the second cycle is determined to be high or low level according to the bit value, so that the number of pulse duration cycles of the clock area and the number of pulse duration cycles of the data area meet the preset difference. The clock region and the data region are spliced ​​together to generate a complete encoded signal, wherein the number of pulse duration cycles in the clock region and the number of pulse duration cycles in the data region have a preset difference; The encoded signal is sent to the receiving end through a single-line transmission link, so that the receiving end extracts the synchronization clock information based on the preset difference filter, restores the extracted synchronization clock information to the target clock signal with the same frequency as the basic clock signal, and analyzes the data area of ​​the encoded signal based on the target clock signal to obtain target bit data that is consistent with the original bit data.

2. A data synchronization transmission method, characterized in that, The data synchronization transmission method, applied to the receiving end of a data synchronization transmission system, includes: The encoded signal is received by the transmitting end through a single-line transmission link. The encoded signal includes a clock area and a data area. The clock area occupies 4 cycles, with the first cycle being low and the next 3 cycles being high. Each bit in the data area occupies 2 cycles, with the first cycle being fixed at low and the next cycle being high or low depending on the bit value. The number of pulse duration cycles in the clock area and the number of pulse duration cycles in the data area have a preset difference. Based on the preset difference, narrow pulses in the data area of ​​the encoded signal are filtered by narrow pulse filtering to extract the synchronization clock information of the clock area; The extracted synchronization clock information is restored to a target clock signal that is in the same frequency as the base clock signal of the transmitting end; Based on the target clock signal, the data area of ​​the encoded signal is analyzed to obtain target bit data that is consistent with the original bit data of the transmitting end.

3. The data synchronization transmission method as described in claim 2, characterized in that, The step of receiving the encoded signal sent by the transmitting end through a single-wire transmission link includes: Serial code stream signals are received via a single-line transmission link, and the header pulse sequence of the serial code stream signals is extracted. The head pulse sequence is compared with a preset clock zone start marker to check for consistency. When a match is detected, it is checked whether the level transition at the end of the head pulse sequence conforms to the preset transition rule between the end of the clock area and the beginning of the data area. When the preset transition rule is met, the serial code stream signal is determined as the encoded signal.

4. The data synchronization transmission method as described in claim 3, characterized in that, The step of extracting the synchronization clock information of the clock region by filtering narrow pulses in the data area of ​​the encoded signal based on the preset difference includes: Based on the preset difference, a preset critical period number is obtained to distinguish the periodic pulses of the clock area from the short-period pulses of the data area; The duration of each pulse in the encoded signal is detected one by one and compared with the preset critical number of cycles; Short-period pulses with a duration of less than the preset critical period number are filtered out, while long-period pulse sequences with a duration of more than the preset critical period number are retained. Verify whether the retained long-period pulse sequence conforms to the preset timing rule of the down-frequency clock of the transmitting end; When a sequence of pulses conforming to the preset timing pattern is detected, the long-period pulse sequence is used as the synchronization clock information.

5. The data synchronization transmission method as described in claim 4, characterized in that, The step of restoring the extracted synchronization clock information to a target clock signal that is in the same frequency as the base clock signal of the transmitting end includes: Based on the frequency of the synchronous clock information, the preset down-frequency ratio, and the preset down-frequency and multiplication matching rules, the target multiplication factor is calculated. The initial recovery clock is obtained by adjusting the frequency of the synchronization clock information to the base clock signal of the transmitting end according to the target frequency multiplication factor; Calculate the frequency error between the initial recovery clock and the base clock signal, and determine whether the frequency error is within a preset allowable range; When the preset allowable range is detected, the initial recovery clock is determined as the target clock signal.

6. The data synchronization transmission method as described in claim 5, characterized in that, The step of parsing the data area of ​​the encoded signal based on the target clock signal to obtain target bit data consistent with the original bit data of the transmitting end includes: By invoking the preset data area encoding rules and combining them with the timing reference of the target clock signal, analytical control parameters are generated, wherein the analytical control parameters include at least the bit splitting period, the level sampling threshold, and the data verification format; The data area of ​​the encoded signal is serially split according to the bit splitting period to obtain continuous bit encoding units. Based on the level sampling threshold and according to the level standard of the preset data area encoding rule, the level sampling detection is performed on each bit encoding unit, and a high / low level state signal matching the preset data area encoding rule is output. Based on the mapping relationship between high / low level state signals and bit values ​​in the preset data area encoding rules, the high / low level state signals of each bit encoding unit are matched one-to-one and converted into corresponding bit values, and all bit values ​​are temporarily stored in the cache file according to the split timing order. According to the data verification format, verify whether the total number of bits and the start / end identifier of the temporarily stored bit values ​​meet the preset bit value verification conditions. When all the bit values ​​are found to meet the preset bit value verification conditions, the verified bit values ​​are spliced ​​together in the splitting time sequence to form the target bit data.

7. An electronic device, characterized in that, The electronic device includes a processor, a memory, and a data synchronization transmission program stored in the memory that can be executed by the processor, wherein when the data synchronization transmission program is executed by the processor, it implements the steps of the data synchronization transmission method as described in any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a data synchronization transmission program, wherein when the data synchronization transmission program is executed by a processor, it implements the steps of the data synchronization transmission method as described in any one of claims 1 to 6.

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