A high-sensitivity frame synchronization algorithm for DVB-S2 signals

Abstract

This invention discloses a high-sensitivity frame synchronization algorithm for DVB-S2 signals, belonging to the field of communication signal processing. The method performs FFT transformation on the received signal, pre-calculates the FFT conjugate values ​​of all possible PLSC synchronization header sequences, performs fully matched correlation operations in the frequency domain, and combines this with Doppler spectral line shift search to achieve high-sensitivity frame header detection. This invention is applicable to software processing platforms such as GPUs and maintains a high detection probability even under low signal-to-noise ratio and large frequency offset conditions, significantly improving the frame synchronization performance of DVB-S2 signals.

Description

Technical Field

[0001] This invention belongs to the field of communication signal reconnaissance technology, and more specifically relates to a high-sensitivity frame synchronization algorithm suitable for DVB-S2 signals. Background Technology

[0002] In the DVB-S2 standard, data is transmitted in frames. For the receiver, accurately locating the start of each frame is crucial. Therefore, frame synchronization technology plays a vital role and is one of the key technologies for DVB-S2 data transmission. The quality of frame synchronization directly affects the acquisition of data from the backend. The DVB-S2 frame header contains a 26-bit SOF (Start of Frame) segment and a 64-bit PLSC (Physical Layer Signaling Code) segment. The SOF segment remains constant, while the PLSC segment is encoded with 7 bits of information.

[0003] Traditional DVB-S2 frame synchronization methods mainly fall into two categories: one is the correlation accumulation method based on SOF sequences, which only utilizes 26 bits of SOF information and suffers from performance degradation under low signal-to-noise ratio; the other is the joint estimation method combining SOF and PLSC differential, which improves sensitivity to a certain extent, but the performance improvement is limited due to the noise introduced by the differential.

[0004] Traditional frame synchronization algorithms typically focus on the computational complexity of frame synchronization. When implementing frame synchronization algorithms on an FPGA, computational complexity directly determines the resources consumed by the FPGA. When using software platforms such as GPUs for DVB-S2 signal demodulation, the computational complexity of frame synchronization only affects the GPU's processing time. Since frame synchronization only needs to be performed once, it can be staggered from real-time demodulation in terms of timing, thus eliminating the timing conflict of frame synchronization on subsequent real-time demodulation processing. Therefore, the requirements for computational complexity can be relaxed when performing DVB-S2 frame synchronization processing on a GPU. This invention proposes a high-sensitivity DVB-S2 frame synchronization algorithm with full frame header matching. Frame synchronization is achieved by traversing all PLSC states corresponding to different information bits (7 bits) and performing matching correlation between SOF and received data. Summary of the Invention

[0005] To address the issue of low sensitivity in existing DVB-S2 frame synchronization algorithms, this invention proposes a high-sensitivity frame synchronization algorithm for DVB-S2 signals, the implementation block diagram of which is shown below. Figure 1 As shown.

[0006] A high-sensitivity frame synchronization algorithm for DVB-S2 signals includes the following steps.

[0007] Step 1: Data caching;

[0008] The input timed synchronized symbol sampling data x(k) is buffered with 32768 buffer points (the longest frame period of the DVB-S2 signal is 32490, and there must be a frame header in the 32768 data points).

[0009] Step 2: Frequency domain transformation of the received signal;

[0010] Perform a Fast Fourier Transform (FFT) on the cached data x(k), and obtain its frequency domain representation X(n) using Equation (1):

[0011] (1);

[0012] Where N=32768.

[0013] Step 3: Pre-calculation and storage of local reference templates;

[0014] This step is a critical preprocessing step, designed to generate and store all possible frame header frequency domain matching templates, which can be directly called during real-time synchronization to avoid redundant calculations (this step can be completed during the initialization phase and will not consume processing resources during normal operation).

[0015] Step 301: Generate all possible PLSC sequences;

[0016] According to the DVB-S2 standard, PLSC is generated by encoding 7 information bits b. By iterating through all values ​​of b from 0 to 127 (a total of 128 states), the corresponding 64-bit PLSC sequence is calculated using the standard encoding formula (2). :

[0017] (2);

[0018] Where B is a 7-bit information vector, G is a standard generator matrix, and S is a fixed mask sequence.

[0019] Step 302: Construct the local synchronization header time-domain sequence;

[0020] For each After merging it with a fixed 26-bit SOF sequence and padding with zeros to form N=32768, the local reference time-domain sequence is obtained. :

[0021] ;

[0022] ;

[0023] .

[0024] Step 303: Generate and store the frequency domain matching template;

[0025] For each perform FFT transformation, take the conjugate, and obtain the frequency-domain matching template through formula (3) :

[0026] (3);

[0027] Store 128 groups in the memory.

[0028] Step 4: Extract the i-th group of data according to the different 7-bit information bits i of the PLSC field .

[0029] Step 5: Doppler frequency offset search spectral line shift;

[0030] To compensate for the possible Doppler frequency offset of the signal, it is necessary to perform a sliding match in the frequency dimension on the local template; for perform circular shift. The shift step is 182m, where -18 < m < 18, and a total of 35 shifts are performed to obtain 35 groups of spectral lines. The m-th group of spectral lines is shown in formula (4):

[0031] {Y}^{m}_{i}(n)={Y}^{m}_{i}\left [ {(n+m)mod(32768)} \right ] (4);

[0032] The above spectral line shift step reflects the search interval of the signal Doppler. The search interval is 182 / 32768 times the symbol rate, and the search range is + / -(18*182 / 32768) = + / - 0.1 times the symbol rate.

[0033] Step 5: Frequency-domain circular correlation calculation;

[0034] Multiply the frequency-domain data X(n) of the received signal point by point with each group of shifted local templates , then transform back to the time domain through the inverse fast Fourier transform (IFFT), take the absolute value, and obtain a set of circular correlation functions through formula (5) :

[0035] (5);

[0036] The peak position n of

[0037] indicates the possible starting position of the frame header under the specific PLSC information bit i and Doppler compensation m assumption, and the peak value reflects the matching degree.

[0038] Iterate through all PLSC information bits i (0~127) and all Doppler shift indices m (-18~18), and in all... Find the maximum value and its corresponding index. , ,in

[0039] This is the estimated position of the frame synchronization header. These are the information bits of the PLSC field, which indicate information such as the modulation scheme, frame length, and presence of pilot signals for the current frame. That is, the signal Doppler estimate, where The symbol rate.

[0040] Simulation analysis shows that using this algorithm, the detection probability can reach 0.9 (false alarm probability is 0) when the symbol noise ratio is -2dB and the frequency offset range is 10% of the symbol rate. The frame synchronization header detection probabilities for different symbol noise ratios are as follows: Figure 2 As shown.

[0041] The advantages of this invention are:

[0042] High sensitivity: It utilizes all 90 bits of synchronization header energy for matching, which significantly increases the gain at low signal-to-noise ratios compared to the traditional method that only uses SOF.

[0043] Full information decoding: The synchronization process directly outputs PLSC information bits without requiring additional decoding steps;

[0044] High robustness: It is insensitive to symbol timing errors through frequency domain cyclic correlation; it can simultaneously compensate for large Doppler frequency offsets through spectral line shifting.

[0045] Suitable for software processing: The main algorithms are FFT / IFFT and matrix operations, which are very suitable for parallel and efficient implementation on GPUs, DSPs or multi-core CPUs. Attached Figure Description

[0046] Figure 1 This is a block diagram of the high-sensitivity frame synchronization algorithm for DVB-S2 signals based on full matching proposed in this invention.

[0047] Figure 2 The figure shows the simulation results of the frame synchronization header detection probability under different symbol signal-to-noise ratios when the false alarm probability is 0. Detailed Implementation

[0048] The present invention will be further described below with reference to embodiments.

[0049] Taking the 7-bit information bit b = 73 as an example, assuming that the signal Doppler is 0.04 times the symbol rate and the starting position of the frame header is the 100th symbol:

[0050] 1. First, cache the input symbol sampling data x(k) after timing synchronization, and the number of cached points is 32768.

[0051] 2. Calculate the FFT of the data x(n) to obtain X(n).

[0052] 3. Pre-calculate and store the FFT conjugate values of the zero-padded sequences corresponding to all 128 PLSC information bits.

[0053] 3.1. Calculate the encoded 64-bit PLSC code according to the 7-bit information bit b through formula (2) , for example, when b = 73, the 64-bit PLSC code calculated according to the above formula = 0x17fb1a503524b463 (hexadecimal).

[0054] 3.2. After merging the 64 bits with the 26-bit SOF and padding with zeros to form a 32768-point sequence , where the 26-bit SOF is equal to 0x18D2E82.

[0055] 3.3. Perform FFT on and take the conjugate to obtain . Traverse all possible information bits b (a total of 128), calculate and store it.

[0056] 4. Select the one corresponding to the information bit i .

[0057] 5. Shift the spectral lines of with a shift step of 182m, where -18 < m < 18, and shift a total of 35 times to obtain 35 groups of spectral lines. The m-th group of spectral lines is denoted as .

[0058] 6. Multiply the FFT value X(n) of the cached data by and then take the IFFT and absolute value to obtain the cyclic correlation function of the input signal .

[0059] 7. Traverse all i and k, and calculate the subscript corresponding to the maximum value , . At this time = 73, = 100, which is consistent with the PLSC field information bit and the frame synchronization header position of the real signal, =9, corresponding to a signal Doppler of 0.0389 times the symbol rate, which is close to the real signal Doppler.

[0060] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A high-sensitivity frame synchronization algorithm for DVB-S2 signals, characterized in that, Includes the following steps: S1: Buffer the symbol sampling data x(k) after timed synchronization, with a buffer length of 32768 points; S2: Perform FFT transformation on the buffered data to obtain the frequency domain sequence X(n); S3: Generate and store the frequency domain matching templates corresponding to all 128 PLSC sequences. ; where each is generated Includes the following sub-steps: S31: According to the DVB-S2 standard encoding formula, traverse all 7-bit information bits b to generate the corresponding 64-bit PLSC sequence. ; S32: The PLSC sequence Combined with a fixed 26-bit SOF sequence and padded with zeros to 32768, a local reference time-domain sequence is constructed. ; S33: For each Perform an FFT transform and take the conjugate to obtain the frequency domain matching template. ; S4: Based on the different 7-bit information bits i in the PLSC field, the frequency domain matching template generated in step S3 is... Extract the i-th set of data ; S5: Yes Spectral line shifting is performed with a shift step of 182m, where -18 ≤ m ≤ 18, generating a total of 35 shifted spectral lines. The m-th spectral line is... ; S6: Combine X(n) with each shifted group of... After multiplication, perform an IFFT and take the absolute value to obtain the loop-related function. ; S7: Iterate through all i and k, and find The index corresponding to the maximum value is used to obtain the frame header position, PLSC information bits, and Doppler estimate.

2. The algorithm according to claim 1, characterized in that, The PLSC sequence is generated as follows: ； Where B is the binary sequence corresponding to 7 information bits, G is the generator matrix, and S is the fixed sequence.

3. The algorithm according to claim 1, characterized in that, The step value of 182 for the spectral line shift corresponds to a Doppler search interval of 182 / 32768 times the symbol rate, and the search range is ±0.1 times the symbol rate.

4. The algorithm according to claim 1, characterized in that, The algorithm is executed on a GPU platform, allowing for higher computational complexity.

5. The algorithm according to claim 1, characterized in that, The local reference time-domain sequence constructed in step S32 satisfy: Where SOF(n) is a fixed 26-bit frame start sequence. This is the b-th type of PLSC sequence.

6. The algorithm according to claim 1, characterized in that, The cyclic correlation function The generation method is as follows: ； Where X(k) is the frequency domain sequence obtained in step S2. The shift spectrum obtained in step S5, where N is 32768; i is the information bit index of the PLSC field, with a value ranging from 0 to 127. m is the shift index for spectral line shifting in step S5, with a value range of -18 to 18; k is the frequency domain index, with a value range of 0 to N-1; and n is the time domain index, with a value range of 0 to N-1.

Images