FOW process anti-wire-punching multi-layer stacked chip and stacking method

Abstract

The invention belongs to the technical field of semiconductor integrated circuit packaging, and particularly relates to an FOW process anti-wire-punching multilayer stacked chip and a stacking method, and the chip comprises a substrate, a plurality of stacked chips, and a plurality of dummy chips. The dummy chip covers the upper part of the top-layer chip, a second FOW adhesive film is arranged between the dummy chip and the top-layer chip, and two welding spots of the top-layer chip and the bonding wires connected with the two welding spots are coated in the second FOW adhesive film and extend to the edge of the adhesive film; a conventional FOW multi-layer stacked chip process is abandoned, a layer of dummy chip is bonded on a top-layer chip, two exposed welding spots are covered, resultant force of transverse component force generated by mold flow at a line arc during plastic packaging is transmitted to the edge of a second FOW film covering the line arc, the stress area is enlarged, and effective support for the line arc is formed; stacking verification is carried out on five layers of chips in actual production, so that the strength of a top-layer wire arc and a welding spot can be effectively improved, the suspension length of the wire arc is reduced, the problem of wire punching in the plastic packaging process of the top-layer chip is solved, and the process stability and the product reliability are improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit packaging technology, specifically relating to a FOW process anti-fracture multilayer stacked chip and stacking method. Background Technology

[0002] Film on Wire (FOW) process uses FOW adhesive film instead of silicon wafers for chip stacking. The main process involves bonding the first layer of chips and wires, then, during the bonding of the next layer of chips, utilizing the excellent fluidity of the FOW adhesive film at high temperatures to coat the underlying bonding wires. This type of process is generally used for large-size, thin chips. To prevent the bonding wires from collapsing during the mounting of the upper layer chips, reverse stand-off stitchbond (RSSB) wire arc technology is typically used, with the arc height controlled below 80μm.

[0003] During multi-layer chip stacking, the top layer chip's traces are longer and taller than those of the lower layers. Additionally, the two solder joints of the top layer chip are exposed because they are not covered by the FOW (foil-on-wood) adhesive film. During molding, refer to... Figures 1-3 When the molding compound melts, the flow of the molding compound generates a lateral force at the top chip arc. The combined force is transmitted to the exposed two solder joints. Because the force-bearing area at the solder joint connection is small, it cannot provide effective support for the arc, which can easily cause deformation of the bonding wire at the solder joint, leading to wire breakage problems, and thus affecting the functional characteristics and reliability of the product. Summary of the Invention

[0004] The purpose of this invention is to provide a FOW process for anti-bursting multilayer stacked chips and a stacking method, which solves the technical problem of arcing of the top layer chip line during plastic encapsulation when using FOW process for multilayer chip stacking.

[0005] The solution of the present invention to the above-mentioned technical problems is as follows: A FOW process anti-blow wire multilayer stacked chip includes a substrate, multiple stacked chips and dummy chips; a first FOW adhesive film is disposed between adjacent chips and between the substrate and the bottom layer of chips; the substrate is connected to the corresponding chip by bonding wire. The dummy chip covers the top of the top-layer chip, and a second FOW adhesive film is disposed between the dummy chip and the top-layer chip. Two solder joints on the top-layer chip and the two solder joint ends of the bonding wires connected to the corresponding two solder joints are covered in the second FOW adhesive film, and one solder joint end of the corresponding bonding wire passes through the edge of the second FOW adhesive film.

[0006] Further specifying, the top-layer chip is connected to the substrate via a second bonding wire, and the remaining chips are connected to the substrate via a first bonding wire, wherein the outer diameter of the second bonding wire is larger than the outer diameter of the first bonding wire.

[0007] Further specifying, the first bonding wire is a gold wire, and the second bonding wire is a gold-palladium-copper wire.

[0008] Further specified, the thickness of the second FOW adhesive film is greater than the thickness of the first FOW adhesive film; the two solder joint ends of the second bonding wire extend from below the dummy film into the second FOW adhesive film and connect with the corresponding two solder joints.

[0009] Further specified, the size of the dummy wafer is larger than the size of the chip, the ends of the dummy wafer and the second FOW adhesive film both extend to the outer side of the corresponding ends of the chip, and the apex of the arc of the second bonding wire is located on the outer side of the dummy wafer.

[0010] Furthermore, the outer surface of the first bonding wire, the outer surface of the second bonding wire, the first bonding wire at the exit point of the first FOW adhesive film, and the second bonding wire at the exit point of the second FOW adhesive film are all coated with a polyimide (PI) coating.

[0011] A method for stacking multilayer chips with anti-fracture wires in FOW process includes the following steps: Determine the wafer thinning thickness and dicing size based on the chip size; The first FOW adhesive film is attached to the wafer and diced to obtain multiple chips; Determine the dummy wafer thinning thickness and dicing size based on the chip size; A second FOW adhesive film is pasted onto the fake wafer and then diced to obtain multiple fake wafers; The obtained chips are stacked on the substrate from bottom to top, and the substrate is connected to the chips below the top layer of chips using the first bonding wire; A second bonding wire is used to connect the substrate to the top-layer chip, and a dummy die is placed over the top-layer chip so that the dummy die covers the two solder joints of the top-layer chip.

[0012] Furthermore, the FOW process anti-blowout multilayer stacked chip stacking method also includes the following steps: The enhanced PAA solution was sprayed onto the outer surfaces of the first bonding wire and the second bonding wire, and the spraying was repeated to reinforce the first bonding wire at the exit point of the first FOW film and the second bonding wire at the exit point of the second FOW film.

[0013] Further specifying, the preparation of the enhanced PAA solution includes the following steps: 3,3',4,4'-biphenyltetracarboxylic acid dianhydride, p-phenylenediamine, and N-methylpyrrolidone were mixed in the specified ratio and stirred to obtain a precursor PAA solution; Nano-SiO2 solution was added to the precursor PAA solution and dispersed using an ultrasonic disperser to obtain an enhanced PAA solution.

[0014] Further specified, the ratio of 3,3',4,4'-biphenyltetracarboxylic acid dianhydride, p-phenylenediamine and N-methylpyrrolidone is 1:1.02:13 by mass.

[0015] The beneficial effects of this invention are as follows: 1. This invention abandons the conventional FOW multilayer stacked chip process. Instead, a dummy die is attached to the top chip to cover the two exposed solder joints. This transfers the resultant force of the lateral component force generated by the molding flow at the arc during molding to the edge of the second FOW film covering the arc, expanding the force-bearing area and forming effective support for the arc. Through actual production and stacking verification of five-layer chips, the strength of the top arc and solder joints can be effectively improved, the overhang length of the arc can be reduced, the wire punching problem in the molding process of the top chip can be solved, and the process stability and product reliability can be improved.

[0016] 2. This invention attaches a dummy wafer with a larger area and a thicker second FOW adhesive film to the top-layer chip, which can effectively shorten the length of the suspended wire arc. At the same time, a second bonding wire with a larger diameter and higher hardness is selected to improve the bending resistance of the wire arc during the molding process. An enhanced PAA solution is sprayed on the outer surfaces of the first bonding wire and the second bonding wire, and repeated to reinforce the spraying at the exit points of the first bonding wire and the second bonding wire at the exit points of the second FOW adhesive film. After heating and imidization, a polyimide (PI) coating is formed, which can further enhance the mechanical strength of the bonding wire as a whole and the exit points of the adhesive film. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a multi-layer stacked chip structure using a conventional FOW process. Figure 2 This is a schematic diagram of wire bonding and punching on the top layer of a multi-layer stacked chip using a conventional FOW process. Figure 3 X-ray inspection image of the wire bonding and punching of the top layer of a conventional FOW process multilayer stacked chip; Figure 4 This is a schematic diagram of the FOW process anti-blow wire multilayer stacked chip structure of the present invention; Figure 5 This is a top view of the FOW process anti-fracture multilayer stacked chip of the present invention; Figure 6 This is an X-ray inspection image of the top layer of the FOW process anti-burst multilayer stacked chip of the present invention; In the diagram, 10-chip; 11-first FOW adhesive film; 12-first bonding wire; 20-dummy die; 21-second FOW adhesive film; 22-second bonding wire; 30-substrate; 31-gold finger; 32-second solder joint; 33-first solder joint; 40-polyimide (PI) coating. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0020] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0021] In the description of the embodiments of the present invention, it should be noted that if terms such as "upper," "lower," "horizontal," or "inner" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, terms such as "first" and "second" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] Taking a three-layer chip stack as an example, during molding, the molten molding compound creates a lateral force at the bonding wire arc. This force is then transferred to the two solder joints 32 on the exposed top-layer chip 10. Because the contact area at the two solder joints 32 is small, it cannot effectively support the arc, easily causing deformation of the bonding wire at these joints, leading to wire breakage issues. Figures 1-3 As shown, the marked area is the region where wire breakage occurs.

[0023] Example 1 This invention provides a FOW process anti-blow wire multilayer stacked chip, including a substrate 30, multiple stacked chips 10 and dummy wafers 20; a first FOW adhesive film 11 is provided between adjacent chips 10 and between the substrate 30 and the bottom layer chip 10, and the first FOW adhesive film 11 is used to bond two adjacent chips 10 and the bottom layer chip to the substrate 30. Gold fingers 31 are provided on the substrate 30, and two solder joints 32 are provided on the top of the chip 10. Bonding wire is used to connect the gold fingers 31 to the corresponding two solder joints 32.

[0024] refer to Figures 4-6 Taking a three-layer chip stack as an example; a dummy die 20 covers the top of the top chip 10, and the thickness of the dummy die 20 can be adjusted according to the height of the upper mold of the actual molding die; a second FOW adhesive film 21 is provided between the dummy die 20 and the top chip 10. When the bonding wire connects the top chip and the gold finger 31, the two solder joint ends of the bonding wire extend into the second FOW adhesive film 21 and connect with the corresponding two solder joints 32. At this time, the two solder joints 32 of the top chip are covered by the second FOW adhesive film 21, which improves the solder joint strength; during the molding process, the resultant force of the lateral component force generated by the mold flow at the bonding wire will be transmitted to the edge of the second FOW film covering the bonding wire. By expanding the force-bearing area, effective support for the bonding wire can be formed, avoiding wire breakage.

[0025] Specifically, the top-layer chip 10 is connected to the substrate 30 via the second bonding wire 22, and the remaining chips 10 are connected to the substrate 30 via the first bonding wire 12. The outer diameter of the second bonding wire 22 is larger than that of the first bonding wire 12. Taking into account the pad area, for example, if the outer diameter of the first bonding wire 12 is 20μm, the outer diameter of the second bonding wire 22 can be selected as 25μm.

[0026] Preferably, the second bonding wire 22 is a gold-palladium-copper wire. The second bonding wire 22, which has a larger wire diameter and higher hardness than the first bonding wire 12, is selected to reduce the possibility of deformation of the second bonding wire 22 under the impact of the mold flow and further avoid wire breakage.

[0027] To further explain, the thickness of the second FOW adhesive film 21 is greater than the thickness of the first FOW adhesive film 11. For example, if the thickness of the first FOW adhesive film 11 is 60μm, then the thickness of the second FOW adhesive film 21 can be selected as 80μm. The two solder joint ends of the second bonding wire 22 extend from below the dummy die 20 into the second FOW adhesive film 21. Since the arc of the second FOW adhesive film 21 is relatively long and its height is relatively high when connecting the top layer chip, by increasing the thickness of the second FOW adhesive film 21, the bottom of the dummy die 20 is prevented from pressing against the second bonding wire 22, which would cause the wire to collapse. Therefore, the height of the top of the second FOW adhesive film 21 does not exceed the height of the arc apex of the second bonding wire 22. At the same time, since the height of the second bonding wire 22 gradually increases from the two solder joints 32 to the arc apex, increasing the thickness of the second FOW adhesive film 21 can provide more sufficient space for the dummy die 20.

[0028] To further explain, as the number of layers in the chip 10 increases, the height and length of the bonding wire arc gradually increase. The dummy wafer 20, which has a larger area than the chip 10, can shorten the suspension length of the second bonding wire 22 through the covering effect of the larger area of ​​the second FOW film 22, thereby improving the bending resistance of the second bonding wire 22 during molding. Therefore, the size of the dummy wafer 20 is larger than that of the chip 10. For example, the length, width and thickness of the chip 10 are 8.5mm × 5.1mm × 0.12mm, and the length, width and thickness of the dummy wafer 20 are 8.6mm × 5.6mm × 0.1mm. The dummy wafer 20 has the same size as the second FOW film 21. The dummy wafer 20 extends to the outer side of the corresponding end of the chip 10 on all four sides. At the same time, it is necessary to ensure that the apex of the arc of the second bonding wire 22 is located on the outer side of the dummy wafer 20, that is, the dummy wafer avoids point contact with the arc of the second bonding wire 22.

[0029] To further explain, in order to enhance the overall mechanical strength of the bonding wires and the points where the first FOW film 11 and the second FOW adhesive film 21 exit, a polyimide PI coating 40 is applied to the outer surface of the first bonding wire 12, the outer surface of the second bonding wire 22, the junction of the first bonding wire 12 and the first FOW adhesive film 11, and the junction of the second bonding wire 22 and the second FOW adhesive film 21. Preferably, a polyimide PI coating 40 is also applied to the substrate 30 and the dummy film 20, with enhanced coating at the points where the bonding wires lead out from the first FOW film 11 and the second FOW adhesive film 21, respectively.

[0030] Example 2 Based on the FOW process anti-blowout multilayer stacked chip described in Example 1, this example provides a FOW process anti-blowout multilayer stacked chip stacking method, including the following steps: The wafer thinning thickness and dicing size are determined based on the chip size; The first FOW adhesive film 11 is attached to the wafer and diced to obtain multiple chips 10; Determine the dummy wafer thinning thickness and dicing size based on the chip 10 dimensions; A second FOW adhesive film 21 is pasted onto the dummy wafer and then diced to obtain multiple dummy wafers 20. The obtained chips 10 are stacked on the substrate 30 from bottom to top, and the substrate 30 is connected to the chips 10 below the top chip 10 using the first bonding wire 12. The second bonding wire 22 is used to connect the substrate 30 and the top chip 10. The dummy chip 20 is then placed on the top chip 10, so that the dummy chip 20 covers the two solder joints of the top chip 10.

[0031] For example, for a five-layer stacked chip product using the FOW process, the substrate dimensions are 189mm × 68mm × 0.33mm, the unit size is 13mm × 20mm, the chip dimensions are 8.5mm × 5.1mm × 0.12mm, the chip pad size is 54μm × 67μm, and the pad spacing is 136μm.

[0032] Specifically, the wafer is thinned to 120μm, and a first FOW adhesive film 11 with a thickness of 60μm is attached. The diced chip 10 has a size of 8.5mm × 5.1mm. The dummy wafer is thinned to 100μm, and a second FOW adhesive film 22 with a thickness of 80μm is attached. The diced dummy wafer 20 has a size of 8.6mm × 5.6mm. The substrate 30 is pre-baked at a temperature of 125℃ for 2 hours.

[0033] A first-layer chip is bonded to the substrate 30 with a pick-up force of 1.5N, a pick-up delay of 500ms, a pick-up time of 500ms, a bonding pressure of 5N, a bonding time of 1500ms, and a heating temperature of 140℃. After the first-layer chip is bonded, the substrate 30 with the first-layer chip is transferred to a pressure oven for curing. The temperature is raised to 150℃ after 30 minutes, held at 150℃ for 60 minutes, and then cooled to room temperature. The entire process uses a pressure of 0.7MPa.

[0034] A RSSB arc layer is applied to substrate 30 using a 20μm first bonding wire 11. First, a spherical bump is formed on the pad of chip 10. Then, the cleaver moves to above the gold finger 31 of substrate 30 to perform ball bonding of solder point 33. Subsequently, the cleaver moves to above the spherical bump to complete the wedge bonding of solder point 32. The height of the highest point of the bonding wire arc from the surface of chip 10 is controlled to be below 80μm.

[0035] Subsequently, the bonding and wire bonding of the second to fifth layers of the chip 10 are repeated; among them, the second bonding wire 22 is used for the top layer chip to reduce the possibility of wire arc deformation under the impact of the mold flow.

[0036] On substrate 30, dummy wafer 20 is attached to the substrate: The pickup force is 1.8N, the pickup delay is 500ms, the pickup time is 500ms, the bonding pressure is 8N, the bonding time is 1500ms, and the core heating temperature is 140℃. After the dummy wafer 20 is cored, the substrate 30 is transferred to a pressure oven for post-curing. The temperature is raised to 150℃ for 30 minutes, held at 150℃ for 60 minutes, and then cooled to room temperature. The pressure is 0.7MPa throughout the process to complete the core bonding of the dummy wafer 20.

[0037] To further explain, the FOW process anti-blowout multilayer stacking chip stacking method also includes: The enhanced PAA solution is sprayed onto the outer surface of the first bonding wire 12 and the outer surface of the second bonding wire 22. The first bonding wire 12 and the first FOW film 11 are repeatedly sprayed at the junction of the second bonding wire 22 and the second FOW film 21. After heating and imidization, a polyimide PI coating 40 is formed.

[0038] In the synthesis of polyimide (PI), 3,3',4,4'-biphenyltetracarboxylic acid dianhydride (BPDA) was selected, p-phenylenediamine (pPDA) was selected as the diamine, and N-methylpyrrolidone (NMP) was selected as the solvent. The BPDA:pPDA:NMP was prepared in a mass ratio of 1:1.02:13. Under nitrogen protection and at 25°C, the mixture was continuously stirred until it was completely dissolved and a low-temperature polycondensation reaction occurred to obtain a precursor PAA solution with a solid content of 15%-20%.

[0039] Nano-SiO2 was used as a filler and reinforcing agent, KH-550 as a silane coupling agent, and anhydrous ethanol as a solvent. The mixture was prepared in a mass ratio of SiO2:KH-550:anhydrous ethanol = 50:1:180. The mixture was continuously stirred at 60-80℃ to allow the hydroxyl groups on the SiO2 surface to react with the coupling agent, thereby reducing agglomeration and obtaining a pretreated nano-SiO2 solution.

[0040] Pretreated nano-SiO2 was added to the precursor PAA solution, with the amount of SiO2 being 5%-15% of the PAA solid mass; the solution was dispersed for 2 hours using an ultrasonic disperser with a power of 500W and a frequency of 30kHz to obtain an enhanced PAA solution.

[0041] Using an ultrasonic thin-film spraying device with a spray width of 10 mm, a spray flow rate of 0.5 ml / min, an ultrasonic frequency of 100 kHz, and a guiding air pressure of 0.15 MPa, an enhanced PAA solution was uniformly sprayed onto the surfaces of the substrate 30, dummy wafer 30, and bonding wires, achieving a spray thickness of 10 μm. The spraying was repeated to reinforce the area where the FOW film was drawn from the bonding wires. After spraying, the substrate 30 was placed in an oven for imidization treatment. The heating process involved raising the temperature to 150°C for 10 minutes, holding at 150°C for 30 minutes, raising the temperature to 250°C for 5 minutes, holding at 250°C for 1 hour, and then cooling to room temperature. After imidization, the substrate underwent plasma cleaning. Subsequent encapsulation processes, such as molding, printing, ball bonding, and dicing, can then be performed.

[0042] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the scope of the invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0043] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be appropriately combined to form other embodiments that can be understood by those skilled in the art. The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A FOW process anti-fracture multilayer stacked chip, characterized in that, It includes a substrate (30), multiple stacked chips (10) and dummy wafers (20); a first FOW adhesive film (11) is provided between adjacent chips (10) and between the substrate (30) and the bottom chip (10); the substrate (30) is connected to the corresponding chip (10) by bonding wires; The dummy chip (20) covers the top of the chip (10). A second FOW adhesive film (21) is provided between the dummy chip (20) and the chip (10). Two solder joints (32) on the chip (10) and the two solder joint ends of the bonding wires connected to the corresponding two solder joints (32) are covered in the second FOW adhesive film (21). One solder joint end of the corresponding bonding wire passes through the edge of the second FOW adhesive film (21).

2. The FOW process anti-burst multilayer stacked chip according to claim 1, characterized in that, The top-layer chip (10) is connected to the substrate (30) via a second bonding wire (22), and the remaining chips (10) are connected to the substrate (30) via a first bonding wire (12). The outer diameter of the second bonding wire (22) is larger than the outer diameter of the first bonding wire (12).

3. The FOW process anti-fracture multilayer stacked chip according to claim 2, characterized in that, The first bonding wire (12) is a gold wire, and the second bonding wire (22) is a gold-palladium-copper wire.

4. The FOW process anti-burst multilayer stacked chip according to claim 2, characterized in that, The thickness of the second FOW film (21) is greater than the thickness of the first FOW film (11); the two solder joint ends of the second bonding wire (22) extend from below the dummy sheet (20) into the second FOW film (21) and connect with the corresponding two solder joints (32).

5. The FOW process anti-burst multilayer stacked chip according to claim 4, characterized in that, The size of the dummy wafer (20) is larger than that of the chip (10). The ends of the dummy wafer (20) and the second FOW adhesive film (21) extend to the outside of the corresponding ends of the chip (10). The arc vertex of the second bonding wire (22) is located outside the dummy wafer (20).

6. The FOW process anti-fracture multilayer stacked chip according to claim 5, characterized in that, The outer surface of the first bonding wire (12), the outer surface of the second bonding wire (22), the first bonding wire (12) at the exit point of the first FOW film (11), and the second bonding wire (22) at the exit point of the second FOW film (21) are all coated with a polyimide PI coating (40).

7. A method for stacking multilayer chips with anti-fracture wires in FOW process, characterized in that, Includes the following steps: The wafer thinning thickness and dicing size are determined based on the chip (10) size; The first FOW adhesive film (11) is pasted on the wafer and diced to obtain multiple chips (10). The dummy wafer thinning thickness and dicing size are determined based on the chip (10) size; A second FOW adhesive film (21) is pasted onto the dummy wafer and then diced to obtain multiple dummy wafers (20). The obtained chips (10) are stacked on the substrate (30) from bottom to top, and the substrate (30) is connected to the chip (10) below the top chip using the first bonding wire (12). Using a second bonding wire (22), the substrate (30) is connected to the top chip (10), and a dummy die (20) is placed on top of the top chip (10), so that the dummy die (20) covers the two solder joints (32) of the top chip (10).

8. The FOW process anti-fracture multilayer stacked chip stacking method according to claim 7, characterized in that, The FOW process anti-fracture multilayer stacked chip stacking method further includes the following steps: The enhanced PAA solution is sprayed onto the outer surface of the first bonding wire (12) and the outer surface of the second bonding wire (22). The first bonding wire (12) is repeatedly sprayed at the exit point of the first FOW film (11) and the second bonding wire (22) is sprayed at the exit point of the second FOW film (21).

9. The FOW process anti-fracture multilayer stacked chip stacking method according to claim 8, characterized in that, The preparation of the enhanced PAA solution includes the following steps: 3,3',4,4'-biphenyltetracarboxylic acid dianhydride, p-phenylenediamine, and N-methylpyrrolidone were mixed in the specified ratio and stirred to obtain a precursor PAA solution; Nano-SiO2 solution was added to the precursor PAA solution and dispersed using an ultrasonic disperser to obtain an enhanced PAA solution.

10. The FOW process anti-fracture multilayer stacked chip stacking method according to claim 9, characterized in that, The ratio of 3,3',4,4'-biphenyltetracarboxylic acid dianhydride, p-phenylenediamine, and N-methylpyrrolidone is 1:1.02:13 by mass.

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