Display device and electronic device including the same

Abstract

The invention discloses a display device and an electronic device including the same. The display device includes: a pixel driving circuit including a transistor; a connection electrode electrically connected to the pixel driving circuit; a first electrode disposed on the connection electrode; a pixel defining layer defining an opening exposing a portion of the first electrode; a connection pattern disposed on the connection electrode and the pixel defining layer, and electrically connected to the connection electrode; an electrode layer disposed on the first electrode and electrically connected to the connection pattern; a separator disposed on the pixel defining layer and the connection pattern, separating the electrode layer into a plurality of second electrodes spaced apart from each other, and covering at least a portion of the connection pattern; and an additional connection pattern disposed on the pixel defining layer and extending in a cross-section from the connection pattern in a direction away from a central portion of the spacer.

Description

Technical Field

[0001] Some aspects of embodiments of this disclosure generally relate to display devices and electronic devices including display devices. Background Technology

[0002] With the development of information technology, the importance of display devices as a medium for connecting users with information has become increasingly apparent. For example, the use of display devices such as liquid crystal displays (“LCD”), organic light-emitting diode (“OLED”) displays, plasma display panels (“PDP”) devices, or quantum dot displays is increasing.

[0003] The display device includes a light-emitting element and a pixel driving circuit for driving the light-emitting element. The light-emitting element can be driven by the pixel driving circuit to emit light. In order to improve the reliability of the display device, research is being conducted on the connection between the light-emitting element and the pixel driving circuit.

[0004] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0005] Some aspects of embodiments of this disclosure generally relate to display devices and electronic devices including display devices. For example, some aspects of embodiments of this disclosure relate to display devices that provide visual information and electronic devices including display devices.

[0006] Some embodiments include a display device having relatively improved display characteristics.

[0007] Some aspects of the embodiments include electronic devices that include a display device.

[0008] A display device according to some embodiments of the present disclosure includes: a pixel driving circuit including a transistor; a connecting electrode electrically connected to the pixel driving circuit; a first electrode disposed on the connecting electrode; a pixel defining layer defining an opening exposing a portion of the first electrode; a connecting pattern disposed on the connecting electrode and the pixel defining layer and electrically connected to the connecting electrode; an electrode layer disposed on the first electrode and electrically connected to the connecting pattern; a separator disposed on the pixel defining layer and the connecting pattern, separating the electrode layer into a plurality of second electrodes spaced apart from each other and covering at least a portion of the connecting pattern; and an additional connecting pattern disposed on the pixel defining layer and extending in a cross-section from the connecting pattern in a direction away from the central portion of the separator.

[0009] According to some embodiments, the side surface of the separator can contact the connecting pattern and can have multiple reverse tapering ramps in the cross section.

[0010] According to some embodiments, the plurality of reverse tapered ramps may include a first reverse tapered ramp and a second reverse tapered ramp. According to some embodiments, the first reverse tapered ramp may be connected to the upper surface of the separator, and the second reverse tapered ramp may contact the connecting pattern.

[0011] According to some embodiments, the additional connection pattern may include the same material as the connection pattern.

[0012] According to some embodiments, the additional connection pattern may include a transparent conductive oxide.

[0013] According to some embodiments, the width of the additional connection pattern can be greater than or equal to 0.3 micrometers and less than or equal to 3 micrometers.

[0014] According to some embodiments, the width of the connection pattern can be greater than or equal to 2 micrometers and less than or equal to 4 micrometers.

[0015] According to some embodiments, the additional connection pattern and the first electrode can be electrically independent of each other.

[0016] According to some embodiments, each of the plurality of second electrodes can be electrically connected to the pixel driving circuit via a connection pattern and a connection electrode.

[0017] According to some embodiments, each of the plurality of second electrodes may contact the connection pattern at a location adjacent to or overlapping with the separator.

[0018] According to some embodiments, the display device may further include an intermediate layer disposed between the first electrode and the electrode layer and including an emissive material.

[0019] A display device according to some embodiments of the present disclosure includes: a pixel driving circuit including transistors; a connecting electrode electrically connected to the pixel driving circuit; a first electrode disposed on the connecting electrode; a pixel defining layer covering a portion of the first electrode and defining an emission region; a connecting pattern electrically connected to the connecting electrode and surrounding at least a portion of the emission region in a plan view; an electrode layer disposed on the first electrode and electrically connected to the connecting pattern; a separator disposed on the pixel defining layer and the connecting pattern, separating the electrode layer into a plurality of second electrodes spaced apart from each other and overlapping the connecting pattern in a plan view; and an additional connecting pattern extending from the connecting pattern and disposed between the connecting pattern and the emission region in a plan view.

[0020] According to some embodiments, in a plan view, an additional connection pattern may surround at least a portion of the emission area.

[0021] According to some embodiments, in a plan view, the connecting pattern may surround at least a portion of an additional connecting pattern.

[0022] According to some embodiments, in a plan view, the separator may completely surround the connecting pattern and the additional connecting pattern.

[0023] According to some embodiments, the side surface of the separator can contact the connecting pattern and has multiple reverse tapering ramps in the cross section.

[0024] According to some embodiments, the additional connection pattern may include the same material as the connection pattern.

[0025] According to some embodiments, the width of the additional connection pattern can be greater than or equal to 0.3 micrometers and less than or equal to 3 micrometers.

[0026] According to some embodiments, the additional connection pattern and the first electrode can be electrically independent of each other.

[0027] According to some embodiments, each of the plurality of second electrodes can be electrically connected to the pixel driving circuit via a connection pattern and a connection electrode.

[0028] An electronic device according to some embodiments of the present disclosure includes: a display device including pixels; and a processor for transmitting image data signals and input control signals to the display device. According to some embodiments, the display device includes: a pixel driving circuit including transistors; a connecting electrode electrically connected to the pixel driving circuit; a first electrode disposed on the connecting electrode; a pixel defining layer defining an opening exposing a portion of the first electrode; a connecting pattern disposed on the connecting electrode and the pixel defining layer and electrically connected to the connecting electrode; an electrode layer disposed on the first electrode and electrically connected to the connecting pattern; a separator disposed on the pixel defining layer and the connecting pattern, separating the electrode layer into a plurality of second electrodes spaced apart from each other and covering at least a portion of the connecting pattern; and an additional connecting pattern disposed on the pixel defining layer and extending in cross-section from the connecting pattern in a direction away from the central portion of the separator.

[0029] The display device according to some embodiments of this disclosure may include connecting electrodes, connecting patterns, and separators. Therefore, the cathode on the anode can be easily connected to the pixel driving circuit. According to some embodiments, the cathode on the anode can be connected to the drain of the driving transistor of the pixel driving circuit via the connecting electrodes and connecting patterns. Accordingly, even when the light-emitting element deteriorates, the gate-source voltage (Vgs) of the driving transistor can remain unchanged. Accordingly, the range of variation in driving current due to the deterioration of the light-emitting element can be relatively reduced. Accordingly, the afterimage defects of the display device that depend on the increase in usage time can be relatively reduced, and the lifespan of the display device can be relatively improved.

[0030] Furthermore, the display device according to some embodiments of this disclosure may further include additional connection patterns extending from the connection patterns. Accordingly, even if process distribution occurs in the process of forming the separator, the double reverse tapering structure can be smoothly formed on the side surface of the separator. Accordingly, it is easier to separate (or disconnect) the electrode layer through the separator. Attached Figure Description

[0031] The illustrative and non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0032] Figure 1A This is a plan view illustrating a display device according to some embodiments of the present disclosure.

[0033] Figure 1B This is a plan view illustrating a display device according to some embodiments of the present disclosure.

[0034] Figure 2A The illustration includes Figure 1A and Figure 1B A circuit diagram illustrating an example of the circuit structure of pixels in a display device.

[0035] Figure 2B The illustration includes Figure 1A and Figure 1B A circuit diagram of another example of the circuit structure of a pixel in a display device.

[0036] Figure 2C The illustration includes Figure 1A and Figure 1B A circuit diagram illustrating yet another example of the circuit structure of pixels in a display device.

[0037] Figure 3 It is a diagram. Figure 1A and Figure 1B A floor plan of a portion of the display device area.

[0038] Figure 4 It is a diagram. Figure 3 An enlarged plan view of one of the unit emission regions in the unit emission region.

[0039] Figure 5 It is along Figure 4 The cross-sectional view taken from line I-I'.

[0040] Figure 6 yes Figure 5 Enlarged cross-sectional view of region A.

[0041] Figure 7 This is a block diagram of an electronic device according to some embodiments of the present disclosure.

[0042] Figure 8This is a schematic diagram of an electronic device according to some embodiments. Detailed Implementation

[0043] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, which illustrate some exemplary embodiments. However, the inventive concept can be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity.

[0044] Various modifications and forms may be made in this disclosure, and specific embodiments will be illustrated in the accompanying drawings and described in detail in the text. However, this is not intended to limit this disclosure to the specific forms disclosed, and it will be understood that all variations, equivalents, or substitutions falling within the spirit and scope of this disclosure should be included.

[0045] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of the inventive concept. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0046] It will be understood that when an element is referred to as "connected" or "linked" to another element, it may be directly connected to or directly linked to that other element, or there may be an intermediary element. Conversely, when an element is referred to as "directly connected" or "directly linked" to another element, there is no intermediary element. Other terms used to describe the relationship between elements (e.g., "between" and "directly between," "adjacent" and "directly adjacent," etc.) should be interpreted in a similar manner.

[0047] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the inventive concept. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to include the plural forms as well. It will be further understood that, when used in this specification, the term “comprising” indicates the presence of the stated features, integrals, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0048] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another illustrated in the figures. It will be understood that, in addition to the orientations depicted in the figures, relative terms are intended to encompass different orientations of the device. For example, if a device in one of the figures is flipped, an element described as being “down” to other elements will be oriented “up” to other elements. Thus, depending on the specific orientation of the figure, the term “down” can encompass both “down” and “up” orientations. Similarly, if a device in one of the figures is flipped, an element described as being “below” or “under” other elements will be oriented “above” to other elements. Thus, the terms “below” or “under” can encompass both “up” and “down” orientations.

[0049] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will be further understood that terms (e.g., those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0050] In the following description, embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same parts in the drawings, and some redundant descriptions of the same parts may be omitted.

[0051] Figure 1A This is a plan view illustrating a display device according to some embodiments of the present disclosure. Figure 1B This is a plan view illustrating a display device according to some embodiments of the present disclosure.

[0052] In this specification, a plane may be defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the first direction DR1 and the second direction DR2 may be perpendicular to each other. The display device and its various components or layers may have a thickness extending along a third direction that intersects or intersects the plane, that is, each of the first direction DR1 and the second direction DR2 may be perpendicular to the third direction.

[0053] refer to Figure 1A and Figure 1BThe display device DD (or DDa) can be a device activated by an electrical signal. For example, the display device DD can be a small display device used in small electronic devices such as smartphones, mobile phones, smartwatches, game consoles, or cameras. Alternatively, the display device DDa can be a medium to large-sized display device used in medium to large-sized electronic devices such as laptops, tablet computers, televisions, computer monitors, vehicle monitors, or external billboards. Figure 1A The illustration shows a display device DD as an example of a small display device, and... Figure 1B The illustration shows a display device DDa as an example of a medium-to-large-sized display device.

[0054] A display device DD (or DDa) may include a display area DA and a peripheral area NDA. The display area DA may be an area that displays an image by generating light or controlling the transmittance of light provided from an external light source. The peripheral area NDA may be located around the display area DA (e.g., on the periphery of the display area DA or outside the coverage area of ​​the display area DA). For example, the peripheral area NDA may surround at least a portion of the display area DA. According to some embodiments, the peripheral area NDA may be an area where no image is displayed. However, embodiments according to this disclosure are not limited to this, and an image may be displayed in at least a portion of the peripheral area NDA. For example, a light-emitting element may be located in at least a portion of the peripheral area NDA.

[0055] The display device DD (or DDa) may include a substrate SUB, pixels PX, gate lines GL, data lines DL, data driver DDV, and gate driver GDV.

[0056] The substrate SUB can serve as the substrate of a display device DD (or DDa). According to some embodiments, examples of materials that can be used as the substrate SUB include glass, quartz, silicon, or polymers. These can be used individually or in combination with each other. Additionally, the substrate SUB can have a single-layer structure or a multi-layer structure in which multiple layers comprising different materials are stacked.

[0057] Pixels PX can be located in the display area DA or on the substrate SUB. Pixels PX can be electrically connected to gate lines GL and data lines DL. For example, pixels PX can be arranged in a matrix or array in the first direction DR1 and the second direction DR2. Each pixel PX may include pixel driving circuitry and a light-emitting element. The light-emitting element can emit light. The light-emitting element can be an organic light-emitting diode or an inorganic light-emitting diode.

[0058] Each of the gate lines GL and each of the data lines DL can intersect each other. For example, each of the gate lines GL can extend substantially in a first direction DR1, and the gate lines GL can be arranged in a second direction DR2. Each of the data lines DL can extend substantially in the second direction DR2, and the data lines DL can be arranged in the first direction DR1. However, embodiments according to this disclosure are not limited thereto.

[0059] The data driver DDV can be located in the peripheral area NDA or on the substrate SUB. The data driver DDV generates a data voltage. The data driver DDV outputs the data voltage to the data line DL. The data voltage can be applied to the pixel PX through the data line DL.

[0060] According to some embodiments, the data driver DDV can be mounted on the substrate SUB. However, embodiments according to this disclosure are not limited thereto, and the data driver DDV can be arranged as a chip on film (“COF”) on a flexible film attached to the substrate SUB.

[0061] According to some embodiments, Figure 1B The display device DDA may include a plurality of data drivers DDV. For example, the data drivers DDV may be located on opposite sides of the display area DA in the second direction DR2. For example, the data drivers DDV may be arranged along each of the long sides of the display device DDA. However, embodiments according to this disclosure are not limited thereto.

[0062] The gate driver GDV can be located in the peripheral region NDA, on the substrate SUB. The gate driver GDV can generate a gate signal. The gate driver GDV can output the gate signal to the gate line GL. The gate signal can be applied to the pixel PX through the gate line GL. According to some embodiments, the gate driver GDV can be located on opposite sides of the display region DA in the first direction DR1. However, embodiments according to this disclosure are not limited thereto.

[0063] According to some embodiments, the transmit driver that generates the transmit control signal may be further located in the peripheral region NDA. The transmit control signal can be applied to pixel PX via the transmit control line.

[0064] Figure 1A and Figure 1B The number or arrangement of data drivers (DDVs) and gate drivers (GDVs) illustrated in the figures are merely examples and are not limited to embodiments of this disclosure.

[0065] In addition, although Figure 1AThe illustration shows a display device DD having a rectangular planar shape (or substantially a rectangular planar shape) having short sides extending in a first direction DR1 and long sides extending in a second direction DR2, but embodiments according to this disclosure are not limited thereto. Furthermore, although Figure 1B The illustration shows a display device DDa having a rectangular planar shape (or substantially a rectangular planar shape) having a long side extending in a first direction DR1 and a short side extending in a second direction DR2, but embodiments of this disclosure are not limited thereto. That is, according to some embodiments, the planar shape of each of the display devices DD and DDa can be varied.

[0066] The following description, together with the accompanying drawings, can be applied in the same (or substantially the same) way. Figure 1A Display device DD and Figure 1B The display device is DDa. Therefore, for ease of description, both display device DD and DDa will be referred to as display device DD below.

[0067] Figure 2A The illustration includes Figure 1A and Figure 1B A circuit diagram illustrating an example of the circuit structure of pixels in a display device. Although Figure 2A Various components in a pixel circuit according to some embodiments are illustrated, but the embodiments of this disclosure are not limited thereto, and the pixel circuit may include additional components without departing from the spirit and scope of the embodiments of this disclosure.

[0068] refer to Figure 2A According to some embodiments, a pixel PX may include a light-emitting element LD and a pixel driving circuit PC connected to the light-emitting element LD. According to some embodiments, the pixel driving circuit PC may include a first transistor T1, a second transistor T2, and a first capacitor C1. Figure 2A In the illustration, both the first transistor T1 and the second transistor T2 are shown as n-type transistors. However, embodiments of this disclosure are not limited thereto, and some of the first transistor T1 and the second transistor T2 may be n-type transistors, while others may be p-type transistors. For example, the first transistor T1 may be an n-type transistor, and the second transistor T2 may be a p-type transistor.

[0069] When a pixel PX includes an n-type transistor and a p-type transistor, the active pattern of the n-type transistor may include an oxide semiconductor material, and the active pattern of the p-type transistor may include a silicon semiconductor material. However, embodiments according to this disclosure are not limited thereto, and both the active patterns of the n-type transistor and the active patterns of the p-type transistor may include silicon semiconductor materials.

[0070] The pixel driving circuit PC can be connected to a first gate line GWL, a data line DL, a first voltage line VL1, and a second voltage line VL2. The first gate line GWL can transmit the first gate signal GW. The data line DL can transmit the data voltage VDATA. The first voltage line VL1 can transmit a first power voltage ELVDD with a relatively high voltage level. The second voltage line VL2 can transmit a second power voltage ELVSS with a relatively low voltage level.

[0071] The first transistor T1 may include a gate terminal, a first terminal, and a second terminal. According to some embodiments, the first terminal of the first transistor T1 may be the source, and the second terminal of the first transistor T1 may be the drain. The gate terminal of the first transistor T1 may be connected to a first node N1. The first terminal of the first transistor T1 may be connected to a second node N2. The second terminal of the first transistor T1 may be connected to a third node N3. The second terminal of the first transistor T1 may be connected to a light-emitting element LD. The first transistor T1 can provide a drive current ID to the light-emitting element LD.

[0072] The second transistor T2 may include a gate terminal, a first terminal, and a second terminal. According to some embodiments, the first terminal of the second transistor T2 may be the source, and the second terminal of the second transistor T2 may be the drain. However, embodiments according to this disclosure are not limited thereto, and the first terminal of the second transistor T2 may be the drain, and the second terminal of the second transistor T2 may be the source. The gate terminal of the second transistor T2 may be connected to a first gate line GWL. The first terminal of the second transistor T2 may be connected to a data line DL. The second terminal of the second transistor T2 may be connected to a first node N1.

[0073] The gate terminal of the second transistor T2 can receive the first gate signal GW through the first gate line GWL. The second transistor T2 can be turned on or off in response to the first gate signal GW. For example, when the second transistor T2 is an n-type transistor, it can be turned off when the first gate signal GW has a negative voltage level, and turned on when the first gate signal GW has a positive voltage level. Conversely, when the second transistor T2 is a p-type transistor, it can be turned off when the first gate signal GW has a positive voltage level, and turned on when the first gate signal GW has a negative voltage level. The first terminal of the second transistor T2 can receive the data voltage VDATA through the data line DL. When the second transistor T2 is turned on, it can provide the data voltage VDATA to the first node N1. Accordingly, the second transistor T2 can drive the first transistor T1.

[0074] The first capacitor C1 may include a first terminal and a second terminal. The first terminal of the first capacitor C1 may be connected to a first node N1. The second terminal of the first capacitor C1 may be connected to a second node N2. Current may be charged into or discharged from the first capacitor C1 according to the data voltage VDATA transmitted to the first node N1.

[0075] A light-emitting element (LD) may include an anode and a cathode. The anode of the LD may be connected to a first voltage line VL1. The cathode of the LD may be connected to a third node N3. For example, the cathode of the LD may be connected to the second terminal of a first transistor T1.

[0076] Figure 2B The illustration includes Figure 1A and Figure 1B A circuit diagram illustrating another example of the circuit structure of pixels in a display device. Although Figure 2B Various components in a pixel circuit according to some embodiments are illustrated, but the embodiments of this disclosure are not limited thereto, and the pixel circuit may include additional or fewer components without departing from the spirit and scope of the embodiments of this disclosure.

[0077] Reference above Figure 2A Compared to the embodiment of the circuit structure of the described pixel PX, the following reference... Figure 2B The pixel driving circuit PC' of some embodiments of the described pixel PX circuit structure may further include third to sixth transistors T3, T4, T5, and T6, and a second capacitor C2. Therefore, some redundant descriptions of certain components can be omitted or simplified.

[0078] refer to Figure 2B According to some embodiments, a pixel PX may include a light-emitting element LD and a pixel driving circuit PC' connected to the light-emitting element LD. According to some embodiments, the pixel driving circuit PC' may include a first transistor to a sixth transistor T1', T2, T3, T4, T5, and T6, a first capacitor C1, and a second capacitor C2. Figure 2B In the diagram, all of the first to sixth transistors T1', T2, T3, T4, T5, and T6 are illustrated as n-type transistors. However, embodiments of this disclosure are not limited thereto, and some of the first to sixth transistors T1', T2, T3, T4, T5, and T6 may be n-type transistors, while the others may be p-type transistors. For example, the first transistor T1' may be an n-type transistor, and some of the second to sixth transistors T2, T3, T4, T5, and T6 may be n-type transistors, while the others may be p-type transistors.

[0079] When a pixel PX includes an n-type transistor and a p-type transistor, the active pattern of the n-type transistor may include an oxide semiconductor material, and the active pattern of the p-type transistor may include a silicon semiconductor material. However, embodiments according to this disclosure are not limited thereto, and both the active patterns of the n-type transistor and the active patterns of the p-type transistor may include silicon semiconductor materials.

[0080] The pixel driving circuit PC' can be connected to the first to third gate lines GWL, GCL, and GRL, the data line DL, the first to fourth voltage lines VL1, VL2, VL3, and VL4, the first transmit control line ECL1, and the second transmit control line ECL2. The first gate line GWL can transmit the first gate signal GW. The second gate line GCL can transmit the second gate signal GC. The third gate line GRL can transmit the third gate signal GR. The data line DL can transmit the data voltage VDATA. The first voltage line VL1 can transmit a first power voltage ELVDD with a relatively high voltage level. The second voltage line VL2 can transmit a second power voltage ELVSS with a relatively low voltage level. The third voltage line VL3 can transmit a first initialization voltage Vcint. The fourth voltage line VL4 can transmit a reference voltage Vref. The reference voltage Vref can have a voltage level lower than the first power voltage ELVDD.

[0081] Apart from Figure 2B The first terminal of the first transistor T1' is connected to the second voltage line VL2 through the sixth transistor T6 and Figure 2B The second terminal of the first transistor T1' is connected to the light-emitting element LD via the fifth transistor T5. Figure 2B The first transistor T1' can be referenced above. Figure 2A The first transistor T1 described is the same (or substantially the same). Therefore, some redundant descriptions can be omitted or simplified. That is, the first transistor T1' of the pixel driving circuit PC' can be connected to the light-emitting element LD through the fifth transistor T5, and the driving current ID can be provided to the light-emitting element LD through the fifth transistor T5.

[0082] Figure 2B The second transistor T2 can be referenced above. Figure 2A The second transistor T2 described is the same (or substantially the same). Accordingly, Figure 2A The description of the second transistor T2 can be applied in the same way. Figure 2B The second transistor T2. That is, when the second transistor T2 is turned on, the second transistor T2 can drive the first transistor T1'.

[0083] The third transistor T3 may include a gate terminal, a first terminal, and a second terminal. According to some embodiments, the first terminal of the third transistor T3 may be the source, and the second terminal of the third transistor T3 may be the drain. However, embodiments according to this disclosure are not limited thereto, and the first terminal of the third transistor T3 may be the drain, and the second terminal of the third transistor T3 may be the source. The gate terminal of the third transistor T3 may be connected to a second gate line GCL. The first terminal of the third transistor T3 may be connected to a third node N3. The second terminal of the third transistor T3 may be connected to a third voltage line VL3.

[0084] The gate terminal of the third transistor T3 can receive the second gate signal GC through the second gate line GCL. The third transistor T3 can be turned on or off in response to the second gate signal GC. For example, when the third transistor T3 is an n-type transistor, it can be turned off when the second gate signal GC has a negative voltage level, and turned on when the second gate signal GC has a positive voltage level. Conversely, when the third transistor T3 is a p-type transistor, it can be turned off when the second gate signal GC has a positive voltage level, and turned on when the second gate signal GC has a negative voltage level. When the third transistor T3 is turned on, it can provide a first initialization voltage Vcint to the third node N3. For example, the third transistor T3 can initialize the cathode voltage by providing the first initialization voltage Vcint to the cathode of the light-emitting element LD.

[0085] The fourth transistor T4 may include a gate terminal, a first terminal, and a second terminal. According to some embodiments, the first terminal of the fourth transistor T4 may be the source, and the second terminal of the fourth transistor T4 may be the drain. However, embodiments according to this disclosure are not limited thereto, and the first terminal of the fourth transistor T4 may be the drain, and the second terminal of the fourth transistor T4 may be the source. The gate terminal of the fourth transistor T4 may be connected to a third gate line GRL. The first terminal of the fourth transistor T4 may be connected to a first node N1. The second terminal of the fourth transistor T4 may be connected to a fourth voltage line VL4.

[0086] The gate terminal of the fourth transistor T4 can receive the third gate signal GR through the third gate line GRL. The fourth transistor T4 can be turned on or off in response to the third gate signal GR. For example, when the fourth transistor T4 is an n-type transistor, it can be turned off when the third gate signal GR has a negative voltage level and turned on when the third gate signal GR has a positive voltage level. Conversely, when the fourth transistor T4 is a p-type transistor, it can be turned off when the third gate signal GR has a positive voltage level and turned on when the third gate signal GR has a negative voltage level. The second terminal of the fourth transistor T4 can receive the reference voltage Vref through the fourth voltage line VL4. When the fourth transistor T4 is turned on, it can provide the reference voltage Vref to the first node N1.

[0087] The fifth transistor T5 may include a gate terminal, a first terminal, and a second terminal. According to some embodiments, the first terminal of the fifth transistor T5 may be the source, and the second terminal of the fifth transistor T5 may be the drain. However, embodiments according to this disclosure are not limited thereto, and the first terminal of the fifth transistor T5 may be the drain, and the second terminal of the fifth transistor T5 may be the source. The gate terminal of the fifth transistor T5 may be connected to the first emitter control line ECL1. The first terminal of the fifth transistor T5 may be connected to the second terminal of the first transistor T1'. The second terminal of the fifth transistor T5 may be connected to the third node N3. The second terminal of the fifth transistor T5 may be connected to the light-emitting element LD.

[0088] The gate terminal of the fifth transistor T5 can receive the first transmit control signal EM1 via the first transmit control line ECL1. The fifth transistor T5 can be turned on or off in response to the first transmit control signal EM1. For example, when the fifth transistor T5 is an n-type transistor, it can be turned off when the first transmit control signal EM1 has a negative voltage level, and it can be turned on when the first transmit control signal EM1 has a positive voltage level. Conversely, when the fifth transistor T5 is a p-type transistor, it can be turned off when the first transmit control signal EM1 has a positive voltage level, and it can be turned on when the first transmit control signal EM1 has a negative voltage level. When the fifth transistor T5 is turned on, it can electrically connect the first transistor T1' and the light-emitting element LD. For example, the fifth transistor T5 can electrically connect the second terminal of the first transistor T1' and the cathode of the light-emitting element LD in response to the first transmit control signal EM1.

[0089] The sixth transistor T6 may include a gate terminal, a first terminal, and a second terminal. According to some embodiments, the first terminal of the sixth transistor T6 may be the source, and the second terminal of the sixth transistor T6 may be the drain. However, embodiments according to this disclosure are not limited thereto, and the first terminal of the sixth transistor T6 may be the drain, and the second terminal of the sixth transistor T6 may be the source. The gate terminal of the sixth transistor T6 may be connected to the second emitter control line ECL2. The first terminal of the sixth transistor T6 may be connected to the second voltage line VL2. The second terminal of the sixth transistor T6 may be connected to the second node N2.

[0090] The gate terminal of the sixth transistor T6 can receive the second transmit control signal EM2 via the second transmit control line ECL2. The sixth transistor T6 can be turned on or off in response to the second transmit control signal EM2. For example, when the sixth transistor T6 is an n-type transistor, it can be turned off when the second transmit control signal EM2 has a negative voltage level, and it can be turned on when the second transmit control signal EM2 has a positive voltage level. Conversely, when the sixth transistor T6 is a p-type transistor, it can be turned off when the second transmit control signal EM2 has a positive voltage level, and it can be turned on when the second transmit control signal EM2 has a negative voltage level. The first terminal of the sixth transistor T6 can receive the second power voltage ELVSS via the second voltage line VL2. When the sixth transistor T6 is turned on, it can supply the second power voltage ELVSS to the second node N2.

[0091] although Figure 2B The illustration shows that the fifth transistor T5 and the sixth transistor T6 are driven independently by different transmit control signals, but embodiments according to this disclosure are not limited thereto. For example, the first transmit control signal EM1 and the second transmit control signal EM2 can be provided as a single transmit control signal, and the fifth transistor T5 and the sixth transistor T6 can be simultaneously turned on or off. In this case, the first transmit control line ECL1 and the second transmit control line ECL2 can be provided as a single transmit control line.

[0092] Figure 2B The first capacitor C1 can be referenced above. Figure 2A The first capacitor C1 described is the same (or substantially the same). Accordingly, Figure 2A The description of the first capacitor C1 can be applied in the same way. Figure 2B The first capacitor C1. That is, according to the data voltage VDATA transmitted to the first node N1, current can be charged into or discharged from the first capacitor C1.

[0093] The second capacitor C2 may include a first terminal and a second terminal. The first terminal of the second capacitor C2 may be connected to the second node N2. The second terminal of the second capacitor C2 may be connected to the second voltage line VL2. For example, the second capacitor C2 may be connected in series with the first capacitor C1. The data voltage VDATA may be transmitted to the first node N1 and may be divided due to the series connection between the first capacitor C1 and the second capacitor C2, so that the divided data voltage VDATA may be transmitted to the second node N2. Because the first transistor T1' generates a drive current ID based on the voltage of the first node N1 and the voltage of the second node N2, the data range can be extended.

[0094] In addition to the cathode being connected to the first terminal of the third transistor T3 and to the second terminal of the first transistor T1' via the fifth transistor T5, Figure 2B The light-emitting element LD can be compared with the above reference. Figure 2A The light-emitting element LD described is the same (or substantially the same). Therefore, some redundant descriptions can be omitted or simplified. That is, the cathode of the light-emitting element LD can be connected to the second terminal of the first transistor T1' via the fifth transistor T5. In addition, the cathode of the light-emitting element LD can receive the first initialization voltage Vcint via the third transistor T3.

[0095] Figure 2C The illustration includes Figure 1A and Figure 1B A circuit diagram illustrating yet another example of the circuit structure of pixels in a display device.

[0096] Reference above Figure 2B Compared to the embodiment of the circuit structure of the described pixel PX, the following reference... Figure 2C The pixel driving circuit "PC" of some embodiments of the described pixel PX circuit structure may further include a seventh transistor T7 and an eighth transistor T8. Therefore, some redundant descriptions of some components can be omitted or simplified.

[0097] refer to Figure 2C According to some embodiments, a pixel PX may include a light-emitting element LD and a pixel driving circuit PC connected to the light-emitting element LD. According to some embodiments, the pixel driving circuit PC may include a first transistor to an eighth transistor T1', T2, T3, T4, T5, T6, T7, and T8, a first capacitor C1, and a second capacitor C2. Figure 2CIn the diagram, all of the first to eighth transistors T1', T2, T3, T4, T5, T6, T7, and T8 are illustrated as n-type transistors. However, embodiments according to this disclosure are not limited thereto, and some of the first to eighth transistors T1', T2, T3, T4, T5, T6, T7, and T8 may be n-type transistors, while others may be p-type transistors. For example, the first transistor T1' may be an n-type transistor, and some of the second to eighth transistors T2, T3, T4, T5, T6, T7, and T8 may be n-type transistors, while others may be p-type transistors.

[0098] When a pixel PX includes an n-type transistor and a p-type transistor, the active pattern of the n-type transistor may include an oxide semiconductor material, and the active pattern of the p-type transistor may include a silicon semiconductor material. However, embodiments according to this disclosure are not limited thereto, and both the active patterns of the n-type transistor and the active patterns of the p-type transistor may include silicon semiconductor materials.

[0099] The pixel driving circuit "PC" can be connected to the first to fourth gate lines GWL, GCL, GRL, and GIL, the data line DL, the first to fifth voltage lines VL1, VL2, VL3, VL4, and VL5, and the transmit control line ECL. The first gate line GWL can transmit the first gate signal GW. The second gate line GCL can transmit the second gate signal GC. The third gate line GRL can transmit the third gate signal GR. The fourth gate line GIL can transmit the fourth gate signal GI. The data line DL can transmit the data voltage VDATA. The first voltage line VL1 can transmit a first power voltage ELVDD with a relatively high voltage level. The second voltage line VL2 can transmit a second power voltage ELVSS with a relatively low voltage level. The third voltage line VL3 can transmit the first initialization voltage Vcint. The fourth voltage line VL4 can transmit a reference voltage Vref. The reference voltage Vref can have a voltage level lower than the first power voltage ELVDD. The fifth voltage line VL5 can transmit a second initialization voltage Vint. The first initialization voltage Vcint and the second initialization voltage Vint can have different voltage levels than each other.

[0100] Figure 2C The first to sixth transistors T1', T2, T3, T4, T5, and T6, the first capacitor C1, and the second capacitor C2 can be respectively connected to the reference above. Figure 2B The first to sixth transistors T1', T2, T3, T4, T5, and T6, the first capacitor C1, and the second capacitor C2 are described as being the same (or substantially the same). Accordingly, Figure 2BThe descriptions of the first to sixth transistors T1', T2, T3, T4, T5 and T6, the first capacitor C1 and the second capacitor C2 can be applied in the same way. Figure 2C The first to sixth transistors T1', T2, T3, T4, T5 and T6, the first capacitor C1 and the second capacitor C2. Therefore, some redundant descriptions can be omitted.

[0101] although Figure 2C The illustration shows that the fifth transistor T5 and the sixth transistor T6 are simultaneously driven by the emitter control signal EM, but embodiments according to this disclosure are not limited thereto. For example, as Figure 2B As in the example, the fifth transistor T5 and the sixth transistor T6 can be controlled by different emitter control signals (e.g., Figure 2B The first transmit control signal EM1 and the second transmit control signal EM2 are driven independently. In this case, the transmit control line connected to the fifth transistor T5 and the transmit control line connected to the sixth transistor T6 can be different transmit control lines from each other (e.g., Figure 2B The first launch control line (ECL1) and the second launch control line (ECL2).

[0102] The seventh transistor T7 may include a gate terminal, a first terminal, and a second terminal. According to some embodiments, the first terminal of the seventh transistor T7 may be the source, and the second terminal of the seventh transistor T7 may be the drain. However, embodiments according to this disclosure are not limited thereto, and the first terminal of the seventh transistor T7 may be the drain, and the second terminal of the seventh transistor T7 may be the source. The gate terminal of the seventh transistor T7 may be connected to a second gate line GCL. The first terminal of the seventh transistor T7 may be connected to a fourth node N4. The second terminal of the seventh transistor T7 may be connected to a third voltage line VL3.

[0103] The gate terminal of the seventh transistor T7 can receive the second gate signal GC via the second gate line GCL. The seventh transistor T7 can be turned on or off in response to the second gate signal GC. For example, when the seventh transistor T7 is an n-type transistor, it can be turned off when the second gate signal GC has a negative voltage level, and it can be turned on when the second gate signal GC has a positive voltage level. Conversely, when the seventh transistor T7 is a p-type transistor, it can be turned off when the second gate signal GC has a positive voltage level, and it can be turned on when the second gate signal GC has a negative voltage level. The second terminal of the seventh transistor T7 can receive the first initialization voltage Vcint via the third voltage line VL3. When the seventh transistor T7 is turned on, it can provide the first initialization voltage Vcint to the fourth node N4. For example, the seventh transistor T7 can compensate for the threshold voltage (Vth) of the first transistor T1' by providing the first initialization voltage Vcint to the fourth node N4.

[0104] although Figure 2C The illustration shows that the gate line connected to the third transistor T3 and the gate line connected to the seventh transistor T7 are provided as a single gate line (i.e., a second gate line GCL), but embodiments according to this disclosure are not limited thereto. For example, the gate line connected to the third transistor T3 and the gate line connected to the seventh transistor T7 may be different gate lines from each other.

[0105] In addition, although Figure 2C The illustration shows that the third transistor T3 and the seventh transistor T7 are simultaneously driven by the second gate signal GC, but embodiments according to this disclosure are not limited to this. For example, the third transistor T3 and the seventh transistor T7 can be driven independently by different gate signals. In this case, the gate lines connected to the third transistor T3 and the gate lines connected to the seventh transistor T7 can be different gate lines from each other.

[0106] The eighth transistor T8 may include a gate terminal, a first terminal, and a second terminal. According to some embodiments, the first terminal of the eighth transistor T8 may be the source, and the second terminal of the eighth transistor T8 may be the drain. However, embodiments according to this disclosure are not limited thereto, and the first terminal of the eighth transistor T8 may be the drain, and the second terminal of the eighth transistor T8 may be the source. The gate terminal of the eighth transistor T8 may be connected to a fourth gate line GIL. The first terminal of the eighth transistor T8 may be connected to a second node N2. The second terminal of the eighth transistor T8 may be connected to a fifth voltage line VL5.

[0107] The gate terminal of the eighth transistor T8 can receive the fourth gate signal GI via the fourth gate line GIL. The eighth transistor T8 can be turned on or off in response to the fourth gate signal GI. For example, when the eighth transistor T8 is an n-type transistor, it can be turned off when the fourth gate signal GI has a negative voltage level, and it can be turned on when the fourth gate signal GI has a positive voltage level. Conversely, when the eighth transistor T8 is a p-type transistor, it can be turned off when the fourth gate signal GI has a positive voltage level, and it can be turned on when the fourth gate signal GI has a negative voltage level. The second terminal of the eighth transistor T8 can receive the second initialization voltage Vint via the fifth voltage line VL5. When the eighth transistor T8 is turned on, it can provide the second initialization voltage Vint to the second node N2.

[0108] Figure 2C The light-emitting element LD can be compared with the above reference. Figure 2B The described light-emitting elements (LDs) are the same (or substantially the same). Accordingly, Figure 2B The description of the light-emitting element LD can be applied in the same way. Figure 2C The light-emitting element is an LD. Therefore, some redundant descriptions can be omitted.

[0109] like Figure 2A , Figure 2B and Figure 2C As shown, according to some embodiments, the anode of the light-emitting element LD can receive a first power voltage ELVDD through the first voltage line VL1, and the cathode of the light-emitting element LD can be connected to the second terminal of the first transistor T1 (or T1'). That is, the potential of the cathode of the light-emitting element LD can be controlled by electrically connecting it to the first transistor T1 (or T1').

[0110] Because the first voltage line VL1 provides a first power voltage ELVDD with a relatively high voltage level and the second voltage line VL2 provides a second power voltage ELVSS with a relatively low voltage level, when the first transistor T1 (or T1') is an n-type transistor, the second terminal of the first transistor T1 (or T1') can be the drain. That is, according to some embodiments, the cathode of the light-emitting element LD can be connected to the drain of the first transistor T1 (or T1').

[0111] When the first transistor T1 (or T1') is an n-type transistor, if the anode of the light-emitting element LD is connected to the source of the first transistor T1 (or T1'), the source voltage of the first transistor T1 (or T1') may shift due to the degradation of the light-emitting element LD, causing the gate-source voltage (Vgs) of the first transistor T1 (or T1') to change. As a result, the range of variation of the drive current ID may increase, potentially leading to afterimage defects and possibly shortening the lifespan of the display device.

[0112] According to some embodiments, the anode of the light-emitting element LD can receive a first power voltage ELVDD, and the cathode of the light-emitting element LD can be connected to the drain of the first transistor T1 (or T1'). Accordingly, even when the light-emitting element LD deteriorates, the gate-source voltage (Vgs) of the first transistor T1 (or T1') can remain unchanged. Consequently, the range of variation in the drive current ID due to the deterioration of the light-emitting element LD can be relatively reduced. Therefore, the afterimage defects of the display device DD that depend on the increase in usage time can be relatively reduced, and the lifespan of the display device DD can be relatively improved.

[0113] at the same time, Figure 2A , Figure 2B and Figure 2C The circuit structure of the pixel PX illustrated in the figure (e.g., the number or arrangement of transistors, the number or arrangement of capacitors) is merely an example and can be modified in various ways according to some embodiments.

[0114] Figure 3 It is a diagram. Figure 1A and Figure 1B A floor plan of a portion of the display device area. Figure 4 It is a diagram. Figure 3 An enlarged plan view of one of the unit emission regions in the unit emission region. Figure 5 It is along Figure 4 The cross-sectional view taken from line I-I'. Figure 6 yes Figure 5 Enlarged cross-sectional view of region A.

[0115] For example, Figure 3 The diagram shows four cell transmission areas, UEA1 and UEA2, arranged in a two-row, two-column matrix. Figure 4 The illustration shows an enlarged view of the first transmission area, UEA1, among the transmission areas UEA1 and UEA2. For ease of description, in... Figure 3 and Figure 4 Omission or emphasis Figure 5 Some of the components shown in the diagram.

[0116] refer to Figure 3 and Figure 4The display device DD may include first pixel driving circuits to third pixel driving circuits PCa, PCb, and PCc, first light-emitting elements to third light-emitting elements LDa, LDb, and LDc, first connecting electrodes to third connecting electrodes CEa, CEb, and CEc, first connecting structures to third connecting structures CNGa, CNGb, and CNGc, and a separator SPR. The first connecting structure CNGa may include a first connecting pattern CNPa and a first additional connecting pattern ADPa. The second connecting structure CNGb may include a second connecting pattern CNPb and a second additional connecting pattern ADPb. The third connecting structure CNGc may include a third connecting pattern CNPc and a third additional connecting pattern ADPc.

[0117] Each of the first pixel driving circuit to the third pixel driving circuits PCa, PCb, and PCc can be referenced above. Figure 2A , Figure 2B and Figure 2C At least one of the described pixel driving circuits PC, PC', and PC' corresponds to this. That is, each of the first to third pixel driving circuits PCa, PCb, and PCc may include at least one transistor and at least one capacitor. For example, each of the first to third pixel driving circuits PCa, PCb, and PCc may include... Figure 5 The diagram shows the first transistor TR1, the second transistor TR2, the first capacitor CAP1, and the second capacitor CAP2.

[0118] in this case, Figure 5 The first transistor TR1 can be a transistor connected to the light-emitting element via connecting electrodes and connecting patterns. For example, when each of the first pixel driving circuit to the third pixel driving circuits PCa, PCb, and PCc is... Figure 2A When the pixel driving circuit PC is used, the first transistor TR1 can be Figure 2A The first transistor T1, and the second transistor TR2 can be Figure 2A The second transistor T2. Additionally, when each of the first pixel driving circuit to the third pixel driving circuits PCa, PCb, and PCc is... Figure 2B When the pixel driving circuit PC' is in operation, the first transistor TR1 can be... Figure 2B The fifth transistor T5, and the second transistor TR2 can be Figure 2B One of the first transistor T1', the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6. Additionally, when each of the first pixel driving circuit to the third pixel driving circuit PCa, PCb, and PCc is... Figure 2C When the pixel driving circuit PC is in use, the first transistor TR1 can be Figure 2CThe fifth transistor T5, and the second transistor TR2 can be Figure 2C The transistor is one of the first transistor T1', the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. However, embodiments according to this disclosure are not limited thereto.

[0119] According to some embodiments, Figure 5 The first capacitor CAP1 can be with Figure 2A , Figure 2B and Figure 2C The first capacitor C1 corresponds to, and Figure 5 The second capacitor CAP2 can be connected with Figure 2B and Figure 2C The second capacitor C2 corresponds to this. That is, when each of the first pixel driving circuit to the third pixel driving circuits PCa, PCb, and PCc is... Figure 2A When using the pixel driving circuit PC, the second capacitor CAP2 can be omitted. However, embodiments according to this disclosure are not limited thereto, and according to some embodiments, Figure 5 The first capacitor CAP1 can be with Figure 2B and Figure 2C The second capacitor C2 corresponds to, and Figure 5 The second capacitor CAP2 can be connected with Figure 2A , Figure 2B and Figure 2C The first capacitor C1 corresponds to this. In this case, when each of the first pixel driving circuit to the third pixel driving circuits PCa, PCb and PCc is... Figure 2A When using the pixel driving circuit PC, the first capacitor CAP1 can be omitted.

[0120] Please refer to later Figure 5 The first transistor TR1, the second transistor TR2, the first capacitor CAP1, and the second capacitor CAP2 are described in more detail.

[0121] Figure 3 and Figure 4 The illustration shows that the first pixel driving circuit to the third pixel driving circuits PCa, PCb, and PCc each have a rectangular shape and are arranged sequentially along the first direction DR1. However, embodiments according to this disclosure are not limited thereto, and according to some embodiments, the shape and arrangement of the first pixel driving circuit to the third pixel driving circuits PCa, PCb, and PCc can be varied.

[0122] Each of the first to third light-emitting elements LDa, LDb, and LDc can be referenced above. Figure 2A , Figure 2B and Figure 2CThe light-emitting element LD is described. For example, the first to third light-emitting elements LDa, LDb, and LDc may include a first electrode (e.g., Figure 5 The first electrode E1), and the intermediate layer located on the first electrode (e.g., Figure 5 The intermediate layer ML) and the electrode layer located on the intermediate layer (e.g., Figure 5 (Electrode layer E2L). According to some embodiments, the first electrode can serve as... Figure 2A , Figure 2B and Figure 2C The anode acts as a conductor, and the electrode layer can serve as... Figure 2A , Figure 2B and Figure 2C The role of the cathode.

[0123] According to some embodiments, the electrode layer can be separated (or disconnected) by the separator SPR into a plurality of second electrodes. For example, the electrode layer can be separated (or disconnected) into a second electrode of the first light-emitting element LTa (e.g., Figure 5 The second electrode (E2), the second electrode of the second light-emitting element (LDb), and the second electrode of the third light-emitting element (LDc) will be described in more detail later.

[0124] The first to third light-emitting elements LDa, LDb, and LDc can be connected to the first to third pixel driving circuits PCa, PCb, and PCc, respectively. For example, the first light-emitting element LDa can be connected to the first pixel driving circuit PCa, the second light-emitting element LDb can be connected to the second pixel driving circuit PCb, and the third light-emitting element LDc can be connected to the third pixel driving circuit PCc. Accordingly, the first pixel driving circuit PCa and the first light-emitting element LDa can form a pixel, the second pixel driving circuit PCb and the second light-emitting element LDb can form a pixel, and the third pixel driving circuit PCc and the third light-emitting element LDc can form a pixel.

[0125] The first to third light-emitting elements LDa, LDb, and LDc can emit light of different colors. For example, the first light-emitting element LDa can emit red light, the second light-emitting element LDb can emit green light, and the third light-emitting element LDc can emit blue light. However, the embodiments according to this disclosure are not limited thereto.

[0126] According to some embodiments, the display device DD may include a first unit transmitting area UEA1 and a second unit transmitting area UEA2. The first unit transmitting area UEA1 and the second unit transmitting area UEA2 may be defined in a matrix form along a first direction DR1 and a second direction DR2. Although Figure 3 Only four unit emission areas are shown, but the entire display area DA (see diagram) is possible. Figure 1A and Figure 1B Multiple cell emission regions are defined in a matrix form along the first direction DR1 and the second direction DR2.

[0127] The first to third light-emitting elements LDa, LDb, and LDc that are adjacent to each other can be located in each of the first unit emission region UEA1 and the second unit emission region UEA2. For example, the first to third emission regions EAa, EAb, and EAc that are adjacent to each other can be defined in each of the first unit emission region UEA1 and the second unit emission region UEA2, and the first to third light-emitting elements LDa, LDb, and LDc can be located in the first to third emission regions EAa, EAb, and EAc, respectively.

[0128] The first to third emission regions EAa, EAb, and EAC can be defined by a pixel-defined layer PDL as described below (see Figure 5 The pixel aperture is defined by the first to third emission regions EAa, EAb, and EAc. That is, each of these regions can be a region that emits light from the light-emitting element. For example, the first light-emitting element LDa can be located in the first emission region EAa, and the first emission region EAa can be a region that emits light from the first light-emitting element LDa. Similarly, the second light-emitting element LDb can be located in the second emission region EAb, and the second emission region EAb can be a region that emits light from the second light-emitting element LDb. Furthermore, the third light-emitting element LDc can be located in the third emission region EAc, and the third emission region EAc can be a region that emits light from the third light-emitting element LDc.

[0129] According to some embodiments, the first unit emission area UEA1 and the second unit emission area UEA2 can be distinguished based on the arrangement relationship between the first light-emitting element and the third light-emitting element LDa, LDb, and LDc (or the arrangement relationship between the first emission area and the third emission area EAa, EAb, and EAc). That is, for each first unit emission area UEA1, the arrangement relationship between the first light-emitting element and the third light-emitting element LDa, LDb, and LDc (or the arrangement relationship between the first emission area and the third emission area EAa, EAb, and EAc) can be the same, and for each second unit emission area UEA2, the arrangement relationship between the first light-emitting element and the third light-emitting element LDa, LDb, and LDc (or the arrangement relationship between the first emission area and the third emission area EAa, EAb, and EAc) can be the same.

[0130] According to some embodiments, such as Figure 3As shown, the first unit transmission area UEA1 and the second unit transmission area UEA2 can be arranged alternately along the first direction DR1 (i.e., the row direction) and the second direction DR2 (i.e., the column direction). However, the embodiments according to this disclosure are not limited thereto, and according to some embodiments, the number of different unit transmission areas included in the display device DD or the arrangement relationship between the unit transmission areas can be changed in various ways.

[0131] Figure 3 and Figure 4 The illustration shows the first to third transmission zones EAa, EAb, and EAc arranged in an S-striped structure. However, embodiments according to this disclosure are not limited to this, and according to some embodiments, the arrangement of the first to third transmission zones EAa, EAb, and EAc can be modified in various ways.

[0132] In the following text, it will be referred to as Figure 4 The connection relationships between the first to third light-emitting elements LDa, LDb, and LDc and the first to third pixel driving circuits PCa, PCb, and PCc are described in more detail, centered on the first unit emission area UEA1. The following description of the connection relationships between the first to third light-emitting elements LDa, LDb, and LDc and the first to third pixel driving circuits PCa, PCb, and PCc can be applied in the same (or substantially the same) manner to all unit emission areas.

[0133] As described above, the display device DD may include first connecting electrodes to third connecting electrodes CEa, CEb, and CEc, and first connecting structures to third connecting structures GNGa, GNGb, and GNGc. The first connecting structure CNGa may include a first connecting pattern CNPa and a first additional connecting pattern ADPa. The second connecting structure CNGb may include a second connecting pattern CNPb and a second additional connecting pattern ADPb. The third connecting structure CNGc may include a third connecting pattern CNPc and a third additional connecting pattern ADPc.

[0134] The first connecting electrode CEa and the first connecting pattern CNPa can electrically connect the first light-emitting element LDa and the first pixel driving circuit PCa. The second connecting electrode CEb and the second connecting pattern CNPb can electrically connect the second light-emitting element LDb and the second pixel driving circuit PCb. The third connecting electrode CEc and the third connecting pattern CNPc can electrically connect the third light-emitting element LDc and the third pixel driving circuit PCc.

[0135] The first to third connecting electrodes CEa, CEb, and CEc can comprise conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides. Examples of conductive materials that can be used as the first to third connecting electrodes CEa, CEb, and CEc include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), alloys containing Al, alloys containing Ag, alloys containing Cu, alloys containing Mo, and aluminum nitride (Al). x N y ), Tungsten nitride (W x N y ), titanium nitride (Ti x N y ), chromium nitride (Cr x N y ), tantalum nitride (Ta x N y Materials such as tin oxide (SnO), gallium oxide (GaO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), zinc oxide (ZnO), indium oxide (InO), or aluminum zinc oxide (AZO) are used. These can be used individually or in combination with each other. According to some embodiments, each of the first to third connecting electrodes CEa, CEb, and CEc can have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked.

[0136] According to some embodiments, the first to third connection patterns CNPa, CNPb, and CNPc may comprise transparent conductive oxides. Examples of transparent conductive oxides that can be used as the first to third connection patterns CNPa, CNPb, and CNPc may include indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), zinc oxide (ZnO), indium oxide (InO), or aluminum zinc oxide (AZO), etc. These may be used individually or in combination with each other.

[0137] According to some embodiments, the first to third connection patterns CNPa, CNPb, and CNPc may include conductive materials such as metals, alloys, or conductive metal nitrides. Examples of conductive materials that can be used as the first to third connection patterns CNPa, CNPb, and CNPc may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), Al-containing alloys, Ag-containing alloys, Cu-containing alloys, Mo-containing alloys, and aluminum nitride (Al). x N y ), Tungsten nitride (W x N y ), titanium nitride (Ti x N y ), chromium nitride (Cr x N y ) or tantalum nitride (Ta x N y These can be used individually or in combination with each other.

[0138] According to some embodiments, each of the first to third connection patterns CNPa, CNPb and CNPc may have a single-layer structure or a multi-layer structure in which multiple conductive layers are stacked.

[0139] According to some embodiments, the first to third additional connection patterns ADPa, ADPb, and ADPc may comprise transparent conductive oxides. However, embodiments according to this disclosure are not limited thereto, and the first to third additional connection patterns ADPa, ADPb, and ADPc may comprise conductive materials such as metals, alloys, or conductive metal nitrides.

[0140] According to some embodiments, each of the first to third additional connection patterns ADPa, ADPb and ADPc may have a single-layer structure or a multi-layer structure in which multiple conductive layers are stacked.

[0141] According to some embodiments, the first to third additional connecting patterns ADPa, ADPb, and ADPc may comprise the same material as the first to third connecting patterns CNPa, CNPb, and CNPc. The first to third additional connecting patterns ADPa, ADPb, and ADPc may be integrally formed with the first to third connecting patterns CNPa, CNPb, and CNPc.

[0142] The first connecting electrode CEa may include a first circuit connecting portion CPa and a first light-emitting connecting portion CNa.

[0143] The first circuit connection portion CPa can be the part of the first connection electrode CEa that is connected to the first pixel driving circuit PCa. For example, the first circuit connection portion CPa can be the first transistor TR1 of the first connection electrode CEa that is connected to the first pixel driving circuit PCa (see...). Figure 5 The location of the first circuit connection portion CPa can correspond to the location of the first transistor TR1 of the first pixel driving circuit PCa. For example, the location of the first circuit connection portion CPa can be such that the first transistor TR1 of the first pixel driving circuit PCa is exposed and penetrates the fifth insulating layer IL5 (see...). Figure 5 Contact holes CNT (see) Figure 5 The position corresponds to the location of ).

[0144] The first light-emitting connection portion CNa can be the portion of the first connection electrode CEa that is connected to the first connection pattern CNPa. For example, the first light-emitting connection portion CNa can be the portion of the first connection electrode CEa that is covered by the sixth insulating layer IL6 (see...). Figure 5 ) and pixel confinement layer PDL (see Figure 5 The portion of the first light-emitting connection portion CNa is exposed to connect to the first connection pattern CNa. Accordingly, the position of the first light-emitting connection portion CNa can be aligned with the opening OP that exposes the first connection electrode CEa and penetrates the pixel defining layer and the sixth insulating layer (see [link to image]). Figure 5 The positions of the first light-emitting connection portion CNa and the first emitting region EAa are corresponding. In the plan view, the first light-emitting connection portion CNa may not overlap with the first emitting region EAa. For example, in the plan view, the first light-emitting connection portion CNa may be located between the first emitting region EAa and the separator SPR.

[0145] The first connection pattern CNPa can be connected to the first connection electrode CEa. For example, the first connection pattern CNPa can contact the first light-emitting connection portion CNa of the first connection electrode CEa. However, embodiments according to this disclosure are not limited thereto, and the first connection pattern CNPa may not directly contact the first connection electrode CEa. For example, the first connection pattern CNPa can contact the capping layer (which contacts the first light-emitting connection portion CNa of the first connection electrode CEa), and can be connected to the first light-emitting connection portion CNa of the first connection electrode CEa through the capping layer. The capping layer may include a conductive material. For example, the capping layer may be connected to the first electrode E1 (see... Figure 5 They are formed simultaneously (or substantially simultaneously) and may include the same material as the first electrode.

[0146] In a plan view, the first connection pattern CNPa may not overlap with the first emitter region EAa. According to some embodiments, in a plan view, the first connection pattern CNPa may surround at least a portion of the first emitter region EAa. For example, in a plan view, the first connection pattern CNPa may have a closed-loop shape that completely surrounds the first emitter region EAa. However, embodiments according to this disclosure are not limited thereto.

[0147] The second electrode E2 of the first light-emitting element LDa (see...) Figure 5 The first light-emitting element LDa can be connected to the first connection pattern CNPa. For example, the second electrode of the first light-emitting element LDa can contact the first connection pattern CNPa. Accordingly, the first connection pattern CNPa can electrically connect the first connection electrode CEa and the second electrode of the first light-emitting element LDa. As a result, the second electrode of the first light-emitting element LDa can be electrically connected to the first pixel driving circuit PCa through the first connection electrode CEa and the first connection pattern CNPa.

[0148] According to some embodiments, in a planar view, the outline of the area where the second electrode of the first light-emitting element LDa and the first connecting pattern CNPa contact each other can be the same (or substantially the same) or similar to the outline of the edge of the first connecting pattern CNPa. For example, when the first connecting pattern CNPa has a closed-loop shape that completely surrounds the first emitting region EAa in a planar view, the area where the second electrode of the first light-emitting element LDa and the first connecting pattern CNPa contact each other can also have a closed-loop shape in a planar view. That is, the second electrode of the first light-emitting element LDa and the first connecting pattern CNPa can contact each other at a location that does not overlap with the first emitting region EAa. Accordingly, the second electrode of the first light-emitting element LDa and the first pixel driving circuit PCa can be electrically connected to each other through the first connecting pattern CNPa and the first connecting electrode CEa without reducing the size (i.e., aperture ratio) of the first emitting region EAa.

[0149] The first additional connecting pattern ADPa may extend from the first connecting pattern CNPa. The first additional connecting pattern ADPa may contact the first connecting pattern CNPa. According to some embodiments, the first additional connecting pattern ADPa may comprise the same material as the first connecting pattern CNPa and may be integrally formed with the first connecting pattern CNPa.

[0150] In a plan view, the first additional connection pattern ADPa may not overlap with the first emitter region EAa. According to some embodiments, in a plan view, the first additional connection pattern ADPa may surround at least a portion of the first emitter region EAa. For example, in a plan view, the first additional connection pattern ADPa may have a closed-loop shape that completely surrounds the first emitter region EAa. However, embodiments according to this disclosure are not limited thereto.

[0151] In a plan view, the first additional connection pattern ADPa may be located between the first connection pattern CNPa and the first emission region EAa. According to some embodiments, in a plan view, the first connection pattern CNPa may surround at least a portion of the first additional connection pattern ADPa. For example, in a plan view, the first connection pattern CNPa may have a closed-loop shape that completely surrounds the first additional connection pattern ADPa. However, embodiments according to this disclosure are not limited thereto.

[0152] The second connecting electrode CEb may include a second circuit connecting portion CPb and a second light-emitting connecting portion CNb.

[0153] The second circuit connection portion CPb can be the part of the second connection electrode CEb that connects to the second pixel driving circuit PCb. For example, the second circuit connection portion CPb can be the first transistor TR1 of the second connection electrode CEb that connects to the second pixel driving circuit PCb (see...). Figure 5 The location of the second circuit connection portion CPb can correspond to the location of the first transistor of the second pixel driving circuit PCb. For example, the location of the second circuit connection portion CPb can be such that it exposes the first transistor of the second pixel driving circuit PCb and penetrates the fifth insulating layer IL5 (see...). Figure 5 The positions of the contact holes correspond to those of the contacts.

[0154] The second light-emitting connection portion CNb can be the portion of the second connection electrode CEb that connects to the second connection pattern CNPb. For example, the second light-emitting connection portion CNb can be the portion of the second connection electrode CEb that is covered by the sixth insulating layer IL6 (see...). Figure 5 ) and pixel confinement layer PDL (see Figure 5 The portion of the second light-emitting connection portion CNb is exposed to connect to the second connection pattern CNPb. Accordingly, the position of the second light-emitting connection portion CNb can correspond to the position of the opening that exposes the second connection electrode CEb and penetrates the pixel defining layer and the sixth insulating layer. In a plan view, the second light-emitting connection portion CNb may not overlap with the second emitting region EAb. For example, the second light-emitting connection portion CNb may be located between the second emitting region EAb and the separator SPR.

[0155] According to some embodiments, in a plan view, the second connecting electrode CEb may be spaced apart from the first connecting electrode CEa. In other words, the first connecting electrode CEa and the second connecting electrode CEb may be different electrodes from each other.

[0156] The second connection pattern CNPb can be connected to the second connection electrode CEb. For example, the second connection pattern CNPb can contact the second light-emitting connection portion CNb of the second connection electrode CEb. However, embodiments according to this disclosure are not limited thereto, and the second connection pattern CNPb may not directly contact the second connection electrode CEb. For example, the second connection pattern CNPb can contact the capping layer (which contacts the second light-emitting connection portion CNb of the second connection electrode CEb), and can be connected to the second light-emitting connection portion CNb of the second connection electrode CEb through the capping layer. The capping layer may include a conductive material. For example, the capping layer may be connected to the first electrode E1 (see... Figure 5 They are formed simultaneously (or substantially simultaneously) and may include the same material as the first electrode.

[0157] In a plan view, the second connection pattern CNPb may not overlap with the second emitter region EAb. According to some embodiments, in a plan view, the second connection pattern CNPb may surround at least a portion of the second emitter region EAb. For example, in a plan view, the second connection pattern CNPb may have a closed-loop shape that completely surrounds the second emitter region EAb. However, embodiments according to this disclosure are not limited thereto.

[0158] According to some embodiments, in a plan view, the second connection pattern CNPb may be spaced apart from the first connection pattern CNPa. In other words, the first connection pattern CNPa and the second connection pattern CNPb may be different patterns from each other.

[0159] The second electrode of the second light-emitting element LDb can be connected to the second connection pattern CNPb. For example, the second electrode of the second light-emitting element LDb can contact the second connection pattern CNPb. Accordingly, the second connection pattern CNPb can electrically connect the second connection electrode CEb and the second electrode of the second light-emitting element LDb. As a result, the second electrode of the second light-emitting element LDb can be electrically connected to the second pixel driving circuit PCb through the second connection electrode CEb and the second connection pattern CNPb.

[0160] According to some embodiments, in a planar view, the outline of the area where the second electrode of the second light-emitting element LDb and the second connection pattern CNPb contact each other can be the same as (or substantially the same as) or similar to the outline of the edge of the second connection pattern CNPb. For example, when the second connection pattern CNPb has a closed-loop shape that completely surrounds the second emission region EAb in the planar view, the area where the second electrode of the second light-emitting element LDb and the second connection pattern CNPb contact each other can have a closed-loop shape in the planar view. That is, the second electrode of the second light-emitting element LDb and the second connection pattern CNPb can contact each other at a location that does not overlap with the second emission region EAb. Accordingly, the second electrode of the second light-emitting element LDb and the second pixel driving circuit PCb can be electrically connected to each other through the second connection pattern CNPb and the second connection electrode CEb without reducing the size (i.e., aperture ratio) of the second emission region EAb.

[0161] The second additional connecting pattern ADPb may extend from the second connecting pattern CNPb. The second additional connecting pattern ADPb may contact the second connecting pattern CNPb. According to some embodiments, the second additional connecting pattern ADPb may comprise the same material as the second connecting pattern CNPb and may be integrally formed with the second connecting pattern CNPb.

[0162] In a plan view, the second additional connection pattern ADPb may not overlap with the second transmit region EAb. According to some embodiments, in a plan view, the second additional connection pattern ADPb may surround at least a portion of the second transmit region EAb. For example, in a plan view, the second additional connection pattern ADPb may have a closed-loop shape that completely surrounds the second transmit region EAb. However, embodiments according to this disclosure are not limited thereto.

[0163] In a plan view, the second additional connection pattern ADPb may be located between the second connection pattern CNPb and the second emitter region EAb. According to some embodiments, in a plan view, the second connection pattern CNPb may surround at least a portion of the second additional connection pattern ADPb. For example, in a plan view, the second connection pattern CNPb may have a closed-loop shape that completely surrounds the second additional connection pattern ADPb. However, embodiments according to this disclosure are not limited thereto.

[0164] According to some embodiments, in a plan view, the second additional connection pattern ADPb may be spaced apart from the first additional connection pattern ADPa. In other words, the first additional connection pattern ADPa and the second additional connection pattern ADPb may be different patterns from each other.

[0165] The third connecting electrode CEc may include a third circuit connecting portion CPC and a third light-emitting connecting portion CNc.

[0166] The third circuit connection portion CPc can be the part of the third connection electrode CEc that is connected to the third pixel driving circuit PCc. For example, the third circuit connection portion CPc can be the first transistor TR1 of the third connection electrode CEc that is connected to the third pixel driving circuit PCc (see...). Figure 5 The location of the third circuit connection portion CPC can correspond to the location of the first transistor TR1 of the third pixel driving circuit PCc. For example, the location of the third circuit connection portion CPC can be such that it exposes the first transistor of the third pixel driving circuit PCc and penetrates the fifth insulating layer IL5 (see...). Figure 5 The positions of the contact holes correspond to those of the contacts.

[0167] The third light-emitting connection portion CNc can be the portion of the third connection electrode CEc that is connected to the third connection pattern CNPc. For example, the third light-emitting connection portion CNc can be the portion of the third connection electrode CEc that is covered by the sixth insulating layer IL6 (see...). Figure 5 ) and pixel confinement layer PDL (see Figure 5 The portion of the third light-emitting connection portion CNc is exposed to connect to the third connection pattern CNPc. Accordingly, the position of the third light-emitting connection portion CNc may correspond to the position of the opening that exposes the third connection electrode CEc and penetrates the pixel defining layer and the sixth insulating layer. In a plan view, the third light-emitting connection portion CNc may not overlap with the third emitting region EAc. For example, the third light-emitting connection portion CNc may be located between the third emitting region EAc and the separator SPR.

[0168] According to some embodiments, in a plan view, the third connecting electrode CEc may be spaced apart from the first connecting electrode CEa and the second connecting electrode CEb. In other words, the first connecting electrode CEa, the second connecting electrode CEb, and the third connecting electrode CEc may be different electrodes from each other.

[0169] The third connection pattern CNPc can be connected to the third connection electrode CEc. For example, the third connection pattern CNPc can contact the third light-emitting connection portion CNc of the third connection electrode CEc. However, embodiments according to this disclosure are not limited thereto, and the third connection pattern CNPc may not directly contact the third connection electrode CEc. For example, the third connection pattern CNPc can contact the capping layer (which contacts the third light-emitting connection portion CNc of the third connection electrode CEc), and can be connected to the third light-emitting connection portion CNc of the third connection electrode CEc through the capping layer. The capping layer may include a conductive material. For example, the capping layer may be connected to the first electrode E1 (see... Figure 5 They are formed simultaneously (or substantially simultaneously) and may include the same material as the first electrode.

[0170] In a plan view, the third connection pattern CNPc may not overlap with the third emitter region EAc. According to some embodiments, in a plan view, the third connection pattern CNPc may surround at least a portion of the third emitter region EAc. For example, in a plan view, the third connection pattern CNPc may have a closed-loop shape that completely surrounds the third emitter region EAc. However, embodiments according to this disclosure are not limited thereto.

[0171] According to some embodiments, the third connecting pattern CNPc may be spaced apart from the first connecting pattern CNPa and the second connecting pattern CNPb. In other words, the first connecting pattern CNPa, the second connecting pattern CNPb, and the third connecting pattern CNPc may be different patterns from each other.

[0172] The second electrode of the third light-emitting element LDc can be connected to the third connection pattern CNPc. For example, the second electrode of the third light-emitting element LDc can contact the third connection pattern CNPc. Accordingly, the third connection pattern CNPc can electrically connect the third connection electrode CEc and the second electrode of the third light-emitting element LDc. As a result, the second electrode of the third light-emitting element LDc can be electrically connected to the third pixel driving circuit PCc through the third connection electrode CEc and the third connection pattern CNPc.

[0173] According to some embodiments, in a planar view, the outline of the area where the second electrode of the third light-emitting element LDc and the third connecting pattern CNPc contact each other can be the same (or substantially the same) or similar to the outline of the edge of the third connecting pattern CNPc. For example, when the third connecting pattern CNPc has a closed-loop shape that completely surrounds the third emitting region EAc in a planar view, the area where the second electrode of the third light-emitting element LDc and the third connecting pattern CNPc contact each other can have a closed-loop shape in a planar view. That is, the second electrode of the third light-emitting element LDc and the third connecting pattern CNPc can contact each other at a location that does not overlap with the third emitting region EAc. Accordingly, the second electrode of the third light-emitting element LDc and the third pixel driving circuit PCc can be electrically connected to each other through the third connecting pattern CNPc and the third connecting electrode CEc without reducing the size (i.e., aperture ratio) of the third emitting region EAc.

[0174] The third additional connecting pattern ADPc may extend from the third connecting pattern CNPc. The third additional connecting pattern ADPc may contact the third connecting pattern CNPc. According to some embodiments, the third additional connecting pattern ADPc may comprise the same material as the third connecting pattern CNPc and may be integrally formed with the third connecting pattern CNPc.

[0175] In a plan view, the third additional connection pattern ADPc may not overlap with the third transmit region EAc. According to some embodiments, in a plan view, the third additional connection pattern ADPc may surround at least a portion of the third transmit region EAc. For example, in a plan view, the third additional connection pattern ADPc may have a closed-loop shape that completely surrounds the third transmit region EAc. However, embodiments according to this disclosure are not limited thereto.

[0176] In a plan view, the third additional connection pattern ADPc may be located between the third connection pattern CNPc and the third transmit region EAc. According to some embodiments, in a plan view, the third connection pattern CNPc may surround at least a portion of the third additional connection pattern ADPc. For example, in a plan view, the third connection pattern CNPc may have a closed-loop shape that completely surrounds the third additional connection pattern ADPc. However, embodiments according to this disclosure are not limited thereto.

[0177] According to some embodiments, in a plan view, the third additional connection pattern ADPc may be spaced apart from the first additional connection pattern ADPa and the second additional connection pattern ADPb. In other words, the first additional connection pattern ADPa, the second additional connection pattern ADPb, and the third additional connection pattern ADPc may be different patterns from each other.

[0178] According to some embodiments, the second electrode may contact the first to third connection patterns CNPa, CNPb, and CNPc at locations where the second electrode does not overlap with the first to third emission regions EAa, EAb, and EAc, respectively. Accordingly, the second electrode may contact the first to third connection patterns CNPa, CNPb, and CNPc, respectively, without reducing the size (i.e., aperture ratio) of each of the first to third emission regions EAa, EAb, and EAc.

[0179] Furthermore, according to some embodiments, the second electrode can be electrically connected to the first pixel driving circuit to the third pixel driving circuit PCa, PCb, and PCc via the first connecting electrode to the third connecting electrode CEa, CEb, and CEc, and the first connecting pattern to the third connecting pattern CNPa, CNPb, and CNPc, respectively. Accordingly, the design limitations on each of the first pixel driving circuit to the third pixel driving circuit PCa, PCb, and PCc due to the position, shape, and size of the first emitter region to the third emitter region EAa, EAb, and EAc can be relatively reduced. For example, even if at least some of the first circuit connection portions to the third circuit connection portions CPa, CPb, and CPc overlap with the first emitter region to the third emitter region EAa, EAb, and EAc, the second electrode can still be easily electrically connected to the first pixel driving circuit to the third pixel driving circuit PCa, PCb, and PCc via the first connecting electrode to the third connecting electrode CEa, CEb, and CEc, and the first connecting pattern to the third connecting pattern CNPa, CNPb, and CNPc, respectively. Accordingly, the shape or arrangement of the first pixel driving circuit to the third pixel driving circuit PCa, PCb, and PCc can be designed independently of the position, shape, and size of the first to third emission regions EAa, EAb, and EAc. Consequently, the design freedom of each of the first to third pixel driving circuits PCa, PCb, and PCc can be relatively increased.

[0180] According to some embodiments, regardless of the position, shape, and size of the first to third emitter regions EAa, EAb, and EAC, the first to third pixel driving circuits PCa, PCb, and PCc can be designed to be identical to each other. Furthermore, as described above, the position of the first circuit connection portion CPa can correspond to the position of the first transistor in the first pixel driving circuit PCa, the position of the second circuit connection portion CPb can correspond to the position of the first transistor in the second pixel driving circuit PCb, and the position of the third circuit connection portion CPc can correspond to the position of the first transistor in the third pixel driving circuit PCc. Accordingly, when the first to third pixel driving circuits PCa, PCb, and PCc are formed to have the same (or substantially the same) dimensions and are arranged along the first direction DR1, the positions of the first circuit connection portion CPa, the second circuit connection portion CPb, and the third circuit connection portion CPc can be arranged along the first direction DR1.

[0181] like Figure 3As shown, for each first unit emitter region UEA1, the shape or arrangement of each of the first to third connecting electrodes CEa, CEb, and CEc, and the arrangement relationship between the first to third connecting electrodes CEa, CEb, and CEc, can be the same. Similarly, for each second unit emitter region UEA2, the shape or arrangement of each of the first to third connecting electrodes CEa, CEb, and CEc, and the arrangement relationship between the first to third connecting electrodes CEa, CEb, and CEc, can be the same.

[0182] Furthermore, for each first unit transmission area UEA1, the shape or arrangement of each of the first to third connection patterns CNPa, CNPb, and CNPc, as well as the arrangement relationship between the first to third connection patterns CNPa, CNPb, and CNPc, can be the same. Similarly, for each second unit transmission area UEA2, the shape or arrangement of each of the first to third connection patterns CNPa, CNPb, and CNPc, as well as the arrangement relationship between the first to third connection patterns CNPa, CNPb, and CNPc, can be the same.

[0183] Furthermore, for each first unit transmission area UEA1, the shape or arrangement of each of the first to third additional connection patterns ADPa, ADPb, and ADPc, as well as the arrangement relationship between the first to third additional connection patterns ADPa, ADPb, and ADPc, can be the same. Similarly, for each second unit transmission area UEA2, the shape or arrangement of each of the first to third additional connection patterns ADPa, ADPb, and ADPc, as well as the arrangement relationship between the first to third additional connection patterns ADPa, ADPb, and ADPc, can be the same.

[0184] As described above, the display device DD may include a separator SPR. The separator SPR may be located on the pixel defining layer PDL, the first to third connection patterns CNPa, CNPb, and CNPc, and the first to third additional connection patterns ADPa, ADPb, and ADPc. According to some embodiments, the separator SPR may include an organic insulating material. For example, the separator SPR may include a photosensitive resin (e.g., a photoresist). However, embodiments according to this disclosure are not limited thereto.

[0185] In a plan view, the separator SPR can be located between the first to third transmission regions EAa, EAb, and EAc. For example, in a plan view, the separator SPR can be located between the first transmission region EAa and the second transmission region EAb, between the second transmission region EAb and the third transmission region EAc, and between the first transmission region EAa and the third transmission region EAc. According to some embodiments, in a plan view, the separator SPR can completely surround the first to third transmission regions EAa, EAb, and EAc.

[0186] In the plan view, the spacer SPR may overlap with the first to third connection patterns CNPa, CNPb, and CNPc. Alternatively, in the plan view, the spacer SPR may completely surround the first to third connection patterns CNPa, CNPb, and CNPc. For example, the spacer SPR may cover a portion of each of the first to third connection patterns CNPa, CNPb, and CNPc, as well as the area between adjacent connection patterns. That is, in the plan view, at least a portion of the spacer SPR may extend along the edge of each of the first to third connection patterns CNPa, CNPb, and CNPc. Accordingly, the area where the second electrode contacts each other with the first to third connection patterns CNPa, CNPb, and CNPc may be adjacent to or overlap with the spacer SPR in the plan view.

[0187] In a plan view, the separator SPR may be located between the first to third additional connecting patterns ADPa, ADPb, and ADPc. For example, in a plan view, the separator SPR may be located between the first additional connecting pattern ADPa and the second additional connecting pattern ADPb, between the second additional connecting pattern ADPb and the third additional connecting pattern ADPc, and between the first additional connecting pattern ADPa and the third additional connecting pattern ADPc. According to some embodiments, in a plan view, the separator SPR may completely surround the first to third additional connecting patterns ADPa, ADPb, and ADPc.

[0188] The separator SPR can separate the electrode layer E2L (see Figure 5 The second electrodes of the first light-emitting element LTa, the second light-emitting element LDb, and the third light-emitting element LDc are separated (or disconnected). Therefore, the second electrodes of the first light-emitting element LTa, the second light-emitting element LDb, and the third light-emitting element LDc can be spaced apart from each other. Furthermore, the second electrodes of the first light-emitting element LTa, the second light-emitting element LDb, and the third light-emitting element LDc can be electrically independent of each other.

[0189] The separator SPR can define first open regions to third open regions OA1, OA2, and OA3, respectively, corresponding to the second electrode. For example, in a plan view, the separator SPR can have a mesh structure surrounding the second electrode. The second electrode of the first light-emitting element LDa can be located in the first open region OA1 of the separator SPR, the second electrode of the second light-emitting element LDb can be located in the second open region OA2 of the separator SPR, and the second electrode of the third light-emitting element LDc can be located in the third open region OA3 of the separator SPR.

[0190] According to some embodiments, the planar shape of the first open region OA1 may be the same as (or substantially the same as) the planar shape of the second electrode of the first light-emitting element LDa, the planar shape of the second open region OA2 may be the same as (or substantially the same as) the planar shape of the second electrode of the second light-emitting element LDb, and the planar shape of the third open region OA3 may be the same as (or substantially the same as) the planar shape of the second electrode of the third light-emitting element LDc.

[0191] The first to third open areas OA1, OA2, and OA3 of the separator SPR can correspond to the first to third connecting patterns CNPa, CNPb, and CNPc, respectively. For example, the first connecting pattern CNPa can overlap with the first open area OA1, the second connecting pattern CNPb can overlap with the second open area OA2, and the third connecting pattern CNPc can overlap with the third open area OA3.

[0192] Furthermore, the first to third open areas OA1, OA2, and OA3 of the separator SPR can correspond to the first to third additional connecting patterns ADPa, ADPb, and ADPc, respectively. For example, the first additional connecting pattern ADPa can overlap with the first open area OA1, the second additional connecting pattern ADPb can overlap with the second open area OA2, and the third additional connecting pattern ADPc can overlap with the third open area OA3.

[0193] In the following text, the first launch zone EAa will be used as the reference point. Figure 5 and Figure 6 The cross-sectional structure of the display device DD is described in more detail below. The following description of the cross-sectional structure of the display device DD can be applied in the same (or substantially the same) manner to all emitting areas.

[0194] Further reference Figure 5 and Figure 6The display device DD may include a substrate SUB, a first bottom conductive layer BML1, a second bottom conductive layer BML2, a first transistor TR1, a second transistor TR2, a first capacitor CAP1, a second capacitor CAP2, a first connecting electrode CEa, a first insulating layer to a sixth insulating layer IL1, IL2, IL3, IL4, IL5 and IL6, a pixel defining layer PDL, a first connecting pattern CNPa and a second connecting pattern CNPb, a first additional connecting pattern ADPa and a second additional connecting pattern ADPb, a first light-emitting element LDa, a separator SPR, a first dummy layer DP1, a second dummy layer DP2 and an encapsulation layer ENC.

[0195] The first transistor TR1 may include a first active pattern AP1, a first gate electrode GE1, a first contact electrode SE1, and a second contact electrode DE1. The second transistor TR2 may include a second active pattern AP2, a second gate electrode GE2, a third contact electrode SE2, and a fourth contact electrode DE2. The first capacitor CAP1 may include a first capacitor electrode CPE1 and a second capacitor electrode CPE2. The second capacitor CAP2 may include a first capacitor electrode CPE1 and a third capacitor electrode CPE3. The first light-emitting element LDa may include a first electrode E1, an intermediate layer ML, and a second electrode E2.

[0196] As described above, the first transistor TR1, the second transistor TR2, the first capacitor CAP1, and the second capacitor CAP2 may be components included in the first pixel driving circuit PCa.

[0197] The substrate SUB can serve as the substrate of the display device DD. According to some embodiments, examples of materials that can be used as the substrate SUB include glass, quartz, silicon, or polymers. These can be used individually or in combination with each other. Additionally, the substrate SUB can have a single-layer structure or a multi-layer structure in which multiple layers comprising different materials are stacked.

[0198] The first bottom conductive layer BML1, the second bottom conductive layer BML2, and the third capacitor electrode CPE3 may be located on the substrate SUB. The first bottom conductive layer BML1, the second bottom conductive layer BML2, and the third capacitor electrode CPE3 may include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides.

[0199] The first insulating layer IL1 may cover the first bottom conductive layer BML1, the second bottom conductive layer BML2, and the third capacitor electrode CPE3, and may be located on the substrate SUB. The first insulating layer IL1 may prevent or reduce the diffusion of metal atoms or impurities from the substrate SUB to the first active pattern AP1 and / or the second active pattern AP2. The first insulating layer IL1 may include an insulating material. Examples of insulating materials that can be used as the first insulating layer IL1 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ) or silicon oxynitride (SiO) x N y These can be used individually or in combination with each other.

[0200] A first active pattern AP1 may be located on a first insulating layer IL1. According to some embodiments, the first active pattern AP1 may overlap with a first bottom conductive layer BML1. The first active pattern AP1 may include an oxide semiconductor material, a silicon semiconductor material, and / or an organic semiconductor material. The first active pattern AP1 may include a first contact region S1, a second contact region D1, and a first channel region CH1 between the first contact region S1 and the second contact region D1. The first contact region S1 and the second contact region D1 may have a higher conductivity than the first channel region CH1.

[0201] The second active pattern AP2 may be located on the first insulating layer IL1. According to some embodiments, the second active pattern AP2 may overlap with the second bottom conductive layer BML2. The second active pattern AP2 may include an oxide semiconductor material, a silicon semiconductor material, and / or an organic semiconductor material. The second active pattern AP2 may include a third contact region S2, a fourth contact region D2, and a second channel region CH2 between the third contact region S2 and the fourth contact region D2. The third contact region S2 and the fourth contact region D2 may have a higher conductivity than the second channel region CH2.

[0202] According to some embodiments, the first active pattern AP1 and the second active pattern AP2 may include oxide semiconductor materials. Examples of oxide semiconductor materials that can be used as the first active pattern AP1 and the second active pattern AP2 may include indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), or indium tin zinc oxide (ITZO), etc. These may be used alone or in combination with each other. However, embodiments according to this disclosure are not limited thereto, and the first active pattern AP1 and the second active pattern AP2 may include materials different from each other. For example, one of the first active pattern AP1 and the second active pattern AP2 may include an oxide semiconductor material, and the other may include a silicon semiconductor material.

[0203] Figure 5The illustration shows a first active pattern AP1 and a second active pattern AP2 located in the same layer as each other. However, embodiments according to this disclosure are not limited thereto, and the first active pattern AP1 and the second active pattern AP2 may be located in different layers as well.

[0204] The second insulating layer IL2 may cover the first active pattern AP1 and the second active pattern AP2, and may be located on the first insulating layer IL1. The second insulating layer IL2 may include an insulating material. Examples of insulating materials that can be used as the second insulating layer IL2 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ) or silicon oxynitride (SiO) x N y These can be used individually or in combination with each other.

[0205] The first gate electrode GE1 may be located on the second insulating layer IL2. The first gate electrode GE1 may overlap with the first channel region CH1 of the first active pattern AP1. The first gate electrode GE1 may include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. According to some embodiments, the first gate electrode GE1 may contact the first bottom conductive layer BML1.

[0206] The second gate electrode GE2 may be located on the second insulating layer IL2. The second gate electrode GE2 may overlap with the second channel region CH2 of the second active pattern AP2. The second gate electrode GE2 may include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. According to some embodiments, the second gate electrode GE2 may contact the second bottom conductive layer BML2.

[0207] The first capacitor electrode CPE1 may be located on the second insulating layer IL2. In a plan view, the first capacitor electrode CPE1 may overlap with the third capacitor electrode CPE3. The first capacitor electrode CPE1 and the third capacitor electrode CPE3 may form a second capacitor CAP2. The first capacitor electrode CPE1 may include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide.

[0208] The third insulating layer IL3 may cover the first gate electrode GE1, the second gate electrode GE2, and the first capacitor electrode CPE1, and may be located on the second insulating layer IL2. The third insulating layer IL3 may include an insulating material. Examples of insulating materials that can be used as the third insulating layer IL3 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ) or silicon oxynitride (SiO) x N yThese can be used individually or in combination with each other.

[0209] The second capacitor electrode CPE2 may be located on the third insulating layer IL3. In a plan view, the second capacitor electrode CPE2 may overlap with the first capacitor electrode CPE1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 may form the first capacitor CAP1. The second capacitor electrode CPE2 may include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide.

[0210] The fourth insulating layer IL4 may cover the second capacitor electrode CPE2 and may be located on top of the third insulating layer IL3. The fourth insulating layer IL4 may include an insulating material. Examples of insulating materials that can be used as the fourth insulating layer IL4 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ) or silicon oxynitride (SiO) x N y These can be used individually or in combination with each other.

[0211] The first to fourth contact electrodes SE1, DE1, SE2, and DE2 may be located on the fourth insulating layer IL4. The first contact electrode SE1 may contact the first contact area S1 of the first active pattern AP1, the second contact electrode DE1 may contact the second contact area D1 of the first active pattern AP1, the third contact electrode SE2 may contact the third contact area S2 of the second active pattern AP2, and the fourth contact electrode DE2 may contact the fourth contact area D2 of the second active pattern AP2. The first to fourth contact electrodes SE1, DE1, SE2, and DE2 may comprise conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive oxides.

[0212] According to some embodiments, the first contact electrode SE1 may contact the first bottom conductive layer BML1, and the third contact electrode SE2 may contact the second bottom conductive layer BML2. However, the embodiments according to this disclosure are not limited thereto. For example, when the first gate electrode GE1 contacts the first bottom conductive layer BML1, the first contact electrode SE1 may not contact the first bottom conductive layer BML1. Furthermore, when the second gate electrode GE2 contacts the second bottom conductive layer BML2, the third contact electrode SE2 may not contact the second bottom conductive layer BML2.

[0213] Accordingly, a first transistor TR1 can be formed, comprising a first active pattern AP1, a first gate electrode GE1, a first contact electrode SE1, and a second contact electrode DE1. As described above, the first transistor TR1 can be a transistor connected to the light-emitting element via connection electrodes and connection patterns. For example, when the first pixel driving circuit PCa is Figure 2A When the pixel driving circuit PC is used, the first transistor TR1 can be Figure 2A The first transistor T1. Additionally, when the first pixel driving circuit PCa is... Figure 2B When the pixel driving circuit PC' is in operation, the first transistor TR1 can be... Figure 2B The fifth transistor T5. Additionally, when the first pixel driving circuit PCa is... Figure 2C When the pixel driving circuit PC is in use, the first transistor TR1 can be Figure 2C The fifth transistor, T5.

[0214] Additionally, a second transistor TR2 can be formed, comprising a second active pattern AP2, a second gate electrode GE2, a third contact electrode SE2, and a fourth contact electrode DE2. For example, when the first pixel driving circuit PCa is... Figure 2A In the pixel driving circuit PC, the second transistor TR2 can be Figure 2A The second transistor T2. Additionally, when the first pixel driving circuit PCa is... Figure 2B When the pixel driving circuit PC' is in use, the second transistor TR2 can be Figure 2B Any one of the first to fourth transistors T1', T2, T3, and T4, and the sixth transistor T6. Additionally, when the first pixel driving circuit PCa is... Figure 2C When the pixel driving circuit PC is in its "pixel driving circuit", the second transistor TR2 can be Figure 2C The first to fourth transistors T1', T2, T3 and T4, and the sixth to eighth transistors T6, T7 and T8.

[0215] The fifth insulating layer IL5 may cover the first contact electrodes to the fourth contact electrodes SE1, DE1, SE2, and DE2, and may be located on the fourth insulating layer IL4. The fifth insulating layer IL5 may include an insulating material. For example, the fifth insulating layer IL5 may include an organic insulating material. Examples of organic insulating materials that can be used as the fifth insulating layer IL5 may include photoresists, polypropylene resins, polyimide resins, polyamide resins, siloxane resins, acrylic resins, or epoxy resins. These may be used alone or in combination with each other.

[0216] The first connection electrode CEa can be located on the fifth insulating layer IL5. As described above, the first connection electrode CEa can be connected to the first transistor TR1. For example, the first connection electrode CEa can contact the first transistor TR1 through a contact hole CNT penetrating the fifth insulating layer IL5. Accordingly, the position of the first circuit connection portion CPa can correspond to the position of the contact hole CNT. The first connection electrode CEa can include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. According to some embodiments, the first connection electrode CEa can have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked.

[0217] The sixth insulating layer IL6 may partially cover the first connecting electrode CEa and may be located on the fifth insulating layer IL5. That is, the sixth insulating layer IL6 may define a first sub-opening SO1 that exposes at least a portion of the first connecting electrode CEa. The sixth insulating layer IL6 may include an insulating material. For example, the sixth insulating layer IL6 may include an organic insulating material. Examples of organic insulating materials that can be used as the sixth insulating layer IL6 may include photoresists, polypropylene resins, polyimide resins, polyamide resins, siloxane resins, acrylic resins, or epoxy resins, etc. These may be used alone or in combination with each other.

[0218] The first electrode E1 can be located on the first connecting electrode CEa. For example, the first electrode E1 can be located on the sixth insulating layer IL6. The first electrode E1 can include a conductive material such as a metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive oxide. As described above, the first electrode E1 can serve as... Figure 2A , Figure 2B and Figure 2C The role of the anode.

[0219] The pixel defining layer PDL may be located on the sixth insulating layer IL6 and the first electrode E1. The pixel defining layer PDL may define a pixel opening that exposes at least a portion of the first electrode E1. The first emitter region EAa may be defined by the pixel opening. The pixel defining layer PDL may include an insulating material. For example, the pixel defining layer PDL may include an organic insulating material.

[0220] The pixel-defining layer PDL can further define a second sub-opening SO2 corresponding to a first sub-opening SO1 of the sixth insulating layer IL6. The second sub-opening SO2 can overlap with the first sub-opening SO1 in a plan view, and the first and second sub-openings SO1 and SO2 can be spatially connected to each other. That is, the first and second sub-openings SO1 and SO2 can be connected to define an opening OP, and the opening OP can expose at least a portion of the first connecting electrode CEa.

[0221] The first connection pattern CNPa can be located on the first connection electrode CEa, the sixth insulating layer IL6, and the pixel defining layer PDL. As described above, the first connection pattern CNPa can be electrically connected to the first connection electrode CEa. For example, the first connection pattern CNPa can be connected to the first connection electrode CEa through an opening OP that penetrates the sixth insulating layer IL6 and the pixel defining layer PDL. Accordingly, the position of the first light-emitting connection portion CNa can correspond to the position of the opening OP.

[0222] According to some embodiments, the first connection pattern CNPa may include a transparent conductive oxide. However, embodiments according to this disclosure are not limited thereto, and the first connection pattern CNPa may include a conductive material such as a metal, alloy, or conductive metal nitride. According to some embodiments, the first connection pattern CNPa may have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked.

[0223] The separator SPR can be located on the pixel-defining layer PDL and the first connection pattern CNPa. In a planar view, the separator SPR can overlap with the first connection pattern CNPa. The separator SPR can cover a portion of the first connection pattern CNPa and a portion of the connection pattern adjacent to the first connection pattern CNPa. For example, as Figure 5 As shown, the separator SPR can cover a portion of the first connection pattern CNPa and a portion of the second connection pattern CNPb adjacent to the first connection pattern CNPa. In this case, one of the first side surface of the separator SPR and the second side surface opposite to the first side surface can contact the first connection pattern CNPa, and the other can contact the second connection pattern CNPb.

[0224] The width of the upper part of the partition SPR can be greater than the width of the lower part of the partition SPR. That is, the side surface of the partition SPR that connects the upper surface of the partition SPR to the lower surface of the partition SPR can have a reverse tapering slope. In other words, at least a portion of the cross-section of the partition SPR can be an inverted trapezoid.

[0225] According to some embodiments, such as Figure 5 As shown, the side surface of the separator SPR can have multiple reverse tapered ramps. That is, the separator SPR can have a double reverse tapered structure. Therefore, it is easier to separate (or disconnect) the electrode layer E2L through the separator SPR.

[0226] The first additional connection pattern ADPa may be located on the pixel defining layer PDL. The first additional connection pattern ADPa may extend from the first connection pattern CNPa. For example, in a cross-section, the first additional connection pattern ADPa may extend from the first connection pattern CNPa in a direction away from the center portion of the separator SPR. The first additional connection pattern ADPa may be spaced apart from the first electrode E1. The first additional connection pattern ADPa and the first electrode E1 may be electrically independent of each other.

[0227] According to some embodiments, the first additional connecting pattern ADPa may comprise the same material as the first connecting pattern CNPa, and may be integrally formed with the first connecting pattern CNPa.

[0228] According to some embodiments, the first additional connection pattern ADPa may include a transparent conductive oxide. However, embodiments according to this disclosure are not limited thereto, and the first additional connection pattern ADPa may include a conductive material such as a metal, alloy, or conductive metal nitride. According to some embodiments, the first additional connection pattern ADPa may have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked.

[0229] The width of each of the connecting patterns CNPa, CNPb, and CNPc can be formed to account for deviations in the process of forming the separator SPR. For example, the width of each of the connecting patterns CNPa, CNPb, and CNPc can be formed to account for alignment errors of the mask used in the process of forming the separator SPR. According to some embodiments, the width of each of the connecting patterns CNPa, CNPb, and CNPc can be greater than or equal to 2 micrometers (or about 2 micrometers) and less than or equal to 4 micrometers (or about 4 micrometers). For example, as Figure 6 As shown, the first width WD1 (e.g., the length in the second direction DR2) of each of the first connecting pattern CNPa and the second connecting pattern CNPb can be greater than or equal to 2 micrometers (or about 2 micrometers) and less than or equal to 4 micrometers (or about 4 micrometers).

[0230] The width of each of the additional connecting patterns ADPa, ADPb, and ADPc can be formed taking into account deviations in the process of forming the separator SPR. For example, the width of each of the additional connecting patterns ADPa, ADPb, and ADPc can be formed taking into account the process distribution of the double reverse tapering structure formed on the side surface of the separator SPR.

[0231] like Figure 6As shown, a plurality of reverse tapering ramps on the side surface of the separator SPR may include a first reverse tapering ramp TP1 and a second reverse tapering ramp TP2. The first reverse tapering ramp TP1 may connect to the upper surface of the separator SPR and the second reverse tapering ramp TP2. The second reverse tapering ramp TP2 may connect to the first reverse tapering ramp TP1 and may contact the first connection pattern CNPa or the second connection pattern CNPb. Here, the first deflection SK1 may be defined as the in-plane distance (e.g., the distance in the second direction DR2) between the end of the upper surface of the separator SPR and the portion where the first reverse tapering ramp TP1 and the second reverse tapering ramp TP2 intersect. Additionally, the second deflection SK2 may be defined as the in-plane distance (e.g., the distance in the second direction DR2) between the end of the upper surface of the separator SPR and the portion where the second reverse tapering ramp TP2 contacts the first connection pattern CNPa or the second connection pattern CNPb.

[0232] According to some embodiments, the width of each of the additional connecting patterns ADPa, ADPb, and ADPc can be greater than or equal to 0.3 micrometers (or approximately 0.3 micrometers) and less than or equal to 3 micrometers (or approximately 3 micrometers). For example, as Figure 6 As shown, the second width WD2 (e.g., the length in the second direction DR2) of each of the first additional connection pattern ADPa and the second additional connection pattern ADPb can be greater than or equal to 0.3 micrometers (or about 0.3 micrometers) and less than or equal to 3 micrometers (or about 3 micrometers).

[0233] The width of each of the additional connecting patterns ADPa, ADPb, and ADPc can be formed taking into account the difference SK2-SK1 between the second skew SK2 and the first skew SK1. For example, the width of each of the additional connecting patterns ADPa, ADPb, and ADPc can be formed taking into account the distribution of the difference SK2-SK1 between the second skew SK2 and the first skew SK1 that occurs during the process of forming the double reverse tapering structure. For example, when the target difference between the second skew SK2 and the first skew SK1 is 0.5 micrometers (or approximately 0.5 micrometers), the width of each of the additional connecting patterns ADPa, ADPb, and ADPc can be 0.3 micrometers (or approximately 0.3 micrometers). In this case, when the width of each of the additional connecting patterns ADPa, ADPb, and ADPc is less than 0.3 micrometers (or approximately 0.3 micrometers), the double reverse tapering structure may not be smoothly formed on the side surface of the separator SPR when the distribution of the difference SK2-SK1 between the second skew SK2 and the first skew SK1 occurs during the process of forming the double reverse tapering structure. However, embodiments according to this disclosure are not limited thereto, and the minimum width of each of the additional connecting patterns ADPa, ADPb and ADPc may be different depending on the target difference between the second skew SK2 and the first skew SK1.

[0234] In addition, the maximum width of each of the additional connection patterns ADPa, ADPb and ADPc can be determined by taking into account the in-plane distance between the first electrode E1 and the corresponding connection pattern.

[0235] In other words, since each of the additional connection patterns ADPa, ADPb, and ADPc can be electrically independent of the first electrode E1, the maximum width of each of the additional connection patterns ADPa, ADPb, and ADPc can be determined by considering the in-plane distance between the first electrode E1 and the corresponding connection pattern. For example, as... Figure 6 As shown, the maximum value of the second width WD2 of the first additional connection pattern ADPa can be determined by taking into account the in-plane distance between the first electrode E1 and the first connection pattern CNPa.

[0236] The intermediate layer ML may be located on the first electrode E1, the pixel defining layer PDL, the first connection pattern CNPa, and the first additional connection pattern ADPa. A portion of the intermediate layer ML may be located within a pixel opening of the pixel defining layer PDL. According to some embodiments, the intermediate layer ML may include a first functional layer comprising an organic material, an emission layer located on the first functional layer and comprising an emission material, and a second functional layer located on the emission layer and comprising an organic material. For example, the first functional layer may include a hole injection layer or a hole transport layer, and the second functional layer may include an electron transport layer or an electron injection layer.

[0237] Shaded areas where the intermediate layer ML is difficult to deposit may exist around the separator SPR with a reverse tapered slope. Accordingly, the intermediate layer ML may have a structure separated (or disconnected) by the separator SPR in and / or around the shaded area. Because the intermediate layer ML has a separated (or disconnected) structure, a portion of the first connection pattern CNPa may be exposed at a location adjacent to or overlapping with the separator SPR. Accordingly, the second electrode E2 of the first light-emitting element LDa may contact the first connection pattern CNPa.

[0238] The first dummy layer DP1 can be located on the separator SPR. Because the intermediate layer ML has a structure that is separated (or disconnected) by the separator SPR, the first dummy layer DP1 can be formed. That is, the first dummy layer DP1 can be formed in the same process as the intermediate layer ML. According to some embodiments, the first dummy layer DP1 can be omitted.

[0239] Electrode layer E2L can be located on the first electrode E1. For example, electrode layer E2L can be located on the intermediate layer ML. Electrode layer E2L can include conductive materials such as metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive materials. As described above, electrode layer E2L can play a role in... Figure 2A , Figure 2B and Figure 2C The role of the cathode.

[0240] According to some embodiments, the electrode layer E2L may have a single-layer structure. However, embodiments according to this disclosure are not limited thereto, and the electrode layer E2L may have a multi-layer structure in which multiple conductive layers are stacked. For example, the electrode layer E2L may have a two-layer structure, which includes a first sub-electrode layer comprising a metal and a second sub-electrode layer located on the first sub-electrode layer and comprising a transparent conductive oxide.

[0241] Shaded areas where electrode layer E2L is difficult to deposit may exist around the separator SPR with a reverse tapered slope. Within and / or around the shaded areas, electrode layer E2L may have a structure separated (or disconnected) by the separator SPR. For example, electrode layer E2L may be separated (or disconnected) into a second electrode E2 of a first light-emitting element LTa, a second electrode of a second light-emitting element LDb, and a second electrode of a third light-emitting element LDc. That is, the second electrodes E2 of the first light-emitting element LTa, the second electrodes of the second light-emitting element LDb, and the second electrodes of the third light-emitting element LDc may be electrically insulated from each other.

[0242] like Figure 5As shown, electrode layer E2L (e.g., second electrode E2) can be electrically connected to the first connection pattern CNPa. For example, electrode layer E2L (e.g., second electrode E2) can contact the first connection pattern CNPa at a location adjacent to or overlapping with the separator SPR. For example, when the deposition angle of the deposition process used to form electrode layer E2L is greater than the deposition angle of the deposition process used to form intermediate layer ML, electrode layer E2L (e.g., second electrode E2) can be formed to cover the side of the separated (or disconnected) intermediate layer ML and contact the first connection pattern CNPa. As a result, second electrode E2 can be electrically connected to first transistor TR1 through first connection electrode CEa and first connection pattern CNPa.

[0243] The second dummy layer DP2 can be located on the separator SPR. For example, the second dummy layer DP2 can be located on the first dummy layer DP1. Because the electrode layer E2L has a structure that is separated (or disconnected) by the separator SPR, the second dummy layer DP2 can be formed. That is, the second dummy layer DP2 can be formed in the same process as the electrode layer E2L. According to some embodiments, the second dummy layer DP2 can be omitted.

[0244] The encapsulation layer ENC may be located on the electrode layer E2L. The encapsulation layer ENC may completely cover the electrode layer E2L, the connection patterns CNPa, CNPb and CNPc, the separator SPR, the first dummy layer DP1, and the second dummy layer DP2. According to some embodiments, the encapsulation layer ENC may include a first inorganic encapsulation layer IEL1 containing inorganic insulating material, an organic encapsulation layer OEL located on the first inorganic encapsulation layer IEL1 and containing organic insulating material, and a second inorganic encapsulation layer IEL2 located on the organic encapsulation layer OEL and containing inorganic insulating material.

[0245] According to some embodiments, the touch sensing layer may be located on the encapsulation layer ENC. For example, the touch sensing layer may include a plurality of touch electrode arrays for capacitively detecting user manipulation, touch pad portions, and a plurality of touch lines electrically connecting the touch pad portions and the touch electrode arrays. However, embodiments according to this disclosure are not limited thereto. According to some embodiments, the touch sensing layer may be omitted.

[0246] According to some embodiments, the display device DD may include connecting electrodes CEa, CEb, and CEc, connecting patterns CNPa, CNPb, and CNPc, and separators SPR. Accordingly, the electrode layer E2L (e.g., cathode) located on the first electrode E1 (e.g., anode) can be easily connected to the pixel driving circuits PCa, PCb, and PCc. For example, the electrode layer E2L located on the first electrode E1 can be connected to the driving transistors (e.g., [missing information]) of each of the pixel driving circuits PCa, PCb, and PCc via the connecting electrodes CEa, CEb, and CEc and the connecting patterns CNPa, CNPb, and CNPc. Figure 2A , Figure 2B and Figure 2C The drain of the first transistor T1 (or T1') is used. Accordingly, even when the light-emitting element deteriorates, the gate-source voltage (Vgs) of the driving transistor remains unchanged. Consequently, the range of driving current variation due to light-emitting element deterioration can be relatively reduced. Therefore, the afterimage defects of the display device DD that depend on increased usage time can be relatively reduced, and the lifespan of the display device DD can be relatively improved.

[0247] Additionally, according to some embodiments, the display device DD may include additional connecting patterns ADPa, ADPb, and ADPc extending from the connecting patterns CNPa, CNPb, and CNPc, respectively. The width of each of the additional connecting patterns ADPa, ADPb, and ADPc may be formed taking into account deviations in the process of forming the separator SPR. For example, the width of each of the additional connecting patterns ADPa, ADPb, and ADPc may be formed taking into account the process distribution of the double reverse tapering structure formed on the side surface of the separator SPR. Since the display device DD includes additional connecting patterns ADPa, ADPb, and ADPc extending from the connecting patterns CNPa, CNPb, and CNPc, respectively, even if a distribution occurs in the process of forming the double reverse tapering structure, the double reverse tapering structure can be smoothly formed on the side surface of the separator SPR.

[0248] Accordingly, it is easier to separate (or disconnect) the electrode layer E2L via the separator SPR.

[0249] Figure 7 This is a block diagram of an electronic device according to some embodiments of the present disclosure.

[0250] refer to Figure 7 According to some embodiments, the electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14. The display device according to some embodiments can be applied to various electronic devices. The electronic device 10 according to some embodiments may include the aforementioned display device, and in addition to the display device, may further include modules or devices with other additional functions.

[0251] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0252] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, it can transmit image data signals and / or input control signals to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0253] The power module 14 may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10. That is, according to the above embodiment, the power module 14 can provide power to the display device.

[0254] According to the above embodiments, at least one of the components of the electronic device 10 may be included in the display device. Additionally, some of the separate modules functionally included in a single module may be included in the display device, while others may be provided separately from the display device. For example, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided as other devices in the electronic device 10 besides the display device.

[0255] Figure 8 These are schematic diagrams of electronic devices according to various embodiments.

[0256] refer to Figure 8 Various electronic devices employing the display device according to the embodiments may include image display electronic devices such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions 10_1d, desktop monitors 10_1e, etc.; wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c; and vehicle electronic devices 10_3 including display modules, such as CID (Central Information Display) and interior mirror displays that can be located, for example, on the instrument panel, central dashboard, and dashboard of a car.

[0257] Some aspects of the embodiments of this disclosure can be applied to various display devices. For example, embodiments of this disclosure can be applied to various display devices such as display devices for vehicles, ships and aircraft, portable communication devices, display devices for display or information transmission, and medical display devices.

[0258] The foregoing description is illustrative of some embodiments of this disclosure and should not be construed as limiting it. Although several embodiments have been described with reference to the accompanying drawings, those skilled in the art will readily understand that many variations and modifications can be made therein without departing from the spirit and scope of this disclosure as defined in the claims and their equivalents.

Claims

1. A display device, comprising: Pixel driving circuit, including transistors; Connecting electrodes are electrically connected to the pixel driving circuit; The first electrode is located on the connecting electrode; A pixel defining layer defines an opening that exposes a portion of the first electrode; A connection pattern is formed on the connection electrode and the pixel defining layer, and is electrically connected to the connection electrode; An electrode layer is placed on the first electrode and electrically connected to the connection pattern; A separator, on the pixel defining layer and the connection pattern, separates the electrode layer into a plurality of second electrodes spaced apart from each other, and covers at least a portion of the connection pattern; as well as An additional connecting pattern is added on the pixel defining layer and extends in the cross section from the connecting pattern in a direction away from the center portion of the separator.

2. The display device according to claim 1, wherein, The side surface of the separator contacts the connection pattern and has multiple reverse tapering slopes in the cross section.

3. The display device according to claim 2, in, The plurality of reverse tapering ramps include a first reverse tapering ramp and a second reverse tapering ramp. Wherein, the first reverse tapering ramp is connected to the upper surface of the separator, and The second reverse tapering slope contacts the connecting pattern.

4. The display device according to claim 1, wherein, The additional connecting pattern is made of the same material as the connecting pattern.

5. The display device according to claim 1, wherein, The additional connection pattern includes a transparent conductive oxide.

6. The display device according to claim 1, wherein, The width of the additional connection pattern is greater than or equal to 0.3 micrometers and less than or equal to 3 micrometers.

7. The display device according to claim 1, wherein, The width of the connection pattern is greater than or equal to 2 micrometers and less than or equal to 4 micrometers.

8. The display device according to claim 1, wherein, The additional connection pattern and the first electrode are electrically independent of each other.

9. The display device according to claim 1, wherein, Each of the plurality of second electrodes is electrically connected to the pixel driving circuit via the connection pattern and the connection electrode.

10. The display device according to claim 1, wherein, Each of the plurality of second electrodes contacts the connection pattern at a position adjacent to or overlapping with the separator.

11. The display device according to claim 1, further comprising: An intermediate layer, located between the first electrode and the electrode layer, includes an emissive material.

12. A display device, comprising: Pixel driving circuit, including transistors; Connecting electrodes are electrically connected to the pixel driving circuit; The first electrode is located on the connecting electrode; A pixel defining layer covers a portion of the first electrode and defines the emission region; A connection pattern, electrically connected to the connection electrode, and surrounding at least a portion of the emission region in a plan view; An electrode layer is placed on the first electrode and electrically connected to the connection pattern; A separator, on the pixel defining layer and the connection pattern, separates the electrode layer into a plurality of second electrodes spaced apart from each other, and overlaps with the connection pattern in the planar view; as well as An additional connecting pattern extends from the connecting pattern and is located between the connecting pattern and the emission area in the plan view.

13. The display device according to claim 12, wherein, In the plan view, the additional connection pattern surrounds at least a portion of the emission region.

14. The display device according to claim 12, wherein, In the plan view, the connecting pattern surrounds at least a portion of the additional connecting pattern.

15. The display device according to claim 12, wherein, In the plan view, the separator completely surrounds the connecting pattern and the additional connecting pattern.

16. The display device according to claim 12, wherein, The side surface of the separator contacts the connection pattern and has multiple reverse tapering ramps in the cross section.

17. The display device according to claim 12, wherein, The additional connecting pattern is made of the same material as the connecting pattern.

18. The display device according to claim 12, wherein, The width of the additional connection pattern is greater than or equal to 0.3 micrometers and less than or equal to 3 micrometers.

19. The display device according to claim 12, wherein, The additional connection pattern and the first electrode are electrically independent of each other.

20. An electronic device comprising: The display device according to any one of claims 1-19 includes pixels; as well as The processor is configured to transmit image data signals and input control signals to the display device.

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