Devices including stacked through-encapsulation via interconnects

Abstract

In one embodiment, a device includes (i) a first device portion including: a die substrate; at least one first dielectric layer; a first plurality of interconnects; a first encapsulation layer; and a first plurality of via interconnects located at least in the first encapsulation layer; (ii) a second device portion comprising: at least one second dielectric layer; a second plurality of interconnects; a second encapsulation layer; and a second plurality of via interconnects at least in the second encapsulation layer; and (iii) a first plurality of solder interconnects coupled to the first device portion and the second device portion, where the first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects, and the second plurality of via interconnects are configured to operate as inductors.

Description

Cross Reference to Related Applications

[0001] This application claims priority to and the benefit of U.S. Non-Provisional Application Serial No. 18 / 352,976, filed July 14, 2023, in the U.S. Patent and Trademark Office, the entire contents of which are incorporated herein by reference as if fully set forth below in their entirety and for all applicable purposes. TECHNICAL FIELD

[0002] Various features relate to passive devices. BACKGROUND

[0003] A package can include a substrate, an integrated device, and a passive device. The substrate can include a plurality of interconnects. The integrated device and / or the passive device can be coupled to the interconnects of the substrate. There is an ongoing need to provide smaller packages with improved performance. SUMMARY

[0004] Various features relate to passive devices.

[0005] One example provides a device comprising: (i) a first device portion comprising: a die substrate; at least one first dielectric layer; a first plurality of interconnects; a first encapsulation layer; and a first plurality of via interconnects located at least in the first encapsulation layer; (ii) a second device portion comprising: at least one second dielectric layer; a second plurality of interconnects; a second encapsulation layer; and a second plurality of via interconnects located at least in the second encapsulation layer; and (iii) a first plurality of solder interconnects coupled to the first device portion and the second device portion, wherein the first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects, and the second plurality of via interconnects are configured to operate as an inductor.

[0006] Another example provides a method of providing a first device portion comprising: a die substrate; at least one first dielectric layer; a first plurality of interconnects; a first encapsulation layer; and a first plurality of via interconnects located at least in the first encapsulation layer. The method couples a second device portion to the first device portion by a first plurality of solder interconnects, the second device portion comprising: at least one second dielectric layer; a second plurality of interconnects; a second encapsulation layer; and a second plurality of via interconnects located at least in the second encapsulation layer. The first plurality of solder interconnects is coupled to the first device portion and the second device portion. The first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects, and the second plurality of via interconnects are configured to operate as an inductor. BRIEF DESCRIPTION OF DRAWINGS

[0007] The various features, nature and advantages can become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify corresponding throughout.

[0008] Figure 1 An example cross-sectional view of a device including a stacked device portion with via interconnects is illustrated.

[0009] Figure 2 An example cross-sectional view of a device including a stacked device portion with via interconnects is illustrated.

[0010] Figure 3 An example cross-sectional view of a device including a stacked device portion with via interconnects is illustrated.

[0011] Figure 4 An example cross-sectional view of a device including a stacked device portion with via interconnects is illustrated.

[0012] Figure 5 An example cross-sectional view of a device including a stacked device portion with via interconnects is illustrated.

[0013] Figure 6 An example cross-sectional view of a device including a stacked device portion with via interconnects is illustrated.

[0014] Figure 7 An example cross-sectional view of a device including a stacked device portion with via interconnects is illustrated.

[0015] Figure 8 An example plot of inductance from an inductor from a device including a stacked device portion with via interconnects is illustrated.

[0016] Figure 9 An example plot of Q-factor from an inductor from a device including a stacked device portion with via interconnects is illustrated.

[0017] Figures 10A-10D An example sequence for fabricating a device portion with via interconnects is illustrated.

[0018] Figure 11 An example sequence for fabricating another device portion with via interconnects and stud interconnects is illustrated.

[0019] Figure 12 An example flowchart of a method for fabricating a device portion with via interconnects is illustrated.

[0020] Figures 13A-13F An example sequence for fabricating a device with a stacked device portion with via interconnects is illustrated.

[0021] Figure 14 An example flow diagram of a method for fabricating a device with stacked device portions having via interconnects is illustrated.

[0022] Figure 15 Various electronic devices that can integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein are illustrated. DETAILED DESCRIPTION

[0023] In the following description, specific details are set forth to provide a thorough understanding of various aspects of the disclosure. However, persons having ordinary skill in the art will appreciate that the aspects can be practiced without the specific details. For example, circuits can be shown in block diagrams in order to avoid obscuring aspects of the present disclosure. In other instances, well-known circuits, structures and techniques have not been shown in order to avoid obscuring aspects of the present disclosure.

[0024] The disclosure describes a device comprising: (i) a first device portion comprising: a die substrate; at least one first dielectric layer; a first plurality of interconnects; a first encapsulation layer; and a first plurality of via interconnects located at least in the first encapsulation layer; (ii) a second device portion comprising: at least one second dielectric layer; a second plurality of interconnects; a second encapsulation layer; and a second plurality of via interconnects located at least in the second encapsulation layer; and (iii) a first plurality of solder interconnects coupled to the first device portion and the second device portion, wherein the first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects, and the second plurality of via interconnects are configured to operate as an inductor. The stacking of two device portions with via interconnects in the encapsulation layers helps to provide an inductor with a high Q-factor. Example device including stacked portions with via interconnects

[0025] Figure 1 A cross-sectional view of a device 100 including a stacked portion with via interconnects is illustrated. In some implementations, the device 100 can be a passive device. The device 100 can be configured to operate as an inductor. The device 100 can include components configured as an inductor (e.g., a solenoid inductor). The device 100 can be coupled to an interposer, a package substrate, or a board (e.g., a printed circuit board).

[0026] Device 100 includes first device portion 101, second device portion 102, plurality of solder interconnects 107, encapsulation layer 170, dielectric layer 112, and plurality of solder interconnects 109. Second device portion 102 is coupled to first device portion 101 by plurality of solder interconnects 107. Encapsulation layer 170 can at least partially encapsulate second device portion 102 and plurality of solder interconnects 107. Encapsulation layer 170 can be coupled to first device portion 101 (e.g., to a surface of first device portion). Encapsulation layer 170 can include a mold, a resin, and / or an epoxy. As will be further described below, components in device 100 can be configured as inductor 103. Figure 1 Inductor 105 is illustrated, which can be a conceptual representation of inductor 103. First device portion 101 and second device portion 102 can be stacked (e.g., vertically stacked) device portions.

[0027] First device portion 101 can be a first passive device portion. First device portion 101 includes die substrate 110, encapsulation layer 120, dielectric layer 130, encapsulation layer 140, dielectric layer 150, dielectric layer 160, plurality of interconnects 121, plurality of interconnects 131, plurality of via interconnects 141, plurality of interconnects 151, and plurality of interconnects 161. Plurality of interconnects 121 can be at least partially located in encapsulation layer 120. Plurality of interconnects 131 can be at least partially located in dielectric layer 130. Plurality of via interconnects 141 can be at least partially located in encapsulation layer 140. Plurality of interconnects 151 can be at least partially located in dielectric layer 150. Plurality of interconnects 161 can be at least partially located in dielectric layer 160. Encapsulation layer 140 can be located between dielectric layer 130 and dielectric layer 150. Encapsulation layer 140 can include a mold, a resin, and / or an epoxy. Encapsulation layer 140 can include a magnetic layer. Encapsulation layer 120 can include a mold, a resin, and / or an epoxy. Encapsulation layer 120 and / or encapsulation layer 140 can be a different type of dielectric layer than encapsulation layer 120, dielectric layer 130, dielectric layer 150, and / or dielectric layer 160. Encapsulation layer 120, dielectric layer 130, encapsulation layer 140, dielectric layer 150, and / or dielectric layer 160 can be located above die substrate 110. Encapsulation layer 120 can be coupled to a surface of die substrate 110. Die substrate 110 can include silicon (Si). In some implementations, die substrate 110 can include a filter and / or a transistor.

[0028] The plurality of interconnects 121 is coupled to the plurality of interconnects 131. The plurality of interconnects 131 is coupled to the plurality of via interconnects 141. The plurality of via interconnects 141 is coupled to the plurality of interconnects 151. The plurality of interconnects 151 is coupled to the plurality of interconnects 161. The plurality of interconnects 121, the plurality of interconnects 131, the plurality of via interconnects 141, the plurality of interconnects 151, and / or the plurality of interconnects 161 can be configured to operate as an inductor (e.g., a solenoid) or a portion of an inductor (e.g., a portion of an inductor). The plurality of interconnects 121, the plurality of interconnects 131, the plurality of via interconnects 141, the plurality of interconnects 151, and / or the plurality of interconnects 161 can define a winding of an inductor (e.g., a winding of a solenoid inductor).

[0029] The second device portion 102 can be a second passive device portion. The second device portion 102 includes an encapsulation layer 122, a dielectric layer 132, an encapsulation layer 142, a dielectric layer 152, a dielectric layer 162, a plurality of interconnects 123, a plurality of interconnects 133, a plurality of via interconnects 143, a plurality of interconnects 153, and a plurality of interconnects 163. The plurality of interconnects 123 can be at least partially located in the encapsulation layer 122. The plurality of interconnects 133 can be at least partially located in the dielectric layer 132. The plurality of via interconnects 143 can be at least partially located in the encapsulation layer 142. The plurality of interconnects 153 can be at least partially located in the dielectric layer 152. The plurality of interconnects 163 can be at least partially located in the dielectric layer 162. The encapsulation layer 142 can be located between the dielectric layer 132 and the dielectric layer 152. The encapsulation layer 142 can include a mold, a resin, and / or an epoxy. The encapsulation layer 142 can include a magnetic layer. The encapsulation layer 122 can include a mold, a resin, and / or an epoxy. The encapsulation layer 122 and / or the encapsulation layer 142 can be a different type of dielectric layer than the dielectric layer 132, the dielectric layer 152, and / or the dielectric layer 162. The dielectric layer 130, the dielectric layer 150, the dielectric layer 160, the dielectric layer 162, the dielectric layer 152, and / or the dielectric layer 132 can include polyimide. Figure 1 It is exemplified that the second device portion 102 can be without a die substrate (e.g., without a silicon substrate).

[0030] Multiple interconnects 123 are coupled to multiple interconnects 133. Multiple interconnects 133 are coupled to multiple via interconnects 143. Multiple via interconnects 143 are coupled to multiple interconnects 153. Multiple interconnects 153 are coupled to multiple interconnects 163. Multiple interconnects 123, multiple interconnects 133, multiple via interconnects 143, multiple interconnects 153 and / or multiple interconnects 163 may be configured to operate as an inductor (e.g., a solenoid) or as part of an inductor (e.g., a portion of an inductor). Multiple interconnects 123, multiple interconnects 133, multiple via interconnects 143, multiple interconnects 153 and / or multiple interconnects 163 may define a winding of an inductor (e.g., a winding of a solenoid inductor).

[0031] Multiple interconnects 121, multiple interconnects 131, multiple via interconnects 141, multiple interconnects 151, multiple interconnects 161, multiple solder interconnects 107, multiple interconnects 163, multiple via interconnects 143, multiple interconnects 133, and / or multiple interconnects 123 may be configured to operate as an inductor 103 (e.g., a solenoid inductor). For example, at least a portion of multiple interconnects 121, multiple interconnects 131, multiple via interconnects 141, multiple interconnects 151, multiple interconnects 161, multiple solder interconnects 107, multiple interconnects 163, multiple via interconnects 143, multiple interconnects 133, and / or multiple interconnects 123 may be defined as windings of inductor 103 (e.g., windings of a solenoid inductor).

[0032] In some implementations, multiple interconnects 131, 151, 161, 163, 153, and / or 133 may include multiple metallized interconnects. Multiple metallized interconnects may include multiple redistributed interconnects. Multiple via interconnects 141 and / or 143 may be examples of through-encapsulated via interconnects. Multiple via interconnects 141 and 143 may represent stacked through-encapsulated via interconnects.

[0033] In some specific implementations, at least some of the interconnects from a plurality of interconnects 131 and / or at least some of the interconnects from a plurality of interconnects 133 may define and / or form the horizontal winding portion of the inductor.

[0034] As mentioned above, the second device portion 102 is coupled to the first device portion 101 via a plurality of solder interconnects 107. The plurality of solder interconnects 107 are coupled to a plurality of interconnects 161 and a plurality of interconnects 163. The location and / or portion of the plurality of solder interconnects 107 may be offset from the plurality of via interconnects 141 and / or the plurality of via interconnects 143 (e.g., horizontal offset, horizontal center-to-center offset). In some embodiments, offsetting the plurality of via interconnects 107 from the plurality of via interconnects 141 and / or the plurality of via interconnects 143 helps reduce dielectric layer delamination, which helps provide a more robust and reliable connection of the interconnects. In some embodiments, offsetting the plurality of via interconnects 107 from the plurality of via interconnects 141 and / or the plurality of via interconnects 143 helps improve the Q factor of the inductor by increasing the effective aperture size of the inductor, which is at least as described below. Figure 2 The following is a more detailed description.

[0035] Dielectric layer 112 is coupled to encapsulation layer 170 and encapsulation layer 122. Dielectric layer 112 may include openings. Multiple solder interconnects 109 may be coupled to multiple interconnects 123 through openings in dielectric layer 112. In some embodiments, dielectric layer 112 may be a solder mask layer.

[0036] Different embodiments may have different heights for device 100. For example, in some embodiments, a plurality of via interconnects 141 may have a thickness in the range of about 150 micrometers to 200 micrometers. In some embodiments, a plurality of via interconnects 143 may have a thickness in the range of about 150 micrometers to 200 micrometers. In some embodiments, a plurality of solder interconnects may have a thickness in the range of about 100 micrometers to 200 micrometers. In some embodiments, a first device portion 101 may have a thickness in the range of about 150 micrometers to 200 micrometers. In some embodiments, a second device portion 102 may have a thickness in the range of about 150 micrometers to 200 micrometers. In some embodiments, device 100 may have a thickness in the range of about 450 micrometers to 600 micrometers. The above dimensions may be applicable to any of the devices and / or device portions described in this disclosure. As will be further described below, some embodiments of the device may include solder post interconnects. In some specific implementations, the combination of post interconnects and solder interconnects can have a total thickness ranging from approximately 150 micrometers to 200 micrometers. It should be noted that the dimensions and / or thickness of any of the devices and / or their components are not limited to the range of values ​​described above.

[0037] As mentioned above, the inductance and / or Q-factor of an inductor can be proportional to the size of the inductor's aperture. Therefore, all else being equal, a larger aperture may result in a larger inductance in the inductor. Figure 2A device 100 having an inductor 103 is illustrated. The inductor 103 includes an aperture 210. The aperture 210 conceptually represents the aperture of the inductor 103 and is not intended to represent the exact shape and / or size of the aperture of the inductor 103. As mentioned above, one advantage of offsetting the plurality of solder interconnects 107 from the plurality of via interconnects 141 and / or the plurality of via interconnects 143 (e.g., center-to-center horizontal offset) is that it increases the aperture of the inductor 103 while also reducing the possibility of dielectric layer delamination.

[0038] Figure 3 Device 300 is illustrated, comprising a stacked device portion having via interconnects. Device 300 is similar to device 100 and includes similar components. Device 300 includes a first device portion 101, a second device portion 102, a plurality of solder interconnects 107, an encapsulation layer 170, a dielectric layer 112, a plurality of solder interconnects 109, and / or an inductor 103, as described with respect to device 100.

[0039] Figure 3 The device 300 also includes a passive component 301. The passive component 301 may include a metal-insulator-metal (MIM) capacitor. The passive component 301 may be coupled to a first device portion 101 via a plurality of solder interconnects 310. The passive component 301 is configured to electrically couple interconnects defining the inductor 103. The passive component 301 is coupled to a plurality of interconnects 161 via the plurality of solder interconnects 310. The passive component 301 may be laterally surrounded by a plurality of solder interconnects 107. The passive component 301 may be located in the device 300 such that the passive component 301 is surrounded by the windings of the inductor 103 (e.g., surrounded by interconnects and / or via interconnects forming the inductor). An encapsulation layer 170 may at least partially encapsulate the passive component 301 and / or the plurality of solder interconnects 310. The back side of the passive component 301 may be a second device portion 102. For example, the back side of passive component 301 may be in contact with dielectric layer 162. However, in some embodiments, an encapsulation layer (e.g., 170) may be present between the back side of passive component 301 and dielectric layer 162. In some embodiments, more than one passive component may be coupled to interconnects defining inductor 103. In some embodiments, passive component 301 may be coupled to multiple interconnects 163 via multiple solder interconnects. In some embodiments, instead of passive component 301 and / or combined with it, an acoustic device may be part of device 300. The acoustic device may be coupled to multiple interconnects 161 and / or multiple via interconnects 163.

[0040] Figure 4Device 400 is illustrated, comprising a stacked device portion having via interconnects. Device 400 is similar to device 100 and / or device 300 and includes similar components. Device 400 includes a first device portion 401, a second device portion 102, a plurality of solder interconnects 107, an encapsulation layer 170, a dielectric layer 112, a plurality of solder interconnects 109, an inductor 103, and / or a passive component 301, as described with respect to device 100 and device 300. The first device portion 401 is similar to the first device portion 101 of device 100. However, the first device portion 401 does not include the encapsulation layer 120 and the plurality of interconnects 121. The dielectric layer 130 is coupled to the surface of the die substrate 110. It should be noted that the encapsulation layer 120 and / or the plurality of interconnects 121 may be optional for any of the devices described in this disclosure.

[0041] Figure 5 Device 500 is illustrated, comprising a stacked device portion having via interconnects. Device 500 is similar to device 100 and includes similar components. Device 500 includes a first device portion 101, a second device portion 102, a plurality of solder interconnects 107, an encapsulation layer 170, a dielectric layer 112, and a plurality of solder interconnects 109, as described with respect to device 100. Figure 5 As shown, the plurality of solder interconnects 107 are not offset from the plurality of via interconnects 141 and / or the plurality of via interconnects 143. However, the plurality of solder interconnects 107 may not be offset from the plurality of via interconnects 141 and / or the plurality of via interconnects 143, as... Figure 1 As shown. Therefore, Figure 5 The center-to-center horizontal offset between the multiple solder interconnects 107 and the multiple via interconnects (e.g., 141, 143) can be less than [amount missing]. Figure 1 The center-to-center horizontal offset between the multiple solder interconnects 107 and the multiple via interconnects (e.g., 141, 143).

[0042] The result is that inductor 503 has an aperture 510 smaller than that of inductor 103. This can lead to Figure 5 The inductor 503 has a higher performance than Figure 1 The inductor 103 has a lower inductance. Multiple interconnects 121, multiple interconnects 131, multiple via interconnects 141, multiple interconnects 151, multiple interconnects 161, multiple solder interconnects 107, multiple interconnects 163, multiple via interconnects 143, multiple interconnects 133 and / or multiple interconnects 123 can be configured to operate as inductor 503 (e.g., solenoid inductor). Figure 5 An example of inductor 505 is shown, which can be a conceptual representation of inductor 503.

[0043] In some specific implementations, the device may include solder post interconnects. Figure 6 Device 600 is illustrated, comprising a stacked device portion having via interconnects. Device 600 is similar to devices 300 and 100 and includes similar components. Device 600 includes a first device portion 101, a second device portion 102, a plurality of solder interconnects 107, an encapsulation layer 170, a dielectric layer 112, a plurality of solder interconnects 109, and a passive component 301, as described with respect to devices 100 and 300.

[0044] like Figure 6 As shown, device 600 includes a plurality of solder pad interconnects 607. The plurality of solder pad interconnects 607 are coupled to a plurality of interconnects 163. A plurality of solder interconnects 107 are coupled to the plurality of solder pad interconnects 607 and the plurality of interconnects 161. An encapsulation layer 170 may at least partially encapsulate the plurality of solder pad interconnects 607. In some embodiments, the plurality of solder pad interconnects 607 may be considered as part of a second device portion 102.

[0045] Multiple interconnects 121, multiple interconnects 131, multiple via interconnects 141, multiple interconnects 151, multiple interconnects 161, multiple solder interconnects 107, multiple solder post interconnects 607, multiple interconnects 163, multiple via interconnects 143, multiple interconnects 133, and / or multiple interconnects 123 may be configured to operate as an inductor 603 (e.g., a solenoid inductor). For example, at least a portion of multiple interconnects 121, multiple interconnects 131, multiple via interconnects 141, multiple interconnects 151, multiple interconnects 161, multiple solder interconnects 107, multiple solder post interconnects 607, multiple interconnects 163, multiple via interconnects 143, multiple interconnects 133, and / or multiple interconnects 123 may be defined as windings of inductor 603 (e.g., windings of a solenoid inductor).

[0046] In some implementations, as an alternative to or supplement to the multiple post interconnects 607, the device may include multiple post interconnects coupled to the multiple interconnects 161. Figure 7 Device 700 is illustrated, comprising a stacked device portion having via interconnects. Device 700 is similar to device 600 and includes similar components. Device 700 includes a first device portion 101, a second device portion 102, a plurality of solder interconnects 107, an encapsulation layer 170, a dielectric layer 112, a plurality of solder interconnects 109, and a passive component 301, as described with respect to devices 100 and 300.

[0047] like Figure 7As shown, device 700 also includes a plurality of solder pad interconnects 607 and a plurality of solder pad interconnects 707. The plurality of solder pad interconnects 607 are coupled to a plurality of interconnects 163. The plurality of solder pad interconnects 707 are coupled to a plurality of interconnects 161. A plurality of solder interconnects 107 are coupled to the plurality of interconnects 161 and the plurality of interconnects 163. In some embodiments, the plurality of solder pad interconnects 707 may be considered as part of a first device portion 101. In some embodiments, the plurality of solder pad interconnects 607 may be considered as part of a second device portion 102.

[0048] Multiple interconnects 121, multiple interconnects 131, multiple via interconnects 141, multiple interconnects 151, multiple interconnects 161, multiple solder interconnects 707, multiple solder interconnects 107, multiple solder interconnects 607, multiple interconnects 163, multiple via interconnects 143, multiple interconnects 133, and / or multiple interconnects 123 may be configured to operate as an inductor 703 (e.g., a solenoid inductor). For example, at least a portion of multiple interconnects 121, multiple interconnects 131, multiple via interconnects 141, multiple interconnects 151, multiple interconnects 161, multiple solder interconnects 707, multiple solder interconnects 107, multiple solder interconnects 607, multiple interconnects 163, multiple via interconnects 143, multiple interconnects 133, and / or multiple interconnects 123 may be defined as windings of inductor 703 (e.g., windings of a solenoid inductor).

[0049] Figure 8 and 9 An exemplary graph of inductance and Q factor of an inductor formed from a stacked device portion having via interconnects is shown. Figure 8 An exemplary graph 800 is illustrated, which includes plotted lines for the inductance of inductor 103 at various frequencies. Figure 9 An exemplary graph 900 is illustrated, which includes plotted lines for the Q factor of inductor 103 across various frequencies.

[0050] As mentioned above, one or more encapsulation layers of the device may include magnetic layers. For example, encapsulation layer 140 and / or encapsulation layer 142 may include at least one magnetic layer. Magnetic layers include insulating layers, dielectric layers, and / or non-conductive materials (e.g., non-conductive materials). Magnetic layers may be both dielectric and magnetic materials. Therefore, magnetic layers may have both dielectric and magnetic properties. Magnetic layers may include one or more materials. Magnetic layers have a permeability value greater than 1 (e.g., about 10 or greater, ranging from 6 to 20). Magnetic layers may have different permeability values ​​at different frequencies. As described in this disclosure, the permeability value of the magnetic material and / or magnetic layer is a relative permeability value, defined as the ratio of the material's permeability to the permeability of free space. Therefore, the permeability values ​​described for the magnetic materials and / or magnetic layers exemplified and / or described in this disclosure may represent relative permeability values ​​relative to a defined permeability value in free space (e.g., a reference permeability value). In some specific implementations, free space can be defined as having μ 0 = 4π × 10 -7 The defined permeability value is H / m (Henry per meter). Materials with a relative permeability value greater than 1 can be considered magnetic materials. Similarly, a material layer with a relative permeability value greater than 1 can be considered a magnetic layer. Magnetic layers may include a magnetic loss tangent in the range of about 0.01 to 0.04. For example, at least one magnetic layer may include a magnetic loss tangent in the range of about 0.01-0.04 for frequencies up to 100 MHz. Magnetic layers may include various magnetic materials. For example, a magnetic layer may include Ajinomoto Magnetic Film (AMF). Magnetic layers may be configured to improve the inductance and / or quality factor of an inductor located in and / or surrounded by at least one magnetic layer. With the improvement of inductor performance, smaller and more compact inductors can be formed in integrated passive devices and / or integrated devices. Any device described in this disclosure (e.g., 100, 200, 300, 400, 500, 600, 700) may be implemented as a passive device (e.g., a discrete passive device) and / or an integrated passive device.

[0051] In some embodiments, any device or device portion of the devices or device sections of this disclosure may be implemented as an integrated device. An integrated device may include a die (e.g., a bare semiconductor die). An integrated device may include a power management integrated circuit (PMIC). An integrated device may include an application processor. An integrated device may include a modem. An integrated device may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs)-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, memories, power management processors, and / or combinations thereof. An integrated device may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). An integrated device may include transistors. An integrated device may be an example of electronic components and / or electronic devices. In some embodiments, an integrated device may include a chiplet. Chipslets can be manufactured using processes that provide better yields compared to other processes used to manufacture other types of integrated devices, which can reduce the overall cost of manufacturing chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or pitches). In some implementations, several chiplets may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). Using several chiplets that perform several functions can reduce the overall cost of the package compared to using a single chip to perform all the functions of the package. Example process for fabricating device portions

[0052] Figures 10A-10D Exemplary steps for providing or manufacturing parts of a device are illustrated. In some specific implementations, Figures 10A-10D The processes described herein can be used to provide or manufacture any device portion of the device portion described in this disclosure. In some specific embodiments, Figures 10A-10D The process can be used to provide or manufacture the first device portion 101 described in this disclosure.

[0053] It should be noted that Figures 10A-10D The processes may be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture device parts. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more of these processes may be substituted or replaced without departing from the spirit of this disclosure. Different embodiments may manufacture device parts in different ways. Figures 10A-10D The processes shown can be performed on a wafer (e.g., a silicon wafer) and subsequently divided into several device portions.

[0054] like Figure 10A As shown, stage 1 illustrates the state after the die substrate 110 has been provided. The die substrate 110 may include silicon (Si). Providing the die substrate 110 may include providing a wafer (e.g., a silicon wafer). In some embodiments, the die substrate 110 may be provided with a plurality of filters and / or transistors.

[0055] Phase 2 illustrates the state after a plurality of interconnects 121 have been formed on the die substrate 110. Plating and patterning processes can be used to form the plurality of interconnects 121.

[0056] Stage 3 illustrates the state after the encapsulation layer 120 is formed. The encapsulation layer 120 can be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. The encapsulation layer 120 can at least partially encapsulate a plurality of interconnects 121. The encapsulation layer 120 may include molding materials, resins, and / or epoxy resins.

[0057] Stage 4 illustrates the state after a plurality of interconnects 1031 have been formed on the encapsulation layer 120. The plurality of interconnects 1031 can be coupled to the plurality of interconnects 121. Plating and patterning processes can be used to form the plurality of interconnects 1031.

[0058] like Figure 10B As shown, stage 5 illustrates the state after at least one dielectric layer 130 has been formed and patterned. At least one dielectric layer 130 can be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. At least one dielectric layer 130 may be formed over encapsulation layer 120. At least one dielectric layer 130 may include at least one via 1032.

[0059] Phase 6 illustrates the state after the formation of a plurality of interconnects 1033. Plating and patterning processes can be used to form the plurality of interconnects 1033. Forming the plurality of interconnects 1033 may include forming via interconnects in at least one via 1032 of at least one dielectric layer 130. The plurality of interconnects 1033 may be coupled to a plurality of interconnects 1031. The plurality of interconnects 1031 and the plurality of interconnects 1033 may represent a plurality of interconnects 131.

[0060] Stage 7 illustrates the state after the formation of multiple via interconnects 141. Plating and patterning processes can be used to form the multiple interconnects 141. The multiple interconnects 141 can be coupled to multiple interconnects 131.

[0061] like Figure 10CAs shown, stage 8 illustrates the state after the encapsulation layer 140 is formed over the dielectric layer 130. The encapsulation layer 140 can be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. The encapsulation layer 140 may at least partially encapsulate a plurality of via interconnects 141. The encapsulation layer 140 may include molding materials, resins, and / or epoxy resins. The encapsulation layer 140 may include a magnetic layer. In some embodiments, the encapsulation layer includes a magnetic layer. In some embodiments, a printing process can be used to form a paste for the magnetic layer.

[0062] Stage 9 illustrates the state after at least one dielectric layer 150 has been formed and patterned. At least one dielectric layer 150 can be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. At least one dielectric layer 150 may be formed over an encapsulation layer 140. At least one dielectric layer 150 may include at least one via 1052.

[0063] like Figure 10D As shown, stage 10 illustrates the state after the formation of a plurality of interconnects 151. Plating and patterning processes can be used to form the plurality of interconnects 151. Forming the plurality of interconnects 151 may include forming via interconnects in at least one via 1052 of at least one dielectric layer 150. The plurality of interconnects 151 may be coupled to a plurality of via interconnects 141.

[0064] Phase 10 also illustrates the state after a plurality of interconnects 161 have been formed on the dielectric layer 150. The plurality of interconnects 161 can be coupled to the plurality of interconnects 151. Plating and patterning processes can be used to form the plurality of interconnects 161.

[0065] Stage 11 illustrates the state after at least one dielectric layer 160 has been formed and patterned. At least one dielectric layer 160 can be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. At least one dielectric layer 160 may be formed over dielectric layer 150. At least one dielectric layer 160 may include at least one opening 1062. Stage 11 may illustrate a first device portion 101.

[0066] As mentioned above, the above processes can be performed on a wafer (e.g., a silicon wafer) to simultaneously form several device portions, and then the wafer can be diced to form individual device portions. The above processes can be manufactured in one facility or at several facilities. Example process for fabricating device portions

[0067] Figure 11 Exemplary steps for providing or manufacturing a device portion including solder post interconnects are illustrated. In some specific embodiments, Figure 11The processes described herein can be used to provide or manufacture any device portion of the device portion described in this disclosure. In some specific embodiments, Figure 11 The process can be used to provide or manufacture the second device portion 102 described in this disclosure.

[0068] It should be noted that Figure 11 The processes can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture device parts. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the spirit of this disclosure. Different embodiments can manufacture device parts in different ways. Figure 11 The processes shown can be performed on a wafer (e.g., a silicon wafer) and subsequently divided into several device portions.

[0069] like Figure 11 As shown, stage 1 illustrates the state of manufacturing or providing a device portion (e.g., 102) after the die substrate 110 has been provided. In some specific embodiments, the device portion 102 may be a... Figures 10A-10D It is manufactured using advanced technology.

[0070] like Figure 11 As shown, stage 2 illustrates the state after the formation of multiple bond interconnects 607. The multiple bond interconnects 607 can be formed using plating and patterning processes. The multiple bond interconnects 607 can be coupled to multiple interconnects 163. Stage 2 can also illustrate a second device portion 102 including the multiple bond interconnects. Example flowchart of a method for fabricating device portions

[0071] In some specific implementations, the manufacturing of the device includes several processes. Figure 12 An exemplary flowchart illustrating a method 1200 for providing or manufacturing a component is shown. In some specific implementations, Figure 12 Method 1200 can be used to provide or manufacture a first device portion 101, a second device portion 102, or any device portion of a device portion. Method 1200 can be implemented on a wafer (e.g., a silicon wafer) and subsequently diced into several device portions.

[0072] It should be noted that Figure 12 Method 1200 may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture part of a device. In some specific implementations, the order of the processes may be changed or modified.

[0073] The method (at 1205) provides a die substrate (e.g., 110). The die substrate 110 may include silicon (Si). The die substrate 110 may include a wafer (e.g., a silicon wafer). Figure 10APhase 1 illustrates and describes an example of the state after the die substrate 110 has been provided. The die substrate 110 may include silicon (Si). Providing the die substrate 110 may include providing a wafer (e.g., a silicon wafer). In some specific embodiments, the die substrate 110 may be provided with a plurality of filters and / or transistors.

[0074] The method (at 1210) forms a plurality of interconnects, an encapsulation layer and at least one dielectric layer. Figure 10A Phase 2 to Figure 10B Stage 6 illustrates an example of forming multiple interconnects, an encapsulation layer, and at least one dielectric layer.

[0075] Figure 10A Stage 2 illustrates and describes an example of the state after a plurality of interconnects 121 have been formed on the die substrate 110. Plating and patterning processes can be used to form the plurality of interconnects 121.

[0076] Figure 10A Stage 3 illustrates and describes an example of the state after the formation of the encapsulation layer 120. The encapsulation layer 120 can be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. The encapsulation layer 120 may at least partially encapsulate a plurality of interconnects 121. The encapsulation layer 120 may include molding materials, resins, and / or epoxy resins.

[0077] Figure 10A Stage 4 illustrates and describes an example of the state after multiple interconnects 1031 are formed on the encapsulation layer 120. Multiple interconnects 1031 can be coupled to multiple interconnects 121. Plating and patterning processes can be used to form the multiple interconnects 1031.

[0078] Figure 10B Stage 5 illustrates and describes an example of the state after at least one dielectric layer 130 has been formed and patterned. At least one dielectric layer 130 can be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. At least one dielectric layer 130 may be formed over an encapsulation layer 120. At least one dielectric layer 130 may include at least one via 1032.

[0079] Figure 10B Stage 6 illustrates and describes an example of the state after the formation of a plurality of interconnects 1033. Plating and patterning processes can be used to form the plurality of interconnects 1033. Forming the plurality of interconnects 1033 may include forming via interconnects in at least one via 1032 of at least one dielectric layer 130. The plurality of interconnects 1033 may be coupled to a plurality of interconnects 1031. The plurality of interconnects 1031 and the plurality of interconnects 1033 may represent a plurality of interconnects 131.

[0080] This method (at 1215) forms multiple via interconnects. Figure 10B Stage 7 illustrates and describes an example of the state after the formation of multiple via interconnects 141. Plating and patterning processes can be used to form the multiple interconnects 141. The multiple interconnects 141 can be coupled to multiple interconnects 131.

[0081] The method (at 1220) forms an encapsulation layer that at least partially encapsulates a plurality of via interconnects. Figure 10C Stage 8 illustrates and describes an example of the state after the encapsulation layer 140 is formed over the dielectric layer 130. The encapsulation layer 140 can be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. The encapsulation layer 140 may at least partially encapsulate a plurality of via interconnects 141. The encapsulation layer 140 may include molding materials, resins, and / or epoxy resins. The encapsulation layer 140 may include a magnetic layer. In some embodiments, the encapsulation layer includes a magnetic layer. In some embodiments, a printing process can be used to form a paste for the magnetic layer.

[0082] This method (at 1225) forms a dielectric layer and multiple interconnects. Figure 10C Stage 9 illustrates and describes an example of the state after at least one dielectric layer 150 has been formed and patterned. At least one dielectric layer 150 can be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. At least one dielectric layer 150 may be formed over an encapsulation layer 140. At least one dielectric layer 150 may include at least one via 1052.

[0083] Figure 10D Stage 10 illustrates and describes an example of the state after the formation of a plurality of interconnects 151. Plating and patterning processes may be used to form the plurality of interconnects 151. Forming the plurality of interconnects 151 may include forming via interconnects in at least one via 1052 of at least one dielectric layer 150. The plurality of interconnects 151 may be coupled to a plurality of via interconnects 141.

[0084] Figure 10D Stage 10 illustrates and describes an example of the state after a plurality of interconnects 161 have been formed on the dielectric layer 150. The plurality of interconnects 161 can be coupled to the plurality of interconnects 151. Plating and patterning processes can be used to form the plurality of interconnects 161.

[0085] Figure 10DStage 11 illustrates and describes an example of the state after at least one dielectric layer 160 has been formed and patterned. At least one dielectric layer 160 may be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. At least one dielectric layer 160 may be formed over dielectric layer 150. At least one dielectric layer 160 may include at least one opening 1062.

[0086] This method (at 1230) forms multiple solder post interconnects coupled to multiple interconnects. Figure 11 Phase 2 illustrates and describes an example of the state after the formation of multiple solder interconnects 607. Multiple solder interconnects 607 can be formed using plating and patterning processes. Multiple solder interconnects 607 can be coupled to multiple interconnects 163.

[0087] As mentioned above, the device portion can be manufactured as part of a chip that includes several device portions. Example process for fabricating a device including stacked device portions

[0088] Figures 13A-13F Exemplary steps for providing or manufacturing a device including stacked device portions are illustrated. In some specific embodiments, Figures 13A-13F The processes described herein can be used to provide or manufacture any of the devices described herein. In some embodiments, the processes 13A to 13F can be used to provide or manufacture the device 300 described herein.

[0089] It should be noted that the processes 13A to 13F may be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture the device. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more of these processes may be substituted or replaced without departing from the spirit of this disclosure. Different embodiments may manufacture the device in different ways. Figures 13A-13F The processes shown can be performed on a wafer (e.g., a silicon wafer) and subsequently diced into several devices.

[0090] like Figure 13A As shown, stage 1 illustrates the state after the manufacture and / or provision of the first device portion 101. Figures 10A-10D An example of the process used to manufacture the parts of the device is shown.

[0091] Phase 2 illustrates the state after the passive component 301 is coupled to the first device portion 101 via a plurality of solder interconnects 310. A solder reflow process can be used to couple the passive component 301 to the plurality of interconnects 161 of the first device portion 101.

[0092] like Figure 13BAs shown, stage 3 illustrates the state in which the second device portion 102 is coupled to the first device portion 101. Figures 10A-10D An example of a process for manufacturing a second device portion is illustrated. The second device portion 102 includes a die substrate 110. The second device portion 102 may also include a plurality of solder interconnects 607. The plurality of solder interconnects 607 are coupled to a plurality of solder interconnects 107. The plurality of solder interconnects 107 are coupled to a plurality of interconnects 161. A solder reflow process can be used to couple the second device portion 102 to the first device portion 101 via the plurality of solder interconnects 607 and the plurality of solder interconnects 107.

[0093] like Figure 13C As shown, stage 4 illustrates the state after the encapsulation layer 170 is formed over the first device portion 101 and the second device portion 102. The encapsulation layer 170 can be formed and provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. The encapsulation layer 170 can be coupled to the surface of the first device portion 101. The encapsulation layer 170 can at least partially encapsulate the passive component 301, the plurality of solder interconnects 607, the plurality of solder interconnects 107, and the second device portion 102. The encapsulation layer 170 can be overmolded over the second device portion 102.

[0094] like Figure 13D As shown, stage 5 illustrates the state after the removal of a portion of the encapsulation layer 170 and a portion of the second device portion 102. For example, grinding and / or polishing processes can be used to remove portions of the die substrate 110 and the encapsulation layer 170 of the second device portion 102, exposing the encapsulation layer 122 and a plurality of interconnects 123.

[0095] like Figure 13E As shown, stage 6 illustrates the state after the dielectric layer 112 is formed over encapsulation layers 122 and 170. It should be noted that in some embodiments, encapsulation layers 122 and 170 may be identical or similar. Openings may be present in the dielectric layer 112. Deposition, lamination, exposure, development, and / or etching processes may be used to form and pattern the dielectric layer 112. In some embodiments, the dielectric layer 112 may be a solder resist layer.

[0096] like Figure 13F As shown, stage 7 illustrates the state after multiple solder interconnects are coupled to multiple interconnects 123. A solder reflow process can be used to couple multiple solder interconnects 109 to multiple interconnects 123. Multiple solder interconnects 123 can be coupled to multiple interconnects 123 through openings in the dielectric layer 112. Stage 7 can illustrate a device 300 including a stacked device portion with via interconnects. Example flowchart of a method for fabricating a device having stacked device portions

[0097] In some specific implementations, manufacturing a device that includes stacked device components involves several processes. Figure 14 An exemplary flowchart illustrating a method 1400 for providing or manufacturing a device including stacked device portions is shown. In some specific implementations, it is possible to use... Figure 14 Method 1400 is used to provide or manufacture device 300. Method 1400 may be implemented on a wafer (e.g., a silicon wafer) and subsequently diced into several integrated devices.

[0098] It should be noted that Figure 14 Method 1400 may combine one or more processes to simplify and / or clarify the methods for providing or manufacturing a device including stacked device portions. For example, one or more processes in method 1400 may include one or more processes in method 1200. In some embodiments, the order of the processes may be changed or modified.

[0099] This method (at 1405) provides a first device portion. Figure 13A Phase 1 illustrates and describes an example of the state after the manufacture and / or delivery of the first device part 101. Figures 10A-10D An example of the process used to manufacture the parts of the device is shown.

[0100] This method (at 1410) couples a passive component to the device portion. Figure 13A Phase 2 illustrates and describes an example of the state after the passive component 301 is coupled to the first device portion 101 via a plurality of solder interconnects 310. A solder reflow process can be used to couple the passive component 301 to the plurality of interconnects 161 of the first device portion 101.

[0101] This method (at 1415) couples the second device portion to the first device portion. Figure 13B Phase 3 illustrates and describes an example of the state in which the second device portion 102 is coupled to the first device portion 101. Figures 10A-10D An example of a process for manufacturing a second device portion is illustrated. The second device portion 102 includes a die substrate 110. The second device portion 102 may also include a plurality of solder interconnects 607. The plurality of solder interconnects 607 are coupled to a plurality of solder interconnects 107. The plurality of solder interconnects 107 are coupled to a plurality of interconnects 161. A solder reflow process can be used to couple the second device portion 102 to the first device portion 101 via the plurality of solder interconnects 607 and the plurality of solder interconnects 107.

[0102] The method forms an encapsulation layer on top of the first device portion and the second device portion (at 1420). Figure 13CStage 4 illustrates and describes an example of the state after the encapsulation layer 170 is formed over the first device portion 101 and the second device portion 102. The encapsulation layer 170 can be formed and provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. The encapsulation layer 170 may be coupled to the surface of the first device portion 101. The encapsulation layer 170 may at least partially encapsulate the passive component 301, the plurality of solder interconnects 607, the plurality of solder interconnects 107, and the second device portion 102. The encapsulation layer 170 may be overmolded over the second device portion 102.

[0103] This method (at 1425) removes a portion of the encapsulation layer and a portion of the second device portion. Figure 13D Phase 5 illustrates and describes an example of the state after the removal of portions of the encapsulation layer 170 and the second device portion 102. For example, grinding and / or polishing processes may be used to remove portions of the die substrate 110 and the encapsulation layer 170 of the second device portion 102, exposing the encapsulation layer 122 and the plurality of interconnects 123.

[0104] This method forms a dielectric layer (at 1430). Figure 13E Stage 6 illustrates and describes an example of the state after the dielectric layer 112 is formed over encapsulation layers 122 and 170. It should be noted that in some embodiments, encapsulation layers 122 and 170 may be identical or similar. Openings may be present in the dielectric layer 112. Deposition, lamination, exposure, development, and / or etching processes may be used to form and pattern the dielectric layer 112. In some embodiments, the dielectric layer 112 may be a solder resist layer.

[0105] This method (at 1435) couples multiple solder interconnects to a second device portion. Figure 13F Phase 7 illustrates and describes an example of the state after multiple solder interconnects are coupled to multiple interconnects 123. A solder reflow process can be used to couple multiple solder interconnects 109 to multiple interconnects 123. Multiple solder interconnects 123 can be coupled to multiple interconnects 123 through openings in the dielectric layer 112. Phase 7 may illustrate a device 300 including a stacked device portion with via interconnects. Example electronic device

[0106] Figure 15Examples of various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-in-packages (SiP), or system-on-a-chip (SoC) are illustrated. For example, mobile phone device 1502, laptop computer device 1504, fixed-location terminal device 1506, wearable device 1508, or motor vehicle 1510 may include device 1500 as described herein. For example, device 1500 may be any of the devices and / or integrated circuit (IC) packages described herein. Figure 15 The devices 1502, 1504, 1506, and 1508 illustrated herein, as well as vehicle 1510, are merely exemplary. Other electronic devices may also feature device 1500, including, but not limited to, a group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0107] Figures 1-9 , Figures 10A-10D , Figure 11 , Figure 12 , Figures 13A-13F and / or Figures 14-15 One or more of the illustrated components, processes, features, and / or functions may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that... Figures 1-9 , Figures 10A-10D , Figure 11 , Figure 12 , Figures 13A-13F and / or Figures 14-15 The corresponding descriptions herein are not limited to dies and / or ICs. In some specific implementations, Figures 1-9 , Figures 10A-10D , Figure 11 , Figure 12 , Figures 13A-13F and / or Figures 14-15 Figures 1-9 Figures 10A-10D Figure 11 Figure 12 Figures 13A-13F Figures 14-15The descriptions and their corresponding information can be used to manufacture, create, supply, and / or produce devices and / or integrated devices. In some specific implementations, devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices, and / or interposers.

[0108] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some specific embodiments, the various components and / or parts in the drawings may be optional.

[0109] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any specific implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. The term “electrically coupled” can mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can travel between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term "enclosing" means that an object can partially enclose or completely enclose another object. A first component "located" within a second component can mean that the first component is "partially located" within or "completely located" within the second component. A first component "embedded" within a second component can mean that the first component is "partially embedded" within or "completely embedded" within the second component. The terms "top" and "bottom" are arbitrary. A component located at the top can be above a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component located "above" a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component can be located above (e.g., above) a first surface of a second component, and a third component can be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term “above” as used in this application in the context of one component being above another component can be used to mean that a component is on and / or in another component (e.g., on the surface of the component or embedded in the component). Thus, for example, “above a second component” can mean: (1) the first component is above the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located “in” the second component can be partially or completely located in the second component. As used in this disclosure, the terms “about 'value X'” or “approximately value X” mean within 10% of “value X”.For example, a value of approximately 1 or roughly 1 would mean a value in the range of 0.9 to 1.1.

[0110] In some embodiments, an interconnect is an element or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some embodiments, an interconnect may include traces, vias, pads, solder pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0111] It should also be noted that the various disclosures contained herein can be described as processes depicted as work diagrams, flowcharts, structural diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. The process terminates when its operations are completed.

[0112] Further examples are described below to facilitate understanding of this disclosure.

[0113] Aspect 1: A device (e.g., a passive device, an integrated passive device) comprising: a first device portion (e.g., a first passive device portion), the first device portion comprising: a die substrate; at least one first dielectric layer; a first plurality of interconnects; a first encapsulation layer; and a first plurality of via interconnects, the first plurality of via interconnects being at least located in the first encapsulation layer; a second device portion (e.g., a second passive device portion), the second device portion comprising: at least one second dielectric layer; a second plurality of interconnects; a second encapsulation layer; and a second plurality of via interconnects, the second plurality of via interconnects being at least located in the second encapsulation layer; and a first plurality of solder interconnects, the first plurality of solder interconnects being coupled to the first device portion and the second device portion, wherein the first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects and the second plurality of via interconnects are configured to operate as inductors.

[0114] Aspect 2: The device according to aspect 1, wherein the first encapsulation layer comprises a magnetic layer or an epoxy resin mold, and / or wherein the second encapsulation layer comprises a magnetic layer or an epoxy resin mold.

[0115] Aspect 3: The device according to aspect 2, wherein the magnetic layer comprises an insulating layer and / or a dielectric layer, wherein the magnetic layer comprises a non-conductive material, and wherein the magnetic layer has a relative permeability value greater than 1.

[0116] Aspect 4: The device according to aspects 1 to 3, wherein the first device portion is a first passive device portion, and wherein the second device portion is a second passive device portion.

[0117] Aspect 5: The device according to aspects 1 to 4, wherein the die substrate includes a plurality of filters.

[0118] Aspect 6: The device according to aspect 5, wherein the device includes an acoustic device.

[0119] Aspect 7: The device according to aspects 1 to 6, wherein the first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects and the second plurality of via interconnects are configured to operate as solenoid inductors.

[0120] Aspect 8: The device according to aspects 1 to 7, wherein the first plurality of interconnects includes a first plurality of first metallized interconnects and a second plurality of first metallized interconnects, and wherein the second plurality of interconnects includes a first plurality of second metallized interconnects and a second plurality of second metallized interconnects.

[0121] Aspect 9: The device according to aspect 8, wherein the first plurality of via interconnects are coupled to the first plurality of first metallized interconnects and the second plurality of first metallized interconnects, and wherein the second plurality of via interconnects are coupled to the first plurality of second metallized interconnects and the second plurality of second metallized interconnects.

[0122] Aspect 10: The device according to aspects 1 to 9, wherein the first plurality of solder interconnects are horizontally offset to the first plurality of via interconnects and the second plurality of via interconnects.

[0123] Aspect 11: The device according to aspects 1 to 10, the device further comprising a plurality of solder interconnects coupled to the first plurality of solder interconnects and the first plurality of interconnects.

[0124] Aspect 12: The device according to aspects 1 to 11, the device further comprising a plurality of solder interconnects coupled to the first plurality of solder interconnects and the second plurality of interconnects.

[0125] Aspect 13: The device according to aspects 1 to 10, the device further comprising: a first plurality of solder post interconnects coupled to the first plurality of solder interconnects and the first plurality of interconnects, and a second plurality of solder post interconnects coupled to the first plurality of solder interconnects and the second plurality of interconnects.

[0126] Aspect 14: The device according to aspects 1 to 13, the device further comprising a third encapsulation layer that at least partially encapsulates the second device portion and the first plurality of solder interconnects, wherein the third encapsulation layer is coupled to the surface of the first device portion.

[0127] Aspect 15: The device according to aspects 1 to 14, wherein the device is selected from the group consisting of: music player, video player, entertainment unit, navigation device, communication device, mobile device, mobile phone, smartphone, personal digital assistant, fixed-location terminal, tablet computer, computer, wearable device, laptop computer, server, Internet of Things (IoT) device and device in motor vehicle.

[0128] Aspect 16: A method for manufacturing a device (e.g., a passive device, an integrated passive device), the method comprising: providing a first device portion (e.g., a first passive device portion), the first device portion including: a die substrate; at least one first dielectric layer; a first plurality of interconnects; a first encapsulation layer; and a first plurality of via interconnects, the first plurality of via interconnects being at least located in the first encapsulation layer; coupling a second device portion (e.g., a second passive device portion) to the first device portion via a first plurality of solder interconnects, the second device portion including: at least one second dielectric layer; a second plurality of interconnects; a second encapsulation layer; and a second plurality of via interconnects, the second plurality of via interconnects being at least located in the second encapsulation layer, wherein the first plurality of solder interconnects are coupled to the first device portion and the second device portion, wherein the first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects and the second plurality of via interconnects are configured to operate as inductors.

[0129] Aspect 17: The method according to aspect 16, wherein the first encapsulation layer comprises a magnetic layer or an epoxy resin mold, and / or wherein the second encapsulation layer comprises a magnetic layer or an epoxy resin mold.

[0130] Aspect 18: The method according to aspects 16 to 17, the method further comprising forming a third encapsulation layer that at least partially encapsulates the second device portion and the first plurality of solder interconnects, wherein the third encapsulation layer is coupled to the surface of the first device portion.

[0131] Aspect 19: The method according to aspects 16 to 18, wherein the first device portion is a first passive device portion, and wherein the second device portion is a second passive device portion.

[0132] Aspect 20: According to the method of aspect 16, the die substrate includes a plurality of filters.

[0133] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be illustrative and not to limit the scope of the appended claims. Therefore, the teachings herein are readily applicable to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A device, the device comprising: The first device portion includes: die substrate; At least one first dielectric layer; The first multiple interconnects; First package seal; and A plurality of via interconnects, wherein the plurality of via interconnects are located at least within the first encapsulation layer; The second device portion includes: At least one second dielectric layer; Second, multiple interconnect components; Second pack sealing layer; and A second plurality of via interconnects, wherein the second plurality of via interconnects are at least located within the second encapsulation layer; and A plurality of solder interconnects coupled to the first device portion and the second device portion, wherein the plurality of interconnects, the plurality of via interconnects, the plurality of solder interconnects, the plurality of interconnects and the plurality of via interconnects are configured to operate as inductors.

2. The device according to claim 1, The first encapsulation layer includes a magnetic layer or an epoxy resin mold, and / or The second encapsulation layer includes a magnetic layer or an epoxy resin mold.

3. The device according to claim 2, The magnetic layer includes an insulating layer and / or a dielectric layer. The magnetic layer comprises a non-conductive material, and The magnetic layer has a relative permeability value greater than 1.

4. The device according to claim 1, The first device portion is the first passive device portion, and The second device part is the second passive device part.

5. The device according to claim 1, wherein the die substrate includes a plurality of filters.

6. The device according to claim 5, wherein the device includes an acoustic device.

7. The device of claim 1, wherein the first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects and the second plurality of via interconnects are configured to operate as solenoid inductors.

8. The device according to claim 1, The first plurality of interconnects includes a first plurality of first metallized interconnects and a second plurality of first metallized interconnects, and The second plurality of interconnects includes a first plurality of second metallized interconnects and a second plurality of second metallized interconnects.

9. The device according to claim 8, The first plurality of via interconnects are coupled to the first plurality of first metallized interconnects and the second plurality of first metallized interconnects, and The second plurality of via interconnects are coupled to the first plurality of second metallized interconnects and the second plurality of second metallized interconnects.

10. The device of claim 1, wherein the first plurality of solder interconnects are horizontally offset to the first plurality of via interconnects and the second plurality of via interconnects.

11. The device of claim 1, further comprising a plurality of solder interconnects coupled to the plurality of solder interconnects and the plurality of interconnects.

12. The device of claim 1, further comprising a plurality of solder post interconnects coupled to the first plurality of solder interconnects and the second plurality of interconnects.

13. The device according to claim 1, further comprising: First plurality of solder post interconnects, the first plurality of solder post interconnects being coupled to first plurality of solder interconnects and first plurality of interconnects, and The second plurality of solder post interconnects are coupled to the first plurality of solder interconnects and the second plurality of interconnects.

14. The device of claim 1, further comprising a third encapsulation layer that at least partially encapsulates the second device portion and the first plurality of solder interconnects, wherein the third encapsulation layer is coupled to a surface of the first device portion.

15. The device of claim 1, wherein the device is selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

16. A method for manufacturing a device, the method comprising: A first device portion is provided, the first device portion comprising: die substrate; At least one first dielectric layer; The first multiple interconnects; First package seal; and A plurality of via interconnects, wherein the plurality of via interconnects are located at least within the first encapsulation layer; and A second device portion is coupled to the first device portion via a first plurality of solder interconnects, the second device portion comprising: At least one second dielectric layer; Second, multiple interconnect components; Second pack sealing layer; and The second plurality of via interconnects, wherein the second plurality of via interconnects are located at least within the second encapsulation layer. The first plurality of solder interconnects are coupled to the first device portion and the second device portion, and The first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects, and the second plurality of via interconnects are configured to operate as inductors.

17. The method according to claim 16, The first encapsulation layer includes a magnetic layer or an epoxy resin mold, and / or The second encapsulation layer includes a magnetic layer or an epoxy resin mold.

18. The method of claim 16, further comprising forming a third encapsulation layer that at least partially encapsulates the second device portion and the first plurality of solder interconnects, wherein the third encapsulation layer is coupled to a surface of the first device portion.

19. The method according to claim 16, The first device portion is the first passive device portion, and The second device part is the second passive device part.

20. The method of claim 16, wherein the die substrate comprises a plurality of filters.

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