Near memory computing system and near memory computing method based on RISC-V instruction set

Abstract

The invention provides a near-memory computing system and a near-memory computing method based on an RISC-V instruction set, and belongs to the technical field of near-memory computing. The system comprises a control unit, an input and output driving module, an RISC-V calculation unit and a storage unit, wherein the RISC-V calculation unit and the storage unit are electrically connected with the control unit. The storage unit comprises a first magnetic storage array unit, a true random number generator, a second magnetic storage array unit and a secondary burning magnetic storage array unit. The magnetic tunnel junctions in the storage units are in-plane anisotropic devices and are elliptical. And the control unit is configured to control the RISC-V calculation unit and / or the storage unit to execute corresponding operation according to the received RISC-V instruction. According to the method, multiple MRAM arrays are integrated on the same wafer, and the near-memory calculation is operated based on the RISC-V calculation unit, so that the memory wall problem of the existing near-memory calculation is solved, and the energy efficiency and the calculation power of the near-memory calculation are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of near-memory computing, in particular to a near-memory computing system based on a RISC-V instruction set and a near-memory computing method. BACKGROUND

[0002] The Von Neumann architecture is the mainstream design paradigm of current computers and processor chips. In this architecture, the computing unit and the storage unit are separated from each other, the computing unit reads data from the memory, and after the operation is completed, the result is written back to the storage unit. This computing-centric structure requires frequent data transfer during execution. Although the main frequency and the number of computing cores continue to grow, the improvement of memory access speed is relatively lagging behind, resulting in the data bus throughput gradually becoming the performance bottleneck of the system, i.e., causing the so-called "memory wall" problem.

[0003] In related technologies, RISC-V is an open and free instruction set architecture (ISA) based on the principle of reduced instruction set (RISC). The emergence and development of RISC-V is a major paradigm shift in the field of computing architecture. However, the RISC-V architecture also follows the Von Neumann system, and therefore also faces the same memory wall problem. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a near-memory computing system based on a RISC-V instruction set and a near-memory computing method, aiming to solve the memory wall problem of existing near-memory computing.

[0005] In order to achieve the above-mentioned purpose, the embodiments of the present application provide a near-memory computing system based on a RISC-V instruction set, which comprises a control unit, an input-output driving module, a RISC-V computing unit and a storage unit electrically connected to the control unit. The storage unit comprises a first magnetic storage array unit, a true random number generator, a second magnetic storage array unit and a twice-programmable magnetic storage array unit. The input-output driving module is electrically connected to the second magnetic storage array unit and the twice-programmable magnetic storage array unit. Wherein, the magnetic tunnel junctions in the first magnetic storage array unit, the true random number generator, the second magnetic storage array unit and the twice-programmable magnetic storage array unit are all in-plane anisotropic devices, and are all elliptical. The control unit is configured to, after receiving a RISC-V instruction, control the RISC-V computing unit and / or the storage unit to perform corresponding operations according to the received RISC-V instruction.

[0006] In an optional embodiment, the aspect ratio of the magnetic tunnel junctions in the first magnetic storage array unit, the true random number generator, the second magnetic storage array unit, and the reprogrammable magnetic storage array unit is in descending order of the aspect ratio of the second magnetic storage array unit, the aspect ratio of the first magnetic storage array unit, the aspect ratio of the true random number generator, and the aspect ratio of the reprogrammable magnetic storage array unit.

[0007] In an optional embodiment, the reprogrammable magnetic storage array unit is configured to store encrypted data, and the true random number generator is configured to generate random numbers after calibration of the encrypted data.

[0008] In an optional embodiment, the RISC-V computing unit includes 2x RISC-V computing subunits, and the first magnetic storage array unit includes 2x+1 magnetic storage subunits, wherein adjacent magnetic storage subunits share the same RISC-V computing subunit, and adjacent RISC-V computing subunits share the same magnetic storage subunit, to realize multi-core parallel operation of near-memory computing. Here, x is a natural number.

[0009] In an optional embodiment, the control unit is further configured to perform computer program space division on RISC-V instructions, to control the RISC-V computing unit and / or the storage unit to perform corresponding operations by matching the received RISC-V instructions with corresponding computer program space division.

[0010] In an optional embodiment, the control of the RISC-V computing unit and / or the storage unit to perform corresponding operations according to the received RISC-V instructions includes: importing the programming data of the reprogrammable magnetic storage array unit into the true random number generator, calibrating the true random number generator, and sending a random data stream to the RISC-V computing unit, or importing data into the second magnetic storage array unit through the input / output driving module, requesting data from the second magnetic storage array unit by the RISC-V computing unit, and importing corresponding first magnetic storage array units; controlling the RISC-V computing unit to perform near-memory computing; exporting the calculated data to the corresponding first magnetic storage array unit; exporting the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage; and exporting the data temporarily stored in the second magnetic storage array unit to the input / output driving module.

[0011] In an optional embodiment, the near-memory computing system further includes an in-memory computing unit electrically connected to the RISC-V computing unit, the true random number generator, and the control unit, and the in-memory computing unit is configured to realize multiple near-memory computing modes.

[0012] In an optional implementation, controlling the RISC-V computing unit and / or the storage unit to perform corresponding operations according to the received RISC-V instructions includes: importing the programming data of the reprogrammable magnetic storage array unit into the true random number generator, calibrating the true random number generator, and sending a random data stream to the RISC-V computing unit and the in-memory computing unit; or importing the data into the second magnetic storage array unit through the input / output driver module, causing the RISC-V computing unit to request data from the second magnetic storage array unit and import it into the corresponding in-memory computing unit; controlling the in-memory computing unit to perform a first near-memory calculation; controlling the RISC-V computing unit to request the calculated data from the in-memory computing unit and import it into the corresponding first magnetic storage array unit; controlling the RISC-V computing unit to perform a second near-memory calculation; exporting the calculated data to the corresponding first magnetic storage array unit; exporting the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage; and exporting the data temporarily stored in the second magnetic storage array unit to the input / output driver module.

[0013] In an optional implementation, controlling the RISC-V computing unit and / or the storage unit to perform corresponding operations according to the received RISC-V instructions includes: importing the programming data of the reprogrammable magnetic storage array unit into the true random number generator, calibrating the true random number generator, and sending a random data stream to the RISC-V computing unit and the in-memory computing unit; or importing data into the second magnetic storage array unit through the input / output driver module, causing the RISC-V computing unit to request data from the second magnetic storage array unit and importing it into the corresponding first magnetic storage array unit and in-memory computing unit; controlling the RISC-V computing unit and the in-memory computing unit to perform near-memory computation; exporting the computed data to the corresponding first magnetic storage array unit; exporting the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage; and exporting the data temporarily stored in the second magnetic storage array unit to the input / output driver module.

[0014] This invention also provides a near-memory computing method based on the RISC-V instruction set. The near-memory computing method is applied to the control unit of the aforementioned near-memory computing system. The near-memory computing method includes: receiving RISC-V instructions; and controlling the RISC-V computing unit and / or the memory unit to perform corresponding operations according to the received RISC-V instructions.

[0015] In an optional implementation, controlling the RISC-V computing unit and / or the storage unit to perform corresponding operations according to the received RISC-V instructions includes: importing the programming data of the reprogrammable magnetic storage array unit into the true random number generator, calibrating the true random number generator, and sending a random data stream to the RISC-V computing unit; or importing the data into the second magnetic storage array unit through the input / output driver module, causing the RISC-V computing unit to request data from the second magnetic storage array unit and import it into the corresponding first magnetic storage array unit; controlling the RISC-V computing unit to perform near-memory computation; exporting the computed data to the corresponding first magnetic storage array unit; exporting the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage; and exporting the data temporarily stored in the second magnetic storage array unit to the input / output driver module.

[0016] In an optional implementation, the near-memory computing system further includes an in-memory computing unit. The step of controlling the RISC-V computing unit and / or the memory unit to perform corresponding operations according to the received RISC-V instructions includes: importing the programming data of the reprogrammable magnetic storage array unit into the true random number generator, calibrating the true random number generator, and sending a random data stream to the RISC-V computing unit and the in-memory computing unit; or importing data into the second magnetic storage array unit through the input / output driver module, causing the RISC-V computing unit to request data from the second magnetic storage array unit and import it into the corresponding in-memory computing unit; controlling the in-memory computing unit to perform a first near-memory calculation; controlling the RISC-V computing unit to request the calculated data from the in-memory computing unit and import it into the corresponding first magnetic storage array unit; controlling the RISC-V computing unit to perform a second near-memory calculation; exporting the calculated data to the corresponding first magnetic storage array unit; exporting the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage; and exporting the data temporarily stored in the second magnetic storage array unit to the input / output driver module.

[0017] In an optional implementation, the near-memory computing system further includes an in-memory computing unit. The step of controlling the RISC-V computing unit and / or the memory unit to perform corresponding operations according to the received RISC-V instructions includes: importing the programming data of the reprogrammable magnetic storage array unit into the true random number generator, calibrating the true random number generator, and sending a random data stream to the RISC-V computing unit and the in-memory computing unit; or importing data into the second magnetic storage array unit through the input / output driver module, causing the RISC-V computing unit to request data from the second magnetic storage array unit and importing it into the corresponding first magnetic storage array unit and the in-memory computing unit; controlling the RISC-V computing unit and the in-memory computing unit to perform near-memory computing; exporting the calculated data to the corresponding first magnetic storage array unit; exporting the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage; and exporting the data temporarily stored in the second magnetic storage array unit to the input / output driver module.

[0018] The near-memory computing system provided by the above technical solutions can include a control unit, an input / output driver module, a RISC-V computing unit electrically connected to the control unit, and a storage unit. The storage unit can include a first magnetic storage array unit, a true random number generator, a second magnetic storage array unit, and a reprogrammable magnetic storage array unit. The input / output driver module is electrically connected to the second magnetic storage array unit and the reprogrammable magnetic storage array unit. The magnetic tunnel junctions in the first magnetic storage array unit, the true random number generator, the second magnetic storage array unit, and the reprogrammable magnetic storage array unit are all in-plane anisotropic devices and are all elliptical. The control unit can be configured to, upon receiving RISC-V instructions, control the RISC-V computing unit and / or the storage unit to perform corresponding operations based on the received RISC-V instructions. This invention, by integrating multiple MRAM arrays on the same wafer and running near-memory computing based on RISC-V computing units, solves the memory wall problem of existing near-memory computing and improves the energy efficiency and computing power of near-memory computing; the multiple MRAM arrays use the same manufacturing process, which simplifies the process flow.

[0019] Other features and advantages of the embodiments of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0020] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0021] Figure 1This is a schematic diagram of the near-memory computing system based on the RISC-V instruction set provided in an embodiment of the present invention. Figure 1 ;

[0022] Figure 2A This is a top view of an example SOT-MTJ device;

[0023] Figure 2B This is a front view of an example SOT-MTJ device;

[0024] Figure 2C This is a schematic diagram of an example SOT-MTJ device;

[0025] Figure 3 This is a schematic diagram of the core structure of the near-memory computing system provided in an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of the control flow of the near-memory computing system provided in the embodiments of the present invention. Figure 1 ;

[0027] Figure 5 This is a schematic diagram of the near-memory computing system based on the RISC-V instruction set provided in an embodiment of the present invention.

[0028] Figure 6 This is a schematic diagram of the control flow of the near-memory computing system provided in an embodiment of the present invention; and

[0029] Figure 7 This is a schematic diagram of the control flow of the near-memory computing system provided in the embodiments of the present invention. Figure 3 . Detailed Implementation

[0030] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.

[0031] As mentioned earlier, the RISC-V architecture, following the von Neumann architecture, faces the memory wall challenge. This problem becomes particularly pronounced when handling data-intensive computational tasks such as artificial neural networks. Therefore, in near-memory computing architectures, issues that need to be addressed include: how to shorten the physical and logical distance between storage and computation units, reducing the frequency of memory access during computation; and maintaining the flexibility and scalability of the architecture to adapt to the diverse and dynamically evolving deployment needs of future neural network algorithms and other signal processing applications. Therefore, this invention provides a near-memory computing system based on the RISC-V instruction set to address the aforementioned technical problems.

[0032] Figure 1This is a schematic diagram of a near-memory computing system based on the RISC-V instruction set provided in an embodiment of the present invention. The near-memory computing system may include a control unit, an input / output driver module, a RISC-V computing unit electrically connected to the control unit, and a storage unit. The storage unit may include a first magnetic storage array unit, a SOT-MTJ true random number generator, a second magnetic storage array unit, and a reprogrammable magnetic storage array unit. The input / output driver module is electrically connected to the second magnetic storage array unit and the reprogrammable magnetic storage array unit. In this embodiment, the magnetic tunnel junctions in the first magnetic storage array unit, the true random number generator, the second magnetic storage array unit, and the reprogrammable magnetic storage array unit are all in-plane anisotropic devices and are all elliptical. The control unit can be configured to, upon receiving a RISC-V instruction, control the RISC-V computing unit and / or the storage unit to perform corresponding operations according to the received RISC-V instruction.

[0033] Please refer to Figure 1 In the near-memory computing system (on the wafer) provided in the embodiments of the present invention, the storage unit may include an integrated array of multiple non-volatile magnetic random access memory (MRAM) arrays, which may include a first magnetic storage array unit, a second magnetic storage array unit, a true random number generator (TRNG) and a reprogrammable magnetic storage array unit (TTP array unit). In this embodiment of the invention, the first magnetic storage array unit is a high-performance magnetic random-access memory (HP-MRAM) array unit, which can adopt a 4T-2SOT-MTJ cell structure, resulting in faster data writing and reading. The second magnetic storage array unit is a high-density magnetic random-access memory (HD-MRAM) array unit, which can adopt a 2T-1SOT-MTJ cell structure or a NAND-SPIN cell, resulting in higher storage density, but slightly slower data writing and reading speeds compared to the high-performance MRAM array. The true random number generator can adopt a random SOT-MTJ structure with an aspect ratio much smaller than that of the storage unit. The reprogrammable magnetic storage array unit can be implemented by breaking down the read channel and fusing the write channel of the MRAM array.

[0034] Please refer to Figure 2A and Figure 2BAll MTJs in the memory cell array are in-plane anisotropy (IPA) devices and are elliptical in shape. In this embodiment of the invention, the various MRAM arrays differ only in cell structure and magnetic junction shape, while the manufacturing process can be the same.

[0035] In a preferred embodiment of the present invention, the aspect ratio of the magnetic tunnel junctions in the first magnetic storage array unit, the true random number generator, the second magnetic storage array unit, and the reprogrammable magnetic storage array unit is represented by AR. HP-MRAM AR TRNG AR HD-MRAM and AR TTP The relationship between them can be:

[0036] AR HD-MRAM >AR HP-MRAM >AR TRNG >AR TTP (1)

[0037] The preferred embodiment of the present invention has a reprogrammable magnetic storage array unit that can be used to store encrypted data; a true random number generator can be used to generate random numbers after the encrypted data has been calibrated.

[0038] Please refer to Figure 2C The relationship between the aspect ratio (AR value, i.e., the ratio of the major axis to the minor axis of the ellipse) of the magnetic tunnel junctions in the first magnetic storage array unit, the true random number generator, the second magnetic storage array unit, and the reprogrammable magnetic storage array unit can be: AR HD-MRAM (That is, the second magnetic storage array unit has a slow read / write speed and low power consumption) > AR HP-MRAM (That is, the first magnetic storage array unit has fast read / write speed but high power consumption) > AR TRNG (That is, a true random number generator is used to generate random numbers after calibrating encrypted data) > AR TTP (That is, the reprogrammable magnetic storage array unit is used to store encrypted data, and data encryption is achieved by using encrypted data to perform TRNG calibration). In Figure 2C In the diagram, the arrows on the film layer represent the direction of the magnetic moment, and the arrows on the MTJ represent the markings of the major and minor axes.

[0039] In a preferred embodiment of the present invention, the RISC-V computing unit may include 2x RISC-V computing sub-units, and the first magnetic storage array unit may include 2x+1 magnetic storage sub-units. Adjacent magnetic storage sub-units share the same RISC-V computing sub-unit, thereby achieving multi-core parallel operation for near-memory computing. Here, x is a natural number.

[0040] Please refer to Figure 3The RISC-V computing unit provided in this embodiment of the invention may include 2x (x>1) RISC-V computing sub-units (e.g., RISC-V computing sub-core 11, RISC-V computing sub-core 12, ..., RISC-V computing sub-core 2x), and the first magnetic storage array unit may include 2x+1 magnetic storage sub-units (e.g., HP-MRAM-01, HP-MRAM-02, ..., HP-MRAM-2x+1), enabling a distributed arrangement of the RISC-V computing unit and the first magnetic storage array unit. In this embodiment of the invention, adjacent magnetic storage sub-units share the same RISC-V computing sub-unit, and adjacent RISC-V computing sub-units share the same magnetic storage sub-unit to achieve multi-core parallel operation of near-memory computing (similar to GPU), which can improve energy efficiency and computing power. Furthermore, the coordination relationship between the required magnetic storage sub-units and RISC-V computing sub-units can be dynamically adjusted, which is beneficial for rationally allocating and calling computing power according to needs, so as to maximize the utilization efficiency of computing resources.

[0041] In a preferred embodiment of the present invention, the control unit may also be configured to partition the computer program space of RISC-V instructions, so as to control the RISC-V computing unit and / or storage unit to perform corresponding operations by matching the received RISC-V instructions with the corresponding computer program space partition.

[0042] For example, RISC-V instructions can be configured as instructions relevant to corresponding in-memory computing units, depending on requirements. That is, the RISC-V instruction set computer program (Opcode) space partitioning can be as shown in the table below:

[0043] Table 1

[0044]

[0045] Please refer to Table 1. The received RISC-V instruction format can be [XX:XX].

[0046] Please refer to Figure 4 In a preferred embodiment of the present invention, controlling the RISC-V computing unit and / or storage unit to perform corresponding operations according to the received RISC-V instructions may include the following steps:

[0047] 1) Import the programming data of the reprogrammable magnetic storage array unit into the true random number generator (e.g., corresponding to the [00:10] instructions), calibrate the true random number generator, and send a random data stream to the RISC-V computing unit (e.g., corresponding to the [10:10] and [00:11] instructions); or

[0048] The input / output driver module imports data into the second magnetic storage array unit (e.g., corresponding to the [00:00] instruction), causing the RISC-V computing unit to request data from the second magnetic storage array unit and import it into the corresponding first magnetic storage array unit (e.g., corresponding to the [00:01] instruction).

[0049] 2) Control the RISC-V computing unit to perform near-memory computation (e.g., corresponding to the [10:00] instruction).

[0050] 3) Export the calculated data to the corresponding first magnetic storage array unit (e.g., corresponding to the [10:00] instruction).

[0051] 4) Export the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage (e.g., corresponding to the [01:01] instruction).

[0052] 5) Export the data temporarily stored in the second magnetic storage array unit to the input / output driver module (e.g., corresponding to the [01:00] instruction).

[0053] Please refer to Figure 5 The preferred near-memory computing system of the present invention may further include an in-memory computing unit electrically connected to a RISC-V computing unit, a true random number generator and a control unit. The in-memory computing unit is used to implement various near-memory computing methods.

[0054] Because RISC-V computing units are characterized by high precision and high energy consumption, they may lead to low system energy efficiency. Therefore, in a preferred embodiment of the present invention, an in-memory computing unit (characterized by low precision and low energy consumption) is added to achieve the following near-memory computing method:

[0055] 1) Coarse calculation followed by fine calculation: First, data is imported from the second magnetic storage array unit into the in-memory computing unit for in-memory calculation to achieve coarse calculation; then, the coarsely calculated data is imported from the in-memory computing unit into the first magnetic storage array unit and near-memory calculation is run to achieve fine calculation through the RISC-V computing unit.

[0056] 2) Coarse and fine calculations are performed simultaneously: The data that needs to be coarsely calculated is imported from the second magnetic storage array unit into the in-memory calculation unit for in-memory calculation to achieve coarse calculation of the corresponding data; at the same time, the data that needs to be finely calculated is imported from the second magnetic storage array unit into the first magnetic storage array unit and near-memory calculation is run to achieve fine calculation of the corresponding data through the RISC-V calculation unit.

[0057] The near-memory computing system provided in this embodiment of the invention reduces the computational load of the RISC-V computing unit by using an in-memory computing unit, thereby further improving the system's energy efficiency and computing power; moreover, it can dynamically configure the required computing method, thereby improving computing flexibility.

[0058] Please refer to Figure 6 In a preferred embodiment of the present invention, controlling the RISC-V computing unit and / or storage unit to perform corresponding operations according to the received RISC-V instructions may include the following steps:

[0059] 1) Import the programming data of the reprogrammable magnetic storage array unit into the true random number generator, calibrate the true random number generator, and send random data streams to the RISC-V computing unit and the in-memory computing unit; or

[0060] The input / output driver module imports data into the second magnetic storage array unit, enabling the RISC-V computing unit to request data from the second magnetic storage array unit and import it into the corresponding in-memory computing unit.

[0061] 2) Control the in-memory computing unit to perform the first near-memory calculation (i.e., coarse calculation).

[0062] 3) Control the RISC-V computing unit to request the data to be calculated from the in-memory computing unit and import it into the corresponding first magnetic storage array unit.

[0063] 4) Control the RISC-V computing unit to perform a second near-memory computation (i.e., fine computation).

[0064] 5) Export the calculated data to the corresponding first magnetic storage array unit.

[0065] 6) Export the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage.

[0066] 7) Export the data temporarily stored in the second magnetic storage array unit to the input / output driver module.

[0067] It should be noted that in the embodiments of the present invention, instructions related to in-memory computing units can be added to the RISC-V instruction Opcode space partition shown in Table (1). The instruction set can be adjusted as needed, and will not be listed here.

[0068] Please refer to Figure 7 In a preferred embodiment of the present invention, controlling the RISC-V computing unit and / or storage unit to perform corresponding operations according to the received RISC-V instructions may include the following steps:

[0069] 1) Import the programming data of the reprogrammable magnetic storage array unit into the true random number generator, calibrate the true random number generator, and send random data streams to the RISC-V computing unit and the in-memory computing unit; or

[0070] The input / output driver module imports data into the second magnetic storage array unit, enabling the RISC-V computing unit to request data from the second magnetic storage array unit and import it into the corresponding first magnetic storage array unit and in-memory computing unit.

[0071] 2) Control the RISC-V computing unit and in-memory computing unit to perform near-memory computing.

[0072] 3) Export the calculated data to the corresponding first magnetic storage array unit.

[0073] 4) Export the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage.

[0074] 5) Export the data temporarily stored in the second magnetic storage array unit to the input / output driver module.

[0075] Accordingly, the near-memory computing system provided in this embodiment of the invention may include a control unit, an input / output driver module, a RISC-V computing unit electrically connected to the control unit, and a storage unit. The storage unit may include a first magnetic storage array unit, a true random number generator, a second magnetic storage array unit, and a reprogrammable magnetic storage array unit. The input / output driver module is electrically connected to the second magnetic storage array unit and the reprogrammable magnetic storage array unit. In this embodiment of the invention, the magnetic tunnel junctions in the first magnetic storage array unit, the SOT-MTJ true random number generator, the second magnetic storage array unit, and the reprogrammable magnetic storage array unit are all in-plane anisotropic devices and are all elliptical. The control unit can be configured to, upon receiving a RISC-V instruction, control the RISC-V computing unit and / or the storage unit to perform corresponding operations according to the received RISC-V instruction. This embodiment of the invention solves the memory wall problem of existing near-memory computing by integrating multiple MRAM arrays on the same wafer and running near-memory computing based on RISC-V computing units, and improves the energy efficiency and computing power of near-memory computing; the multiple MRAM arrays use the same manufacturing process, which helps simplify the process flow. Furthermore, the first magnetic storage array unit and the RISC-V computing unit are arranged in blocks and in a distributed manner, which can realize multi-core parallel operation of near-memory computing, further improving the system's energy efficiency and computing power; and it is also conducive to rationally allocating and calling computing power according to demand, so as to maximize the utilization efficiency of computing resources. The embodiments of the present invention can also combine in-memory computing and near-memory computing to further improve the energy efficiency and computing power of the system's in-memory computing.

[0076] This invention also provides a near-memory computing method based on the RISC-V instruction set. This near-memory computing method can be applied to the control unit of the aforementioned near-memory computing system. The near-memory computing method may include the following steps S110-S120:

[0077] Step S110: RISC-V instruction received.

[0078] Step S120: Based on the received RISC-V instructions, control the RISC-V computing unit and / or storage unit to perform corresponding operations.

[0079] Please refer to Figure 4 In a preferred embodiment of the present invention, step S120 may include the following steps:

[0080] 1) Import the programming data of the reprogrammable magnetic storage array unit into the true random number generator (e.g., corresponding to the [00:10] instructions), calibrate the true random number generator, and send a random data stream to the RISC-V computing unit (e.g., corresponding to the [10:10] and [00:11] instructions); or

[0081] The input / output driver module imports data into the second magnetic storage array unit (e.g., corresponding to the [00:00] instruction), causing the RISC-V computing unit to request data from the second magnetic storage array unit and import it into the corresponding first magnetic storage array unit (e.g., corresponding to the [00:01] instruction).

[0082] 2) Control the RISC-V computing unit to perform near-memory computation (e.g., corresponding to the [10:00] instruction).

[0083] 3) Export the calculated data to the corresponding first magnetic storage array unit (e.g., corresponding to the [10:00] instruction).

[0084] 4) Export the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage (e.g., corresponding to the [01:01] instruction).

[0085] 5) Export the data temporarily stored in the second magnetic storage array unit to the input / output driver module (e.g., corresponding to the [01:00] instruction).

[0086] Please refer to Figure 5 In a preferred embodiment of the present invention, the near-memory computing system may further include an in-memory computing unit. Please refer to... Figure 6 Step S120 may include the following steps:

[0087] 1) Import the programming data of the reprogrammable magnetic storage array unit into the true random number generator, calibrate the true random number generator, and send random data streams to the RISC-V computing unit and the in-memory computing unit; or

[0088] The input / output driver module imports data into the second magnetic storage array unit, enabling the RISC-V computing unit to request data from the second magnetic storage array unit and import it into the corresponding in-memory computing unit.

[0089] 2) Control the in-memory computing unit to perform the first near-memory calculation (i.e., coarse calculation).

[0090] 3) Control the RISC-V computing unit to request the data to be calculated from the in-memory computing unit and import it into the corresponding first magnetic storage array unit.

[0091] 4) Control the RISC-V computing unit to perform a second near-memory computation (i.e., fine computation).

[0092] 5) Export the calculated data to the corresponding first magnetic storage array unit.

[0093] 6) Export the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage.

[0094] 7) Export the data temporarily stored in the second magnetic storage array unit to the input / output driver module.

[0095] Please refer to Figure 5 In a preferred embodiment of the present invention, the near-memory computing system may further include an SOT-MTJ in-memory computing unit. Please refer to... Figure 7 Step S120 may include the following steps:

[0096] 1) Import the programming data of the reprogrammable magnetic storage array unit into the true random number generator, calibrate the true random number generator, and send random data streams to the RISC-V computing unit and the in-memory computing unit; or

[0097] The input / output driver module imports data into the second magnetic storage array unit, enabling the RISC-V computing unit to request data from the second magnetic storage array unit and import it into the corresponding first magnetic storage array unit and in-memory computing unit.

[0098] 2) Control the RISC-V computing unit and in-memory computing unit to perform near-memory computing.

[0099] 3) Export the calculated data to the corresponding first magnetic storage array unit.

[0100] 4) Export the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage.

[0101] 5) Export the data temporarily stored in the second magnetic storage array unit to the input / output driver module.

[0102] This invention also provides a machine-readable storage medium storing instructions that cause a machine to execute the aforementioned near-memory computation method.

[0103] It should be noted that the above-described near-memory computing method and machine-readable storage medium based on the RISC-V instruction set can be applied to the near-memory computing system based on the RISC-V instruction set provided in the above embodiments. For specific implementation methods, please refer to the description of the near-memory computing system based on the RISC-V instruction set in the above embodiments, which will not be repeated here.

[0104] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0105] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0106] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0107] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0108] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0109] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0110] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0111] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0112] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A near-memory computing system based on RISC-V instruction set, characterized in that, The near-memory computing system comprises a control unit, an input-output driving module, a RISC-V computing unit electrically connected with the control unit, and a storage unit, the storage unit comprises a first magnetic storage array unit, a true random number generator, a second magnetic storage array unit, and a rewritable magnetic storage array unit, the input-output driving module is electrically connected with the second magnetic storage array unit and the rewritable magnetic storage array unit, wherein the magnetic tunnel junctions in the first magnetic storage array unit, the true random number generator, the second magnetic storage array unit, and the rewritable magnetic storage array unit are all in-plane anisotropic devices, and are all elliptical, the control unit is configured to, after receiving a RISC-V instruction, control the RISC-V computing unit and / or the storage unit to perform corresponding operations according to the received RISC-V instruction.

2. The near-memory computing system of claim 1, wherein, The aspect ratio of the magnetic tunnel junctions in the first magnetic storage array unit, the true random number generator, the second magnetic storage array unit, and the rewritable magnetic storage array unit is in the order from large to small as follows: the aspect ratio of the second magnetic storage array unit, the aspect ratio of the first magnetic storage array unit, the aspect ratio of the true random number generator, and the aspect ratio of the rewritable magnetic storage array unit; the rewritable magnetic storage array unit is used to store encrypted data, and the true random number generator is used to generate random numbers after the encrypted data is calibrated.

3. The near-memory computing system of claim 1, wherein, The RISC-V computing unit comprises 2x RISC-V computing sub-units, and the first magnetic storage array unit comprises 2x+1 magnetic storage sub-units, adjacent magnetic storage sub-units share the same RISC-V computing sub-unit, and adjacent RISC-V computing sub-units share the same magnetic storage sub-unit, to realize multi-core parallel operation of near-memory computing, wherein x is a natural number.

4. The near-memory computing system of claim 1, wherein, The control unit is further configured to perform computer program space division on the RISC-V instruction, so as to control the RISC-V computing unit and / or the storage unit to perform corresponding operations by matching the corresponding computer program space division with the received RISC-V instruction. 5.The near-memory computing system of claim 1 or 4, wherein, The control of the RISC-V computing unit and / or the storage unit to perform corresponding operations according to the received RISC-V instruction comprises: importing the programming data of the rewritable magnetic storage array unit into the true random number generator, calibrating the true random number generator, and sending a random data stream to the RISC-V computing unit, or importing data into the second magnetic storage array unit through the input-output driving module, making the RISC-V computing unit request data from the second magnetic storage array unit, and importing corresponding first magnetic storage array units; controlling the RISC-V computing unit to perform near-memory computing; exporting the calculated data to the corresponding first magnetic storage array unit; exporting the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage; and exporting the data temporarily stored in the second magnetic storage array unit to the input-output driving module.

6. The near-memory computing system of claim 1, wherein, The near-memory computing system further comprises a near-memory computing unit electrically connected to the RISC-V computing unit, the true random number generator, and the control unit, and the near-memory computing unit is configured to implement multiple near-memory computing modes.

7. The near-memory computing system of claim 6, wherein, The operation of controlling the RISC-V computing unit and / or the storage unit to perform corresponding operations according to the received RISC-V instruction comprises: introducing the burn-in data of the second-burnable magnetic storage array unit into the true random number generator, calibrating the true random number generator, and sending a random data stream to the RISC-V computing unit and the near-memory computing unit, or introducing data into the second magnetic storage array unit through the input-output driving module, requesting data from the RISC-V computing unit to the second magnetic storage array unit, and introducing the corresponding near-memory computing unit; controlling the near-memory computing unit to perform first near-memory computing; controlling the RISC-V computing unit to request the calculated data from the near-memory computing unit and introduce the corresponding first magnetic storage array unit; controlling the RISC-V computing unit to perform second near-memory computing; exporting the calculated data to the corresponding first magnetic storage array unit; exporting the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage; and exporting the data temporarily stored in the second magnetic storage array unit to the input-output driving module.

8. The near-memory computing system of claim 6, wherein, The operation of controlling the RISC-V computing unit and / or the storage unit to perform corresponding operations according to the received RISC-V instruction comprises: introducing the burn-in data of the second-burnable magnetic storage array unit into the true random number generator, calibrating the true random number generator, and sending a random data stream to the RISC-V computing unit and the near-memory computing unit, or introducing data into the second magnetic storage array unit through the input-output driving module, requesting data from the RISC-V computing unit to the second magnetic storage array unit, and introducing the corresponding first magnetic storage array unit and near-memory computing unit; controlling the RISC-V computing unit and the near-memory computing unit to perform near-memory computing; exporting the calculated data to the corresponding first magnetic storage array unit; exporting the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage; and exporting the data temporarily stored in the second magnetic storage array unit to the input-output driving module. 9.A method for near-memory computing based on RISC-V instruction set, characterized in that, The near-memory computing method is applied to the control unit of the near-memory computing system in any one of claims 1-8, and the near-memory computing method comprises: receiving a RISC-V instruction; and controlling the RISC-V computing unit and / or the storage unit to perform corresponding operations according to the received RISC-V instruction.

10. The near-memory computing method of claim 9, wherein, The operation of controlling the RISC-V computing unit and / or the storage unit to perform corresponding operations according to the received RISC-V instruction comprises: introducing the burn-in data of the second-burnable magnetic storage array unit into the true random number generator, calibrating the true random number generator, and sending a random data stream to the RISC-V computing unit and the near-memory computing unit, or introducing data into the second magnetic storage array unit through the input-output driving module, requesting data from the RISC-V computing unit to the second magnetic storage array unit, and introducing the corresponding near-memory computing unit; controlling the near-memory computing unit to perform first near-memory computing; controlling the RISC-V computing unit to request the calculated data from the near-memory computing unit and introduce the corresponding first magnetic storage array unit; controlling the RISC-V computing unit to perform second near-memory computing; exporting the calculated data to the corresponding first magnetic storage array unit; exporting the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage; and exporting the data temporarily stored in the second magnetic storage array unit to the input-output driving module. importing the burn-in data of the reprogrammable magnetic storage array unit into the true random number generator, calibrating the true random number generator, and sending a random data stream to the RISC-V computing unit, or importing data into the second magnetic storage array unit through the input-output driving module, requesting data from the second magnetic storage array unit by the RISC-V computing unit, and importing the corresponding first magnetic storage array unit; controlling the RISC-V computing unit to perform near-memory computing; exporting the calculated data to the corresponding first magnetic storage array unit; exporting the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage; and exporting the data temporarily stored in the second magnetic storage array unit to the input-output driving module.

11. The near-data-computing method of claim 9, wherein, The near-memory computing system further comprises an in-memory computing unit, and the RISC-V computing unit and / or the storage unit are controlled to perform corresponding operations according to the received RISC-V instructions, including: importing the burn-in data of the reprogrammable magnetic storage array unit into the true random number generator, calibrating the true random number generator, and sending a random data stream to the RISC-V computing unit and the in-memory computing unit, or importing data into the second magnetic storage array unit through the input-output driving module, requesting data from the second magnetic storage array unit by the RISC-V computing unit, and importing the corresponding first magnetic storage array unit and in-memory computing unit; controlling the RISC-V computing unit and the in-memory computing unit to perform near-memory computing; controlling the RISC-V computing unit to request the calculated data from the in-memory computing unit and importing the corresponding first magnetic storage array unit; controlling the RISC-V computing unit to perform near-memory computing for the second time; exporting the calculated data to the corresponding first magnetic storage array unit; exporting the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage; and exporting the data temporarily stored in the second magnetic storage array unit to the input-output driving module.

12. The near-data-computing method of claim 9, wherein, The near-memory computing system further comprises an in-memory computing unit, and the RISC-V computing unit and / or the storage unit are controlled to perform corresponding operations according to the received RISC-V instructions, including: importing the burn-in data of the reprogrammable magnetic storage array unit into the true random number generator, calibrating the true random number generator, and sending a random data stream to the RISC-V computing unit and the in-memory computing unit, or importing data into the second magnetic storage array unit through the input-output driving module, requesting data from the second magnetic storage array unit by the RISC-V computing unit, and importing the corresponding first magnetic storage array unit and in-memory computing unit; controlling the RISC-V computing unit and the in-memory computing unit to perform near-memory computing; controlling the RISC-V computing unit to request the calculated data from the in-memory computing unit and importing the corresponding first magnetic storage array unit; controlling the RISC-V computing unit to perform near-memory computing for the second time; exporting the calculated data to the corresponding first magnetic storage array unit; exporting the data in the first magnetic storage array unit to the second magnetic storage array unit for temporary storage; and exporting the data temporarily stored in the second magnetic storage array unit to the input-output driving module. exporting data temporarily stored by the second magnetic storage array unit to the input / output drive module.

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