Data transmission method and device, storage medium, program product and computer equipment

Abstract

The invention discloses a data transmission method and device, a storage medium, a program product and computer equipment, and relates to the technical field of artificial intelligence chips. Adding the current request to a to-be-sent request queue; when a preset sending condition is met, a target request is generated according to all the requests in the to-be-sent request queue, the target request is sent to a target cache, and all the requests in the to-be-sent request queue are emptied along with sending of the target request; when the preset sending condition is not met and the next request meets the combination condition of the current request, after the next request is received, the next request is added to the to-be-sent request queue, so that the number of the requests sent to the cache can be reduced, the occupied bus resources are further reduced, and the service life of the to-be-sent request queue is prolonged. Therefore, the performance of the chip is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of artificial intelligence chip, and particularly relates to a data transmission method and device, a storage medium, a program product and a computer device. BACKGROUND

[0002] In the technical field of artificial intelligence chip, in order to perform a specified operation on a cache in a chip, a request indicating the specified operation is usually sent to the cache through a bus.

[0003] However, since the bus is a shared resource among various modules in the chip, each module may need to compete for access to the bus when using the bus, so that sending a request to the cache will occupy bus resources in the chip. If requests are frequently sent to the cache, the bus resources will be occupied too much, causing waste of bus resources and affecting the performance of the chip. SUMMARY

[0004] To solve the above technical problems, the embodiments of the present application provide a data transmission method, device, storage medium, program product and computer device, which can reduce the number of requests sent to the cache, thereby reducing the required bus resources, so as to improve the performance of the chip.

[0005] In a first aspect, the embodiments of the present application provide a data transmission method, comprising: receiving a current request; adding the current request to a to-be-sent request queue; when a preset sending condition is met, generating a target request according to all requests in the to-be-sent request queue, and sending the target request to a target cache, wherein all requests in the to-be-sent request queue are emptied along with the sending of the target request; when the preset sending condition is not met, and a next request meets a combination condition with the current request, after receiving the next request, adding the next request to the to-be-sent request queue.

[0006] Optionally, the preset sending condition comprises at least one of the following: a to-be-sent data amount size corresponding to the target request reaches a preset upper limit; the next request does not meet the combination condition with the current request.

[0007] Optionally, the target request is a request of a burst transmission type; the to-be-sent data amount size corresponding to the target request is determined by a current burst transmission parameter of the target request.

[0008] Optionally, the target request is a burst transmission type request, and the combination condition is: the next request and the current request correspond to the same target cache; and the address corresponding to the next request and the address corresponding to the current request are both burst size aligned addresses.

[0009] Optionally, both the current request and the next request are write requests.

[0010] Optionally, before adding the current request to the queue of requests to be sent, the method further includes: Determine the target cache line in the target cache based on the current request; If the target cache line is in a dirty state, an eviction request is sent to the target cache line, wherein the eviction request is used to evict dirty data in the target cache line that is in a dirty state.

[0011] Secondly, embodiments of this application provide a data transmission apparatus, including: The request processing module is used to receive the current request; The queue update module is used to add the current request to the queue of requests to be sent; The target request sending module is used to generate a target request based on all requests in the request queue to be sent when a preset sending condition is met, and send the target request to the target cache, wherein all requests in the request queue to be sent are cleared when the target request is sent; The combined prediction module is used to add the next request to the queue of requests to be sent after receiving the next request, when the preset sending conditions are not met and the next request meets the combined conditions with the current request.

[0012] Thirdly, embodiments of this application provide a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method described in any of the above-mentioned embodiments.

[0013] Fourthly, embodiments of this application provide a computer program product, including computer instructions that, when executed by a processor, implement the steps of the method described in any of the above-described embodiments.

[0014] Fifthly, embodiments of this application provide a computer device including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement the steps of the method described in any of the preceding claims.

[0015] In summary, the embodiments of this application have at least the following beneficial effects: By employing the embodiments of this application, a current request is received; the current request is added to a queue of requests to be sent; when a preset sending condition is met, a target request is generated based on all requests in the queue of requests to be sent, and the target request is sent to a target cache, wherein all requests in the queue of requests to be sent are cleared upon sending the target request; when the preset sending condition is not met, and the next request meets the combination condition with the current request, the next request is added to the queue of requests to be sent after receiving the next request, thereby reducing the number of requests sent to the cache, and thus reducing the required bus resources, in order to improve the performance of the chip. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the data transmission method provided in an embodiment of this application; Figure 2 This is a schematic diagram of data transmission provided in an embodiment of this application; Figure 3 This is a schematic diagram illustrating the processing order after receiving each write request, provided in an embodiment of this application. Figure 4 This is another schematic diagram illustrating the processing order after receiving each write request, provided in an embodiment of this application. Figure 5 This is a schematic diagram of the data transmission device provided in an embodiment of this application; Figure 6 This is a schematic diagram of the computer device provided in the embodiments of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0018] In the description of this application, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," "third," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more. In the description of this application, the term "comprising" and its variations are open-ended, meaning "including but not limited to." The term "based on" means "at least partially based on." The term "according to" means "at least partially according to." The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments."

[0019] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0020] In the description of this application, it should be noted that, unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit the application. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0021] The following provides an exemplary explanation of some terms and concepts involved in the embodiments of this application.

[0022] Chip: The chip involved in any embodiment of this application can be an artificial intelligence (AI) chip. The AI ​​chip can be a hardware processor used to accelerate the computing tasks of artificial intelligence algorithms (such as machine learning and deep learning). For example, the AI ​​chip can include one or more of the following: graphics processing unit (GPU), general-purpose computing on graphics processing unit (GPGPU), tensor processing unit (TPU), neural processing unit (NPU), application-specific integrated circuit (ASIC), etc.

[0023] Bus: A bus is a set of physical wires or circuit channels used to transmit at least one of the following signals: data, address, and control signals, between various modules within a chip (e.g., a central processing unit (CPU) core, AI accelerator, cache, memory controller, etc.) or between the chip and external devices. The cache in this embodiment typically utilizes the chip's internal interconnect bus. Within the chip, the bus generally includes one or more of the following: a data bus, an address bus, and a control bus. When a processor or core within the chip needs to perform a specific operation on the cache (e.g., a read operation, a write operation, a prefetch operation, a invalidation operation, etc.), the processor or core sends a request to the cache controller via the bus. This request may include: the operation type (read / write / invalidate, etc.), the target memory address, and, if it is a write operation, the request may also include the data to be written to the cache. However, in some cases, at least some of the modules within the chip can share the bus for communication. Therefore, if the processor or a certain core sends too many / too frequent requests to the cache while sharing the bus, it will cause congestion on the shared bus, preventing other cores or modules from using the bus for communication in a timely manner. This increases the waiting time for requests, leading to increased latency and ultimately resulting in a decrease in the overall performance of the chip.

[0024] Cache: A cache is a high-speed memory in computer systems and chips used to temporarily store frequently accessed data or instructions so that they can be accessed faster the next time they are needed, thereby improving overall system performance. For example, the cache hierarchy may include L1 cache, L2 cache, L3 cache, and main memory, wherein the speed of L1 cache, L2 cache, L3 cache, and main memory decreases and the capacity increases in that order.

[0025] A cache line is the basic unit of data storage and management in the cache. When the processor accesses data, it typically doesn't load the single piece of data directly, but instead loads the entire cache line containing that data from main memory into the cache. In other words, cache loading, replacement, and write-back operations can be performed on a per-line basis. For example, in one architecture, the size of each cache line can be fixed, such as 64 bytes. A cache line can correspond to a contiguous and aligned address region in memory; for example, a 64-byte cache line's starting address can be a multiple of 64. Each cache line can contain at least one of the following: a tag, representing the high-order bits of the memory address corresponding to the cache line, used to determine if a cache hit has occurred; data, i.e., the actual stored data, the size of which is equal to the cache line size (e.g., 64 bytes); and status flags, such as valid, dirty, or consistency flags.

[0026] Burst transfer: Burst transfer is an efficient data transfer method in computer storage systems. It allows for the continuous and concentrated transfer of multiple data units (beats), such as a contiguous block of data, rather than a single data unit (e.g., a single byte or word). A Burst transfer can specify a starting address at the beginning of the transfer, and subsequent data will be automatically transferred from that starting address in consecutive addresses. This eliminates the need to send address information individually / repeatedly for each data unit. For example, a Burst transfer can specify a starting address of 0x1000, and then continuously transfer data at addresses 0x1000, 0x1004, 0x1008, etc. (assuming 4-byte alignment). With the continuous expansion of computing power demands, the performance and processing speed requirements for high-performance computing chips are also increasing. Artificial intelligence chips (such as GPUs, NPUs, and TPUs) require efficient data handling capabilities, but bus resources are extremely limited. Therefore, using Burst transfer can accelerate data handling and improve computational efficiency.

[0027] In some scenarios, the bandwidth (the total amount of data that can be transferred per unit of time) corresponding to a cache can be limited. Therefore, the number of requests that the cache can process normally within a cycle is also limited by this bandwidth. For example, when sending a request to the cache, each request sent to the cache is limited based on the bandwidth corresponding to that cache. If a request exceeds the maximum limit of the corresponding bandwidth, it can be split into multiple requests, none of which exceed the maximum limit, and sent separately in different cycles to ensure that each request received by the cache does not exceed the corresponding bandwidth limit. However, this requires sending multiple requests to the cache frequently, which can lead to excessive bus resource consumption, wasting bus resources and ultimately affecting the chip's performance and processing speed.

[0028] Taking a write request as an example, in the field of artificial intelligence chip technology, if a write request hits a cache line, but the cache line contains modified dirty data, and the write operation indicated by the current write request needs to overwrite the cache line, then the dirty data in the cache line needs to be evicted / written back to main memory first so that main memory can save the modification corresponding to the dirty data. Due to the bandwidth limitation of the cache, it may not be possible to include the eviction request and the write request in a single request. Therefore, the relevant request to indicate that the dirty data should be evicted / written back to main memory can be sent to the cache in the current cycle, and then the write request can be sent to the cache in a subsequent cycle. Furthermore, suppose two or more consecutive write requests hit a cache line containing modified dirty data. Due to cache bandwidth limitations, the technology might first send an eviction request to the cache corresponding to the first of the two or more write requests, then send that first write request to the cache again, and so on, until all two or more write requests are sent to the cache. However, it is understandable that an eviction request needs to be sent between each of the two or more adjacent write requests, which greatly increases the number of requests that need to be sent to the cache.

[0029] Firstly, see [the following] Figure 1 The diagram shows a flowchart of a data transmission method provided in an embodiment of this application. This data transmission method can be applied to a cache controller in a chip. The data transmission method includes S101-S104, as detailed below.

[0030] S101, Receive the current request.

[0031] In some examples, the current request mentioned above may be sent by the processor or a core in the chip, and the current request may be used to instruct the processor or a core to perform a specific operation (such as a read operation, write operation, prefetch operation, invalidation operation, etc.) on the target cache.

[0032] In some examples, the current request mentioned above can be a write request, which can be used to instruct the first data to be written to the target cache line in the target cache.

[0033] S102, add the current request to the pending request queue.

[0034] In some examples, the initial state of the above-mentioned request queue to be sent can be an empty queue. In this case, if after adding a request, there is only the current request in the request queue to be sent, it is easy to understand that the request queue to be sent at this time is the current request itself. Furthermore, at this time, the current request can be directly used as the target request for the subsequent request.

[0035] It is understood that the above-mentioned request queue is only used to represent each request that has been received and meets the subsequent relevant conditions and is ready to be sent. Therefore, the request queue can also be formed or updated by marking each request as a request to be sent when it is received.

[0036] S103, when the preset sending conditions are met, a target request is generated based on all requests in the request queue to be sent, and the target request is sent to the target cache, wherein all requests in the request queue to be sent are cleared as the target request is sent.

[0037] In some examples, the aforementioned preset sending condition refers to the condition under which a target request can be sent to the target cache after it is determined that the condition is met. Specific examples are diverse and will be further explained in the subsequent corresponding embodiments.

[0038] In some examples, the target request is redefined when the queue of requests to be sent is updated. For instance, if a new request (such as the current request or the next request) is added to the queue of requests to be sent, and then the target request is sent, the target request is generated based on the queue of requests to be sent after the new request was added. If a new request is added to the queue of requests to be sent after the queue of requests to be sent is cleared, the target request is determined based on the new request that was added.

[0039] In some examples, when there is only one request in the request queue (e.g., only the current request), that single request can be directly used as the target request. Alternatively, a new target request can be regenerated based on the information of that single request; this is not specifically limited here. When there are more than one request in the request queue (e.g., the current request and any subsequently received requests added to the queue), the target request is typically a new request regenerated from all requests in the queue. For example, when a new request needs to be regenerated, the target request can be generated based on the information indicated by each request in the request queue (at least one of the specified operations and data mentioned above), so that the target request can be used to indicate the information indicated by each request in the request queue (at least one of the specified operations and data mentioned above).

[0040] In some examples, each time a target request is sent, all requests in the queue to be sent are cleared accordingly, so that the queue to be sent becomes an empty queue after being cleared.

[0041] S104, if the preset sending conditions are not met, and the next request meets the combination conditions with the current request, after receiving the next request, add the next request to the queue of requests to be sent.

[0042] In some examples, the cache controller can obtain information about the next request through other underlying circuitry before receiving it. This allows it to determine, based on the information about the next request and the current request, whether the next request meets the combination conditions for being sent together with the current request. Therefore, it is possible to determine whether the next request meets the combination conditions for being sent together with the current request before receiving it.

[0043] In some examples, the above next request is the request following the current request.

[0044] In some examples, the next request mentioned above may be sent by the processor or a core in the chip, and the current request mentioned above may be used to instruct the processor or a core to perform a specific operation (such as a read operation, write operation, prefetch operation, invalidation operation, etc.) on the target cache.

[0045] In some examples, the next request mentioned above can be a write request, which can be used to instruct the second data to be written to the cache line corresponding to the next request in the target cache.

[0046] In some examples, the above combination condition means that the next request and the current request can be sent together. This combined sending can mean that the specified operations indicated by the next request and the current request for the target cache can be completed by sending the above target request to the target cache.

[0047] Understandably, after adding the next request to the queue of requests to be sent, if a target request is to be sent, the target request to be sent also needs to take the newly added next request into account when it is generated.

[0048] In this embodiment, the target request can be determined based on each request in the request queue to be sent. This changes the original requirement of sending all requests in the request queue separately to sending only the target request once. Furthermore, by judging the combination conditions, it is ensured that each newly added request in the request queue can be combined with the previously added request for sending. Therefore, the number of requests sent to the cache can be reduced, thereby reducing the bus resources required and improving the chip's performance and processing speed.

[0049] In one optional implementation, the preset sending conditions include at least one of the following: The amount of data to be sent corresponding to the target request has reached a preset upper limit; The next request does not satisfy the combined conditions with the current request.

[0050] In some examples, the bandwidth corresponding to the target cache is limited (maximum limit). Therefore, if the preset sending conditions include "the size of the data to be sent corresponding to the target request reaches the preset upper limit," this embodiment can send the target request to the target cache when the size of the data to be sent corresponding to the target request (which can be determined in real time according to the queue of requests to be sent) reaches the preset upper limit. This ensures that the target request can be transmitted within one cycle, thus better adapting to the bandwidth limitations of the target cache. However, in some other examples, the size of the data to be sent corresponding to the target request may exceed the preset upper limit. In this case, it can be achieved, for example, by splitting the target request into several sub-requests whose corresponding data sizes do not exceed the preset upper limit when it needs to be sent later. It should be noted that in this case, the number of sub-requests can be controlled by splitting the target request. Therefore, the number of sub-requests may still be less than the number of requests in the queue of requests to be sent, thus still achieving the effect of reducing the number of requests to be transmitted.

[0051] In some examples, where the preset sending condition includes "the next request does not meet the combination condition for being sent together with the current request," it can be understood that the next request and the current request cannot be sent together. Therefore, the latest pending request queue will not contain the next request, and the target request being sent is unrelated to it. Thus, the next request can be sent to the target cache separately later, or it can be added to a pending request queue that does not contain the current request and then sent to the target cache as a new target request, thereby achieving mutual isolation between the next request and the current request. For example, a target request can be sent to the target cache based on the latest pending request queue (which does not contain the next request) before the next request has even been received.

[0052] In some examples, where the preset sending conditions include "the size of the data to be sent corresponding to the target request reaches a preset upper limit, and the next request does not meet the combination conditions with the current request," please refer to [the relevant documentation]. Figure 2 Taking the zeroth write request 0 and the first write request 1 as the current request and the next request respectively as examples, we can determine whether the amount of data to be sent has reached the preset limit by checking whether the current burst size corresponding to the target request has reached the limit after receiving the zeroth write request 0 (the current request). If it has, the current target request can be sent to the target cache. If it has not yet reached the limit, we can further determine whether the first write request 1 (the next request) meets the combination condition for sending together with the zeroth write request 0 (the current request). If it does not meet the condition, the current target request can be sent.

[0053] In one alternative implementation, the target request is a burst transmission type request; The amount of data to be sent corresponding to the target request is determined by the current burst transmission parameters of the target request.

[0054] In some examples, when the target request in this embodiment is a request constructed based on a burst transfer, the target request can be referred to as a Burst request. As can be seen from the above description related to burst transfer in this embodiment, this embodiment can achieve the continuous and centralized transmission of multiple data units (Beats) to the target cache by sending a target request (Burst request) to the target cache. Since a Burst transfer can specify a starting address at the beginning of the transfer, and subsequent data will be automatically transmitted from the starting address in a continuous address sequence, it is easy to understand that the target request (Burst request) in this embodiment can carry a specified starting address (at this time, the request queue to be sent can be used to determine the starting address carried in the target request), so that the target cache performs Burst transfer according to the starting address carried in the target request (Burst request), thereby eliminating the need to send a request carrying address information separately / repeatedly for each data unit in the data to be sent corresponding to the request queue to be sent, thus achieving the effect of reducing the number of required transmission requests.

[0055] In some examples, when the target request is a Burst request, the size of the data to be sent corresponding to the target request (Burst request) can be determined by the current burst transmission parameters corresponding to the target request (Burst request). For example, as described above in the embodiments of this application related to burst transmission, since burst transmission can continuously and centrally transmit multiple data units (Beats), that is, the data volume corresponding to a complete Burst request can be expressed as the burst size (Burst Size), which is Burst Length × Beat Size, where Burst Length is the actual number of Beats to be transmitted (the number of data beats in the burst transmission), and Beat Size is the number of bytes per Beat (the size of each data unit). Therefore, the current burst transmission parameters can include at least one of the following: Burst Length and Beat Size. Thus, in this embodiment, the Burst Length and Beat Size corresponding to the target request (Burst request) can be determined by the request queue to be sent, and then the size of the data to be sent corresponding to the target request can be determined by the Burst Length and Beat Size corresponding to the target request (Burst request). Here, it is not difficult to understand that in some cases, one of BurstLength and Beat Size can be fixed in advance, while the other can be determined in real time by the queue of requests to be sent.

[0056] In some examples, the current burst transmission parameter may include the current burst size. For instance, if the current burst size of the target request reaches a preset size limit, it can be determined that the amount of data to be sent corresponding to the target request has reached the preset size limit. For example, the preset size limit can be determined based on the bus resource limitations of the chip, as shown in [reference needed]. Figure 2 Assuming the upper limit of the burst size is 4 data units (one data unit equals 1kb), each time a request corresponding to one data unit is added to the pending request queue, the current burst size of the Burst request will increment by 1 data unit (represented by the "++" symbol). In this case, the preset upper limit of the size can be set to 4kb according to the bus resource limitations of some chips. Of course, other values ​​can also be selected depending on the situation, which will not be elaborated here.

[0057] In some examples, when the target request is a Burst request, the conditions for determining whether the current request and the next request can be sent together can be varied. For example, the addresses of the two requests can be consecutive and aligned, the data size transmitted by each request can be the same, the two requests can correspond to the same burst type, and the target address space of the two requests can be the same.

[0058] In one optional implementation, the target request is a burst transmission type request, and the combination condition is: the next request corresponds to the same target cache as the current request; and the address corresponding to the next request and the address corresponding to the current request are burst size aligned addresses.

[0059] In some examples, when the target request is a Burst request, this combined condition may include the address alignment condition described above. Here, whether two addresses are burst-size aligned can be determined by whether they are integer multiples of the burst size. If both addresses are integer multiples of the burst size, then they are burst-size aligned. For example, with a burst size of 8 bytes, the two addresses are aligned to 8 bytes. Further examples include 0x1000, 0x1008, and 0x1004. Since 0x1000 is a hexadecimal address with a decimal value of 4096, which is a multiple of 8, 0x1000 is 8-byte aligned. Similarly, 0x1008 is also 8-byte aligned. Conversely, if the decimal value corresponding to the hexadecimal address is not a multiple of 8, then it is not 8-byte aligned, such as 0x1004.

[0060] In some examples, the cache controller can obtain the address information of the next request from the previous level (such as a register) through other underlying circuitry before it receives the next request, so as to determine the above address alignment conditions, thus eliminating the need to wait until the next request is received before making the relevant judgment.

[0061] In one alternative implementation, both the current request and the next request are write requests.

[0062] As can be seen from the examples of the aforementioned related technologies, in the interval between two or more write requests, a request for eviction needs to be sent, which greatly increases the number of requests that need to be sent to the cache.

[0063] In this embodiment, to address this issue, since the current request and the next request both correspond to the same target cache, this embodiment only needs to send a request to evict dirty data in the target cache before sending the target request. This reduces the number of eviction requests that need to be sent to the cache, thereby reducing the required bus resources and improving the chip's performance and processing speed.

[0064] In an optional implementation, before adding the current request to the queue of requests to be sent, the method further includes: Determine the target cache line in the target cache based on the current request; If the target cache line is in a dirty state, an eviction request is sent to the target cache line, wherein the eviction request is used to evict dirty data in the target cache line that is in a dirty state.

[0065] See in some examples Figure 2 When a current request is received (e.g., write request 0), the system can first identify whether the target cache line that was hit is dirty. If it is dirty, the dirty data in the target cache line can be evicted so that the system can directly perform preset operations on the target cache line through the target request, such as writing the first data into the target cache line.

[0066] In this embodiment, by evictting dirty data in the target cache line that is in a dirty state before adding the request to the queue to be sent, that is, before the queue to be sent is updated, the target cache line will be in a clean state when the target request is sent later. This avoids having to occupy a cycle to send an eviction request to the target cache line when it is determined that the target request can be sent, thereby improving the real-time response speed of the target request.

[0067] In an optional implementation, the method further includes: Upon receiving the next request, it can be treated as a new current request, and the default sending conditions can be reassessed.

[0068] In some examples, if it is determined that the preset sending conditions are not met, and it is determined that the next request meets the combination conditions for sending in combination with the current request, the next request can be treated as a new current request and the above-described embodiments can be re-executed. This achieves the effect of cyclically performing the processing corresponding to the above-described embodiments for each received request. For example, upon receiving the next request (e.g., in...), Figure 2 In this context, if the zeroth write request 0 is taken as the current request, then the first write request 1 is taken as the next request; or, if the first write request 1 is taken as the current request, then the second write request 2 is taken as the next request; or, if the second write request 2 is taken as the current request, then the third write request 3 is taken as the next request. It is easy to understand that this reflects the process of re-executing the above-mentioned embodiments by taking the next request as the new current request. As the target request is sent, the queue of requests to be sent is cleared. At the same time, the first request received later can be re-recorded as the zeroth write request 0. The cache line corresponding to the next request can be determined in the target cache. If the cache line is in a dirty state, the corresponding eviction request can also be sent to the cache line first.

[0069] In specific examples of related technologies, taking a cache bandwidth of 1kb as an example, if two consecutive write requests hit a cache line containing dirty data, and each write request needs to transmit 1kb of data, then the two write requests need to be transmitted in two cycles. Before each of the two write requests is transmitted, a request to evict the dirty data in the corresponding cache line also needs to be transmitted, for a total of 4 requests need to be sent.

[0070] Furthermore, in this example scenario, see [link / reference]. Figure 3 If four consecutive write requests (write request 0, write request 1, write request 2, and write request 3) all hit a cache line containing dirty data, and assuming the cache bandwidth is 1kb and each write request requires 1kb of data to be transferred, then each write request needs to send a corresponding eviction request before it is sent. Therefore, a total of eight requests are needed to complete the task indicated by these four requests.

[0071] For the above-mentioned example scenarios, embodiments of this application provide, as follows: Figure 4The scheme shown can predict whether a write request and the next write request can be combined into a Burst request before each of the four write requests is sent. Therefore, it is equivalent to reducing the original four write requests to only one Burst request. In addition, there are four eviction requests sent to evict the zeroth to the third old data, which is equivalent to sending a total of five requests (one Burst request and four eviction requests). Compared with the eight requests required in the example scenario above, the bus resources occupied by this embodiment are 5 / 8 of those in the example scenario.

[0072] It is not difficult to understand, in Figure 3 , Figure 4 In practice, there may be cases where write requests miss or hit cache lines that do not contain dirty data. In such cases, there is no need to send a corresponding eviction request. Furthermore, in an example scenario, suppose four consecutive write requests (write request 0, write request 1, write request 2, and write request 3) all fall under the category of write request misses or hit cache lines that do not contain dirty data. Figure 4 The scheme shown only requires sending one Burst request, while Figure 3 The scheme shown requires sending four write requests, which can be understood as the scheme provided in the embodiments of this application. Figure 4 The scheme shown is compared to Figure 3 In the illustrated scheme, the bus resources used are reduced to 1 / 4 of the original, which can improve the chip's performance by 400%. Similarly, for the example scenario of two consecutive write requests, the bus resources used in this embodiment can be 1 / 2 of the example scenario, which can be understood as improving the chip's performance by 200%. This embodiment does not require increasing chip resources (e.g., it does not require increasing cache-related storage resources), is applicable to almost all caches, has strong versatility and significant effect, and can effectively reduce the chip's PPA (Power / Performance / Area, which is one of the evaluation criteria for chip performance), ultimately improving the overall chip performance and yield, and the effect is more obvious when bus resources are limited.

[0073] Secondly, correspondingly, this application also provides a data transmission device capable of implementing all the processes of the data transmission method provided in the above embodiments.

[0074] See Figure 5 The diagram shows a schematic representation of a data transmission device 500 provided in an embodiment of this application. The data transmission device 500 includes: Request processing module 501 is used to receive the current request; The queue update module 502 is used to add the current request to the queue of requests to be sent; The target request sending module 503 is used to generate a target request based on all requests in the request queue to be sent when a preset sending condition is met, and send the target request to the target cache, wherein all requests in the request queue to be sent are cleared when the target request is sent; The combined prediction module 504 is used to add the next request to the queue of requests to be sent after receiving the next request when the preset sending conditions are not met and the next request meets the combined conditions with the current request.

[0075] In one optional implementation, the preset sending conditions include at least one of the following: The amount of data to be sent corresponding to the target request has reached a preset upper limit; The next request does not satisfy the combined conditions with the current request.

[0076] In one alternative implementation, the target request is a burst transmission type request; The amount of data to be sent corresponding to the target request is determined by the current burst transmission parameters of the target request.

[0077] In one optional implementation, the target request is a burst transmission type request, and the combination condition is: the next request corresponds to the same target cache as the current request; and the address corresponding to the next request and the address corresponding to the current request are burst size aligned addresses.

[0078] In one alternative implementation, both the current request and the next request are write requests.

[0079] In one optional implementation, the data transmission device further includes an ejection module, which is configured to: Before adding the current request to the queue of requests to be sent, the target cache line in the target cache is determined based on the current request; If the target cache line is in a dirty state, an eviction request is sent to the target cache line, wherein the eviction request is used to evict dirty data in the target cache line that is in a dirty state.

[0080] Thirdly, embodiments of this application provide a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method described in any of the above-mentioned embodiments.

[0081] Fourthly, embodiments of this application provide a computer program product, including computer instructions that, when executed by a processor, implement the steps of the method described in any of the above-described embodiments.

[0082] Fifthly, embodiments of this application provide a computer device including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement the steps of the method described in any of the preceding claims.

[0083] See Figure 6 The computer device in this embodiment includes a processor 601, a memory 602, and a computer program, such as a data transfer program, stored in the memory 602 and executable on the processor 601. When the processor 601 executes the computer program, it implements the steps in the various data transfer method embodiments described above, for example... Figure 1 The steps S101-S104 are shown.

[0084] For example, the computer program may be divided into one or more modules / units, which are stored in the memory 602 and executed by the processor 601 to complete this application. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the computer device.

[0085] The computer device may be a desktop computer, laptop, handheld computer, or cloud server, etc. The computer device may include, but is not limited to, a processor 601 and a memory 602. Those skilled in the art will understand that the schematic diagram is merely an example of a computer device and does not constitute a limitation on the computer device. It may include more or fewer components than shown, or combine certain components, or different components. For example, the computer device may also include input / output devices, network access devices, buses, etc.

[0086] The processor 601 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor, or processor 601 can be any conventional processor. The processor 601 is the control center of the computer device, connecting various parts of the entire computer device through various interfaces and lines.

[0087] The memory 602 can be used to store the computer programs and / or modules. The processor 601 implements various functions of the computer device by running or executing the computer programs and / or modules stored in the memory 602 and calling the data stored in the memory 602. The memory 602 may mainly include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of the mobile phone (such as audio data, phonebook, etc.). In addition, the memory 602 may include high-speed random access memory, and may also include non-volatile memory, such as hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital card (SD) card, flash card, at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0088] Wherein, if the modules / units integrated into the computer device are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a non-transitory computer-readable storage medium. When the computer program is executed by the processor 601, it can implement the steps of the various method embodiments described above. Wherein, the computer program includes computer program code, which can be in the form of source code, object code, executable file, or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc.

[0089] In summary, the embodiments of this application have at least the following beneficial effects: By employing the embodiments of this application, a current request is received; the current request is added to a queue of requests to be sent; when a preset sending condition is met, a target request is generated based on all requests in the queue of requests to be sent, and the target request is sent to a target cache, wherein all requests in the queue of requests to be sent are cleared upon sending the target request; when the preset sending condition is not met, and the next request meets the combination condition with the current request, the next request is added to the queue of requests to be sent after receiving the next request, thereby reducing the number of requests sent to the cache, and thus reducing the required bus resources, in order to improve the performance of the chip.

[0090] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary hardware platforms, or it can be implemented entirely by hardware. Based on this understanding, all or part of the technical solutions of this application that contribute to the background technology can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM (Read-Only Memory) / RAM (Random Access Memory), magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0091] The above description is the preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

Claims

1. A data transmission method, characterized by, The method comprises: receiving a current request; adding the current request to a to-be-sent request queue; generating a target request according to all requests in the to-be-sent request queue and sending the target request to a target cache when a preset sending condition is met, wherein all requests in the to-be-sent request queue are emptied along with the sending of the target request; when the preset sending condition is not met and a next request meets a combination condition with the current request, adding the next request to the to-be-sent request queue after the next request is received.

2. The method of claim 1, wherein, The preset sending condition comprises at least one of: a to-be-sent data size corresponding to the target request reaches a preset upper limit; the next request does not meet the combination condition with the current request.

3. The method of claim 2, wherein, The target request is a burst transmission type request; the to-be-sent data size corresponding to the target request is determined by a current burst transmission parameter of the target request.

4. The method of claim 1, wherein, The target request is a burst transmission type request, and the combination condition is that the next request corresponds to a same target cache as the current request, and an address corresponding to the next request and an address corresponding to the current request are burst size aligned addresses.

5. The method of claim 1, wherein, The current request and the next request are both write requests.

6. The method according to any one of claims 1 to 5, characterized in that, Before the current request is added to the to-be-sent request queue, the method further comprises: determining a target cache line in the target cache according to the current request; when the target cache line is in a dirty state, sending an eviction request to the target cache line, wherein the eviction request is used to evict dirty data in the target cache line in the dirty state.

7. A data transmission apparatus, characterized by comprising: The method comprises: a request processing module configured to receive a current request; a queue updating module configured to add the current request to a to-be-sent request queue; a target request sending module configured to generate a target request according to all requests in the to-be-sent request queue and send the target request to a target cache when a preset sending condition is met, wherein all requests in the to-be-sent request queue are emptied along with the sending of the target request; a combination prediction module configured to add a next request to the to-be-sent request queue after the next request is received when the preset sending condition is not met and the next request meets a combination condition with the current request.

8. A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by a processor to implement the method of any one of claims 1-6.

9. A computer program product comprising computer instructions, characterized in that, The computer instructions are executed by a processor to implement the method of any one of claims 1-6.

10. A computer device, comprising: The apparatus comprises a processor, a memory, and computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement the method of any one of claims 1-6.

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