A high-voltage power supply failure mode analysis method based on fuzzy dynamic fault tree

Abstract

The application discloses a high-voltage power supply failure mode analysis method based on a fuzzy dynamic fault tree, and belongs to the field of high-voltage power supply reliability engineering.System analysis and fault disintegration; a static fault tree is constructed; a dynamic fault tree is constructed; the dynamic fault tree is disintegrated into dynamic sub-fault trees, and the failure rate of the sub-dynamic fault trees is calculated; and the static fault tree and the dynamic sub-fault trees are combined for analysis.The application combines the dynamic fault tree with the fuzzy theory, considers the fuzziness of the logical relationship between faults in reality and the mutual influence of all bottom events, can accurately calculate the top event failure probability of the whole system more in line with the reality, and improves the accuracy and reliability of the failure rate analysis.

Description

Technical Field

[0001] This invention relates to the field of high-voltage power supply fault technology, and specifically to a high-voltage power supply fault mode analysis method based on fuzzy dynamic fault tree. Background Technology

[0002] Fault Tree Analysis (FTA) is a deductive method for analyzing system failures, either from top to bottom or bottom to top. It constructs a tree-like model using logical symbols and event relationships to trace the root cause of system failures (the top event). Its core lies in using Boolean logic (such as AND and OR gates) to combine low-order events, quantitatively or qualitatively assessing risk. It is widely used in high-reliability fields such as aerospace, nuclear power, and chemical engineering.

[0003] High-voltage power supplies, also known as high-voltage generators, refer to power supply equipment with an output voltage typically exceeding 5000 volts (5 kV), and sometimes reaching hundreds of thousands of volts or even higher. Their core function is to convert low-voltage input (such as AC mains power) into high-voltage output, while simultaneously meeting technical requirements such as stability, low ripple, and high precision. High-voltage power supplies have numerous applications in fields such as medical and healthcare, industrial manufacturing, and military aerospace. Due to their high precision, high-voltage power supplies, as energy components, are fundamental support equipment for modern technology, making fault mode analysis (FMA) and targeted design and maintenance essential. Existing methods, such as FMECA (Fault Mode, Effects, and Severity Analysis), cannot quantitatively analyze faults to determine their occurrence rate. While traditional FTA and dynamic FTA methods can perform qualitative and quantitative analysis of fault modes and consider the mutual influence between faults, they do not account for the ambiguity of this correlation. For example, the occurrence of event A does not necessarily lead to the occurrence of event B, but only has a probability of causing event B to occur. This ambiguity is something that dynamic FTA methods cannot consider. Furthermore, simply replacing existing static logic gates with dynamic logic gates ignores the mutual influence between lower-level faults belonging to different higher levels. This limits the accuracy and reference value of the failure mode analysis results for complex systems. Summary of the Invention

[0004] To overcome the aforementioned problems in existing technologies, this invention proposes a high-voltage power supply fault mode analysis method based on fuzzy dynamic fault trees, belonging to the field of high-voltage power supply reliability engineering. The method includes: system analysis and fault decomposition; construction of a static fault tree; construction of a dynamic fault tree; decomposition of the dynamic fault tree into dynamic sub-fault trees and calculation of the failure rate of the sub-dynamic fault trees; and synthesis analysis of the static fault tree and dynamic sub-fault trees. This invention combines dynamic fault trees with fuzzy theory, considering the fuzziness of logical relationships between faults in reality and the mutual influence of all underlying events. It can accurately calculate the failure probability of the top event of the entire system in a more realistic manner, improving the accuracy and reliability of failure rate analysis.

[0005] A high-voltage power supply fault mode analysis method based on fuzzy dynamic fault tree, such as Figure 1 As shown, the steps are as follows:

[0006] Step 1: System analysis and fault deconstruction;

[0007] Step 2: Construct a static fault tree;

[0008] Step 3: Construct a dynamic fault tree; identify fault modes with dynamic logical relationships, and replace the static logic gates connected to the fault modes with dynamic logical relationships with fuzzy dynamic logic gates;

[0009] Step 4: Decompose the dynamic fault tree into dynamic sub-fault trees and calculate the failure rate of the sub-dynamic fault trees;

[0010] Step 5: Combine and analyze the static fault tree and the dynamic sub-fault tree.

[0011] Furthermore, in step 1, the system analysis and fault decomposition process is as follows:

[0012] Step 1.1, determine the top event:

[0013] The top event is a top-level failure of the high-voltage power supply; the ultimate failure mode of the high-voltage power supply is an abnormal output of the high-voltage power supply system, denoted as... ;

[0014] Step 1.2, break down intermediate events:

[0015] The high-voltage power supply consists of three parts: the high-voltage section, the input protection section, and the control section. The high-voltage section and the input protection section operate under the control of the control section. Faults in these three sections do not affect each other, but a fault in any section will cause abnormal output of the high-voltage power supply. Level 1 events include high-voltage section faults. Control section malfunction and input protection section fault ;

[0016] The high-voltage section, control section, and input protection section are disassembled sequentially:

[0017] The high-voltage section comprises five parts: an inverter, a high-voltage transformer, a high-voltage filter circuit, a voltage multiplier rectifier circuit, and a voltage and current acquisition module. A malfunction in any of these five modules will cause a high-voltage section failure. Secondary events in the high-voltage section include inverter failure. High-voltage transformer fault High-voltage filter circuit fault 1. Voltage doubler rectifier circuit failure and voltage and current acquisition module failure ;

[0018] The control unit comprises six parts: a filament power supply control module, a suppression stage power supply control module, a suspension power supply control module, an acceleration stage power supply control module, a central processing unit, and a communication processing unit. A failure in any of these six parts will result in a control unit failure. Secondary events in the control unit include filament power supply control module failure P9 and suppression stage power supply control module failure P... 10 Floating power supply control module failure P 11 Accelerator stage power control module failure P 12 Central processing unit failure P 13 and communication processing unit failure P 14 ;

[0019] The input protection section comprises five parts: a 24V input module, a three-level surge protection module, a reverse power supply prevention module, a bipolar-to-unipolar conversion module, and a temperature monitoring module. A failure in any of these five parts will result in a failure in the control section. The secondary events of the input protection section include a 24V input module failure (P). 15 Level 3 lightning protection absorption module failure P 16 Preventing reverse power supply module failure P 17 Bipolar to unipolar conversion module fault P 18 Temperature monitoring module malfunction P 19 ;

[0020] Step 1.3, determine the underlying events:

[0021] Based on the secondary events P4 to P1 decomposed in step 1.2 19 The causes of Level 2 events are all simple electronic component or program failures at the underlying level, and cannot be further divided. The components involved in Level 2 events are broken down into simple electronic components or programs, and Level 3 events, i.e. underlying events, are defined according to the specific failure causes of Level 2 events, as shown in Table 1.

[0022] The causes of inverter module failure P4 include IGBT short-circuit failure. 20 IGBT open circuit failure P 21 1. Abnormal trigger pulse of control circuit P22 and the drive power supply is not working P 23 ;

[0023] Causes of high-voltage transformer fault P5 include short circuits in the current-carrying system windings. 24 Overheating of current-carrying system winding P 25 Short circuit between iron core segments P 26 and insulating oil aging P 27 ;

[0024] Causes of high-voltage filter circuit failure P6 include an open circuit in the filter capacitor. 28 , filter capacitor short circuit P 29 Overheating of filter inductor winding P 30 and filter inductor parameter drift P 31 ;

[0025] Causes of voltage doubler rectifier circuit P7 failure include short circuit of rectifier diode P. 32 1. Rectifier diode open circuit P 33 Ceramic capacitor short circuit P 34 And ceramic capacitor parameter drift P 35 ;

[0026] The causes of voltage and current acquisition module failure P8 include loss of voltage signal acquisition. 36 Excessive stream sampling error P 37 The causes of filament power control module failure P9 include filament controller signal loss. 38 1. Filament drive circuit open circuit P 39 Stability of connection to dynamic influence module P 40 ;

[0027] This leads to a failure in the suppression stage power control module P. 10 The reasons include output voltage overshoot P 41 Short circuit protection triggered P 42 firmware upgrade failed P 43 ;

[0028] Caused the floating power supply control module to malfunction P 11 The causes include abnormal voltage sampling P 44 Signal transmission abnormality P 45 The overheating of the control module triggered the protection P. 46 ;

[0029] This caused the acceleration stage power control module to malfunction. 12 The reasons include PWM signal loss P 47 short circuit in drive circuit P 48 The calculation error P of the summation algorithm 49 ;

[0030] Caused to central processing unit failure P 13 The reasons include abnormal power supply indication P in the power distribution system. 50 1. Start-stop control failure P 51 Data processing module error P 52 Central processor and communication module interface failure P 53 ;

[0031] Caused communication processing unit malfunction P 14 The reasons include data transmission interruption P 54 Signal decoding error P 55 Filament control and central processing unit signal loss P 56 Interference causes communication delay P 57 ;

[0032] Caused 24V input module malfunction P 15 The causes include input voltage regulator circuit failure P 58 Filter module failure P 59 Input voltage overshoot P 60 and protection module abnormal P 61 ;

[0033] This caused the third-level lightning protection absorption module to malfunction. 16 The reasons include short circuit of surge protection components P 62 Lightning protection response hysteresis P 63 Post-lightning strike recovery delay P 64 And the surge protection module is damaged. 65 ;

[0034] This leads to the failure of the reverse power supply module P. 17 Reasons include diode breakdown P 66 Open circuit diode P 67 Circuit load abnormality P 68 and pressure reverse flow P 69 ;

[0035] Single-stage conversion module failure P 18 Reasons include circuit switching failure P 70 Output voltage drift P 71 Control signal loss P 72 The current protection module malfunctioned. 73 ;

[0036] Caused temperature monitoring module malfunction P 19 Including temperature sensor failure P 74 Signal acquisition error P 75 Temperature data processing anomaly P 76 and overheat protection malfunction P 77 .

[0037] Furthermore, in step 2, the process of constructing the static fault tree is as follows:

[0038] Arrange the top event, first-level event, second-level event, and bottom-level event extracted in step 1 into a tree structure from top to bottom in rows;

[0039] Examine the relationships between different layers in the following order: top event and first-level event, first-level event and second-level event, and second-level event and bottom-level event.

[0040] The parent event occurs only when all the lower-level events have occurred, using an AND gate to link the parent and lower-level events;

[0041] When any one of the subordinate events occurs, the superior event will occur; use an OR gate to link the superior and subordinate events.

[0042] When one of the lower-level events occurs and the upper-level event occurs, an XOR gate is used to link the upper-level event and the lower-level event.

[0043] A parent event will only occur if more than or equal to r of the n lower-level events occur. A voting gate is used to link the parent and lower-level events.

[0044] There may be other events with subordinate events, but they have not yet been found; these are recorded as undeveloped events.

[0045] Low-level events are represented by circles, and intermediate events by rectangles; the gate symbols in static logic gates are as follows: Figure 2 As shown;

[0046] High voltage section fault Control section malfunction and input protection section fault When any one of these occurs, the high-voltage power supply output is abnormal. Both will occur; OR gates are used for linking.

[0047] Voltage signal acquisition lost P 36 And the current sampling error is too large P 37 The voltage and current acquisition module fault P8 will only occur when both faults occur, and an AND gate is used for connection.

[0048] High voltage section fault Control section malfunction and input protection section fault When any one of these occurs, the high-voltage power supply output is abnormal. Both will occur; OR gates are used for linking.

[0049] High voltage section fault Static fault tree: Inverter fault High-voltage transformer High-voltage filter circuit fault 1. Voltage doubler rectifier circuit failure and voltage and current acquisition module failure Any one of these events could lead to a fault in the high-voltage section. The occurrence;

[0050] The inverter malfunction :P 20 P 21 All occurred or P 21 Occurrence or P 23 Any of these occurrences will lead to inverter failure. The occurrence of P; therefore 20 P 21 After using AND gates, P is used separately. 21 P 23 Together, use OR gates and Link;

[0051] The high-voltage transformer fault :P 24 P 25 Simultaneous occurrence or P 26 P 27 Both occurrences simultaneously can lead to high-voltage transformer failure. The occurrence of P; therefore 24 P 25 and P 26 P 27 First, connect using AND gates, then connect using OR gates. Link;

[0052] The high-voltage filter circuit malfunction :P 28 P 29 All occurred or P 30 Occurrence or P 31 Both of these events can lead to high-voltage filter circuit failure. The occurrence of P; therefore 28 P 29 First, use an AND gate to connect, then connect to P respectively. 30 P 31 Together, use OR gates and Link;

[0053] The voltage doubler rectifier circuit malfunctioned. :P 32 P 33 Simultaneous occurrence or P 34 P 35 Both occurrences simultaneously can lead to high-voltage transformer failure. The occurrence of P; therefore 32 P 33and P 34 P 35 First, connect using AND gates, then connect using OR gates. Link;

[0054] The voltage and current acquisition module malfunctioned. :P 36 P 37 When they occur simultaneously It will only happen then; therefore P 36 P 37 Connect using an AND gate;

[0055] The fault was ultimately determined to be in the high-voltage section. The static fault tree; as shown in Figure 3(b);

[0056] Control section failure Static fault tree: Filament power supply control module fault P9, suppression stage power supply control module fault P 10 Floating power supply control module failure P 11 Accelerator stage power control module failure P 12 Central processing unit failure P 13 and communication processing unit failure P 14 The occurrence of any one of these will lead to a malfunction in the control system. The occurrence;

[0057] The filament power control module malfunctions (P9): P 38 P 39 Simultaneous occurrence or P 40 Any occurrence of these events will lead to a filament power supply control module malfunction P9; therefore, P... 38 P 39 After using an AND gate to connect with P 40 Ultimately, it connects to P9 via an OR gate;

[0058] The suppression stage power control module malfunction P 10 :P 41 P 42 Simultaneous occurrence or P 43 All of these occurrences will lead to a failure of the suppression stage power control module. 10 The occurrence of P; therefore 41 P 42 After using an AND gate to connect with P 43 Ultimately, through the OR gate and P 10 Link;

[0059] The floating power supply control module malfunction P 11 :P 44 P 45 Simultaneous occurrence or P 46 All of these events will lead to a malfunction of the floating power supply control module.11 The occurrence of P; therefore 44 P 45 After using an AND gate to connect with P 46 Ultimately, through the OR gate and P 11 Link;

[0060] The acceleration stage power control module malfunction P 12 :P 47 P 48 Simultaneous occurrence or P 49 All of these events will lead to a malfunction of the floating power supply control module. 12 The occurrence of P; therefore 47 P 48 After using an AND gate to connect with P 49 Ultimately, through the OR gate and P 12 Link;

[0061] The central processing unit failure P 13 :P 50 P 51 All occurred or P 52 Occurrence or P 53 All of these events will lead to a central processing unit (CPU) failure. 13 The occurrence of P 50 P 51 First, use an AND gate to connect, then connect with P. 52 P 53 Together, use OR gates with P 13 Link;

[0062] The communication processing unit malfunction P 14 :P 54 P 55 Simultaneous occurrence or P 56 P 57 Both occurrences simultaneously will lead to a communication processing unit malfunction. 14 The occurrence of P; therefore 54 P 55 and P 56 P 57 First, connect them using AND gates, then connect them to P using OR gates. 14 Link;

[0063] The final diagnosis was a fault in the control section. The static fault tree; as shown in Figure 3(c);

[0064] Input protection section malfunction Static fault tree: 24V input module fault P 15 Level 3 lightning protection absorption module failure P 16 Preventing reverse power supply module failure P 17 Bipolar to unipolar conversion module fault P 18Temperature monitoring module malfunction P 19 Any one of these events will cause the input protection section to malfunction. occur;

[0065] The 24V input processing module P 15 :P 58 P 59 Simultaneous occurrence or P 60 P 61 Both occurrences simultaneously will lead to a communication processing unit malfunction. 14 The occurrence of P; therefore 58 P 59 and P 60 P 61 First, connect using an AND gate, then connect using an OR gate to P. 15 Link;

[0066] The three-level lightning protection absorption module P 16 :P 62 P 63 Simultaneous occurrence or P 64 P 65 Both occurrences will cause the Level 3 lightning protection absorption module P to... 16 The occurrence of P; therefore 62 P 63 and P 64 P 65 First, connect them using AND gates, then connect them to P using OR gates. 16 Link;

[0067] The reverse power supply module failure prevention P 17 :P 66 P 67 All occurred or P 68 Occurrence or P 69 All of these occurrences will lead to a failure of the reverse power supply module P. 17 The occurrence of P; therefore 66 P 67 First, use an AND gate to connect, then connect with P. 68 P 69 Together, use OR gates with P 17 Link;

[0068] The bipolar-to-unipolar conversion module malfunction P 18 :P 70 P 71 All occurred or P 72 Occurrence or P 73 Both occurrences will lead to failure of the bipolar-to-unipolar conversion module P. 18 The occurrence of P; therefore 70 P 71 First, use an AND gate to connect, then connect with P. 72 P73 Together, use OR gates with P 18 Link;

[0069] The temperature monitoring module malfunctioned (P) 19 :P 75 P 76 All occurred or P 74 Occurrence or P 77 All of these events will lead to a malfunction of the temperature monitoring module. 19 The occurrence of P; therefore 75 P 76 First, use an AND gate to connect, then connect with P. 74 P 77 Together, use OR gates with P 19 Link;

[0070] The final conclusion was that the input protection section was faulty. The static fault tree is shown in Figure 3(d).

[0071] Furthermore, in step 3, the process of constructing the dynamic fault tree is as follows:

[0072] The types, functions, and meanings of dynamic logic gates and fuzzy dynamic logic gates are as follows: Figure 4 As shown;

[0073] Step 3.1, confirm the relationship between the events:

[0074] If events A and B occur sequentially within 10 seconds, and the occurrence time of event A is earlier than that of event B, and the output event Y occurs, then the priority AND gate PAND is used instead of the original static logic gate.

[0075] If event A and event B, or multiple events, occur sequentially from A to B or in chronological order, and event Y is output, then the sequential dependent gate SEQ is used instead of the original static logic gate.

[0076] If events A and B occur sequentially from A to B or in chronological order, the output event Y occurs; otherwise, the probability of Y occurring is ε, which is the fuzzy functional correlation degree, and the range of ε is 0.05-0.95. In this case, the fuzzy sequential correlation gate FSEQ is used to replace the original static logic gate.

[0077] If triggering event A causes related event B to occur and output event Y to occur, then the function-dependent gate FDEP is used instead of the original static logic gate.

[0078] If the occurrence of event A does not directly cause the occurrence of output event Y, but probabilistically triggers the occurrence of related event B and causes the occurrence of output event Y, then the fuzzy functional related gate FFDEP is used to replace the original static logic gate.

[0079] If input event A fails, backup event B starts working; if backup event B also fails, output event Y occurs. If backup event B does not work, it will not fail, and the cold spare gate CSP will be used to replace the original static logic gate.

[0080] If input event A fails, backup event B starts working; if backup event B also fails, output event Y occurs. If whether backup event B works or not does not affect the failure rate, then the warm spare gate (WSP) is used instead of the original static logic gate.

[0081] If input event A fails, backup event B starts working; if backup event B also fails, output event Y occurs. Whether backup event B works or not affects the failure rate, so a hot spare gate (HSP) is used instead of the original static logic gate.

[0082] Step 3.2: Based on the static fault tree, identify the fault modes with dynamic logical relationships, and replace the static logic gates connected to the fault modes with dynamic logical relationships with fuzzy dynamic logic gates.

[0083] Step 3.2.1, fault in the high-voltage section Based on the static fault tree, fault modes with dynamic logical relationships are identified. Static logic gates connected to fault modes with dynamic logical relationships are replaced with fuzzy dynamic logic gates, forming faults in the high-voltage section. The dynamic fault tree is shown in Figure 5(a);

[0084] Inverter malfunction middle: , They occurred sequentially within 10 seconds, and Prior to When it occurs, excessive current causes This occurred, causing an inverter malfunction. If it happens, then , and If dynamic logical relationships exist, then a PAND gate is used instead of an AND gate. , Connected AND gates;

[0085] High voltage transformer fault middle: and The occurrence of this may directly trigger This reflects and and The fuzzy functional dependencies among the three; to model the fuzzy triggering behavior, the fuzzy functional dependence gate FFDEP is used to describe the main fault ( , For dependent events The direct impact; when , When this occurs, the fuzzy function-dependent gate FFDEP is triggered. probability , The range is 0.05-0.95, and it does not need to wait for its own conditions to be met; the fuzzy functional correlation gate FFDEP is used instead of AND. , Connected AND gates;

[0086] High voltage filter circuit failure middle: , There is a vague sequential relationship between them. Prior to When it happens, occur; Prior to When it happens, The probability of occurrence is , The range is 0.05-0.95; therefore, the fuzzy sequential correlation gate FSEQ is used instead. , Connected AND gates;

[0087] Fault in the voltage doubler rectifier circuit middle: The occurrence directly triggers And led to The occurrence, The occurrence of this will not lead to The occurrence of the fault; the main fault is described using the Functionally Dependent Prefix (FDEP) gate. Direct impact of dependency failures; use functionally dependent gates (FDEP gates) instead. , Connected AND gates;

[0088] Step 3.2.2, in the case of a control section fault. Based on the static fault tree, fault modes with dynamic logical relationships are identified. Static logic gates connected to fault modes with dynamic logical relationships are replaced with fuzzy dynamic logic gates, forming control part faults. The dynamic fault tree is shown in Figure 5(b);

[0089] Filament power control module malfunction Chinese: P 38 With P 39 There is a time-order dependency between them, if P 38 First, it occurs, causing the control signal to be lost and triggering P. 39If the sequence of occurrences is reversed, the system enters a failure state; if the sequence of occurrences is reversed, the system failure probability is... , The range is 0.05-0.95; the fuzzy sequential correlation gate FSEQ is used instead of P. 38 With P 39 Connected to the door;

[0090] Acceleration stage power control module malfunction Chinese: P 47 P 48 There is a sequential logical relationship between them, when P 47 Prior to P 48

[0091] When it happens, Since this occurs, the sequential correlation gate SEQ is used instead of P. 47 P 48 Connected AND gates;

[0092] Central processing unit malfunction China: To and Backup of component system settings, when , When it happens, the backup system , When the system starts working, and the backup system also fails, the corresponding higher-level failure occurs. , This will only happen if there is a malfunction in the control section. Add a backup system based on the static fault tree , ; and will , Through the newly added cold spare parts gate CSP and Connect, , Through the newly added cold spare parts gate CSP and Establish connection; in case of fault and In the design of the system, backups were set up for the corresponding modules. and When an incident occurs, the backup module starts working; the failure only occurs when the backup module also fails.

[0093] Step 3.2.3, fault in the input protection section Based on the static fault tree, fault modes with dynamic logical relationships are identified. Static logic gates connected to fault modes with dynamic logical relationships are replaced with fuzzy dynamic logic gates to form input protection section faults. The dynamic fault tree is shown in Figure 5(c);

[0094] In the 24V input processing module P 15 Chinese: P 60 With P 61 There is a temporal relationship between them, when P 60 When it occurs, it will cause P to be triggered. 61 This can lead to system failure; if P 61 Prior to P 60 If this occurs, it will not cause a system failure; therefore, a sequential dependency gate (SEQ) is used instead of P. 60 P 61 Connected AND gates;

[0095] In the three-level lightning protection absorption module P 16 Chinese: P 62 With P 63 There is a functional dependency between them; P 62 When it occurs, P is triggered. 63 The probability is No need to wait for other conditions. The range is 0.05-0.95; the fuzzy functional correlation gate FFDEP is used instead of P. 62 P 63 Connected AND gates;

[0096] To prevent reverse power supply module failure P 17 Chinese: P 66 With P 67 There is a time order dependency between P and P. 66 First it happens, then P 67 If this occurs, the system enters a failure state; if the order is reversed or both occur simultaneously, the probability of triggering a critical failure is... , The range is 0.05-0.95; the fuzzy sequential correlation gate FSEQ is used instead of P. 66 With P 67 Connected AND gates;

[0097] Fault in bipolar-to-unipolar conversion module P 18 Chinese: P 70 With P 71 There is a time-sequence dependency. First it happened, then If the sequence of events occurs, the system enters a failure state; if the sequence is reversed or both occur simultaneously, no critical failure will be triggered; in this case, a priority AND gate (PAND) is used instead of an AND gate (P). 70 P 71 Connected AND gates;

[0098] Temperature monitoring module malfunction P 19 Chinese: P 75 With P 76There is a direct functional dependency between them, when When it occurs, it will be forcibly triggered. No need to wait for other conditions; use fuzzy sequential correlation gate FDEP instead of P. 75 P 76 Connected AND gates.

[0099] Furthermore, in step 4, the process of decomposing the dynamic fault tree into dynamic sub-fault trees is as follows:

[0100] Step 4.1, decompose the dynamic fault tree into dynamic sub-fault trees:

[0101] The purpose of decomposition is to separate the dynamic fault tree from the static fault tree, and to treat the dynamic logic gates and related underlying events as a new event.

[0102] First, find all dynamic logic gates in the dynamic fault tree, and regard the output of each dynamic logic gate as a new event D. The structure of D is the dynamic logic gate separated from the dynamic fault tree and the event that constitutes the dynamic logic gate. Figure 6(a) shows the structure of event D1. The new event D is used to replace the dynamic logic gate in the original dynamic fault tree as shown in Figure 6(b)-(d). The structure of the dynamic logic gate is separated into a fault tree to calculate the failure rate of event D.

[0103] P 20 P 22 The dynamic logic gate formed is event D1; P 20 P 24 P 25 The dynamic logic gate formed is event D2; P 28 P 29 The dynamic logic gate formed is event D3; P 32 P 33 The dynamic logic gate formed is event D4; P 38 P 39 The dynamic logic gate formed is event D5; P 47 P 48 The dynamic logic gate formed is event D6; P 52 The dynamic logic gate formed by R1 is event D7; P 54 The dynamic logic gate formed by R2 is event D8; P 60 P 61 The dynamic logic gate formed is event D9; P 62 P 63 The dynamic logic gate formed is event D10; P 66 P 67 The dynamic logic gate formed is event D11; P 70 P 71The dynamic logic gate formed is event D12; P 75 P 76 The dynamic logic gate is event D13; as shown in Figures 6(a) to (d);

[0104] Finally, the failure rates of the events represented by the dynamic sub-fault trees are incorporated into the static fault tree for the final solution.

[0105] Step 4.2, Failure Rate Modeling:

[0106] Each underlying event represents a failure rate. Obtaining the failure rate model of the underlying events is a prerequisite for solving the failure rate of the dynamic sub-fault tree. The distribution and parameters of the failure rate are obtained from the manuals of the components used by the power supply, as shown in Table 2.

[0107] The failure rate follows distributions including exponential, Weibull, log-normal, and Poisson distributions; each distribution includes a probability density function, a cumulative distribution function, and a failure probability; the probability density function and the cumulative distribution function are inherent properties in statistics; the failure probability is the probability that a device or system will fail at failure time T, and the failure probability of each fault can be obtained through the following formula;

[0108] The failure rate of the exponential distribution is modeled as follows:

[0109] probability density function of exponential distribution for:

[0110] (3-30);

[0111] Cumulative distribution function of exponential distribution for:

[0112] (3-31);

[0113] Failure probability of exponential distribution for:

[0114] (3-32);

[0115] In the formula, The failure rate of the exponential distribution is denoted by the parameter. , representing the probability of system failure per unit time, in hours; T is the failure time, in hours; if the failure rate Therefore, the probability of a system failure per hour is 1%; e is a constant.

[0116] The failure rate of the Weibull distribution is modeled as follows:

[0117] The probability density function of the Weibull distribution for:

[0118] (3-33);

[0119] Cumulative distribution function of Weibull distribution for:

[0120] (3-34);

[0121] Failure probability of Weibull distribution for:

[0122] (3-36);

[0123] In the formula, The scale parameter determines the range of failure time; The shape parameter determines the shape of the failure mode;

[0124] The failure rate model for the log-normal distribution is as follows:

[0125] probability density function of log-normal distribution for:

[0126] (3-37);

[0127] Cumulative distribution function of log-normal distribution for:

[0128] (3-38);

[0129] Failure probability of a log-normally distributed fault for:

[0130] (3-39);

[0131] In the formula, The mean of a log-normal distribution; is the standard deviation; T is the failure time of the event, in hours; t represents the failure time in the integral formula;

[0132] The failure rate model for the Poisson distribution is as follows:

[0133] probability density function of Poisson distribution for;

[0134] (3-41);

[0135] Cumulative distribution function of Poisson distribution for:

[0136] (3 - 42);

[0137] Failure probability of faults with Poisson distribution is:

[0138] (3 - 43);

[0139] In the formula, k is the number of times an event occurs; the parameter of the Poisson distribution represents the number of events expected to occur per unit time; when , it means that 5 events occur on average per unit time;

[0140] Step 4.3, Dynamic logic gate derivation and calculation:

[0141] According to the dynamic sub - fault tree, regard the output of each dynamic logic gate as an independent event; regard the whole dynamic sub - tree as an event, calculate the failure rate of the dynamic sub - fault tree event, and finally substitute the independent events into the static fault tree for the calculation of the top - event failure probability;

[0142] (1) Priority AND gate PAND:

[0143] Failure probability of the priority AND gate is expressed by double integral as:

[0144] (3 - 44);

[0145] Where is the failure probability of the priority AND gate, is the probability density function of is the probability density function of is the failure time of is the failure time of

[0146] (2) Sequence - dependent gate SEQ:

[0147] [[ID=……]]Failure probability of the sequence - dependent gate is expressed as:

[0148] (3 - 45);

[0149] Where<……>is the failure probability of the priority AND gate, is the cumulative distribution function of is the cumulative distribution function of Note: There seems to be some incomplete or incorrect formatting in the original text, especially in the part where some tags are not fully specified in the description. I've translated as accurately as possible based on the provided content. for Failure time, for Failure time;

[0150] (3) Fuzzy sequential correlation gate FSEQ:

[0151] Failure probability of fuzzy sequential correlation gate Represented as:

[0152] (3-46);

[0153] in, for The cumulative distribution function, For the event The cumulative distribution function, for Failure time, for Failure time; for and Fuzzy order correlation;

[0154] (4) Functionally Dependent Expansion Gate (FDEP):

[0155] Failure probability of function-dependent gates Represented as:

[0156] (3-47);

[0157] in The failure probability of a function-dependent gate. for The cumulative distribution function, for The cumulative distribution function;

[0158] (5) Fuzzy Functional Related Gate FFDEP:

[0159] Failure probability of fuzzy functionally related gates Represented as:

[0160] (3-48);

[0161] in, For the failure probability of the fuzzy functionally related gate, for The cumulative distribution function, for The cumulative distribution function; for and Fuzzy functional relevance;

[0162] (3) Cold Storage Door (CSP) and Warm Storage Door (WSP):

[0163] The failure probabilities of the cold storage gate (CSP) and the warm storage gate (WSP) are difficult to solve mathematically. Therefore, a Monte Carlo simulation method is used for estimation. In this method, a loop is constructed in the computer program with time as the variable. For each unit of time, the failure probability of the underlying events at the current time is calculated based on the failure rate model of the underlying events. Then, a random number is used to determine whether the underlying events have failed. Finally, the properties of the dynamic logic gates are used to determine whether the top event has failed. If the top event has not failed, the system is trained until the top event fails. The Monte Carlo simulation is performed 10,000 times to obtain the probability of system failure within a specified time (corresponding to the value of t in the failure probability formula).

[0164] (4) Heat storage gate HSP:

[0165] Failure probability of thermal storage door Represented as:

[0166] (3-49);

[0167] in, For the event The cumulative distribution function; n is the number of events connected to the thermal storage gate; i is the i-th event among the n events;

[0168] Combining the failure rate modeling in step 4.2, the parameters of each event are substituted into the calculation formula of the corresponding dynamic logic gate to obtain the failure probability of the event containing the dynamic logic gate.

[0169] Furthermore, in step 5, the method for synthesizing and analyzing the dynamic subtree and the static subtree is as follows:

[0170] After calculating the failure rate of the events represented by the dynamic logic gates in step 4, the dynamic fault tree is transformed into a static fault tree. The BDD quantitative analysis method of the static fault tree is used to analyze the static fault tree to obtain the probability of the top event.

[0171] An electronic device includes: one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs are configured to perform the above-described high-voltage power supply fault mode analysis method.

[0172] A computer-readable storage medium storing program code that can be invoked by a processor to execute the above-described high-voltage power supply fault mode analysis method.

[0173] The technical effects of this invention are as follows:

[0174] This invention disassembles the high-voltage section of a high-voltage power supply to construct a dynamic fault tree and perform quantitative analysis to obtain the high-voltage section failure rate. By fuzzifying the dynamic logic gates, it more accurately and realistically describes the sequence and coupling relationships between faults, better describing the failure probability of some fault modes that cannot be accurately obtained in reality. This invention combines fuzzy theory with the dynamic fault tree from both the fault tree structure and input data aspects, improving the scientific rigor and accuracy of high-voltage power supply failure rate prediction. Considering the fuzziness of the dynamic logic gates and the mutual influence between all underlying events, it uses probability theory to calculate the failure rate, enabling more accurate and realistic calculations of the failure rate of complex systems or processes. This eliminates the problem of inaccurate failure rate estimation in traditional methods, improving the accuracy and reliability of fault mode, impact, and severity analysis. Attached Figure Description

[0175] Figure 1 This is an overall flowchart of the present invention;

[0176] Figure 2 This is a symbolic diagram of a static fault tree;

[0177] Figure 3(a) shows a fault at the top layer of the high-voltage power supply. The static fault tree; Figure 3(b) shows the fault in the high-voltage section. The static fault tree; Figure 3(c) shows the faults in the control section. The static fault tree; Figure 3(d) shows the fault in the input protection section. Static fault tree;

[0178] Figure 4 A symbolic diagram of a fuzzy dynamic logic gate;

[0179] Figure 5(a) shows a fault in the high-voltage section. The dynamic fault tree; Figure 5(b) shows the faults in the control section. The dynamic fault tree; Figure 5(c) shows the fault in the input protection section. Dynamic fault tree;

[0180] Figure 6(a) shows the structure of event D1; Figure 6(b) shows the control section fault after eliminating the dynamic logic gate. The dynamic fault tree; Figure 6(c) shows the input protection section fault of the dynamic logic gate after elimination. The dynamic fault tree; Figure 6(d) shows the input protection section fault after eliminating the dynamic logic gate. Dynamic fault tree. Detailed Implementation

[0181] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments and accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0182] Taking a high-voltage power supply as an example, the technical solution of the present invention will be described.

[0183] First, identify the top event: a fault at the top level of the high-voltage power supply manifests as an abnormal output. We define the ultimate failure mode of the high-voltage power supply as an abnormal output from the high-voltage power supply system, denoted as... .

[0184] Dissecting the intermediate events, the operating principle of the high-voltage power supply is as follows: the high-voltage section and the input protection section operate under the control of the control section. These three sections are independent, and a fault in any one section will cause abnormal output from the high-voltage power supply. The first-level event is defined as: a fault in the high-voltage section. Control section malfunction Input protection section malfunction .

[0185] Next, the high-voltage section, control section, and input protection section are disassembled sequentially. The high-voltage section comprises five parts: inverter, high-voltage transformer, high-voltage filter circuit, voltage doubler rectifier circuit, and voltage / current acquisition module. A malfunction in any of these modules will cause a high-voltage section failure. Therefore, a failure in these five parts is recorded as a level-two event. The control section comprises six parts: four power control modules, central processing unit, and communication processing unit. A malfunction in any of these six modules will cause a control section failure. Therefore, a failure in these five parts is recorded as a level-two event. The input protection section comprises five parts: 24V input module, three-level surge protection module, reverse power supply prevention module, bipolar-to-unipolar conversion module, and temperature monitoring module. A malfunction in any of these five modules will cause a control section failure. Therefore, a failure in these five parts is recorded as a level-two event.

[0186] The secondary events identified above are all caused by simple electronic component or program malfunctions at the underlying level and cannot be further subdivided. Therefore, all causes leading to secondary events are defined as underlying events, as shown in Table 1.

[0187] Construct a static fault tree. The high-voltage section, input protection section, and control section are independent, and a fault in each section will cause abnormal output of the high-voltage power supply. Therefore, an OR gate is used to connect to the top event (abnormal output of high-voltage power supply), as shown in Figure 3(a).

[0188] All event codes in the following text are shown in Table 1. Taking the high-voltage section as an example for analysis, the events... , When both occur simultaneously, it will lead to a Level 2 event. The occurrence; the event , When both occur simultaneously, it will lead to a Level 2 event. The occurrence; the event , When both occur simultaneously, it will lead to a Level 2 event. The occurrence; the event , When both occur simultaneously, it will lead to a Level 2 event. The occurrence; the event , When both occur simultaneously, it will lead to a Level 2 event. The occurrence; the event , When both occur simultaneously, it will lead to a Level 2 event. The occurrence; the event , When both occur simultaneously, it will lead to a Level 2 event. The occurrence of the event was determined. The sub-fault trees of the three first-level events are shown in Figures 3(b) to (d).

[0189] Table 1. Event Disassembly Results and Code Diagram

[0190]

[0191]

[0192]

[0193]

[0194]

[0195]

[0196]

[0197] After constructing the static fault tree, we continue to analyze the relationships and impacts between the underlying events.

[0198] In submodule In the middle, the voltage multiplier capacitor failed ( ) and winding short circuit ( There is a strict temporal dependency between them. If First it happened, then If the event occurs only once, the system enters a failure state; if the order is reversed or both occur simultaneously, no critical failure will be triggered. To accurately describe this characteristic, a priority AND gate is used instead of a traditional AND gate to dynamically characterize the temporal dependency of sub-events.

[0199] In submodule In the middle, the voltage doubler rectifier circuit is faulty ( ) and winding short circuit ( The occurrence of this may directly trigger a filter capacitor failure. This reflects the fuzzy functional dependency among the three. To model this fuzzy triggering behavior, a fuzzy functional dependency gate is used to describe the main fault ( , ) for dependent events ( The direct impact of ). When When it occurs, the FDEP gate uses probability trigger It does not need to wait for its own conditions to be met.

[0200] In submodule In the middle, the filter capacitor is open-circuited ( ), filter capacitor short circuit ( They have a loose temporal relationship. For example, when First happened and then When this occurs, the system may enter a failure state; otherwise, no fault will occur. To describe this behavior, fuzzy sequential correlation gates are introduced instead of traditional logic gates, thus accurately reflecting the sequential dependence of faults in the filter circuit.

[0201] The final dynamic fault tree is shown in Figures 5(a) to 5(c).

[0202] Decompose the dynamic fault subtree and replace the dynamic logic gates in the dynamic fault tree with a synthesized event, P 20 P 22 The dynamic logic gates formed are events D1 and P. 20 P 24 P 25 The dynamic logic gates formed are events D2 and P. 28 P 29 The dynamic logic gates formed are events D3 and P. 32 P 33 The constructed dynamic logic gate is time D4, as shown in Figures 6(a) to 6(d). Specific fault parameters for the high-voltage section are shown in Table 2. For the disassembled dynamic logic gates, the formulas and methods in step 4.3 are used for calculation, and the final failure rates of the dynamic logic gates are shown in Table 3, where the failure rate of the FFDEP gate is... FSEQ gate .

[0203] Table 2 Distribution and parameters of the failure rate of underlying events in high-voltage power supplies

[0204]

[0205] Table 3 Calculation results of the failure probability of the dynamic subtree in the high-voltage section of the high-voltage power supply

[0206]

[0207] By incorporating the failure rate of dynamic logic gates into the static fault trees in Figures 6(a) to 6(d) and performing quantitative analysis using BDD analysis, the occurrence rate of the top event (abnormal output of high-voltage power supply) is finally obtained as follows: .

Claims

1. A high-voltage power supply fault mode analysis method based on fuzzy dynamic fault tree, characterized in that, The high-voltage power supply fault mode analysis method includes the following steps: Step 1: System analysis and fault deconstruction; Step 1.1, determine the top event: The top event is a top-level fault in the high-voltage power supply; Step 1.2, break down intermediate events; The top-level faults of a high-voltage power supply include three primary events: high-voltage section faults, input protection section faults, and control section faults. Secondary events, or intermediate events, are defined based on the specific fault causes of each primary event. Step 1.3, determine the underlying events: Level 3 events, or lower-level events, are defined based on the specific causes of failures in Level 2 events; Step 2: Construct a static fault tree; Step 3: Construct a dynamic fault tree; identify fault modes with dynamic logical relationships, and replace the static logic gates connected to the fault modes with dynamic logical relationships with fuzzy dynamic logic gates; Step 4: Decompose the dynamic fault tree into dynamic sub-fault trees and calculate the failure rate of the sub-dynamic fault trees; Step 5: Analysis of the synthesis of static fault tree and dynamic sub-fault tree: After calculating the failure rate of the events represented by the dynamic logic gates in step 4, the dynamic fault tree is transformed into a static fault tree. The BDD quantitative analysis method of the static fault tree is used to analyze the static fault tree to obtain the probability of the top event.

2. The high-voltage power supply fault mode analysis method based on fuzzy dynamic fault tree according to claim 1, characterized in that, In step 1, the system analysis and fault decomposition process is as follows: Step 1.1, determine the top event: The top event is a top-level failure of the high-voltage power supply; the ultimate failure mode of the high-voltage power supply is an abnormal output of the high-voltage power supply system, denoted as... ; Step 1.2, break down intermediate events: The high-voltage power supply consists of three parts: the high-voltage section, the input protection section, and the control section. The high-voltage section and the input protection section operate under the control of the control section. Faults in these three sections do not affect each other, but a fault in any section will cause abnormal output of the high-voltage power supply. Level 1 events include high-voltage section faults. Control section malfunction and input protection section fault ; The high-voltage section, control section, and input protection section are disassembled sequentially: The high-voltage section comprises five parts: an inverter, a high-voltage transformer, a high-voltage filter circuit, a voltage multiplier rectifier circuit, and a voltage and current acquisition module. A malfunction in any of these five modules will cause a high-voltage section failure. Secondary events in the high-voltage section include inverter failure. High-voltage transformer fault High-voltage filter circuit fault 1. Voltage doubler rectifier circuit failure and voltage and current acquisition module failure ; The control unit comprises six parts: a filament power supply control module, a suppression stage power supply control module, a suspension power supply control module, an acceleration stage power supply control module, a central processing unit, and a communication processing unit. A failure in any of these six parts will result in a control unit failure. Secondary events in the control unit include filament power supply control module failure P9 and suppression stage power supply control module failure P... 10 Floating power supply control module failure P 11 Accelerator stage power control module failure P 12 Central processing unit failure P 13 and communication processing unit failure P 14 ; The input protection section comprises five parts: a 24V input module, a three-level surge protection module, a reverse power supply prevention module, a bipolar-to-unipolar conversion module, and a temperature monitoring module. A failure in any of these five parts will result in a failure in the control section. The secondary events of the input protection section include a 24V input module failure (P). 15 Level 3 lightning protection absorption module failure P 16 Preventing reverse power supply module failure P 17 Bipolar to unipolar conversion module fault P 18 Temperature monitoring module malfunction P 19 ; Step 1.3, determine the underlying events: Based on the secondary events P4 to P1 decomposed in step 1.2 19 The causes of Level 2 events are all simple electronic component or program malfunctions at the lower level, and cannot be further divided. The components involved in Level 2 events are broken down into simple electronic components or programs, and Level 3 events, i.e., lower-level events, are defined based on the specific malfunction causes of Level 2 events. The causes of inverter module failure P4 include IGBT short-circuit failure. 20 IGBT open circuit failure P 21 1. Abnormal trigger pulse of control circuit P 22 and the drive power supply is not working P 23 ; Causes of high-voltage transformer fault P5 include short circuits in the current-carrying system windings. 24 Overheating of current-carrying system winding P 25 Short circuit between iron core segments P 26 and insulating oil aging P 27 ; Causes of high-voltage filter circuit failure P6 include an open circuit in the filter capacitor. 28 , filter capacitor short circuit P 29 Overheating of filter inductor winding P 30 and filter inductor parameter drift P 31 ; Causes of voltage doubler rectifier circuit P7 failure include short circuit of rectifier diode P. 32 1. Rectifier diode open circuit P 33 Ceramic capacitor short circuit P 34 And ceramic capacitor parameter drift P 35 ; The causes of voltage and current acquisition module failure P8 include loss of voltage signal acquisition. 36 Excessive stream sampling error P 37 The causes of filament power control module failure P9 include filament controller signal loss. 38 1. Filament drive circuit open circuit P 39 Stability of connection to dynamic influence module P 40 ; This leads to a failure in the suppression stage power control module P. 10 The reasons include output voltage overshoot P 41 Short circuit protection triggered P 42 firmware upgrade failed P 43 ; Caused the floating power supply control module to malfunction P 11 The causes include abnormal voltage sampling P 44 Signal transmission abnormality P 45 The overheating of the control module triggered the protection P. 46 ; This caused the acceleration stage power control module to malfunction. 12 The reasons include PWM signal loss P 47 short circuit in drive circuit P 48 The calculation error P of the summation algorithm 49 ; Caused to central processing unit failure P 13 The reasons include abnormal power supply indication P in the power distribution system. 50 1. Start-stop control failure P 51 Data processing module error P 52 Central processor and communication module interface failure P 53 ; Caused communication processing unit malfunction P 14 The reasons include data transmission interruption P 54 Signal decoding error P 55 Filament control and central processing unit signal loss P 56 Interference causes communication delay P 57 ; Caused 24V input module malfunction P 15 The causes include input voltage regulator circuit failure P 58 Filter module failure P 59 Input voltage overshoot P 60 and protection module abnormal P 61 ; This caused the third-level lightning protection absorption module to malfunction. 16 The reasons include short circuit of surge protection components P 62 Lightning protection response hysteresis P 63 Post-lightning strike recovery delay P 64 And the surge protection module is damaged. 65 ; This leads to the failure of the reverse power supply module P. 17 Reasons include diode breakdown P 66 Open circuit diode P 67 Circuit load abnormality P 68 and pressure reverse flow P 69 ; Single-stage conversion module failure P 18 Reasons include circuit switching failure P 70 Output voltage drift P 71 Control signal loss P 72 The current protection module malfunctioned. 73 ; Caused temperature monitoring module malfunction P 19 Including temperature sensor failure P 74 Signal acquisition error P 75 Temperature data processing anomaly P 76 and overheat protection malfunction P 77 .

3. The high-voltage power supply fault mode analysis method based on fuzzy dynamic fault tree according to claim 2, characterized in that, In step 2, the process of constructing the static fault tree is as follows: Arrange the top event, first-level event, second-level event, and bottom-level event extracted in step 1 into a tree structure from top to bottom in rows; Examine the relationships between different layers in the following order: top event and first-level event, first-level event and second-level event, and second-level event and bottom-level event. The parent event occurs only when all the lower-level events have occurred, using an AND gate to link the parent and lower-level events; When any one of the subordinate events occurs, the superior event will occur; use an OR gate to link the superior and subordinate events. When one of the lower-level events occurs and the upper-level event occurs, an XOR gate is used to link the upper-level event and the lower-level event. A parent event will only occur if more than or equal to r of the n lower-level events occur. A voting gate is used to link the parent and lower-level events. There are events with subordinate events that exist but have not yet been found; these are recorded as undeveloped events. High voltage section fault Control section malfunction and input protection section fault When any one of these occurs, the high-voltage power supply output is abnormal. Both will occur; OR gates are used for linking. Voltage signal acquisition lost P 36 And the current sampling error is too large P 37 The voltage and current acquisition module fault P8 will only occur when both faults occur, and an AND gate is used for connection. High voltage section fault Control section malfunction and input protection section fault When any one of these occurs, the high-voltage power supply output is abnormal. Both will occur; OR gates are used for linking. High voltage section fault Static fault tree: Inverter fault High-voltage transformer High-voltage filter circuit fault 1. Voltage doubler rectifier circuit failure and voltage and current acquisition module failure Any one of these events could lead to a fault in the high-voltage section. The occurrence; The inverter malfunction :P 20 P 21 All occurred or P 21 Occurrence or P 23 Any of these occurrences will lead to inverter failure. The occurrence of P; therefore 20 P 21 After using AND gates, P is used separately. 21 P 23 Together, use OR gates and Link; The high-voltage transformer fault :P 24 P 25 Simultaneous occurrence or P 26 P 27 Both occurrences simultaneously can lead to high-voltage transformer failure. The occurrence of P; therefore 24 P 25 and P 26 P 27 First, connect using AND gates, then connect using OR gates. Link; The high-voltage filter circuit malfunction :P 28 P 29 All occurred or P 30 Occurrence or P 31 Both of these events can lead to high-voltage filter circuit failure. The occurrence of P; therefore 28 P 29 First, use an AND gate to connect, then connect to P respectively. 30 P 31 Together, use OR gates and Link; The voltage doubler rectifier circuit malfunctioned. :P 32 P 33 Simultaneous occurrence or P 34 P 35 Both occurrences simultaneously can lead to high-voltage transformer failure. The occurrence of P; therefore 32 P 33 and P 34 P 35 First, connect using AND gates, then connect using OR gates. Link; The voltage and current acquisition module malfunctioned. :P 36 P 37 When they occur simultaneously It will only happen then; therefore P 36 P 37 Connect using an AND gate; The fault was ultimately determined to be in the high-voltage section. Static fault tree; Control section failure Static fault tree: Filament power supply control module fault P9, suppression stage power supply control module fault P 10 Floating power supply control module failure P 11 Accelerator stage power control module failure P 12 Central processing unit failure P 13 and communication processing unit failure P 14 The occurrence of any one of these will lead to a malfunction in the control system. The occurrence; The filament power control module malfunctions (P9): P 38 P 39 Simultaneous occurrence or P 40 Any occurrence of these events will lead to a filament power supply control module malfunction P9; therefore, P... 38 P 39 After using an AND gate to connect with P 40 Ultimately, it connects to P9 via an OR gate; The suppression stage power control module malfunction P 10 :P 41 P 42 Simultaneous occurrence or P 43 All of these occurrences will lead to a failure of the suppression stage power control module. 10 The occurrence of P; therefore 41 P 42 After using an AND gate to connect with P 43 Ultimately, through the OR gate and P 10 Link; The floating power supply control module malfunction P 11 :P 44 P 45 Simultaneous occurrence or P 46 All of these events will lead to a malfunction of the floating power supply control module. 11 The occurrence of P; therefore 44 P 45 After using an AND gate to connect with P 46 Ultimately, through the OR gate and P 11 Link; The acceleration stage power control module malfunction P 12 :P 47 P 48 Simultaneous occurrence or P 49 All of these events will lead to a malfunction of the floating power supply control module. 12 The occurrence of P; therefore 47 P 48 After using an AND gate to connect with P 49 Ultimately, through the OR gate and P 12 Link; The central processing unit failure P 13 :P 50 P 51 All occurred or P 52 Occurrence or P 53 All of these events will lead to a central processing unit (CPU) failure. 13 The occurrence of P 50 P 51 First, use an AND gate to connect, then connect with P. 52 P 53 Together, use OR gates with P 13 Link; The communication processing unit malfunction P 14 :P 54 P 55 Simultaneous occurrence or P 56 P 57 Both occurrences simultaneously will lead to a communication processing unit malfunction. 14 The occurrence of P; therefore 54 P 55 and P 56 P 57 First, connect them using AND gates, then connect them to P using OR gates. 14 Link; The final diagnosis was a fault in the control section. Static fault tree; Input protection section malfunction Static fault tree: 24V input module fault P 15 Level 3 lightning protection absorption module failure P 16 Preventing reverse power supply module failure P 17 Bipolar to unipolar conversion module fault P 18 Temperature monitoring module malfunction P 19 Any one of these events will cause the input protection section to malfunction. occur; The 24V input processing module P 15 :P 58 P 59 Simultaneous occurrence or P 60 P 61 Both occurrences simultaneously will lead to a communication processing unit malfunction. 14 The occurrence of P; therefore 58 P 59 and P 60 P 61 First, connect using an AND gate, then connect using an OR gate to P. 15 Link; The three-level lightning protection absorption module P 16 :P 62 P 63 Simultaneous occurrence or P 64 P 65 Both occurrences will cause the Level 3 lightning protection absorption module P to... 16 The occurrence of P; therefore 62 P 63 and P 64 P 65 First, connect them using AND gates, then connect them to P using OR gates. 16 Link; The reverse power supply module failure prevention P 17 :P 66 P 67 All occurred or P 68 Occurrence or P 69 All of these occurrences will lead to a failure of the reverse power supply module P. 17 The occurrence of P; therefore 66 P 67 First, use an AND gate to connect, then connect with P. 68 P 69 Together, use OR gates with P 17 Link; The bipolar-to-unipolar conversion module malfunction P 18 :P 70 P 71 All occurred or P 72 Occurrence or P 73 Both occurrences will lead to failure of the bipolar-to-unipolar conversion module P. 18 The occurrence of P; therefore 70 P 71 First, use an AND gate to connect, then connect with P. 72 P 73 Together, use OR gates with P 18 Link; The temperature monitoring module malfunctioned (P) 19 :P 75 P 76 All occurred or P 74 Occurrence or P 77 All of these events will lead to a malfunction of the temperature monitoring module. 19 The occurrence of P; therefore 75 P 76 First, use an AND gate to connect, then connect with P. 74 P 77 Together, use OR gates with P 19 Link; The final conclusion was that the input protection section was faulty. Static fault tree.

4. The high-voltage power supply fault mode analysis method based on fuzzy dynamic fault tree according to claim 2, characterized in that, In step 3, the process of constructing the dynamic fault tree is as follows: Step 3.1: Confirm the relationship between the events; Step 3.2: Based on the static fault tree, identify the fault modes with dynamic logical relationships, and replace the static logic gates connected to the fault modes with dynamic logical relationships with fuzzy dynamic logic gates. Step 3.1 confirms the relationships between the events, including: If events A and B occur sequentially within 10 seconds, and the occurrence time of event A is earlier than that of event B, and the output event Y occurs, then the priority AND gate PAND is used instead of the original static logic gate. If event A and event B, or multiple events, occur sequentially from A to B or in chronological order, and event Y is output, then the sequential dependent gate SEQ is used instead of the original static logic gate. If events A and B occur sequentially from A to B or in chronological order, the output event Y occurs; otherwise, the probability of Y occurring is ε, which is the fuzzy functional correlation degree, and the range of ε is 0.05-0.

95. In this case, the fuzzy sequential correlation gate FSEQ is used to replace the original static logic gate. If triggering event A causes related event B to occur and output event Y to occur, then the function-dependent gate FDEP is used instead of the original static logic gate. If the occurrence of event A does not directly cause the occurrence of output event Y, but probabilistically triggers the occurrence of related event B and causes the occurrence of output event Y, then the fuzzy functional related gate FFDEP is used to replace the original static logic gate. If input event A fails, backup event B starts working; if backup event B also fails, output event Y occurs. If backup event B does not work, it will not fail, and the cold spare gate CSP will be used to replace the original static logic gate. If input event A fails, backup event B starts working; if backup event B also fails, output event Y occurs. If whether backup event B works or not does not affect the failure rate, then the warm spare gate (WSP) is used instead of the original static logic gate. If input event A fails, backup event B starts working; if backup event B also fails, output event Y occurs. Whether backup event B works or not affects the failure rate, so a hot spare gate (HSP) is used instead of the original static logic gate. Step 3.2: Based on the static fault tree, identify the fault modes with dynamic logical relationships, and replace the static logic gates connected to the fault modes with dynamic logical relationships with fuzzy dynamic logic gates. Step 3.2.1, fault in the high-voltage section Based on the static fault tree, fault modes with dynamic logical relationships are identified. Static logic gates connected to fault modes with dynamic logical relationships are replaced with fuzzy dynamic logic gates, forming faults in the high-voltage section. Dynamic fault tree; Inverter malfunction middle: , They occurred sequentially within 10 seconds, and Prior to When it occurs, excessive current causes This occurred, causing an inverter malfunction. If it happens, then , and If dynamic logical relationships exist, then a PAND gate is used instead of an AND gate. , Connected AND gates; The main fault is described using the fuzzy functional correlation gate FFDEP. and For dependent events The direct impact; when , When this occurs, the fuzzy function-dependent gate FFDEP is triggered. probability , The range is 0.05-0.95, and it does not need to wait for its own conditions to be met; the fuzzy functional correlation gate FFDEP is used instead of AND. , Connected AND gates; High voltage filter circuit failure middle: , There is a vague sequential relationship between them. Prior to When it happens, occur; Prior to When it happens, The probability of occurrence is , The range is 0.05-0.95; therefore, the fuzzy sequential correlation gate FSEQ is used instead. , Connected AND gates; Fault in the voltage doubler rectifier circuit middle: The occurrence directly triggers And led to The occurrence, The occurrence of this will not lead to The occurrence of the fault; the main fault is described using the Functionally Dependent Prefix (FDEP) gate. Direct impact of dependency failures; use functionally dependent gates (FDEP gates) instead. , Connected AND gates; Step 3.2.2, in the control section fault Based on the static fault tree, fault modes with dynamic logical relationships are identified. Static logic gates connected to fault modes with dynamic logical relationships are replaced with fuzzy dynamic logic gates, forming control part faults. Dynamic fault tree; Filament power control module malfunction Chinese: P 38 With P 39 There is a time order dependency between them, if P 38 First, it occurs, causing the control signal to be lost and triggering P. 39 If the sequence of occurrences is reversed, the system enters a failure state; if the sequence of occurrences is reversed, the system failure probability is... , The range is 0.05-0.95; the fuzzy sequential correlation gate FSEQ is used instead of P. 38 With P 39 Connected to the door; Acceleration stage power control module malfunction Chinese: P 47 P 48 There is a sequential logical relationship between them, when P 47 Prior to P 48 When it happens, Since this occurs, the sequential correlation gate SEQ is used instead of P. 47 P 48 Connected AND gates; Central processing unit malfunction China: To and Backup of component system settings, when , When it happens, the backup system , When the system starts working, and the backup system also fails, the corresponding higher-level failure occurs. , This will only happen if there is a malfunction in the control section. Add a backup system based on the static fault tree , ; and will , Through the newly added cold spare parts gate CSP and Connect, , Through the newly added cold spare parts gate CSP and Establish connection; in case of fault and In the design of the system, backups were set up for the corresponding modules. and When an incident occurs, the backup module starts working; the failure only occurs when the backup module also fails. Step 3.2.3, fault in the input protection section Based on the static fault tree, fault modes with dynamic logical relationships are identified. Static logic gates connected to fault modes with dynamic logical relationships are replaced with fuzzy dynamic logic gates, forming faults in the input protection section. Dynamic fault tree; In the 24V input processing module P 15 Chinese: P 60 With P 61 There is a temporal relationship between them, when P 60 When it occurs, it will cause P to be triggered. 61 This can lead to system failure; if P 61 Prior to P 60 If this occurs, it will not cause a system failure; therefore, a sequential dependency gate (SEQ) is used instead of P. 60 P 61 Connected AND gates; In the three-level lightning protection absorption module P 16 Chinese: P 62 With P 63 There is a functional dependency between them; P 62 When it occurs, P is triggered. 63 The probability is No need to wait for other conditions. The range is 0.05-0.95; the fuzzy functional correlation gate FFDEP is used instead of P. 62 P 63 Connected AND gates; To prevent reverse power supply module failure P 17 Chinese: P 66 With P 67 There is a time order dependency between P and P. 66 First it happens, then P 67 If this occurs, the system enters a failure state; if the order is reversed or both occur simultaneously, the probability of triggering a critical failure is... , The range is 0.05-0.95; the fuzzy sequential correlation gate FSEQ is used instead of P. 66 With P 67 Connected AND gates; Fault in bipolar-to-unipolar conversion module P 18 Chinese: P 70 With P 71 There is a time-sequence dependency. First it happened, then If the sequence of events occurs, the system enters a failure state; if the sequence is reversed or both occur simultaneously, a critical failure will not be triggered; in this case, a priority AND gate (PAND) is used instead of an AND gate (P). 70 P 71 Connected AND gates; Temperature monitoring module malfunction P 19 Chinese: P 75 With P 76 There is a direct functional dependency between them, when When it occurs, it will be forcibly triggered. No need to wait for other conditions; use fuzzy sequential correlation gate FDEP instead of P. 75 P 76 Connected AND gates.

5. The high-voltage power supply fault mode analysis method based on fuzzy dynamic fault tree according to claim 2, characterized in that, In step 4, the process of decomposing the dynamic fault tree into dynamic sub-fault trees is as follows: Step 4.1: Decompose the dynamic fault tree into dynamic sub-fault trees; Step 4.2, Failure Rate Modeling: Each bottom event represents a failure rate. Obtaining the failure rate model of the bottom event is a prerequisite for solving the failure rate of the dynamic sub-fault tree. The distribution and parameters of the failure rate are obtained from the manuals of the components used by the power supply. Step 4.3, Derivation and Calculation of Dynamic Logic Gates: Based on the dynamic sub-fault tree, the output of each dynamic logic gate is regarded as an independent event; the entire dynamic subtree is regarded as an event, the failure rate of the dynamic sub-fault tree event is calculated, and finally the independent events are brought into the static fault tree to calculate the failure probability of the top event. Step 4.1, decomposing the dynamic fault tree into dynamic sub-fault trees, includes: Treat dynamic logic gates and related underlying events together as a new event; First, find all dynamic logic gates in the dynamic fault tree, and treat the output of each dynamic logic gate as a new event D. The structure of D is the dynamic logic gate separated from the dynamic fault tree and the events that constitute the dynamic logic gate. Replace the dynamic logic gate with the new event D in the original dynamic fault tree. Separate the structure of the dynamic logic gate into a separate fault tree to calculate the failure rate of event D. P 20 P 22 The dynamic logic gate formed is event D1; P 20 P 24 P 25 The dynamic logic gate formed is event D2; P 28 P 29 The dynamic logic gate formed is event D3; P 32 P 33 The dynamic logic gate formed is event D4; P 38 P 39 The dynamic logic gate formed is event D5; P 47 P 48 The dynamic logic gate formed is event D6; P 52 The dynamic logic gate formed by R1 is event D7; P 54 The dynamic logic gate formed by R2 is event D8; P 60 P 61 The dynamic logic gate formed is event D9; P 62 P 63 The dynamic logic gate formed is event D10; P 66 P 67 The dynamic logic gate formed is event D11; P 70 P 71 The dynamic logic gate formed is event D12; P 75 P 76 The dynamic logic gate formed is event D13; Finally, the failure rates of the events represented by the dynamic sub-fault trees are incorporated into the static fault tree for the final solution. Step 4.2 Failure rate modeling includes: The failure rate follows distributions including exponential, Weibull, log-normal, and Poisson distributions; each distribution includes a probability density function, a cumulative distribution function, and a failure probability; the probability density function and the cumulative distribution function are inherent properties in statistics; the failure probability is the probability that a device or system will fail at failure time T, and the failure probability of each fault can be obtained through the following formula; The failure rate of the exponential distribution is modeled as follows: probability density function of exponential distribution for: (3-30)； Cumulative distribution function of exponential distribution for: (3-31)； Failure probability of exponential distribution for: (3-32)； In the formula, The failure rate of the exponential distribution is denoted by the parameter. , representing the probability of system failure per unit time, in hours; T is the failure time, in hours; if the failure rate Therefore, the probability of a system failure per hour is 1%; e is a constant. The failure rate of the Weibull distribution is modeled as follows: The probability density function of the Weibull distribution for: (3-33)； Cumulative distribution function of Weibull distribution for: (3-34)； Failure probability of Weibull distribution for: (3-36)； In the formula, The scale parameter determines the range of failure time; The shape parameter determines the shape of the failure mode; The failure rate model for the log-normal distribution is as follows: probability density function of log-normal distribution for: (3-37)； Cumulative distribution function of log-normal distribution for: (3-38)； Failure probability of a log-normally distributed fault for: （3-39）； In the formula, The mean of a log-normal distribution; is the standard deviation; T is the failure time of the event, in hours; t represents the failure time in the integral formula; The failure rate model for the Poisson distribution is as follows: The probability density function of the Poisson distribution for; (3-41)； Cumulative distribution function of Poisson distribution for: (3-42)； Failure probability of Poisson distribution for: (3-43)； In the formula, k represents the number of times the event occurs; the parameters of the Poisson distribution are... This represents the expected number of events to occur per unit of time. Step 4.3, dynamic logic gate derivation and calculation, includes: PAND gate: Failure probability of priority AND gate This can be expressed using double integrals as follows: (3-44)； in To determine the failure probability of the priority AND gate, for The probability density function, for The probability density function, for Failure time, for Failure time; Sequential gate SEQ: Failure probability of sequentially related gates Represented as: (3-45)； in To determine the failure probability of the priority AND gate, for The cumulative distribution function, for The cumulative distribution function, for Failure time, for Failure time; Fuzzy sequential correlation gate FSEQ: Failure probability of fuzzy sequential correlation gate Represented as: (3-46)； in, for The cumulative distribution function, For the event The cumulative distribution function, for Failure time, for Failure time; for and Fuzzy order correlation; Function-dependent gates (FDEP): Failure probability of function-dependent gates Represented as: (3-47)； in The failure probability of a function-dependent gate. for The cumulative distribution function, for The cumulative distribution function; Fuzzy Functional Related Gate FFDEP: Failure probability of fuzzy functionally related gates Represented as: (3-48)； in, For the failure probability of the fuzzy functionally related gate, for The cumulative distribution function, for The cumulative distribution function; for and Fuzzy functional relevance; Cold Storage Door (CSP) and Warm Storage Door (WSP): The failure probabilities of the cold storage gate (CSP) and the warm storage gate (WSP) were estimated using Monte Carlo simulation. Specifically, a loop was constructed in the computer program with time as the variable. For each unit of time increment, the failure probability of the bottom event at the current time was calculated based on the failure rate model followed by the bottom events. Then, a random number method was used to determine if the bottom event had failed. Finally, the properties of the dynamic logic gates were used to determine if the top event had failed. If the top event had not failed, the program was trained until the top event failed. The Monte Carlo simulation was performed 10,000 times to obtain the probability of system failure within a specified time. Heat storage door HSP: Failure probability of thermal storage door Represented as: (3-49)； in, For the event The cumulative distribution function; n is the number of events connected to the thermal storage gate; i is the i-th event among the n events; Combining the failure rate modeling in step 4.2, the parameters of each event are substituted into the calculation formula of the corresponding dynamic logic gate to obtain the failure probability of the event containing the dynamic logic gate.

6. An electronic device, characterized in that, include: One or more processors; Memory; One or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs being configured to perform the method as described in any one of claims 1 to 5.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores program code that can be invoked by a processor to execute the method as described in any one of claims 1 to 5.

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