Automatic generation method for reduction summation hardware structure with optimal power consumption delay product

Abstract

The invention discloses a power consumption delay product optimal reduction summation hardware structure automatic generation method and a reduction summation hardware system.The power consumption delay product optimal reduction summation hardware structure automatic generation method comprises the steps that S1, an accurate circuit model is established, and an objective function is formalized; the CISA algorithm is realized by a script program, the script can call a synthesis tool for synthesis and analysis, S3, final hardware generation, and S31, after the algorithm is executed, the program outputs a final optimal solution Solbest, that is, the optimal solution is (Tbest netlist, kbest), the optimal solution Solbest comprises an optimal topological structure code, and an exact position of a pipeline register is inserted into the code, so that the optimal topological structure code is obtained. And S32, a designer or a subsequent automatic process generates a final hardware description language file which can be used for physical implementation according to the optimal solution Solbest.

Description

Technical Field

[0001] This invention belongs to the field of processor microarchitecture design and optimization. Specifically, this invention relates to a systematic design method for automatically generating high-performance, low-power parallel reduction and summing circuits during the chip design stage, and a hardware system with optimal energy efficiency generated by this method. Background Technology

[0002] In modern high-performance computing chips, especially in massively parallel computing architectures such as graphics processing units (GPUs) and deep learning accelerators, reduction summation networks are a ubiquitous and crucial fundamental functional module. The core function of this network is to efficiently and accurately aggregate the numerous partial sums generated by hundreds or thousands of parallel processing units (PEs) within the same cycle into a single final result. This network is typically physically implemented as an adder tree composed of multiple stages of adders or compressors. The performance (represented by latency or clock frequency), power consumption, and area of ​​the reduction summation network directly impact the final performance of the entire chip, making it one of the core bottlenecks in circuit structure optimization.

[0003] Existing reduction and summation structural design methods can be mainly classified into the following categories:

[0004] The first type is manual / experience-driven design: This mainly relies on the designer manually selecting a classic adder tree topology (such as Wallace Tree, Dadda Tree, Balanced Tree, etc.), and then manually inserting pipeline registers on the critical path after timing analysis to meet the clock frequency requirements. This method is not only time-consuming and labor-intensive, with poor repeatability, but also completely fails to guarantee the global optimality of the designed circuit.

[0005] The second category is automatic synthesis based on a single objective: This uses synthesis tools to automatically generate circuits with a single performance indicator as the primary optimization goal. For example:

[0006] (1) Performance-first strategy: With minimizing latency (Timing-Driven) as the highest constraint, the tool tends to generate the shallowest topology (such as Wallace tree) and may use complex, highly driven cells, but this usually comes at the cost of huge area and power consumption.

[0007] (2) Power-first strategy: With minimizing power consumption as the highest constraint, the tool tends to select the topology and cell with the lowest switching activity, but this often leads to longer logic paths and sacrifices circuit structure performance.

[0008] The third category involves conventional pipelined partitioning, where the selection of pipeline register insertion locations is often local and greedy. For example, it might simply involve splitting the pipeline at the geometric midpoint of the longest combinational logic path, or using heuristic register balancing by synthesis tools. This approach does not systematically evaluate the combined impact of pipeline partitioning on global power consumption (especially the register's own power consumption) and performance.

[0009] Existing design methods have the following fundamental flaws in pursuing the highest "energy efficiency," that is, completing a single calculation with the least amount of energy consumption:

[0010] (1) Lack of a globally optimal metric: Performance (low latency) and low power consumption are often contradictory in physical implementation (i.e., there is a power-performance trade-off). Simply optimizing a single metric will inevitably lead to damage to the other metric. Existing methods lack a golden metric that can scientifically and quantitatively evaluate this complex trade-off and directly address the essence of "energy efficiency".

[0011] (2) Incompleteness of design space exploration: The final energy efficiency of a reduction and summing circuit is determined by two closely coupled dimensions: 1) the choice of logic topology and 2) the partitioning of pipeline cut-points. Existing methods usually decouple these two design steps (e.g., first determine a topology and then partition the pipeline on that topology). This approach severs the intrinsic connection between the two, limiting the search process to a very small subset of the entire design space, thus making it impossible to find the true global optimum.

[0012] (3) Insufficient assessment of the overall cost of pipelined systems: Inserting pipelined registers is not without its costs. The registers themselves introduce additional clock tree power consumption, data switching power consumption, and static leakage power consumption, and occupy chip area. A simple, greedy pipeline insertion strategy does not systematically quantify the overall benefits between these additional physical costs and the resulting reduction in clock cycles, and may sometimes even lead to an increase in total power consumption instead of a decrease.

[0013] The reduction and summation unit is used in many systems, and its energy efficiency accounts for a significant portion of the overall system performance. Therefore, optimizing the energy efficiency of the reduction and summation structure to its maximum extent is of great importance. However, traditional design methods based on a single objective have consistently failed to find a satisfactory balance between performance and power consumption.

[0014] The technical challenge of this invention lies in how to create a systematic and automated design process that can explore both topology and pipeline partitioning within a unified framework, and find the optimal design solution from both mathematical and physical perspectives based on a global metric that can accurately quantify the "power-delay product". Summary of the Invention

[0015] This invention provides an automatic generation method for a reduction summation hardware structure with optimal power consumption delay product and a reduction summation hardware system, in order to solve the technical problems existing in the prior art.

[0016] To achieve the above objectives, this invention provides an automatic generation method for a power-delay product-optimal reduction and summation hardware structure, comprising:

[0017] S1: Establish an accurate circuit model and formalize the objective function.

[0018] S2: The CISA algorithm is executed programmatically. The CISA algorithm is implemented by a script program, which can call synthesis tools for synthesis and analysis.

[0019] S3: Final Hardware Generation

[0020] S31: After the algorithm completes, the program outputs the final optimal solution Sol_best, which is (T_best_netlist, k_best). The optimal solution Sol_best contains the optimal topology code and the exact location where the pipeline register is inserted in that code.

[0021] S32: Designers or subsequent automated processes generate the final hardware description language file that can be used for physical implementation based on the optimal solution Sol_best.

[0022] In an optional embodiment of the present invention, step S1 may include:

[0023] S11: Structural formalization: Abstract a hardware task to be designed, which contains N input operands, into a mathematical tuple (T, k), where T represents the logical topology of the adder tree, i.e., the type and connection method of the adder / compressor unit, and k represents the physical location of the cut point of the pipeline register level inserted into the logical topology of the adder tree.

[0024] S12: Establish the delay model T_clk(T, k): Using delay data from static timing analysis tools or library cells, establish a model to calculate the clock cycle. T_clk(T, k) = max(Delay(Stage_1), Delay(Stage_2)), where Stage_1 and Stage_2 are two combinational logic stages divided by the cutoff point k. The max function calculates the maximum value of the data within the parentheses, and the Delay function is expressed as... , The delay is the i-th operation unit in the logic path, and m represents the corresponding combinational logic stage;

[0025] S13: Calculate the total power consumption P_total(T, k): Use power analysis tools or power consumption data from the standard cell library to build a model to calculate the total power consumption. P_total(T, k) = P_comb(T) + P_reg(k), where P_comb(T) represents the total power consumption of all combinational logic gates in topology T, including adders and compressors. The total power consumption includes switching power consumption and leakage power consumption. P_reg(k) represents the total power consumption generated by all pipeline registers inserted at the cut point k.

[0026] S14: Formalizing the objective function: The optimization objective is explicitly and formally defined as minimizing the PDP, i.e., MinimizePDP(T, k): Minimize PDP(T, k) = (P_comb(T) + P_reg(k)) × max(Delay(Stage_1), Delay(Stage_2)).

[0027] In an optional embodiment of the present invention, step S2 may include:

[0028] S21: Candidate Topology Generation

[0029] S211: The program calls a comprehensive tool.

[0030] S212: Given N inputs, the program performs synthesis multiple times with different, even contradictory, constraints to generate a small, high-quality candidate topology set Candidate_Set. For each reduction tree in the set, the following (1)-(3) are executed:

[0031] (1) Run the high-performance constraint with the constraint create_clock -period 1.0, and save the result as T_speed.v.

[0032] (2) Run the small area constraint with the constraint set_max_area 0, and save the result as T_area.v.

[0033] (3) Manually design a well-structured balanced tree topology T_balanced.v.

[0034] Candidate_Set = {T_speed.v, T_area.v, T_balanced.v},

[0035] Through the above steps (1)-(3), the infinite topological space is intelligently pruned into a finite number of high-quality candidates.

[0036] S22: Integrated Evaluation and Optimization

[0037] The program initializes the global minimum PDP value Sol_bestPDP_min and the optimal solution Sol_best, setting Sol_bestPDP_min to infinity and Sol_best to null.

[0038] Outer loop: For each netlist T_netlist in Candidate_Set, perform the following operations: The program first analyzes the netlist T_netlist and identifies the set of all possible and valid pipeline cutpoint locations, Cut_Points_Set. A valid cutpoint is a set of connections in the circuit; cutting the connections divides the circuit into two sub-circuits that do not produce combinational logic loops.

[0039] Inner loop: For each cut point in Cut_Points_Set, perform the following operations (1)-(3):

[0040] (1) The program virtually or physically inserts a pipeline register at position k in the netlist T_netlist.

[0041] (2) Call the STA and power analysis tools, and accurately calculate the current PDP value (PDP_current) of the current (T_netlist, k) combination based on the circuit model in step S1.

[0042] (3) Comparison and update: Determine whether PDP_current is less than PDP_min. If so, set PDP_min to PDP_current and set Sol_best to (T_netlist, k).

[0043] The present invention also provides a reduction summation hardware system, wherein the topology selection and pipeline register layout of the physical circuit structure of the reduction summation hardware system are determined and generated by the above-mentioned automatic generation method of the reduction summation hardware structure with optimal power-delay product.

[0044] The automatic generation method for the power consumption delay product optimal reduction summation hardware structure and the reduction summation hardware system provided by this invention have the following beneficial technical effects:

[0045] 1. Achieving Provable Global Energy Efficiency Optimization: This invention proposes for the first time a systematic method to find the globally optimal energy-efficiency design (within the candidate set). Compared with traditional methods, the resulting hardware design has significant and quantifiable advantages in energy efficiency.

[0046] 2. Automation of the design process and determinism of design quality: The complex, experience-dependent design trade-off process is transformed into a formalized, automatically executed, deterministic algorithm. This not only greatly improves design efficiency and frees up manpower, but also ensures the quality and optimality of the output hardware design, eliminating the uncertainty caused by human factors.

[0047] 3. Universality and Scalability of the Method: The integrated search methodology targeting PDP proposed in this invention has good versatility. It is not only applicable to the reduction and summation unit in this patent, but can also be extended to the design of any complex arithmetic logic unit (ALU) that requires deep pipeline optimization, such as floating-point multipliers, FFT butterfly units, etc. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This invention provides a hardware structure for optimal reduction summation of a PDP with a two-stage pipeline, generated using the CISA method for 24 input operands. Detailed Implementation

[0050] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] The core objective of this invention is to address the problem that existing parallel reduction and summation hardware unit design methods cannot systematically achieve optimal energy efficiency due to the lack of a global energy efficiency metric, incomplete design space exploration, and insufficient assessment of pipeline synthesis costs. This invention aims to provide an automated hardware structure generation method and corresponding system with the power-delay product (PDP) as the sole optimization objective. This method can collaboratively and integratedly explore the logic topology space and physical pipeline partitioning space of the circuit within a unified framework, thereby automatically and deterministically generating a reduction and summation hardware design that achieves optimal energy efficiency.

[0052] The breakthrough in this invention can be achieved through two key steps:

[0053] 1. Step One: Determining the Core Optimization Metric – Minimizing PDP. The inventors began by addressing the essence of the problem, seeking a physical quantity that transcends mere speed or power consumption and represents energy efficiency. After in-depth research, they ultimately determined the "Power-Delay Product" (PDP) as the core standard for measuring the total energy required to complete a single operation. PDP = P_total × T_clk, where P_total is the total power consumption and T_clk is the clock cycle. Minimizing PDP is equivalent to achieving the highest energy efficiency. The establishment of this metric pointed the way for the entire optimization problem.

[0054] 2. Second Step: Solving the "Combinatorial Explosion" Search Problem – Proposing the CISA Algorithm. After establishing the PDP as the objective function, the next major goal is how to search within the vast design space. The number of possible topologies and pipeline tangents is enormous, and a complete exhaustive search requires substantial computational resources and is time-consuming. To address this "combinatorial explosion" problem, the inventors devised a novel and efficient two-stage ensemble search strategy, named the "Candidate-Based Integrated Search Algorithm" (CISA). The core idea of ​​this algorithm is "heuristic pruning followed by local exhaustive search," cleverly balancing the breadth and depth of the search.

[0055] Phase 1 (Breadth-of-Sight Pruning): Instead of blindly searching through all possible topologies, this phase leverages the heuristic capabilities of the tool to quickly generate a very small (e.g., containing only 3-5 topologies) but high-quality and representative set of candidate topologies (Candidate_Set). This set should include representative structures with different design styles, such as a topology with optimal speed or an optimal area. This step significantly reduces the breadth of the search.

[0056] Phase Two (Depth Exhaustive Search): Within this significantly narrowed, high-quality candidate set, an exhaustive search and precise PDP evaluation are performed on all possible pipeline cut-off points for each candidate topology. Since the candidate set is small and the number of possible cut-off points for each topology is finite, the computational cost of this step is entirely manageable.

[0057] This innovative CISA algorithm integrates the previously decoupled steps of topology selection and pipeline partitioning into a unified optimization framework oriented towards the Product-Pipeline Decomposition (PDP). Through a clever search strategy, it makes it feasible to efficiently find the globally optimal PDP solution within a vast design space.

[0058] This invention provides an automatic generation method for a power-delay product-optimal reduction and summation hardware architecture, comprising:

[0059] S1: Establish an accurate circuit model and formalize the objective function (before executing the algorithm, a circuit model that can accurately predict the PDP needs to be established first).

[0060] S2: The CISA algorithm is executed programmatically. The CISA algorithm is implemented by a script program, which can call synthesis tools for synthesis and analysis.

[0061] S3: Final Hardware Generation

[0062] S31: After the algorithm completes, the program outputs the final optimal solution Sol_best, which is (T_best_netlist, k_best). The optimal solution Sol_best contains the optimal topology code and the exact location where the pipeline register is inserted in that code.

[0063] S32: Designers or subsequent automated processes generate the final hardware description language file that can be used for physical implementation based on the optimal solution Sol_best.

[0064] like Figure 1 The figure shows the optimal reduction summation hardware structure of the PDP with a two-stage pipeline generated by the CISA method of this invention for 24 input operands.

[0065] In an optional embodiment of the present invention, step S1 may include:

[0066] S11: Structural formalization: Abstract a hardware task to be designed, which contains N input operands, into a mathematical tuple (T, k), where T represents the logical topology of the adder tree, i.e., the type and connection method of the adder / compressor unit, and k represents the physical location of the pipeline register-level cut-point inserted into the logical topology of the adder tree;

[0067] S12: Establish the delay model T_clk(T, k): Using delay data from Static Timing Analysis (STA) tools or library cells, establish a model to calculate the clock cycle. T_clk(T, k) = max(Delay(Stage_1), Delay(Stage_2)), where Stage_1 and Stage_2 are two combinational logic stages divided by the cutoff point k. The max function calculates the maximum value of the data within the parentheses, and the Delay function is expressed as... , Let m be the delay of the i-th operation unit in the logic path, and m represent the corresponding combinational logic stage. This represents the sum of the delays of all operational units in the combinational logic stage m;

[0068] S13: Calculate the total power consumption P_total(T, k): Use power analysis tools or power consumption data from the standard cell library to build a model to calculate the total power consumption. P_total(T, k) = P_comb(T) + P_reg(k), where P_comb(T) represents the total power consumption of all combinational logic gates in topology T, including adders and compressors. The total power consumption includes switching power consumption and leakage power consumption. P_reg(k) represents the total power consumption generated by all pipeline registers inserted at the cut point k.

[0069] S14: Formalizing the objective function: The optimization objective is explicitly and formally defined as minimizing the PDP, i.e., MinimizePDP(T, k): Minimize PDP(T, k) = (P_comb(T) + P_reg(k)) × max(Delay(Stage_1), Delay(Stage_2)).

[0070] In an optional embodiment of the present invention, step S2 may include:

[0071] S21: Candidate Topologies Generation

[0072] S211: The program calls a comprehensive tool.

[0073] S212: Given N inputs, the program performs synthesis multiple times with different, even contradictory, constraints to generate a small, high-quality candidate topology set Candidate_Set. For each reduction tree in the set, the following (1)-(3) are executed:

[0074] (1) Run the high-performance constraint with the constraint create_clock -period 1.0, and save the result as T_speed.v.

[0075] (2) Run the small area constraint with the constraint set_max_area 0, and save the result as T_area.v.

[0076] (3) Manually design a well-structured balanced tree topology T_balanced.v.

[0077] Candidate_Set = {T_speed.v, T_area.v, T_balanced.v},

[0078] Through the above steps (1)-(3), the infinite topological space is intelligently pruned into a finite number of high-quality candidates.

[0079] It should be noted that the high-performance constraints, small area constraints, and balanced tree topology in steps (1)-(3) above are different for each reduction tree and need to be determined according to the actual situation.

[0080] S22: Integrated Evaluation and Optimization

[0081] The program initializes the global minimum PDP value Sol_bestPDP_min and the optimal solution Sol_best, setting Sol_bestPDP_min to infinity and Sol_best to null.

[0082] Outer loop: For each netlist T_netlist in Candidate_Set, perform the following operations: The program first analyzes the netlist T_netlist and identifies the set of all possible and valid pipeline cutpoint locations, Cut_Points_Set. A valid cutpoint is a set of connections in the circuit; cutting the connections divides the circuit into two sub-circuits that do not produce combinational logic loops.

[0083] Inner loop: For each cut point in Cut_Points_Set, perform the following operations (1)-(3):

[0084] (1) The program virtually or physically inserts a pipeline register at position k in the netlist T_netlist.

[0085] (2) Call the STA and power analysis tools, and accurately calculate the current PDP value (PDP_current) of the current (T_netlist, k) combination based on the circuit model in step S1.

[0086] (3) Comparison and update: Determine whether PDP_current is less than PDP_min. If so, set PDP_min to PDP_current and set Sol_best to (T_netlist, k).

[0087] The present invention also provides a reduction summation hardware system, wherein the topology selection and pipeline register layout of the physical circuit structure of the reduction summation hardware system are determined and generated by the above-mentioned automatic generation method of the reduction summation hardware structure with optimal power-delay product.

[0088] The key technical points and corresponding technical effects of this invention are as follows:

[0089] Key technical point 1: A hardware automation design method for reduction summation that takes minimizing the power-delay product (PDP) as the sole and final global optimization objective.

[0090] Technical benefits: It provides a scientific, accurate, and comprehensive energy efficiency measurement standard, ensuring that the direction of design optimization is directly aimed at the essential goal of "minimizing total energy consumption per operation", avoiding blind or heuristic trade-offs between performance and power consumption.

[0091] Key technical point 2: This method searches for combinations of the logic topology and physical pipeline tangent locations of the circuit within a unified, integrated optimization framework.

[0092] Technical benefits: It overcomes the local optima problem caused by the decoupling of design steps in traditional methods, and can explore in a broader and more complete design space, thus having the ability to find the true global optimal solution.

[0093] Key technical point 3: The specific algorithm implementation of this method, namely CISA (Candidate-Based Ensemble Search), includes the following core steps: a) First, a small set of high-quality candidate topologies is generated using heuristics to intelligently prune the design space; b) Second, for each candidate topology in the set, all possible pipeline cut points are evaluated exhaustively, and the PDP value of each combination is calculated based on an accurate physical model; c) Finally, the unique combination of topology and cut points that produces the global minimum PDP value is selected as the final design scheme.

[0094] Technical effect: It provides a computationally efficient and feasible search strategy that cleverly combines the breadth coverage of heuristic methods with the depth optimality of exhaustive methods, successfully avoiding the combinatorial explosion problem of the design space while ensuring the quality of the solution.

[0095] Technical key point 4: A reduction summation hardware system, the topology selection of its physical circuit structure and the pipeline register layout are determined and generated by the above-mentioned PDP optimization automation method.

[0096] Technical benefits: In terms of physical implementation, this hardware system consumes the least total energy (within the candidate set) for a single summation operation. Applying it to parallel computing chip systems can directly and significantly reduce computational power consumption and improve the overall system's energy efficiency.

[0097] The automatic generation method for the power consumption delay product optimal reduction summation hardware structure and the reduction summation hardware system provided by this invention have the following beneficial technical effects:

[0098] 1. Achieving Provable Global Energy Efficiency Optimization: This invention proposes for the first time a systematic method to find the globally optimal energy-efficiency design (within the candidate set). Compared with traditional methods, the resulting hardware design has significant and quantifiable advantages in energy efficiency.

[0099] 2. Automation of the design process and determinism of design quality: The complex, experience-dependent design trade-off process is transformed into a formalized, automatically executed, deterministic algorithm. This not only greatly improves design efficiency and frees up manpower, but also ensures the quality and optimality of the output hardware design, eliminating the uncertainty caused by human factors.

[0100] 3. Universality and Scalability of the Method: The integrated search methodology targeting PDP proposed in this invention has good versatility. It is not only applicable to the reduction and summation unit in this patent, but can also be extended to the design of any complex arithmetic logic unit (ALU) that requires deep pipeline optimization, such as floating-point multipliers, FFT butterfly units, etc.

[0101] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of one embodiment, and the modules or processes shown in the drawings are not necessarily essential for implementing the present invention.

[0102] Those skilled in the art will understand that the modules in the apparatus of the embodiments can be distributed in the apparatus of the embodiments as described in the embodiments, or they can be located in one or more devices different from this embodiment with corresponding changes. The modules of the above embodiments can be combined into one module, or they can be further divided into multiple sub-modules.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for automatically generating a hardware structure of a reduced sum with optimal power-delay product, characterized in that, Comprises: S1: Establishing an accurate circuit model and formalizing the objective function S2: CISA algorithm programmed execution, CISA algorithm is realized by a script program, which can call a synthesis tool for synthesis and analysis, S3: Final hardware generation S31: After the algorithm is executed, the program outputs the final optimal solution Sol_best, that is, the optimal solution is (T_best_netlist, k_best), and the optimal solution Sol_best includes the optimal topology structure code and the exact position of the pipeline register inserted in the code, S32: The designer or subsequent automatic process generates the final hardware description language file that can be used for physical implementation according to the optimal solution Sol_best.

2. The method of claim 1, wherein, Step S1 comprises: S11: Structure formalization: abstract a reduction sum hardware to be designed containing N input operands into a mathematical tuple (T, k), wherein T represents the logical topology of the adder tree, that is, the type and connection mode of the adder / compressor unit, and k represents the physical position of the cut point of inserting a pipeline register stage in the logical topology of the adder tree; S12: Establish delay model T_clk(T, k): using static timing analysis tool or library cell delay data, establish model to calculate clock period, T_clk(T, k) = max(Delay(Stage_1), Delay(Stage_2)), wherein Stage_1 and Stage_2 are two combinational logic stages divided by cut point k, max function represents calculating maximum value of data in parentheses, and Delay function represents , Delay(m) is delay of the i-th operation cell of the logic path, and m represents corresponding combinational logic stage. S13: Calculate total power consumption P_total(T, k): use power consumption analysis tools or power consumption data of standard cell libraries to establish a model to calculate total power consumption, P_total(T, k) = P_comb(T) + P_reg(k), P_comb(T) represents the total power consumption of all combinatorial logic gates in the topology T, the combinatorial logic gates include adders and compressors, and the total power consumption includes switching power consumption and leakage power consumption, P_reg(k) represents the total power consumption generated by all pipeline registers inserted at the cut point k themselves; S14: Objective function formalization: explicitly and formally define the optimization target as minimizing PDP, that is, Minimize PDP(T, k): Minimize PDP(T, k) = (P_comb(T) + P_reg(k)) × max(Delay(Stage_1), Delay(Stage_2)).

3. The method of claim 1, wherein the method further comprises: Step S2 comprises: S21: Candidate topology generation S211: The program calls a synthesis tool, S212: For the given N inputs, the program runs synthesis multiple times with different, even contradictory constraints to generate a small, high-quality candidate topology set Candidate_Set, and for each reduction tree in the set, the following (1)-(3) are executed: (1) Run the high-performance constraint with the constraint create_clock -period 1.0, and save the result as T_speed.v, (2) Run the small area constraint with the constraint set_max_area 0, and save the result as T_area.v, (3) Manually design a balanced tree topology T_balanced.v with regular structure, Candidate_Set = {T_speed.v, T_area.v, T_balanced.v}, By the above steps (1)-(3), the infinite topological space is intelligently pruned into a few high-quality candidates, S22: integrated evaluation and optimization The program initializes the global minimum PDP value Sol_best PDP_min and the optimal solution Sol_best, sets Sol_best PDP_min equal to infinity, and sets the optimal solution Sol_best equal to null, Outer loop: for each netlist T_netlist in Candidate_Set, the program first analyzes the netlist T_netlist and identifies all possible and valid pipeline cut point position sets Cut_Points_Set, and an effective cut point is a set of wires in the circuit, and cutting the wires can divide the circuit into two sub-circuits that do not generate combinational logic loops, Inner loop: for each cut point in Cut_Points_Set, the following operations (1)-(3) are performed: (1) The program virtually or actually inserts a pipeline register at position k of the netlist T_netlist, (2) According to the circuit model in step S1, the STA and power consumption analysis tool are called to accurately calculate the current PDP of the current combination (T_netlist, k), that is, PDP_current value, (3) Comparison and update: determine whether PDP_current is less than PDP_min, if yes, set PDP_min equal to PDP_current and set Sol_best equal to (T_netlist, k).

4. A reduction-sum hardware system, characterized by, The topology selection and pipeline register layout of the physical circuit structure of the reduction sum hardware system are determined and generated by the method of any one of claims 1-3.

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