LED cascade display chip and series system of LED cascade display chip

Abstract

The application discloses an LED cascade display chip and a series system of the LED cascade display chip, and the LED cascade display chip comprises a power supply amplitude modulation carrier judgment circuit, a data decoding module, a data analysis module, a parameter analysis module and a driving module, the power supply amplitude modulation carrier judgment circuit generates corresponding digital signals according to the amplitude of a voltage signal; the data decoding module decodes the digital signals to obtain control data; the data analysis module analyzes the control data to obtain display data; the parameter analysis module analyzes the control data to obtain parameter data; and the driving module controls the display state of an LED lamp module according to the display data and the parameter data; the technical scheme introduces a signal judgment and analysis mechanism based on the power supply amplitude modulation carrier, reliably acquires display signals without adding additional communication lines, and analyzes the display signals corresponding to the chip address, so that each LED cascade display chip can independently complete display control.

Description

Technical Field

[0001] This invention relates to the field of display chip technology, and in particular to an LED cascaded display chip and a series connection system of LED cascaded display chips. Background Technology

[0002] like Figure 1 As shown, a common solution in existing LED cascaded display systems is a series connection system using a single-line return-to-zero (RZZ) code protocol for cascaded display chips. In this type of system, each display chip is connected in series via a single-line RZZ code data line. The system typically only requires three connection lines: a single-line RZZ code data line (DIN1), a power line (VDD), and a ground line (GND). The overall wiring structure is relatively simple, and the system cost is low.

[0003] However, because this type of system uses a serially cascaded data transmission structure, the display chips transmit control data step by step through data lines. When any display chip in the system fails, loses power, or experiences a communication anomaly, the subsequent cascaded display chips will not be able to receive valid control data, which will lead to all subsequent display chips losing control and failing to display normally, thus significantly reducing the overall reliability of the system. Summary of the Invention

[0004] This invention provides an LED cascaded display chip and a series system of LED cascaded display chips to solve the above-mentioned technical problems.

[0005] A first aspect of this invention provides an LED cascaded display chip, the LED cascaded display chip being connected to an LED lamp module, the LED cascaded display chip comprising:

[0006] The power supply amplitude modulation carrier judgment circuit is configured to acquire the display signal corresponding to the address of the LED cascaded display chip, sample the voltage signal in the display signal, and generate a corresponding digital signal based on the amplitude of the voltage signal.

[0007] The data decoding module, connected to the power supply amplitude modulation carrier judgment circuit, is configured to decode the digital signal to obtain control data;

[0008] A data parsing module, connected to the data decoding module, is configured to parse display data from the control data;

[0009] The parameter parsing module, connected to the data decoding module, is configured to parse parameter data from the control data;

[0010] The driving module is connected to the data parsing module and the parameter parsing module respectively, and is configured to control the display state of the LED light module according to the display data and the parameter data.

[0011] Optionally, the power supply amplitude modulation carrier determination circuit is further configured to:

[0012] When the amplitude of the voltage signal is greater than a preset voltage value, a first level signal is output;

[0013] When the amplitude of the voltage signal is less than a preset voltage value, a second level signal is output;

[0014] In this configuration, one of the first level signal and the second level signal is a high-level signal, and the other is a low-level signal.

[0015] Optionally, the power supply amplitude modulation carrier determination circuit is further configured to:

[0016] Obtain the reference voltage value from the displayed signal;

[0017] When the amplitude of the voltage signal is greater than the reference voltage value, a third level signal is output;

[0018] If the amplitude of the voltage signal is less than the reference voltage value, a fourth level signal is output;

[0019] Among them, one of the third level signal and the fourth level signal is a high level signal and the other is a low level signal.

[0020] Optionally, the power supply amplitude modulation carrier determination circuit is further configured to:

[0021] The amplitude of the voltage signal is compared with multiple pre-divided voltage intervals, and the data code corresponding to the voltage interval to which the amplitude of the voltage signal belongs is output.

[0022] Optionally, the power supply amplitude modulation carrier determination circuit is further configured to:

[0023] When the amplitude of the voltage signal is within the first voltage range, it is parsed as the first data symbol;

[0024] When the amplitude of the voltage signal is within the second voltage range, it is parsed as the second data code element;

[0025] When the amplitude of the voltage signal is within the third voltage range, it is parsed as the third data symbol;

[0026] When the amplitude of the voltage signal is in the fourth voltage range, it is parsed as the fourth data symbol;

[0027] The four voltage ranges each correspond to a different two-bit binary data symbol.

[0028] Optionally, the data decoding module is configured as follows:

[0029] The corresponding display effect is determined based on the digital signal, and the corresponding control signal is output based on the determined display effect.

[0030] Optionally, the driver module is further configured to:

[0031] The display content of the LED light module is determined based on the display data, and the corresponding driving current is output based on the parameter data to drive the LED light module to emit light.

[0032] Optionally, the LED cascaded display chip further includes:

[0033] A chip address storage module, connected to the data decoding module, is used to store the chip address corresponding to the LED cascaded display chip, and to provide the chip address to the power amplitude modulation carrier judgment circuit through the data decoding module for address matching of the received display signal;

[0034] A built-in display effect storage module is connected to the data decoding module and is used to store a variety of preset display effects. When the data decoding module determines the target display effect based on the digital signal, it retrieves the corresponding display effect data from the built-in display effect storage module.

[0035] Optionally, the LED cascaded display chip further includes:

[0036] A power-on reset module, connected to the data decoding module, is used to reset the data decoding module when the LED cascaded display chip is powered on, so that the data decoding module enters a preset initial working state.

[0037] An oscillation circuit, connected to the data decoding module, is used to provide a working clock signal for the data decoding module.

[0038] A second aspect of the present invention provides a series system for LED cascaded display chips. The series system includes the LED cascaded display chips described in the first aspect, at least one LED lamp module, and an LED cascaded display chip controller. Each LED cascaded display chip is connected to one LED lamp module. The power output terminal of the LED cascaded display chip controller is connected to the power supply terminal of each LED cascaded display chip and each LED lamp module, respectively. The ground terminal of the LED cascaded display chip controller is connected to the ground terminal of each LED cascaded display chip.

[0039] The technical effects of this invention are as follows: By introducing a signal judgment and parsing mechanism based on power amplitude modulation carrier into the LED cascaded display chip, reliable acquisition of display signals can be achieved without adding additional communication lines. Combined with the parsing of display signals corresponding to chip addresses, each LED cascaded display chip can independently complete display control. At the same time, by separating and parsing display data and parameter data and unifying them under the control of the driver module, the flexibility and reliability of LED display control are improved, making it suitable for LED cascaded display application scenarios with high requirements for both cost and system stability. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a circuit diagram of a series system of LED cascaded display chips provided by existing technology;

[0042] Figure 2 This is a schematic diagram of the first structure of an LED cascaded display chip provided in Embodiment 1 of the present invention;

[0043] Figure 3 This is a schematic diagram of binary power amplitude modulation carrier data and quaternary power amplitude modulation carrier data of an LED cascaded display chip provided in Embodiment 1 of the present invention;

[0044] Figure 4 This is a schematic diagram of a second structure of an LED cascaded display chip provided in Embodiment 1 of the present invention;

[0045] Figure 5 This is a circuit diagram of a series system of LED cascaded display chips provided in Embodiment 1 of the present invention;

[0046] In the diagram: 101, Power supply amplitude modulation carrier judgment circuit; 102, Data decoding module; 103, Data parsing module; 104, Parameter parsing module; 105, Driver module; 106, LED module; 107, Chip address storage module; 108, Built-in display effect storage module; 109, Power-on reset module; 110, Oscillation circuit; 201, LED cascade display chip; 202, LED cascade display chip controller. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0049] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0050] To fully understand this invention, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0051] Example 1

[0052] This embodiment provides an LED cascaded display chip, such as Figure 2 As shown, the LED cascaded display chip is connected to the LED lamp module 106. The LED cascaded display chip includes:

[0053] The power supply amplitude modulation carrier judgment circuit 101 is configured to acquire the display signal corresponding to the address of the LED cascaded display chip, sample the voltage signal in the display signal, and generate a corresponding digital signal based on the amplitude of the voltage signal.

[0054] The data decoding module 102 is connected to the power supply amplitude modulation carrier judgment circuit 101 and is configured to decode digital signals to obtain control data;

[0055] The data parsing module 103, connected to the data decoding module 102, is configured to parse display data from control data.

[0056] The parameter parsing module 104 is connected to the data decoding module 102 and is configured to parse parameter data from control data;

[0057] The driver module 105 is connected to the data parsing module 103 and the parameter parsing module 104 respectively, and is configured to control the display state of the LED module 106 according to the display data and parameter data.

[0058] The LED cascaded display chip is used to connect to and drive the LED lamp module 106 to control the display status of the LED lamp module 106. The LED cascaded display chip includes a power amplitude modulation carrier judgment circuit 101, a data decoding module 102, a data parsing module 103, a parameter parsing module 104, and a driving module 105. These modules work together to complete signal acquisition, parsing, and display control. The power amplitude modulation carrier judgment circuit 101 receives the display signal corresponding to the chip address and samples the voltage signal in the display signal. By judging the amplitude of the sampled voltage signal, the power amplitude modulation carrier judgment circuit 101 converts the voltage change into a corresponding digital signal, thereby realizing data acquisition based on the power amplitude modulation carrier. The data decoding module 102 is connected to the power amplitude modulation carrier judgment circuit 101 and is used to decode the digital signal. Through the decoding operation, the data decoding module 102 recovers control data conforming to predetermined communication rules from the digital signal, providing a basis for subsequent data parsing. The data parsing module 103 is connected to the data decoding module 102. It extracts information related to the display of the LED module 106 from the control data and parses this information into display data. The display data describes the display content of the LED module 106, including but not limited to on / off states, color information, or display order. The parameter parsing module 104 is also connected to the data decoding module 102. It is configured to obtain parameter data from the control data to characterize the operating parameters of the LED module 106. The parameter data reflects the driving parameters or display configuration parameters of the LED to meet control requirements under different display needs. The driving module 105 is connected to both the data parsing module 103 and the parameter parsing module 104. Based on the display data and parameter data, it comprehensively controls the display state of the LED module 106. Through the coordinating action of the driving module 105, precise control of the display mode of the LED module 106 is achieved, thereby completing the corresponding display effect.

[0059] The technical advantages of this embodiment are as follows: By introducing a signal judgment and parsing mechanism based on power amplitude modulation carrier into the LED cascaded display chip, reliable acquisition of display signals can be achieved without adding additional communication lines. Combined with the parsing of display signals corresponding to chip addresses, each LED cascaded display chip can independently complete display control. At the same time, by separating and parsing display data and parameter data and controlling them uniformly by the driver module 105, the flexibility and reliability of LED display control are improved, making it suitable for LED cascaded display application scenarios with high requirements for cost and system stability.

[0060] In one implementation, the power supply amplitude modulation carrier determination circuit 101 is further configured as follows:

[0061] When the amplitude of the voltage signal is greater than the preset voltage value, the first level signal is output;

[0062] When the amplitude of the voltage signal is less than the preset voltage value, a second level signal is output;

[0063] In this signal, one of the first level signal and the second level signal is a high level signal, and the other is a low level signal.

[0064] The power supply amplitude modulation carrier judgment circuit 101 is used to determine the amplitude of the acquired voltage signal. This judgment circuit has a preset voltage value, which serves as the voltage decision threshold. When the amplitude of the sampled voltage signal is higher than the preset voltage value, the power supply amplitude modulation carrier judgment circuit 101 outputs a first high-level signal (first level signal); when the amplitude of the voltage signal is lower than the preset voltage value, the power supply amplitude modulation carrier judgment circuit 101 outputs a first low-level signal (second level signal). In this way, the amplitude change of the voltage signal can be converted into a corresponding digital level state, thereby realizing data signal judgment based on power supply amplitude modulation carrier.

[0065] The technical advantage of this embodiment is that by setting a fixed preset voltage value as the decision threshold, the power supply amplitude modulation carrier judgment circuit 101 can complete the amplitude differentiation of the voltage signal in a simple structure and clear judgment manner, and reliably convert the continuously changing voltage signal into a stable digital level signal. This is beneficial to improving the accuracy and real-time performance of amplitude modulation carrier data judgment, while reducing the complexity of circuit implementation. It is suitable for application in LED cascaded display chips where cost is limited and reliability is required.

[0066] In one implementation, the power supply amplitude modulation carrier determination circuit 101 is further configured as follows:

[0067] Obtain the reference voltage value from the display signal;

[0068] When the amplitude of the voltage signal is greater than the reference voltage value, a third-level signal is output;

[0069] When the amplitude of the voltage signal is less than the reference voltage value, a fourth level signal is output;

[0070] Among them, one of the third level signal and the fourth level signal is a high level signal, and the other is a low level signal.

[0071] In this embodiment, the power amplitude modulation carrier determination circuit 101 is configured to extract a reference voltage value from the display signal and use the reference voltage value as a reference threshold for voltage amplitude determination. During transmission, the display signal may initially contain reference voltage information characterizing the current power state, which the power amplitude modulation carrier determination circuit 101 identifies and stores. After acquiring the reference voltage value, the power amplitude modulation carrier determination circuit 101 samples the voltage signal in the display signal. When the amplitude of the sampled voltage signal is higher than the reference voltage value, the power amplitude modulation carrier determination circuit 101 outputs a high-level signal (third-level signal); when the amplitude of the voltage signal is lower than the reference voltage value, it outputs a low-level signal (fourth-level signal), thereby achieving power amplitude modulation carrier determination based on an adaptive reference.

[0072] For example, in a certain display control process, the control terminal can first send a reference voltage information through the display signal to indicate the reference level for the current power amplitude modulation determination; the subsequently sent amplitude modulation voltage signal changes high or low relative to the reference voltage, and the power amplitude modulation carrier determination circuit 101 outputs the corresponding high or low level signal according to the magnitude relationship between the sampled voltage and the reference voltage, for subsequent data decoding and parsing processing.

[0073] The technical effect of this embodiment is that by obtaining the reference voltage value from the display signal and completing the amplitude modulation carrier determination accordingly, the power supply amplitude modulation carrier determination circuit 101 can dynamically establish a voltage decision reference according to the actual communication environment, effectively reducing the determination error caused by power supply fluctuations, line voltage drops or load changes, improving the reliability and consistency of amplitude modulation carrier data recognition, thereby enhancing the stable working capability of the LED cascaded display chip in complex application scenarios.

[0074] In one implementation, the power supply amplitude modulation carrier determination circuit 101 is further configured as follows:

[0075] The amplitude of the voltage signal is compared with multiple pre-divided voltage ranges, and the data code corresponding to the voltage range to which the amplitude of the voltage signal belongs is output.

[0076] The power supply amplitude modulation carrier determination circuit 101 is configured to analyze the voltage signal using a multi-voltage range determination method. Specifically, the power supply amplitude modulation carrier determination circuit 101 pre-divides the amplitude range of the voltage signal into multiple distinct voltage ranges. After sampling the voltage signal, it compares the sampled voltage amplitude with the multiple voltage ranges to determine the voltage range to which the voltage signal belongs and outputs the data symbol corresponding to that voltage range. In this embodiment, when the voltage signal amplitude is in the first voltage range, the power supply amplitude modulation carrier determination circuit 101 analyzes it as the first data symbol; when the voltage signal amplitude is in the second voltage range, it analyzes it as the second data symbol; when the voltage signal amplitude is in the third voltage range, it analyzes it as the third data symbol; and when the voltage signal amplitude is in the fourth voltage range, it analyzes it as the fourth data symbol. The four voltage ranges correspond to different binary data symbols, thereby realizing multi-level power supply amplitude modulation carrier data transmission.

[0077] like Figure 3 As shown, in a specific application scenario, compared to the method of distinguishing high and low levels solely by a single voltage judgment, which can only achieve binary data transmission, the power supply amplitude modulation carrier judgment circuit 101 can divide the amplitude range of the supply voltage VDD into multiple voltage intervals. For example, the interval where the amplitude modulation voltage is located at (0V, 0.25VDD) can be interpreted as data symbol "00", the interval where the amplitude modulation voltage is located at (0.25VDD, 0.5VDD) can be interpreted as data symbol "01", the interval where the amplitude modulation voltage is located at (0.5VDD, 0.75VDD) can be interpreted as data symbol "10", and the interval where the amplitude modulation voltage is located at (0.75VDD, VDD) can be interpreted as data symbol "11", thereby carrying more data information within the same amplitude modulation cycle. It should be understood that the above voltage interval division method is only an example, and it can be divided into more intervals as needed to achieve octal, hexadecimal, or higher base power supply amplitude modulation carrier data transmission.

[0078] The technical advantages of this implementation are as follows: by dividing the voltage amplitude of the power supply amplitude modulation carrier into multiple determination intervals, a single amplitude modulation is no longer limited to distinguishing between high and low levels, but can carry multiple binary data symbols, thereby significantly improving the data transmission capacity without increasing the complexity of communication lines and hardware; at the same time, the multi-voltage interval determination method enhances the flexibility of power supply amplitude modulation carrier transmission, providing LED cascaded display chips with higher data carrying capacity and expansion space in complex display control scenarios.

[0079] In one implementation, the data decoding module 102 is configured as follows:

[0080] The corresponding display effect is determined based on the digital signal, and the corresponding control signal is output based on the determined display effect.

[0081] The data decoding module 102 processes the digital signal output by the power supply amplitude modulation carrier judgment circuit 101. The data decoding module 102 analyzes the digital signal according to a preset data format and encoding rules to determine the corresponding display effect. The display effect can be one of the preset display modes within the chip, used to indicate the display mode of the LED lights.

[0082] After determining the display effect, the data decoding module 102 generates corresponding control signals based on the display effect and outputs the control signals to subsequent functional modules. The control signals are used to indicate the calling method of display data and related parameters, so that subsequent modules can control the LED display status accordingly.

[0083] The technical advantage of this embodiment is that by directly determining the corresponding display effect based on the digital signal in the data decoding module 102 and outputting a control signal that matches the display effect, the display control logic can complete the classification and guidance during the decoding stage, reducing the complexity of subsequent processing, which is conducive to improving the efficiency and consistency of display control response, thereby enhancing the adaptability of the LED cascaded display chip to different display requirements.

[0084] In one implementation, the driver module 105 is further configured to:

[0085] The display content of the LED light module 106 is determined based on the display data, and the corresponding driving current is output based on the parameter data to drive the LED light module 106 to emit light.

[0086] In this embodiment, the driving module 105 is connected to the data parsing module 103 and the parameter parsing module 104 to comprehensively process display data and parameter data. The driving module 105 first determines the display content of the LED module 106 based on the display data. The display content includes, but is not limited to, on / off state, color information, or brightness level. By recognizing the display content, the driving module 105 can clearly identify the LED to be driven and the corresponding display mode. After determining the display content, the driving module 105 generates a driving current matching the display content based on the parameter data and outputs the driving current to the corresponding LED to drive the LED to emit light. The parameter data is used to characterize the driving parameters or operating conditions of the LED, thereby ensuring that the output driving current meets the display requirements.

[0087] The technical advantages of this embodiment are as follows: by co-processing the display data and parameter data in the driving module 105, the display content of the LED lamp and the driving current are precisely matched, thereby ensuring the consistency and stability of the LED lamp's luminous effect; at the same time, this method is conducive to flexibly adjusting the driving parameters under different display scenarios, improving the adaptability of the LED cascaded display chip to complex display requirements.

[0088] As one implementation method, such as Figure 4 As shown, the LED cascaded display chip also includes:

[0089] The chip address storage module 107 is connected to the data decoding module 102. It is used to store the chip address corresponding to the LED cascaded display chip and to provide the chip address to the power amplitude modulation carrier judgment circuit 101 through the data decoding module 102 for address matching of the received display signal.

[0090] The built-in display effect storage module 108 is connected to the data decoding module 102 and is used to store a variety of preset display effects. When the data decoding module 102 determines the target display effect based on the digital signal, it retrieves the corresponding display effect data from the built-in display effect storage module 108.

[0091] The LED cascaded display chip further includes a chip address storage module 107 and a built-in display effect storage module 108, both connected to the data decoding module 102 to expand the chip's addressing capabilities and display control functions. The chip address storage module 107 stores the chip address information corresponding to the LED cascaded display chip. When decoding the received digital signal, the data decoding module 102 can retrieve the chip address from the chip address storage module 107 and provide it to the power supply amplitude modulation carrier judgment circuit 101, enabling it to perform matching judgments based on the chip address when parsing the display signal, thus responding only to display signals with the same address. The built-in display effect storage module 108 stores various preset display effect data. After the data decoding module 102 determines the target display effect based on the digital signal, it can read the display effect data corresponding to the target display effect from the built-in display effect storage module 108 and use the display effect data in the subsequent display control process, thereby realizing the selection and switching of various display effects.

[0092] The technical advantages of this embodiment are as follows: by introducing a chip address storage module 107 into the LED cascaded display chip, effective differentiation and addressing control of different chips are achieved under the condition of shared power supply amplitude modulation carrier, avoiding multiple chips responding to the same display signal at the same time; at the same time, with the help of the built-in display effect storage module 108, the display control no longer relies entirely on external data transmission, which reduces the communication load while enriching the display effect, thereby improving the flexibility and reliability of the LED cascaded display system.

[0093] As one implementation method, such as Figure 4 As shown, the LED cascaded display chip also includes:

[0094] The power-on reset module 109 is connected to the data decoding module 102 and is used to reset the data decoding module 102 when the LED cascaded display chip is powered on, so that the data decoding module 102 enters the preset initial working state.

[0095] The oscillation circuit 110 is connected to the data decoding module 102 and is used to provide the data decoding module 102 with a working clock signal.

[0096] The LED cascaded display chip further includes a power-on reset module 109 and an oscillation circuit 110, both connected to the data decoding module 102 to ensure stable operation of the chip during power-on and operation. The power-on reset module 109 is triggered when the LED cascaded display chip is powered on, resetting the data decoding module 102 to a preset initial operating state before it begins parsing digital signals, thus avoiding decoding anomalies caused by power-on transients or uncertain states. The oscillation circuit 110 generates a stable operating clock signal and provides it to the data decoding module 102. Driven by the operating clock signal, the data decoding module 102 completes the sampling, decoding, and related processing operations of the digital signals to ensure the timing consistency of each processing step.

[0097] The technical effect of this embodiment is that by setting a power-on reset module 109 and an oscillation circuit 110 in the LED cascaded display chip, the data decoding module 102 can reliably enter the initial state during the power-on phase and operate in an orderly manner with the support of a stable clock signal, thereby improving the reliability and timing stability of the decoding process, reducing the impact of abnormal states on display control, and enhancing the working stability of the LED cascaded display chip in complex application environments.

[0098] In one embodiment, the LED cascaded display chip is configured to support local loop and automatic update control of the display effect, that is, in the absence of receiving new display signals or control data, it can automatically maintain or update the display state of the LED module 106 based on the internally stored display effect data.

[0099] Specifically, the built-in display effect storage module 108 pre-stores various display effect data. Each display effect data includes at least one or a combination of the following information: display mode identifier, display cycle parameter, brightness change parameter, color change parameter, display order parameter, and loop count parameter. After receiving the display signal and determining the target display effect, the data decoding module writes the corresponding display effect index information into the internal register unit or status register as the basis for subsequent local loop execution.

[0100] After loading the target display effect, the drive module 105, without receiving a new display signal, automatically performs a cyclic drive operation on the LED module 106 according to the preset display order and time parameters based on the parameter information corresponding to the current display effect. For example, the drive module 105 can automatically update the brightness level, emission color, or lighting status of the LED module 106 at the end of each display cycle based on its internal timing unit, thereby achieving effects such as flowing water display, breathing display, flashing display, or gradient display.

[0101] In one specific implementation, the display effect loop can be set to an infinite loop until a new display signal is received; in another implementation, the display effect loop can be set to a finite number of loops, and after completing a preset number of loops, it remains in the final display state.

[0102] In an optional implementation, the driving module 105 is further configured to automatically switch between multiple display effects when preset conditions are met. These preset conditions may include, but are not limited to: the current display effect's cycle count reaching a preset threshold; the internal timer reaching a preset time; a preset delay after power-on; and the parameter parsing module detecting a specific parameter state. When the preset conditions are met, the driving module 105 can automatically switch to the next display effect according to the display effect sequence table in the built-in display effect storage module 108, and repeatedly execute the corresponding local loop control process.

[0103] When the LED cascaded display chip receives a new display signal during the execution of local loop and automatic update of display effects, the data decoding module 102 immediately parses the newly received digital signal and updates the current display effect index according to the parsing result, thereby interrupting the original local loop display process and executing the newly indicated display effect. In this way, the priority of external display control signals is ensured, so that the local loop and automatic update mechanism does not affect the overall controllability of the system.

[0104] By introducing a local loop and automatic update mechanism for display effects, the LED cascaded display chip can stably output the expected display effect without relying on continuous external control signals, effectively reducing the requirements for communication frequency and data throughput at the control end. Simultaneously, this method can maintain continuous and smooth display output even under brief power line interference, communication interruptions, or discontinuous control signal updates, significantly improving the reliability, robustness, and user experience of the LED cascaded display system in practical applications.

[0105] In one embodiment, the LED cascaded display chip is configured to support hierarchical management of multi-level local display states, so that the LED cascaded display chip can control the connected LED lamp modules according to preset rules in different operating stages and different system states.

[0106] Specifically, the multi-level local display state includes at least an initial display state, a current cycle display state, and a standby display state. The initial display state represents the default display state of the LED cascaded display chip after power-on or reset; the current cycle display state represents the local cycle display state executed by the LED cascaded display chip during normal operation; and the standby display state is activated when an abnormal situation is detected or when no display signal is received for an extended period.

[0107] After the LED cascaded display chip is powered on, the power-on reset module 109 resets the data decoding module 102, causing the data decoding module to enter a preset initial working state. The drive module 105 then enters the initial display state and drives the LED module 106 to display according to the pre-stored first display effect. The first display effect can be a fixed brightness display, a low brightness indicator display, or other display effects used to characterize the initial state.

[0108] After the data decoding module 102 successfully parses the display control data that matches the address of the LED cascaded display chip, the data decoding module 102 sends a state switching indication signal to the driver module, and the driver module 105 switches from the initial display state to the current cyclic display state. In the current cyclic display state, the driver module 105 performs local cyclic display control on the LED module 106 according to the corresponding display effect data in the built-in display effect storage module 108, and according to the preset display order, display cycle and related parameters.

[0109] In the current cyclic display state, if the driving module 105 does not detect a new display signal within a preset time, or if the power supply amplitude modulation carrier judgment circuit detects a power supply abnormality or amplitude modulation carrier abnormality, the driving module switches from the current cyclic display state to the standby display state. In the standby display state, the driving module 105 controls the LED lamp module 106 to display according to a preset standby display effect, which can be a fixed display, a reduced brightness display, or other safety display methods.

[0110] When the abnormal state is resolved, or when display control data matching the chip address is detected again, the driver module 105 switches from the standby display state back to the current loop display state and loads the corresponding display effect data to continue executing the local loop display.

[0111] In a preferred embodiment, there is a preset hierarchical priority relationship between the initial display state, the current cycle display state, and the standby display state. When multiple state switching conditions are met simultaneously, the drive module determines the final display state to be executed according to the hierarchical priority relationship, so as to ensure the determinism of the display control logic.

[0112] In addition, during the display state switching process, the drive module is configured to smoothly adjust the drive parameters so that the brightness, current or display content of the LED module gradually transitions over multiple display cycles, thereby avoiding sudden display changes.

[0113] By implementing the hierarchical management method of multi-level local display status, the LED cascaded display chip has clear and controllable display behavior in power-on initialization, normal operation, and abnormal or idle states, thereby improving the stability and reliability of the LED cascaded display system in complex operating environments.

[0114] Example 2

[0115] This second embodiment provides a series system for cascaded LED display chips, such as... Figure 5As shown, the series system includes at least one LED cascaded display chip 201 provided in Embodiment 1, at least one LED lamp module 106, and an LED cascaded display chip controller 202. Each LED cascaded display chip is connected to one LED lamp module 106. The power output terminal of the LED cascaded display chip controller 202 is connected to the power supply terminal of each LED cascaded display chip 201 and each LED lamp module 106, respectively. The ground terminal of the LED cascaded display chip controller 202 is connected to the ground terminal of each LED cascaded display chip 201, respectively.

[0116] In this system, each LED cascade display chip 201 is connected to an LED lamp module 106 for display control of the corresponding LED lamp module. The LED cascade display chip controller 202 has a power output terminal and a ground terminal. The power output terminal is connected to the power supply terminals of each LED cascade display chip and each LED lamp module, providing operating power to the LED cascade display chip 201 and LED lamp module 106. The ground terminal is connected to the ground terminal of each LED cascade display chip 201 to form a complete power supply loop. Through this connection method, the LED cascade display chip controller 202 can provide unified power supply conditions for multiple LED cascade display chips 201 and their corresponding LED lamp modules 106. After receiving power, each LED cascade display chip performs corresponding display control on the connected LED lamp module according to the received control signal, thereby realizing the coordinated display of multiple LED lamp modules in the series system.

[0117] The LED cascade display chip controller 202 first provides operating power to each LED cascade display chip 201 and each LED lamp module 106 through its power output terminal, and at the same time forms a common grounding loop with the grounding terminal of each LED cascade display chip 201 through its grounding terminal, thereby completing the power supply establishment of the system.

[0118] After the system is powered on, each LED cascade display chip 201 enters the working state after receiving power, and detects and processes the power supply voltage output by the LED cascade display chip controller 202. During the power supply process, the LED cascade display chip controller 202 modulates the output power supply and superimposes display control information on the power supply voltage, so that the power supply voltage simultaneously carries the amplitude modulation carrier signal used for display control.

[0119] Each cascaded LED display chip 201 samples the received power supply voltage and extracts the amplitude-modulated carrier signal from it, then parses it to obtain display control data corresponding to its own chip address. After parsing, each cascaded LED display chip 201 outputs a corresponding drive current to the connected LED lamp module 106 according to the acquired display data and parameter data, so as to control the display state of the corresponding LED lamp module 106.

[0120] Through the above working process, the series system achieves unified power supply and display control of multiple LED cascade display chips 201 and their corresponding LED lamp modules 106 by the LED cascade display chip controller 202, relying solely on the power supply line.

[0121] The technical advantages of this embodiment are as follows: by adopting a series system structure with the LED cascaded display chip controller as the unified power supply node, centralized power supply and unified management of multiple LED cascaded display chips and LED lamp modules are realized, simplifying the system wiring structure; at the same time, each LED cascaded display chip is independently connected to the corresponding LED lamp module, which helps to improve the flexibility of display control, enabling the series system to meet the needs of multi-lamp module cascaded applications while ensuring display consistency.

[0122] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. An LED cascaded display chip, characterized in that, The LED cascade display chip is connected with an LED lamp module, and the LED cascade display chip comprises: The power supply amplitude carrier judgment circuit is configured to obtain a display signal corresponding to an address of the LED cascade display chip, sample a voltage signal in the display signal, and generate a corresponding digital signal according to an amplitude of the voltage signal; The data decoding module is connected with the power supply amplitude carrier judgment circuit and is configured to decode the digital signal to obtain control data; The data analysis module is connected with the data decoding module and is configured to analyze the display data from the control data; The parameter analysis module is connected with the data decoding module and is configured to analyze parameter data from the control data; The driving module is connected with the data analysis module and the parameter analysis module respectively and is configured to control a display state of the LED lamp module according to the display data and the parameter data; The power supply amplitude carrier judgment circuit is further configured to: compare the amplitude of the voltage signal with a plurality of voltage intervals divided in advance, and output a data symbol corresponding to a voltage interval to which the amplitude of the voltage signal belongs; The LED cascade display chip further comprises: The chip address storage module is connected with the data decoding module and is configured to store a chip address corresponding to the LED cascade display chip, and provide the chip address to the power supply amplitude carrier judgment circuit through the data decoding module, so as to perform address matching on the received display signal; The built-in display effect storage module is connected with the data decoding module and is configured to store a plurality of preset display effects, and when the data decoding module determines a target display effect according to the digital signal, call corresponding display effect data from the built-in display effect storage module.

2. The LED cascaded display chip according to claim 1, wherein, The power supply amplitude carrier judgment circuit is further configured to: output a first level signal when the amplitude of the voltage signal is greater than a preset voltage value; output a second level signal when the amplitude of the voltage signal is less than the preset voltage value; wherein one of the first level signal and the second level signal is a high level signal, and the other is a low level signal.

3. The LED cascaded display chip of claim 1, wherein, The power supply amplitude carrier judgment circuit is further configured to: obtain a reference voltage value from the display signal; output a third level signal when the amplitude of the voltage signal is greater than the reference voltage value; output a fourth level signal when the amplitude of the voltage signal is less than the reference voltage value; wherein one of the third level signal and the fourth level signal is a high level signal, and the other is a low level signal.

4. The LED cascaded display chip of claim 1, wherein, The power supply amplitude carrier judgment circuit is further configured to: analyze as a first data symbol when the amplitude of the voltage signal is in a first voltage interval; analyze as a second data symbol when the amplitude of the voltage signal is in a second voltage interval; analyze as a third data symbol when the amplitude of the voltage signal is in a third voltage interval; analyze as a fourth data symbol when the amplitude of the voltage signal is in a fourth voltage interval; wherein the four voltage intervals correspond to different two-bit binary data symbols respectively.

5. The LED cascaded display chip of claim 1, wherein, The data decoding module is configured to: determine a corresponding display effect according to the digital signal, and output a corresponding control signal according to the determined display effect.

6. The LED cascaded display chip of claim 1, wherein, The driving module is further configured to: determine display content of the LED lamp module according to the display data, and output a corresponding driving current to drive the LED lamp module to emit light according to the parameter data.

7. The LED cascaded display chip of claim 1, wherein, The LED cascade display chip further comprises: a power-on reset module connected with the data decoding module, configured to perform reset control on the data decoding module when the LED cascade display chip is powered on, so that the data decoding module enters a preset initial working state; an oscillation circuit connected with the data decoding module, configured to provide a working clock signal for the data decoding module.

8. A series connection system of LED cascaded display chips, characterized in that, The series system comprises at least one LED cascade display chip according to any one of claims 1 to 7, at least one LED lamp module, and an LED cascade display chip controller, each LED cascade display chip is connected with one LED lamp module, a power supply output end of the LED cascade display chip controller is connected with a power supply end of each LED cascade display chip and each LED lamp module, and a grounding end of the LED cascade display chip controller is connected with a grounding end of each LED cascade display chip.

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