Data driver and display device including the same

Abstract

A data driver and a display device including the same are disclosed. The data driver is configured to drive a display panel including a plurality of data lines, a plurality of sensing lines, and a plurality of sub-pixels, the data driver includes a driving block configured to provide a data signal to each of the plurality of sub-pixels, a sensing block configured to measure an electrical characteristic of each of the plurality of sub-pixels, a plurality of data internal lines configured to connect a plurality of driving block nodes included in the driving block to a plurality of data pads connected to the plurality of data lines, and a plurality of sensing internal lines configured to connect a plurality of sensing nodes included in the sensing block to a plurality of sensing pads connected to the plurality of sensing lines, wherein each of the plurality of sensing internal lines includes a line portion between at least one data internal line and one sensing internal line.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0100548, filed on July 29, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device, and for example, to a data driver for driving a display panel to display an image on the display panel, and a display device including the same. Background Technology

[0004] Display devices include a display panel for displaying images and a display driving circuit for driving the display panel. The display driving circuit drives the display panel by receiving image data from an external source and applying an image signal corresponding to the received image data to the data lines of the display panel. Recently, the use of OLED display panels, in which each of the multiple sub-pixels in the pixel array has an organic light-emitting diode (hereinafter referred to as OLED), has been increasing.

[0005] In OLED display panels, the image quality of the image displayed on the panel may degrade when the electrical characteristics, such as threshold voltage and mobility, of the driving transistors supplied in the sub-pixels are non-uniform between sub-pixels and change due to sub-pixel degradation. Therefore, techniques for external compensation have been investigated, which detect the electrical characteristics of the sub-pixels and compensate the sub-pixel data to be supplied to each of the sub-pixels by using compensation values ​​determined based on the detected electrical characteristics. Summary of the Invention

[0006] The present invention provides a data driver and a display device that can reduce the line capacitance deviation of the sensing internal lines connected to the display panel and arranged on the data driver that drives the display panel.

[0007] According to some exemplary embodiments of the present invention, a data driver is provided, configured to drive a display panel including multiple data lines, multiple sensing lines, and multiple sub-pixels connected to the multiple data lines and the multiple sensing lines. The data driver includes: a driving block configured to provide a data signal to each of the multiple sub-pixels; a sensing block configured to measure the electrical characteristics of each of the multiple sub-pixels; multiple internal data lines configured to connect multiple driving block nodes included in the driving block to multiple data pads connected to the multiple data lines; and multiple internal sensing lines configured to connect multiple sensing nodes included in the sensing block to multiple sensing pads connected to the multiple sensing lines, wherein each of the multiple internal sensing lines includes a line portion between at least one internal data line and one internal sensing line.

[0008] According to some exemplary embodiments of the present invention, a data driver is provided, configured to drive a display panel including multiple data lines, multiple sensing lines, and multiple sub-pixels connected to the multiple data lines and the multiple sensing lines. The data driver includes: a driving block configured to provide a data signal to each of the multiple sub-pixels; a sensing block configured to measure the electrical characteristics of each of the multiple sub-pixels; multiple internal data lines configured to connect multiple driving block nodes included in the driving block to multiple data pads connected to the multiple data lines; and multiple internal sensing lines configured to connect multiple sensing nodes included in the sensing block to multiple sensing pads connected to the multiple sensing lines, wherein two of the multiple internal sensing lines are located between the multiple internal data lines.

[0009] According to other exemplary embodiments of the present invention, a display device is provided, including a display panel and a data driver. The display panel includes multiple data lines, multiple sensing lines, and multiple sub-pixels connected to the multiple data lines and the multiple sensing lines. The data driver is configured to drive the display panel, wherein the data driver includes: a driving block configured to provide a data signal to each of the multiple sub-pixels; a sensing block configured to measure the electrical characteristics of each of the multiple sub-pixels; multiple internal data lines configured to connect multiple driving block nodes included in the driving block to multiple data pads connected to the multiple data lines; and multiple internal sensing lines configured to connect multiple sensing nodes included in the sensing block to multiple sensing pads connected to the multiple sensing lines, wherein two of the multiple internal sensing lines are located between the multiple internal data lines. Attached Figure Description

[0010] Some exemplary embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1This is a block diagram illustrating a display system according to some example embodiments;

[0012] Figure 2A and Figure 2B These are diagrams of the equivalent circuits of sub-pixels and timing diagrams of the equivalent circuits, based on some example embodiments.

[0013] Figure 3 The arrangement of lines in a data driver according to some example embodiments is shown;

[0014] Figure 4 The layout of a data drive according to some example embodiments is shown;

[0015] Figure 5A and Figure 5B The arrangement of sensing internal lines and data internal lines in region A according to some example embodiments is shown;

[0016] Figure 6A and Figure 6B The arrangement of sensing internal lines and data internal lines in region B according to some example embodiments is shown;

[0017] Figure 7A and Figure 7B The arrangement of sensing internal lines and data internal lines in region C according to some example embodiments is shown;

[0018] Figure 8A and Figure 8B The arrangement of sensing internal lines and data internal lines in region D according to some example embodiments is shown;

[0019] Figure 9A and Figure 9B The arrangement of sensing internal lines and data internal lines in region A according to some example embodiments is shown;

[0020] Figure 10 The arrangement of lines on a display panel according to some example embodiments is shown;

[0021] Figure 11 An implementation example of a display device according to an embodiment is shown; and

[0022] Figure 12 An implementation example of a display device according to an embodiment is shown. Detailed Implementation

[0023] In the following description, some exemplary embodiments of the inventive concept are described in conjunction with the accompanying drawings.

[0024] It should be understood that an element and / or its properties may be described herein as “identical” or “equal” to other elements, and it should be further understood that an element and / or its properties described herein as “completely identical,” “identical,” or “equal” to other elements may be “completely identical,” “identical,” or “equal” to other elements and / or its properties, or “substantially identical,” “substantially identical,” or “substantially equal” to other elements and / or its properties. Element and / or its properties that are “substantially identical,” “substantially identical,” or “substantially equal” to other elements and / or its properties will be understood to include elements and / or its properties that are completely identical, identical, or equal to other elements and / or its properties within manufacturing tolerances and / or material tolerances. Element and / or its properties that are completely identical or substantially identical and / or identical or substantially identical to other elements and / or its properties may be structurally identical or substantially identical, functionally identical or substantially identical, and / or compositionally identical or substantially identical.

[0025] It should be understood that the description of elements and / or properties as “substantially” identical and / or completely identical herein encompasses elements and / or properties with a relative magnitude difference of equal to or less than 10%. Furthermore, regardless of whether the elements and / or properties are modified to be “substantially”, it should be understood that these elements and / or properties should be interpreted to include manufacturing or operational tolerances (e.g., ±10%) surrounding said elements and / or properties.

[0026] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, the numerical values ​​intended to be associated include tolerances of ±10% around said value. When a range is specified, the range includes all values ​​within that range, such as increments of 0.1%. Furthermore, regardless of whether numerical values ​​or shapes are modified to “about” or “substantially”, it should be understood that these values ​​and shapes should be interpreted to include manufacturing or operational tolerances (e.g., ±10%) around said numerical values ​​or shapes.

[0027] Figure 1 This is a block diagram illustrating a display system 1 according to some example embodiments.

[0028] The display system 1, according to some example embodiments, can be installed on an electronic device with image display capabilities. Examples of electronic devices may include smartphones, tablet PCs, portable multimedia players (PMPs), cameras, wearable devices, televisions, digital video disc (DVD) players, refrigerators, air conditioners, air purifiers, set-top boxes, various medical devices, navigation devices, global positioning system (GPS) receivers, vehicle equipment, furniture, and / or various measuring devices.

[0029] refer to Figure 1The display system 1 may include a display driving circuit 10, a display panel 20, and / or a host processor 30. The display driving circuit 10 may include a data driver 100, a timing controller 200, and / or a gate driver 300. The display driving circuit 10 and the display panel 20 may be implemented as a single module and may be referred to as a display device.

[0030] The host processor 30 generally controls the display system 1. The host processor 30 can generate image data to be displayed on the display panel 20 and send the image data and / or control commands to the display driver circuit 10. The host processor 30 may be a graphics processor. However, the inventive concept is not limited thereto, and the host processor 30 can be implemented as various types of processors, such as a central processing unit (CPU), microprocessor, multimedia processor, and / or application processor. In some example embodiments, the host processor 30 can be implemented as an integrated circuit (IC) and / or a system-on-a-chip (SoC).

[0031] The display panel 20 may include multiple signal lines, such as multiple gate lines GL, multiple data lines DL, multiple sensing lines SL, and / or multiple pixels PX connected to the multiple signal lines and arranged in a matrix.

[0032] Each or more of the plurality of pixels PX may include a plurality of sub-pixels SPX, for example, a first sub-pixel SPX1, a second sub-pixel SPX2, and / or a third sub-pixel SPX3. Each or more of the plurality of sub-pixels SPX included in the display panel 20 may be connected to a corresponding gate line GL, data line DL, and / or sensing line SL. In some example embodiments, sub-pixels SPX included in a pixel PX may be connected to the same sensing line SL.

[0033] Subpixels SPX included in a pixel PX can be of different colors. For example, red (R), green (G), and / or blue (B) subpixels can be included in each or one or more of the pixel PX. In other words, the pixel PX can have an RGB structure. However, the inventive concept is not limited thereto, and the pixel PX can have an RGBW structure that further includes a white (W) subpixel for brightness enhancement. Alternatively, the pixel PX can be implemented as a combination of subpixels SPX of different colors.

[0034] In some example embodiments, the display panel 20 may be an organic light-emitting diode (OLED) display panel, wherein each or more of the sub-pixels SPX includes an OLED. In some example embodiments, the display panel 20 may be a quantum dot (QD) display panel, wherein each or more of the sub-pixels SPX includes a QD layer. However, the inventive concept is not limited thereto, and the display panel 20 may be implemented as another type of flat panel display or flexible display panel.

[0035] The timing controller 200 can control the driving timing of the data driver 100 and the gate driver 300 based on control commands received from the host processor 30. The timing controller 200 can perform various image processing operations on the image data received from the host processor 30 to change the image data format, reduce power consumption, etc. For example, when the display panel 20 has an RGBW structure and the received image data has an RGB format corresponding to the RGB structure, the timing controller 200 can change the image data format from RGB to RGBW format by performing data format change processing. The timing controller 200 can then provide the image data with the processed image data to the data driver 100.

[0036] The timing controller 200 can also perform data compensation, i.e., external compensation, on the image data during image processing operations and provide the compensated image data to the data driver 100. The timing controller 200 may include a data compensator (not shown). The timing controller 200 can receive from the data driver 100 reference sense values ​​representing the electrical characteristics of each or more of the plurality of sub-pixels SPX (or sub-pixels in the compensation unit) included in the display panel 20, and generate compensation values ​​based on the reference sense values ​​to compensate for changes in electrical characteristics caused by deviations and / or deterioration of the electrical characteristics of the plurality of sub-pixels SPX. For example, electrical characteristics may include the threshold voltage of the driving transistor in the sub-pixel SPX, the mobility of the driving transistor, the threshold voltage of the light-emitting element, etc. The timing controller 200 may store the compensation values ​​internally and / or externally, and perform data compensation on the image data based on the compensation values.

[0037] The gate driver 300 can drive multiple gate lines GL of the display panel 20 using a gate control signal received from the timing controller 200. The gate driver 300 can provide pulses of gate on-voltage (e.g., scan voltage and / or sense on-voltage) to the corresponding gate line GL during the corresponding driving period of each of the multiple gate lines GL or one or more gate lines based on the gate control signal.

[0038] The data driver 100 may include a driving block 110 and / or a sensing block 120, and can drive multiple sub-pixels PX via multiple data lines DL, and measure the electrical characteristics of multiple sub-pixels SPX via multiple sensing lines SL.

[0039] The driver block 110 can perform digital-to-analog conversion on the received image data and provide the converted analog data signal to the display panel 20 via multiple data lines DL. The data signal can be provided to multiple sub-pixels SPX respectively.

[0040] In display mode and / or sensing mode, driver block 110 can convert image data and / or internally set sensing data provided by timing controller 200 into data signals (e.g., data voltages) and output the data voltages to multiple data lines DL of display panel 20. Driver block 110 may include multiple digital-to-analog converters, and each of the multiple digital-to-analog converters can convert input data (e.g., subpixel data) into data voltages.

[0041] Multiple data lines (DL) can be connected to multiple data pads, and multiple data pads can be connected to multiple internal data lines.

[0042] The sensing block 120 can periodically or non-periodically measure the electrical characteristics of a plurality of sub-pixels SPX. The sensing block 120 can measure the electrical characteristics of each or one or more of the plurality of sub-pixels SPX in a sensing mode, and the sensing mode can be set in the manufacturing operation of the display device, the booting period after the power-on of the display system 1, the end of the power-off period, and / or the dummy period (or vertical blanking period) between the frame display periods of the display panel 20.

[0043] The sensing block 120 can receive sensing signals, such as pixel voltage and / or pixel current, representing the electrical characteristics of each or one or more of the multiple sub-pixels SPX via multiple sensing lines SL, and generate sensing values ​​by performing analog-to-digital conversion on the sensing signals.

[0044] In sensing mode, sensing block 120 can provide initialization voltage and / or low potential voltage to each or one or more of multiple sub-pixels SPX via multiple sensing lines SL. The multiple sensing lines SL can be connected to multiple sensing pads, and the multiple sensing pads can be connected to multiple internal sensing lines. The multiple sensing lines SL can receive the initialization voltage and / or low potential voltage from the voltage supply unit 121 of sensing block 120 via the multiple internal sensing lines.

[0045] Multiple sensing internal lines can have varying line capacitances depending on their arrangement. For example, multiple sensing internal lines can have different line capacitances depending on the type of adjacent lines. Deviations in the line capacitance of multiple sensing internal lines can affect the quality of electrical characteristic measurements of multiple sub-pixel SPXs.

[0046] In some example embodiments, each or one or more of the multiple sensing internal lines may include a line arranged between at least one data internal line and one sensing internal line. In other words, two sensing internal lines may be arranged between multiple data internal lines.

[0047] According to some example embodiments, regardless of the arrangement of the multiple sensing internal lines, the line capacitance deviation of the multiple sensing internal lines can be reduced, and thus the quality of electrical characteristic measurements of multiple sub-pixels SPX can be improved.

[0048] Figure 2A and Figure 2B These are, respectively, diagrams of the equivalent circuits of sub-pixels according to some example embodiments and timing diagrams of the equivalent circuits.

[0049] refer to Figure 2A and Figure 2B Subpixels SPX may include switching transistors SWT, driving transistors DT, OLED 25, storage capacitors Cst, and / or sensing transistors SST. However, Figure 2A The configuration and structure of the subpixel SPX in the example are merely examples of the subpixel SPX circuitry and can be changed in various ways.

[0050] A first driving voltage ELVDD and / or a second driving voltage ELVSS can be applied to the sub-pixel SPX. The first driving voltage ELVDD can be relatively higher than the second driving voltage ELVSS.

[0051] The switching transistor SWT, sensing transistor SST, and / or driving transistor DT may each include amorphous silicon (a-Si) thin film transistors (TFTs), polycrystalline Si TFTs, oxide TFTs, and / or organic TFTs.

[0052] The switching transistor SWT can be connected between the data line DL and the gate node N1 of the driving transistor DT, and can be controlled by the first scan signal Scan1.

[0053] The sensing transistor SST can be connected between the source node N2 of the driving transistor DT and the sensing line SL, and can be controlled by the second scan signal Scan2. The sensing line SL can be connected to the sensing pad SP, and the voltage supplied from the voltage supply unit 121 of the sensing block 120 can be applied to the sensing pad SP.

[0054] The voltage supply unit 121 may include a first switch SW1 that transmits an initialization voltage VINIT and / or a second switch SW2 that transmits a low-level voltage VCM, and the first switch SW1 and / or the second switch SW2 may be connected to a sensing node SN. The low-level voltage VCM may be lower than the initialization voltage VINIT. For example, the low-level voltage VCM may be 0.9V, and the initialization voltage VINIT may be in the range of about 2V to about 6V; however, the example embodiment is not limited thereto.

[0055] During the first time period T1, when the first scan signal Scan1 with a conduction level is applied, the switching transistor SWT can be turned on, so that the data voltage Vdata supplied through the data line DL can be applied to the gate node N1 of the driving transistor DT.

[0056] During the first time period T1, the first switch SW1 can be turned on, so that the initial voltage VINIT is applied to the sensing pad SP through the sensing internal line SIL, and the sensing transistor SST can be turned on through the second scan signal Scan2, so that the initial voltage VINIT applied to the sensing pad SP is applied to the source node N2 of the driving transistor DT through the sensing line SL.

[0057] Therefore, in the first time period T1, the driving voltage Vgs of the driving transistor DT, which is the difference between the data voltage Vdata and the initialization voltage VINIT, can be stored in the storage capacitor Cst.

[0058] During the second time period T2, the switching transistor SWT can be turned off when the first scan signal Scan1, which is at the turn-off level, is applied.

[0059] During the second time period T2, the second switch SW2 can be turned on, allowing the low-potential voltage VCM to be applied to the sensing pad SP through the sensing internal line SIL, and a drive current Idt proportional to the drive voltage Vgs stored in the storage capacitor Cst can flow. Simultaneously with the flow of the drive current Idt, the sensing line capacitor Csl (a parasitic capacitor of the sensing line SL), the sensing internal line capacitor Csil (a parasitic capacitor of the sensing internal line SIL), and the sampling capacitor Cspl between the second switch SW2 and the supply node of the low-potential voltage VCM can be charged.

[0060] Therefore, during the second time period T2, the sampling voltage Vspl stored in the sensing line capacitor Csl, the sensing internal line capacitor Csil, and the sampling capacitor Csp1 can be gradually increased.

[0061] In the third time period T3, when the second switch SW2 is opened, the voltage stored in the sampling capacitor Cspl can be sent to the timing controller 200 through the analog-to-digital converter, and the timing controller 200 can perform external compensation based on the received voltage.

[0062] In other words, the capacitor storing the drive current Idt for external compensation may include the sensing line capacitor Csl, the sensing internal line capacitor Csil, and / or the sampling capacitor Cspl, and the deviation between the sensing line capacitor Csl and the sensing internal line capacitor Csil of multiple sensing lines SL and multiple sensing internal lines SIL can affect the display quality.

[0063] The storage capacitor Cst can store the difference between the data voltage Vdata applied to the gate node N1 of the driving transistor DT and the initial voltage VINIT supplied to the source node N2 of the driving transistor DT through the sensing transistor SST, thereby supplying a constant driving voltage Vgs to the driving transistor DT for a certain period of time, for example, during a frame.

[0064] The first driving voltage ELVDD can be applied to the drain node of the driving transistor DT, and the driving transistor DT can supply the OLED 25 with a driving current Idt proportional to the driving voltage Vgs.

[0065] OLED 25 includes an anode connected to the source node N2 of the driving transistor DT, a cathode to which a second driving voltage ELVSS is applied, and / or an organic emitting layer between the cathode and the anode. The cathode may be a common electrode shared by all or one or more sub-pixels. When a driving current Idt is supplied from the driving transistor DT, OLED 25 can generate light in the organic emitting layer. The intensity of the light may be proportional to the driving current Idt.

[0066] Figure 3 The arrangement of lines in a data driver 100 according to some example embodiments is shown.

[0067] refer to Figure 3 Multiple internal data lines DIL and / or multiple internal sensing lines SIL can be arranged inside the data driver 100, and multiple data link lines DLL and / or multiple sensing link lines SLL connected to the multiple internal data lines DIL and / or multiple internal sensing lines SIL can be connected to multiple data lines DL and multiple sensing lines SL arranged on the display panel 20.

[0068] Multiple data link lines (DLLs) and / or multiple sense link lines (SLLs) can be patterned wiring on a chip-on-film (COF) or printed circuit board (PCB). Multiple data link lines (DLLs) and / or multiple sense link lines (SLLs) can be connected to multiple internal data lines (DILs) and / or multiple internal sense lines (SILs) via multiple data pads (DPs) and / or multiple sense pads (SPs).

[0069] The data driver 100 may include node units ND and / or pad units PAD. It may include multiple node units ND and / or multiple pad units PAD, and the multiple node units ND may be arranged side by side at the center of the data driver 100, and the multiple pad units PAD may be arranged separately at the edges of the data driver 100.

[0070] Multiple driver block nodes and / or multiple sensing nodes may be included in node unit ND, and multiple data pads and / or multiple sensing pads may be included in pad unit PAD. Driver block nodes may be inside and / or outside of driver block 110, and sensing nodes may be inside and / or outside of sensing block 120. Multiple driver block nodes and multiple sensing nodes may be arranged side by side on the same line, but the example embodiment is not limited thereto.

[0071] Multiple sensing internal lines (SILs) can extend from multiple sensing nodes to multiple sensing pads, and multiple data internal lines (DILs) can extend from multiple driver block nodes to multiple data pads. When pad units (PADs) are arranged at the upper and lower edges of the data driver 100, some of the sensing internal lines (SILs) and / or some of the data internal lines (DILs) can extend to the pad unit (PAD) arranged at the upper edge of the data driver 100, and the remaining sensing internal lines (SILs) and / or the remaining data internal lines (DILs) can extend to the pad unit (PAD) arranged at the lower edge of the data driver 100.

[0072] Multiple sensing internal lines (SILs) and / or multiple data internal lines (DILs) can have different lengths and / or line widths. For example, some sensing internal lines (SILs) and some data internal lines (DILs) can be configured to be longer and have a wider line width than other sensing internal lines (SILs) and other data internal lines (DILs).

[0073] When the pad unit PAD is arranged at the upper and lower edges of the data driver 100, some of the sensing link lines SLL and / or some of the data link lines DLL can extend from the pad unit PAD arranged at the upper edge of the data driver 100 to the display panel 20, and the remaining sensing link lines SLL and / or the remaining data link lines DLL can extend from the pad unit PAD arranged at the lower edge of the data driver 100 to the display panel 20.

[0074] Although not shown, when a pad unit PAD is arranged at the upper edge of the data driver 100, multiple sensing internal lines SIL and / or multiple data internal lines DIL can extend to the pad unit PAD arranged at the upper edge of the data driver 100, and multiple sensing link lines SLL and / or multiple data link lines DLL can extend straight from the pad unit PAD arranged at the upper edge of the data driver 100 to the display panel 20.

[0075] Some of the data pads within the pad unit (PAD) can be activated depending on the resolution. For example, in high-resolution mode, all data pads from multiple data pads can be activated, while in low-resolution mode, some data pads from multiple data pads can be activated. High-resolution mode can be referred to as the first mode, and low-resolution mode can be referred to as the second mode.

[0076] In some example embodiments, each or one or more of the plurality of data pads may be a data output pad, and data input pads may be arranged together with the data output pads on the pad unit PAD. For example, data input pads may be arranged at the center of the pad unit PAD arranged on the lower part of the data driver 100, and data output pads may be arranged in the area where no data input pads are arranged.

[0077] Figure 4 The layout of a data drive 100 according to some example embodiments is shown.

[0078] refer to Figure 4 The data driver 100 may include a source amplifier 111, a decoder and shift register 112, a voltage supply unit 121, an analog front-end 122, a digital-to-analog converter 123, an input processing unit 130, etc. The source amplifier 111 and / or the decoder and shift register 112 may be configured as a driver block 110, and the analog front-end 122 and the digital-to-analog converter 123 may be configured as a sensing block 120. The input processing unit 130 may be configured to receive and / or process input data.

[0079] Two node elements ( Figure 3The ND and / or two voltage supply units 121 in the data driver 100 can be arranged horizontally at the center of the data driver 100, and the pad units PAD can be arranged at the edge of the data driver 100.

[0080] A plurality of source amplifiers 111 may be arranged above the voltage supply unit 121 of the data driver 100, and a plurality of decoders and shift registers 112 may be arranged below.

[0081] Analog front-end 122 and / or digital-to-analog converter 123 may be arranged among multiple source amplifiers 111 of data driver 100, and input processing unit 130 may be arranged among multiple decoders and shift registers 112.

[0082] Multiple internal lines (ILs) can be arranged in Figure 3 Between the node unit ND and the pad unit PAD of the data driver 100. Multiple internal lines IL can include Figure 3 Multiple internal data lines DIL and Figure 3 Multiple sensing internal lines SIL in the middle.

[0083] Region A can indicate the area including the first channel, Region B can indicate the area including the last channel, Region C can indicate the area including the relatively long internal line IL, and Region D can indicate the area including the intermediate channel. References will be made below. Figure 5A to Figure 8B The arrangement of the sensing internal lines and data internal lines in each region according to some example embodiments will be described in detail, but only the node unit ND and the pad unit PAD will be described.

[0084] Figure 5A and Figure 5B The arrangement of the sensing internal line (SIL) and the data internal line (DIL) in region A according to some example embodiments is shown.

[0085] refer to Figure 5A and Figure 5B , Figure 5B The line layout is Figure 5A The line arrangement in region A is the area extending from the right-hand node cell ND located at the center of the data drive 100 to the pad cell PAD located at the lower edge of the data drive 100. That is, Figure 5B The line arrangement shows the first line arrangement of the right-side node element ND.

[0086] According to some example embodiments, a node unit ND refers to an area where a plurality of drive block nodes DN included in drive block 110 and a plurality of sensing nodes SN included in sensing block 120 are arranged.

[0087] According to some example embodiments, three drive block nodes (DNs) and one sensing node (SN) can be arranged sequentially and repeatedly in a node cell (ND), and three data pads (DPs) and one sensing pad (SP) can be arranged sequentially and repeatedly in a pad cell (PAD). In other words, two or more drive block nodes (DNs) can be arranged between two sensing nodes (SNs), and two or more data pads (DPs) can be arranged between two sensing pads (SPs). The three drive block nodes (DNs) and one sensing node (SN) can have the same arrangement order as their corresponding three data pads (DPs) and one sensing pad (SP). In the form of repeated arrangement of three data pads (DPs) and one sensing pad (SP), four channels can be referred to as one cell.

[0088] The three data pads DP can be data pads DP connected to the data line DL connected to the R subpixel, the data line DL connected to the G subpixel, and / or the data line DL connected to the B subpixel.

[0089] A sensing pad SP can be a sensing pad SP connected to a sensing line SL, which is connected to an R sub-pixel, a G sub-pixel, and / or a B sub-pixel.

[0090] Although not shown, according to some example embodiments, four drive block nodes DN and one sensing node SN can be arranged sequentially and repeatedly in node cell ND, and four data pads DP and one sensing pad SP can be arranged sequentially and repeatedly in pad cell PAD. The four drive block nodes DN and one sensing node SN can have the same arrangement order as their corresponding four data pads DP and one sensing pad SP. In the form of repeated arrangement of four data pads DP and one sensing pad SP, five channels can be referred to as one cell.

[0091] The four data pads DP can be data pads DP connected to the data line DL connected to the R subpixel, the data line DL connected to the G subpixel, the data line DL connected to the B subpixel, and / or the data line DL connected to the W subpixel.

[0092] A sensing pad SP can be a sensing pad SP connected to a sensing line SL, which is connected to an R sub-pixel, a G sub-pixel, a B sub-pixel, and / or a W sub-pixel.

[0093] For example, in region A, the first driving block nodes DN1 to the third driving block nodes DN3, the first sensing node SN1, the fourth driving block nodes DN4 to the sixth driving block nodes DN6 and / or the second sensing node SN2 can be arranged sequentially in the node unit ND, and the first data pads DP1 to the third data pads DP3, the first sensing pads SP1, the fourth data pads DP4 to the sixth data pads DP6 and / or the second sensing pads SP2 can be arranged sequentially on the pad unit PAD.

[0094] According to some example embodiments, each or one or more of the multiple sensing internal lines SILs includes a line portion arranged between at least one data internal line DIL and one sensing internal line SIL. In a certain region, the three drive block nodes DN and one sensing node SN may have a different arrangement order than their corresponding three data internal lines DIL and one sensing internal line SIL. The data internal lines DIL and sensing internal lines SIL may have the same linewidth.

[0095] For example, in region A, in the area between node unit ND and pad unit PAD, the first internal data lines DIL1 to the third internal data lines DIL3, the first internal sensing line SIL1, the fourth internal data lines DIL4 to the sixth internal data lines DIL6, and / or the 2-1 sensing internal line portion SIL2-1 of the second internal sensing line SIL2 can be arranged sequentially. Furthermore, the 2-3 sensing internal line portion SIL2-3 of the first internal data lines DIL1 to the third internal data lines DIL3, the first internal sensing line SIL1, and the second internal sensing line SIL2, and / or the fourth internal data lines DIL4 to the sixth internal data lines DIL6, can be arranged sequentially. The 2-1 sensing internal line portion SIL2-1 can indicate the portion connected to the second sensing node SN2 and the portion connected to the second sensing pad SP2, and the 2-3 sensing internal line portion SIL2-3 can indicate the portion adjacent to the first internal sensing line SIL1.

[0096] In other words, the second sensing internal line SIL2 may include 2-1 sensing internal line portions SIL2-1 and 2-3 sensing internal line portions SIL2-3, which are separated from the fourth data internal lines DIL4 to the sixth data internal lines DIL6 adjacent to the second sensing internal line SIL2.

[0097] According to some example embodiments, the first distance between the third data internal line DIL3 and the first sensing internal line SIL1, the second distance between the first sensing internal line SIL1 and the second sensing internal line SIL2-3 (sensing internal line portion 2-3) of the second sensing internal line SIL2, and / or the third distance between the second sensing internal line SIL2-3 (sensing internal line portion 2-3) of the second sensing internal line SIL2 and the fourth data internal line DIL4 may be the same, but are not limited thereto.

[0098] The 2-1 sensing internal line portions SIL2-1 and 2-3 sensing internal line portions SIL2-3 can be connected to each other via the 2-2 sensing internal line portion SIL2-2 of the second sensing internal line SIL2. The number of 2-1 sensing internal line portions SIL2-1 can be the same as the number of 2-2 sensing internal line portions SIL2-2. The 2-2 sensing internal line portions SIL2-2 can be located in different layers to overlap with the fourth to sixth data internal lines DIL4 to DIL6 adjacent to the second sensing internal line SIL2.

[0099] For example, the 2-1 sensing internal line portion SIL2-1 and the 2-3 sensing internal line portion SIL2-3 can be disposed in the same layer as the fourth data internal line DIL4 to the sixth data internal line DIL6, and the 2-2 sensing internal line portion SIL2-2 can be disposed in a different layer than the fourth data internal line DIL4 to the sixth data internal line DIL6. The 2-2 sensing internal line portion SIL2-2, the 2-1 sensing internal line portion SIL2-1, and / or the 2-3 sensing internal line portion SIL2-3 can be electrically connected to each other via contact CNT.

[0100] In other words, the second sensing internal line SIL2 may include a 2-2 sensing internal line portion SIL2-2 that intersects with the fourth data internal line DIL4 to the sixth data internal line DIL6 adjacent to the second sensing internal line SIL2.

[0101] The first sensing internal line SIL1, which is adjacent to the 2-3 sensing internal line portion SIL2-3 of the second sensing internal line SIL2, can be arranged separately from the first data internal lines DIL1 to the third data internal line DIL3 and the second sensing internal line SIL2, which are adjacent to the first sensing internal line SIL1.

[0102] According to some example embodiments, the length of the 2-3 sensing internal line portion SIL2-3 can be longer than the sum of the lengths of the two 2-1 sensing internal line portions SIL2-1.

[0103] According to some example embodiments, the first sensing internal line SIL1 can be arranged between the first data internal line DIL1 to the third data internal line DIL3 and the second sensing internal line SIL2's 2-3 sensing internal line portion SIL2-3, and the second sensing internal line SIL2's 2-3 sensing internal line portion SIL2-3 can be arranged between the first sensing internal line SIL1 and the fourth data internal line DIL4 to the sixth data internal line DIL6.

[0104] In other words, the 2-3 sensing internal line portions SIL2-3 of the first sensing internal line SIL1 and the second sensing internal line SIL2 are arranged between the sensing internal line SIL and the data internal line DIL. The sensing internal line SIL is a line to which a signal with the same phase is applied, and the data internal line DIL is a line to which a signal with a different phase is applied. As a result, since the amplitude of the coupling capacitance caused by the adjacent lines of the first sensing internal line SIL1 and the second sensing internal line SIL2 is similar, the line capacitance of the first sensing internal line SIL1 and the second sensing internal line SIL2 can be reduced compared to when the first sensing internal line SIL1 and the second sensing internal line SIL2 are arranged between the data internal line DIL.

[0105] As a result, the quality of electrical characteristic measurements of multiple sub-pixels SPX can be improved while maintaining the arrangement order of the driving block node DN and the sensing node SN, as well as the arrangement order of the data pad DP and the sensing pad SP.

[0106] In the following text, we will focus on... Figure 5A and Figure 5B Detailed description of different configurations Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A and Figure 9B And will omit or briefly describe with Figure 5A and Figure 5B The configuration is the same as the previous one.

[0107] Figure 6A and Figure 6B The arrangement of the sensing internal line (SIL) and the data internal line (DIL) in region B according to some example embodiments is shown.

[0108] refer to Figure 6A and Figure 6B , Figure 6B The line layout is Figure 6A The line arrangement in region B, that is, the region extending from the left node cell ND located at the center of the data driver 100 to the pad cell PAD located at the lower edge of the data driver 100. In other words, Figure 6B The line arrangement shows the final line arrangement of the left node element ND.

[0109] For example, in region B, driver block nodes DN955 to DN957 (955th to 957th), sensing node SN319 (319th), driver block nodes DN958 to DN960 (958th to 960th), and / or sensing node SN320 (320th) can be sequentially arranged in node cell ND, and data pads DP955 to DP957 (955th to 957th), sensing pad SP319 (319th), data pads DP958 to DP960 (958th to 960th), and / or sensing pad SP320 (320th) can be sequentially arranged on pad cell PAD. Sensing node SN320 may correspond to the last node of the left node cell ND, and data node DN and / or sensing node SN may not be arranged to the right of sensing node SN320. The 320th sensing pad SP320 may correspond to the last pad corresponding to the left node unit ND, and the data pad DP and / or sensing pad SP may no longer be arranged to the right of the 320th sensing pad SP320.

[0110] In region B, in the area between node unit ND and pad unit PAD, the following internal data lines can be arranged sequentially: DIL955 to DIL957 (data internal lines 955 to 957), SIL319 (sensor internal line 319), DIL958 to DIL960 (data internal lines 958 to 960), and / or the 320-1 sensing internal line portion SIL320-1 of SIL320 (sensor internal line 320). Furthermore, the following internal data lines can be arranged sequentially: DIL955 to DIL957 (data internal lines 955 to 957), SIL958 to DIL960 (sensor internal lines 958 to 960), and / or the 320-1 sensing internal line portion SIL320-1 of SIL320 (sensor internal line 320-1). 19. Sensing internal line SIL319, 320-3 (sensing internal line portion SIL320-3) of 320 (sensing internal line SIL320), and / or 958 (data internal line DIL958) to 960 (data internal line DIL960). 320-1 (sensing internal line portion SIL320-1) may indicate the portion connected to 320 (sensing node SN320) and the portion connected to 320 (sensing pad SP320), and 320-3 (sensing internal line portion SIL320-3) may indicate the portion adjacent to 319 (sensing internal line SIL319). 320 (sensing internal line SIL320) may correspond to the last line corresponding to the left node cell ND, and the data internal line DIL and sensing internal line SIL may no longer be arranged to the right of 320 (sensing internal line SIL320).

[0111] According to some example embodiments, the 319th sensing internal line SIL319 may be arranged between the 955th data internal line DIL955 to the 957th data internal line DIL957 and the 320-3 sensing internal line portion SIL320-3 of the 320th sensing internal line SIL320, and the 320-3 sensing internal line portion SIL320-3 of the 320th sensing internal line SIL320 may be arranged between the 319th sensing internal line SIL319 and the 958th data internal line DIL958 to the 960th data internal line DIL960.

[0112] In other words, the 320-3 sensing internal line portion SIL320-3 of the 319th sensing internal line SIL319 and the 320th sensing internal line SIL320 can be arranged between the sensing internal line SIL and the data internal line DIL. The sensing internal line SIL is the line to which a signal with the same phase is applied, and the data internal line DIL is the line to which a signal with a different phase is applied. As a result, since the amplitudes of the coupling capacitance caused by the adjacent lines of the 319th sensing internal line SIL319 and the 320th sensing internal line SIL320 are similar, the deviation of the line capacitance of the 319th sensing internal line SIL319 and the 320th sensing internal line SIL320 can be reduced compared to when the 319th sensing internal line SIL319 is arranged between the data internal lines DIL and the data internal lines DIL are arranged only on one side of the 320th sensing internal line SIL320.

[0113] Figure 7A and Figure 7B The arrangement of the sensing internal line (SIL) and the data internal line (DIL) in region C according to some example embodiments is shown.

[0114] refer to Figure 7A and Figure 7B , Figure 7B The line arrangement shows Figure 7A The line arrangement of region C, that is, the region extending from the right node cell ND located at the center of the data drive 100 to the center of the pad cell PAD located at the upper edge of the data drive 100.

[0115] For example, in region C, the 160th sensing node SN160, the 480th driving block nodes DN480 to 478th driving block nodes DN478, the 159th sensing node SN159 and / or the 477th driving block nodes DN477 to 475th driving block nodes DN475 can be sequentially arranged in node unit ND, and the 160th sensing pad SP160, the 480th data pad DP480 to 478th data pad DP478, the 159th sensing pad SP159 and / or the 477th data pad DP477 to 475th data pad DP475 can be sequentially arranged on pad unit PAD.

[0116] In region C, in the area between node unit ND and pad unit PAD, the 160-1 sensing internal line portion SIL160-1 of the 160th sensing internal line SIL160, the 480th data internal lines DIL480 to DIL478 of the 470th data internal lines, the 159th sensing internal line SIL159 and / or the 477th data internal lines DIL477 to DIL475 of the 475th data internal lines can be arranged sequentially. Furthermore, the 480th data internal line DIL480 to DIL478 of the 478th data internal lines, the 160-1th data internal line portion SIL160-1, the 480th data internal lines DIL480 to DIL478 of the 478th data internal lines, and the 160-1th data internal line portion SIL160-1 of the 160th sensing internal line SIL160, the 480th data internal lines DIL480 to DIL478 of the 470th data internal lines, and the 160-1th data internal line portion SIL160-1 of the 160th sensing internal line SIL160, the 480th data internal lines DIL480 to DIL478 of the 470th data internal lines, and the 160-1th data internal line portion SIL160-1 of the 478th data internal line ... The 160-3 sensing internal line portion SIL160-3 of the 60 sensing internal line SIL160, the 159th sensing internal line SIL159, and / or the 477th to 475th data internal lines DIL477 to DIL475. The 160-1 sensing internal line portion SIL160-1 can indicate the portion connected to the 160th sensing node SN160 and the portion connected to the 160th sensing pad SP160, and the 160-3 sensing internal line portion SIL160-3 can indicate the portion adjacent to the 159th sensing internal line SIL159.

[0117] According to some example embodiments, the 160-3 sensing internal line portion SIL160-3 of the 160th sensing internal line SIL160 can be arranged between the 480th data internal line DIL480 to the 478th data internal line DIL478 and the 159th sensing internal line SIL159, and the 159th sensing internal line SIL159 can be arranged between the 160-3 sensing internal line portion SIL160-3 of the 160th sensing internal line SIL160 and the 477th data internal line DIL477 to the 475th data internal line DIL475.

[0118] The sensing line SL arranged in region C can be formed to be longer than the sensing line SL arranged in another region, and can have a wider linewidth than the sensing line SL arranged in another region to reduce resistance. Therefore, the line capacitance of the sensing line SL arranged in region C can be greater than the line capacitance of the sensing line SL arranged in another region.

[0119] According to some example embodiments, the 160-3 sensing internal line portions SIL160-3 of the 159th sensing internal line SIL159 and the 160th sensing internal line SIL160 can be arranged between the sensing internal line SIL and the data internal line DIL, where the sensing internal line SIL is the line to which a signal of the same phase is applied and the data internal line DIL is the line to which a signal of a different phase is applied. As a result, the amplitude of the coupling capacitance caused by the adjacent lines of the 159th sensing internal line SIL159 and the 160th sensing internal line SIL160 is reduced, and the deviation of the line capacitance of other sensing internal lines SIL can be reduced.

[0120] Figure 8A and Figure 8B The arrangement of the sensing internal line SIL and the data internal line DIL in region D according to some example embodiments is shown.

[0121] refer to Figure 8A and Figure 8B , Figure 8B The line arrangement shows Figure 8A The line arrangement of region D, that is, the region extending from the left node unit ND located at the center of the data driver 100 to the pad unit PAD located at the lower edge of the data driver 100.

[0122] For example, in region D, the 715th driver block node DN715 to the 717th driver block node DN717, the 239th sensing node SN239, the 718th driver block node DN718 to the 720th driver block node DN720, the 240th sensing node SN240 and / or the 721st driver block node DN721 to the 722nd driver block node DN722 can be sequentially arranged in node unit ND, and the 715th data pad DP715 to the 717th data pad DP717, the 239th sensing pad SP239, the 718th data pad DP718 to the 720th data pad DP720, the 240th sensing pad SP240 and / or the 721st data pad DP721 to the 722nd data pad DP722 can be sequentially arranged on pad unit PAD.

[0123] In region D, in the area between node unit ND and pad unit PAD, internal data lines DIL715 to DIL717 (715th data line), SIL239 (239th sensing line), DIL718 to DIL720 (718th data line), SIL240-1 (240-1 sensing line portion SIL240-1) of SIL240 (240th sensing line), and / or DIL721 to DIL722 (721st data line) can be arranged sequentially. Furthermore, internal data lines DIL715 to DIL722 can be arranged sequentially. 17 Data internal line DIL717, 239 Sensing internal line SIL239, 240 Sensing internal line SIL240, 240 Sensing internal line SIL240, and / or 718 Data internal lines DIL718 to 722 Data internal lines DIL722. 240-1 Sensing internal line portion SIL240-1 may indicate the portion connected to the 240 Sensing node SN240 and the portion connected to the 240 Sensing pad SP240, and 240-3 Sensing internal line portion SIL240-3 may indicate the portion adjacent to the 239 Sensing internal line SIL239.

[0124] According to some example embodiments, the 239th sensing internal line SIL239 may be arranged between the 715th data internal line DIL715 to the 717th data internal line DIL717 and the 240-3th sensing internal line portion SIL240-3 of the 240th sensing internal line SIL240, and the 240-3th sensing internal line portion SIL240-3 of the 240th sensing internal line SIL240 may be arranged between the 239th sensing internal line SIL239 and the 718th data internal line DIL718 to the 722nd data internal line DIL722.

[0125] Here, for example, according to some exemplary embodiments, data pads 721 to 722 can be activated in low-resolution mode. Therefore, data signals can be floated and not applied to internal data lines 721 to 722.

[0126] Therefore, in terms of signal application, the 240th sensing internal line SIL240 can correspond to the last line corresponding to the left node unit ND, and the 240-3 sensing internal line portion SIL240-3 of the 240th sensing internal line SIL240 can be arranged between the 239th sensing internal line SIL239 and the 718th data internal line DIL718 to the 720th data internal line DIL720.

[0127] According to some example embodiments, the 240-3 sensing internal line portion SIL240-3 of the 240th sensing internal line SIL240 can be adjacent to the 239th sensing internal line SIL239, and therefore, regardless of whether a data signal is applied to the data internal line DIL adjacent to the sensing internal line SIL, the deviation of the line capacitance of the 239th sensing internal line SIL239 and the 240th sensing internal line SIL240 can be reduced (e.g., constantly reduced).

[0128] Figure 9A and Figure 9B The arrangement of the sensing internal line (SIL) and the data internal line (DIL) in region A according to some example embodiments is shown.

[0129] Figure 9A and Figure 9B The line arrangement shows Figure 5A The line arrangement of region A, that is, the region extending from the right node cell ND located at the center of the data driver 100 to the pad cell PAD located at the lower edge of the data driver 100.

[0130] According to some example embodiments, the arrangement order of multiple driver block nodes DN and multiple sensor nodes SN in region A may differ from the arrangement order of multiple data pads DP and multiple sensor pads corresponding to the multiple driver block nodes DN and multiple sensor nodes SN. This can be applied to Figure 9A and Figure 9B as well as Figure 5A and Figure 5B , Figure 6A and Figure 6B , Figure 7A and Figure 7B as well as Figure 8A and Figure 8B The regions are A to D, but the example embodiment is not limited to this.

[0131] refer to Figure 9A For example, multiple drive block nodes DN can be arranged between the first sensing node SN1 and the second sensing node SN2, and the first sensing pad SP1 and the second sensing pad SP2 corresponding to the first sensing node SN1 and the second sensing node SN2 respectively can be adjacent to each other.

[0132] For example, in region A, the first driving block nodes DN1 to the third driving block nodes DN3, the first sensing node SN1, the fourth driving block nodes DN4 to the sixth driving block nodes DN6 and / or the second sensing node SN2 can be arranged sequentially in the node unit ND, and the first data pads DP1 to the third data pads DP3, the first sensing pads SP1, the second sensing pads SP2 and / or the fourth data pads DP4 to the sixth data pads DP6 can be arranged sequentially on the pad unit PAD.

[0133] For example, in region A, in the area between node unit ND and pad unit PAD, the first internal data lines DIL1 to the third internal data lines DIL3, the first internal sensing line SIL1, the fourth internal data lines DIL4 to the sixth internal data lines DIL6, and / or the 2-1 sensing internal line portion SIL2-1 of the second internal sensing line SIL2 can be arranged sequentially. Furthermore, the 2-3 sensing internal line portion SIL2-3 of the first internal data lines DIL1 to the third internal data lines DIL3, the first internal sensing line SIL1, and the second internal sensing line SIL2, and / or the fourth internal data lines DIL4 to the sixth internal data lines DIL6, can be arranged sequentially. The 2-1 sensing internal line portion SIL2-1 can indicate the portion connected to the second sensing node SN2, and the 2-3 sensing internal line portion SIL2-3 can indicate the portion connected to the second sensing pad SP2 and adjacent to the first internal sensing line SIL1.

[0134] In other words, the second sensing internal line SIL2 may include 2-1 sensing internal line portions SIL2-1 and / or 2-3 sensing internal line portions SIL2-3, which are separated from the adjacent fourth data internal lines DIL4 to sixth data internal lines DIL6.

[0135] The 2-1 sensing internal line portion SIL2-1 and the 2-3 sensing internal line portion SIL2-3 can be connected to each other via the 2-2 sensing internal line portion SIL2-2 of the second sensing internal line SIL2. When only one 2-1 sensing internal line portion SIL2-1 exists, only one 2-2 sensing internal line portion SIL2-2 can exist. The 2-2 sensing internal line portion SIL2-2 can overlap with the fourth data internal line DIL4 to the sixth data internal line DIL6.

[0136] In other words, the second sensing internal line SIL2 may include a 2-2 sensing internal line portion SIL2-2 that intersects with the adjacent fourth data internal lines DIL4 to sixth data internal lines DIL6.

[0137] The first sensing internal line SIL1 can be arranged separately from the adjacent first data internal lines DIL1 to third data internal lines DIL3 and the second sensing internal line SIL2.

[0138] According to some example embodiments, the length of the 2-3 sensing internal line portion SIL2-3 can be longer than the length of the 2-1 sensing internal line portion SIL2-1.

[0139] According to some example embodiments, the first sensing internal line SIL1 may be arranged between the first data internal line DIL1 to the third data internal line DIL3 and the second sensing internal line SIL2's 2-3 sensing internal line portion SIL2-3, and / or the second sensing internal line SIL2's 2-3 sensing internal line portion SIL2-3 may be arranged between the first sensing internal line SIL1 and the fourth data internal line DIL4 to the sixth data internal line DIL6.

[0140] In other words, the 2-3 sensing internal line portions SIL2-3 of the first sensing internal line SIL1 and the second sensing internal line SIL2 can be arranged between the sensing internal line SIL and the data internal line DIL. The sensing internal line SIL is the line to which a signal with the same phase is applied, and the data internal line DIL is the line to which a signal with a different phase is applied. As a result, since the amplitude of the coupling capacitance caused by the adjacent lines of the first sensing internal line SIL1 and the second sensing internal line SIL2 is similar, and / or compared with when the first sensing internal line SIL1 and the second sensing internal line SIL2 are arranged between the data internal line DIL, the deviation of the line capacitance of the first sensing internal line SIL1 and the second sensing internal line SIL2 can be reduced.

[0141] refer to Figure 9B For example, the first sensing node SN1 and the second sensing node SN2 can be adjacent to each other, and multiple driving pads DP can be arranged between the first sensing pad SP1 and the second sensing pad SP2 corresponding to the first sensing node SN1 and the second sensing node SN2.

[0142] For example, in region A, the first driving block nodes DN1 to the third driving block nodes DN3, the first sensing node SN1, the second sensing node SN2 and / or the fourth driving block nodes DN4 to the sixth driving block nodes DN6 can be arranged sequentially in the node unit ND, and the first data pads DP1 to the third data pads DP3, the first sensing pads SP1, the fourth data pads DP4 to the sixth data pads DP6 and / or the second sensing pads SP2 can be arranged sequentially on the pad unit PAD.

[0143] For example, in region A, in the area between node unit ND and pad unit PAD, the first internal data lines DIL1 to the third internal data lines DIL3, the first internal sensing line SIL1, the 2-1 sensing internal line portion SIL2-1 of the second internal sensing line SIL2, and / or the fourth internal data lines DIL4 to the sixth internal data lines DIL6 can be arranged sequentially. The 2-1 sensing internal line portion SIL2-1 can indicate the portion connected to the second sensing node SN2 and adjacent to the first internal sensing line SIL1, and the 2-3 sensing internal line portion SIL2-3 can indicate the portion connected to the second sensing pad SP2.

[0144] In other words, the second sensing internal line SIL2 may include the 2-1 sensing internal line portion SIL2-1 and the 2-3 sensing internal line portion SIL2-3, which are separated from the adjacent fourth data internal lines DIL4 to sixth data internal lines DIL6.

[0145] The 2-1 sensing internal line portion SIL2-1 and the 2-3 sensing internal line portion SIL2-3 can be connected to each other via the 2-2 sensing internal line portion SIL2-2 of the second sensing internal line SIL2. When only one 2-1 sensing internal line portion SIL2-1 exists, only one 2-2 sensing internal line portion SIL2-2 can exist. The 2-2 sensing internal line portion SIL2-2 can overlap with the fourth data internal line DIL4 to the sixth data internal line DIL6.

[0146] In other words, the second sensing internal line SIL2 may include a 2-2 sensing internal line portion SIL2-2 that intersects with the adjacent fourth data internal lines DIL4 to sixth data internal lines DIL6.

[0147] The first sensing internal line SIL1 can be arranged separately from the adjacent first data internal lines DIL1 to third data internal lines DIL3 and the second sensing internal line SIL2.

[0148] According to some example embodiments, the length of the 2-1 sensing internal line portion SIL2-1 can be longer than the length of the 2-3 sensing internal line portion SIL2-3.

[0149] According to some example embodiments, the first sensing internal line SIL1 may be arranged between the first data internal line DIL1 to the third data internal line DIL3 and the 2-1 sensing internal line portion SIL2-1 of the second sensing internal line SIL2, and the 2-1 sensing internal line portion SIL2-1 of the second sensing internal line SIL2 may be arranged between the first sensing internal line SIL1 and the fourth data internal line DIL4 to the sixth data internal line DIL6.

[0150] In other words, the 2-1 sensing internal line portions SIL2-1 of the first sensing internal line SIL1 and the second sensing internal line SIL2 can be arranged between the sensing internal line SIL and the data internal line DIL. The sensing internal line SIL is the line to which a signal with the same phase is applied, and the data internal line DIL is the line to which a signal with a different phase is applied. As a result, since the amplitude of the coupling capacitance caused by the adjacent lines of the first sensing internal line SIL1 and the second sensing internal line SIL2 is similar, the deviation of the line capacitance of the first sensing internal line SIL1 and the second sensing internal line SIL2 can be reduced compared to when the first sensing internal line SIL1 and the second sensing internal line SIL2 are arranged between the data internal line DIL. According to some example embodiments, even when the arrangement order of the driving block node DN and the sensing node SN is partially different from the arrangement order of the data pad DP and the sensing pad SP, the quality of electrical characteristic measurements of multiple sub-pixels SPX can be improved.

[0151] Figure 10 The arrangement of lines on a display panel 20 according to some example embodiments is shown.

[0152] When the arrangement order of the data pads DP and sensing pads SP of the pad unit PAD is... Figure 9A When the arrangement order is the same, it can be applied. Figure 10 .

[0153] refer to Figure 10 Multiple data pads DP and multiple sensing pads SP of the pad unit PAD connected to the data driver 100, along with multiple data lines DL and multiple sensing lines SP, can extend between the sub-pixels SPX of the display panel 20.

[0154] According to some example embodiments, the first data line DL1 to the sixth data line DL6 may extend to one side of the first sub-pixel column to the sixth sub-pixel column, and the first sensing line SL1 and the second sensing line SL2 may extend adjacent to each other between the first pixel column and the second pixel column.

[0155] The first pixel column may include eleventh R, G and B sub-pixels R11, G11 and B11, and the second pixel column may include twelfth R, G and B sub-pixels R12, G12 and B12.

[0156] According to some example embodiments, two sensing lines SL are adjacent to each other and extend to the display panel 20, and therefore, the deviation of the line capacitance of the sensing lines SL can be reduced compared to when the sensing lines SL extend adjacent to the data lines DL.

[0157] Figure 11 An implementation example of a display device 1000 according to some example embodiments is shown. Figure 11 The display device 1000 is a device that includes a medium and / or large-size display panel 1200 and can be applied to devices such as televisions and monitors.

[0158] refer to Figure 11 The display device 1000 may include a data driver 1110, a timing controller 1120, a gate driver 1130, and / or a display panel 1200.

[0159] The timing controller TCON IC 1120 can be configured as one or more ICs or modules. The timing controller TCON IC 1120 can communicate with multiple data driver ICs (DDICs) and multiple gate driver ICs (GDICs) via a configuration interface.

[0160] The timing controller TCON IC 1120 can generate control signals for controlling the drive timing of multiple data driver ICs (DDICs) and / or multiple gate driver ICs (GDICs), and can provide the control signals to the multiple data driver ICs (DDICs) and / or multiple gate driver ICs (GDICs).

[0161] The timing controller TCON IC 1120 can divide the image data received from the outside and provide multiple divided image data to multiple data driver ICs (DDICs). Furthermore, the timing controller TCON IC 1120 can detect the electrical characteristics of sub-pixels based on reference sensing values ​​received from the data driver 1110 and determine compensation values ​​for data compensation. The timing controller TCON IC 1120 can perform data compensation on the received image data.

[0162] Data driver 1110 may include multiple data driver ICs DDIC, and the multiple data driver ICs DDIC may be mounted on a circuit film such as tape-on package (TCP), COF and / or flexible printed circuit (FPC) and attached to display panel 1200 by tape auto-bonding (TAB) method, and / or mounted on non-display area of ​​display panel 1200 by chip-on-glass (COG) method.

[0163] According to some example embodiments, each or one or more of the multiple sensing internal lines SILs included in the data driver 1110 includes a line portion arranged between at least one data internal line DIL and one sensing internal line SIL, and therefore, regardless of the line arrangement position and resolution, the deviation of the line capacitance of the multiple sensing internal lines SILs can be reduced, and as a result, the quality of electrical characteristic measurements of the multiple sub-pixels SPX can be improved.

[0164] The gate driver 1130 may include a plurality of gate driver ICs (GDICs), which may be mounted on a circuit film and attached to the display panel 1200 using a TAB method, and / or mounted on a non-display area of ​​the display panel 1200 using a COG method. Alternatively, the gate driver 1130 may be directly formed on the lower substrate of the display panel 1200 using a gate in-panel (GIP) method. The gate driver 1130 may be formed in a non-display area of ​​the display panel 1200 outside the pixel array in which sub-pixels are formed, and may be formed using the same TFT process as the sub-pixels.

[0165] Figure 12 An implementation example of a display device 2000 according to some example embodiments is shown. Figure 12 The display device 2000 is a device that includes a small-sized display panel 2200 and can be applied to, for example, mobile devices such as smartphones and / or tablet PCs.

[0166] refer to Figure 12 The display device 2000 may include a display driving circuit 2100 and / or a display panel 2200. The display driving circuit 2100 may include one or more ICs, which are mounted on the circuit film of TCP, COF and / or FPC, attached to the display panel 2200 by a TAB method, and / or mounted on the non-display area of ​​the display panel 2200 by a COG method.

[0167] The display driving circuit 2100 may include a data driver 2110 and / or a timing controller 2120, and may also include a gate driver. In some example embodiments, the gate driver may be mounted on the display panel 2200.

[0168] refer to Figure 1The described data driver 100 can be applied as data driver 2110. Data driver 2110 can measure the electrical characteristics of sub-pixels of display panel 2200 in sensing mode and provide the measured electrical characteristics of the sub-pixels to timing controller 2120. Timing controller 2120 can compensate image data based on the detected electrical characteristics of the sub-pixels. Timing controller 2120 can provide the compensated image data to data driver 2110, and data driver 2110 can drive display panel 2200 based on the compensated image data.

[0169] As the display panel 2200 of the display device 2000 is miniaturized, the line capacitance of the sensing line SL decreases, and the line capacitance of the sensing internal line SIL may have a relatively greater impact on the quality of electrical characteristic measurements of multiple sub-pixels SPX. According to some example embodiments, each or one or more of the multiple sensing internal lines SIL included in the data driver 2110 includes a line portion arranged between at least one data internal line DIL and one sensing internal line SIL. Therefore, regardless of the line arrangement position and resolution, the deviation of the line capacitance of the multiple sensing internal lines SIL can be reduced, and as a result, the quality of electrical characteristic measurements of the multiple sub-pixels can be improved.

[0170] One or more of the elements disclosed above may include or be implemented in one or more processing circuits, such as hardware including logic circuits; hardware / software combinations, such as a processor executing software; or combinations thereof. For example, the processing circuits may more specifically include, but are not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0171] While the inventive concept has been shown and described with reference to some exemplary embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A data driver configured to drive a display panel including a plurality of data lines, a plurality of sense lines, and a plurality of subpixels connected to the plurality of data lines and the plurality of sense lines, the data driver comprising: a driving block configured to provide a data signal to each of the plurality of subpixels; a sensing block configured to measure an electrical characteristic of each of the plurality of subpixels; a plurality of data internal lines configured to connect a plurality of driving block nodes included in the driving block to a plurality of data pads connected to the plurality of data lines; and a plurality of sense internal lines configured to connect a plurality of sense nodes included in the sensing block to a plurality of sense pads connected to the plurality of sense lines, wherein each of the plurality of sense internal lines includes a line portion between at least one data internal line and one sense internal line.

2. The data driver of claim 1, wherein, a first sense internal line of the plurality of sense internal lines includes a first line portion and a second line portion, the first line portion is separated from at least one data internal line adjacent to the first sense internal line, and the second line portion crosses the at least one data internal line adjacent to the first sense internal line.

3. The data driver of claim 2, wherein, The at least one data internal line adjacent to the first sense internal line and the second line portion are located on different layers.

4. The data driver of claim 3, wherein the at least one data internal line adjacent to the first sense internal line and the first line portion are provided on a same layer, and the first line portion and the second line portion are electrically connected to each other by a contact.

5. The data driver of claim 2, wherein, a second sense internal line of the plurality of sense internal lines adjacent to the first sense internal line is arranged separately from at least one data internal line adjacent to the second sense internal line.

6. The data driver of claim 5, wherein, The first sense internal line and the second sense internal line are spaced apart.

7. The data driver according to claim 2, wherein, A number of the second line portions is one or more.

8. The data driver of claim 2, wherein, A number of the second line portions is two or more.

9. The data driver of claim 2, wherein two or more driving block nodes are arranged between a first sense node connected to the first sense internal line and a second sense node connected to a second sense internal line of the plurality of sense internal lines adjacent to the first sense internal line, and two or more data pads are located between a first sense pad connected to the first sense internal line and a second sense pad connected to the second sense internal line.

10. The data driver of claim 9, wherein at least three driving block nodes are located between the first sense node and the second sense node, at least three data pads are located between the first sense pad and the second sense pad, and the at least three data pads are respectively connected to a data line connected to a red subpixel, a data line connected to a green subpixel, and a data line connected to a blue subpixel.

11. The data driver of claim 2, wherein an order of the plurality of driving block nodes and the plurality of sense nodes is the same as, and is different from, an order of the plurality of data pads and the plurality of sense pads respectively corresponding to the plurality of drive block nodes and the plurality of sense nodes. 12.The data driver of claim 2, wherein two or more drive block nodes are located between a first sense node connected to the first sense internal line and a second sense node connected to a second sense internal line of the plurality of sense internal lines adjacent to the first sense internal line, and a first sense pad connected to the first sense internal line and a second sense pad connected to the second sense internal line are adjacent to each other. 13.The data driver of claim 2, wherein an order of the plurality of drive block nodes and the plurality of sense nodes is different from an order of the plurality of data pads and the plurality of sense pads respectively corresponding to the plurality of drive block nodes and the plurality of sense nodes.

14. The data driver of claim 1, wherein, each of the plurality of sense nodes is connected to a first switch configured to transfer an initialization voltage and a second switch configured to transfer a low potential voltage.

15. The data driver of claim 1, wherein, a line width of each of the plurality of data internal lines is the same as a line width of each of the plurality of sense internal lines.

16. The data driver of claim 1, wherein, two sense lines of the plurality of sense lines are adjacent to an area between two columns of sub-pixels of the display panel. 17.The data driver of claim 1, wherein at least one data pad of the plurality of data pads is activated in a first mode and is deactivated in a second mode, and the first mode and the second mode have different resolutions. 18.A data driver configured to drive a display panel, the display panel including a plurality of data lines, a plurality of sense lines, and a plurality of sub-pixels connected to the plurality of data lines and the plurality of sense lines, the data driver comprising: a drive block configured to provide a data signal to each of the plurality of sub-pixels; a sense block configured to measure an electrical characteristic of each of the plurality of sub-pixels; a plurality of data internal lines configured to connect a plurality of drive block nodes included in the drive block to a plurality of data pads connected to the plurality of data lines; and a plurality of sense internal lines configured to connect a plurality of sense nodes included in the sense block to a plurality of sense pads connected to the plurality of sense lines, wherein two of the plurality of sense internal lines are located between the plurality of data internal lines.

19. The data driver of claim 18, wherein, a distance between the two of the plurality of sense internal lines is the same as a distance between each of the two of the plurality of sense internal lines and a data internal line adjacent to the two of the plurality of sense internal lines. 20.A display apparatus including a display panel and a data driver, the display panel including a plurality of data lines, a plurality of sense lines, and a plurality of sub-pixels connected to the plurality of data lines and the plurality of sense lines, the data driver configured to drive the display panel, wherein the data driver comprising a driving block configured to provide a data signal to each of the plurality of sub-pixels; a sensing block configured to measure an electrical characteristic of each of the plurality of sub-pixels; a plurality of data internal lines configured to connect a plurality of driving block nodes included in the driving block to a plurality of data pads connected to the plurality of data lines; and a plurality of sensing internal lines configured to connect a plurality of sensing nodes included in the sensing block to a plurality of sensing pads connected to the plurality of sensing lines, wherein two of the plurality of sensing internal lines are located between the plurality of data internal lines.

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