Quantum computing-oriented low-temperature broadband CMOS (complementary metal oxide semiconductor) voltage-controlled oscillator

Abstract

The invention discloses a quantum computing-oriented low-temperature broadband CMOS (Complementary Metal Oxide Semiconductor) voltage-controlled oscillator, which belongs to the technical field of CMOS integrated circuits and comprises a Class-C dual-core push-pull cross coupling amplification circuit, a dual-mode resonant inductance network, a symmetric inductance mode switching circuit and a digital control capacitor array. The Class-C dual-core push-pull cross-coupling amplification circuit realizes current multiplexing through alternate conduction of upper and lower symmetrical transistors, reduces power consumption and inhibits phase noise. The dual-mode resonant inductor network and the symmetric inductor mode switching circuit cooperatively switch a low-frequency / high-frequency mode, so that the frequency coverage range is expanded; the digital control capacitor array adjusts equivalent capacitance and compensates frequency deviation caused by inductance change at low temperature. The oscillator is suitable for scenes of quantum calculation control, low-temperature radio frequency communication, high-precision frequency synthesis and the like.

Description

Technical Field

[0001] This invention relates to the field of CMOS integrated circuit technology, and more specifically to a low-temperature voltage-controlled oscillator circuit with low phase noise and wide frequency tuning range suitable for quantum computing applications. Background Technology

[0002] With the development of quantum computing technology, the control precision of qubits is constantly improving, placing higher demands on the performance of signal processing circuits in low-temperature environments. To suppress thermal noise and maintain the coherence of quantum states, quantum computing systems typically operate at extremely low temperatures around 4 K, requiring higher stability and phase noise control of microwave signals. The voltage-controlled oscillator (VCO), as a core module, is responsible for providing a low-noise microwave signal with adjustable frequency, and is a crucial foundation for achieving precise control of qubits. Furthermore, to achieve high-precision control of superconducting qubits, the operating frequency band of the VCO must match the energy level transitions of the qubits. The 4–8 GHz band meets this requirement and exhibits both good signal stability and low noise characteristics in low-temperature environments, thus it is widely used in quantum computing systems.

[0003] However, existing cryogenic voltage-controlled oscillators (VCOs) struggle to achieve a balance between frequency stability, phase noise, and power consumption, and their frequency tuning range is limited, failing to simultaneously meet the demands of quantum systems for wide bandwidth coverage, high spectral purity, and low power consumption. Furthermore, the significant changes in parasitic parameters at low temperatures further restrict the tuning characteristics and noise performance of VCOs. Traditional dual-mode structures have limited tuning ranges, while multi-mode structures, although capable of covering a wider frequency band, often come at the cost of increased power consumption and noise. Therefore, existing technologies struggle to achieve a balance between phase noise, power consumption, and tuning range, necessitating a simple, stable, and cryogenic broadband low-noise oscillator design.

[0004] Existing technologies propose a low-temperature CMOS circuit and system architecture for quantum computing. By integrating key modules such as oscillators and amplifiers under low-temperature conditions, it achieves low-noise signal generation and readout, providing a microwave drive source for quantum processors. This Cryo-CMOS oscillator employs a traditional LC resonant structure and an F-like topology to reduce phase noise and improve frequency stability, achieving a high quality factor at low temperatures. However, this approach still has shortcomings in frequency tuning capability, phase noise stability, power efficiency, and overall performance. Its adjustable frequency range is generally limited to a single resonant circuit or a fixed inductor structure, making it difficult to cover a wider operating frequency band. Simultaneously, changes in parasitic parameters at low temperatures limit tuning characteristics, resulting in insufficient frequency variability. Since it mainly relies on improving the Q-value of the resonant circuit rather than topology optimization, although phase noise is improved, noise performance is prone to degradation under wideband tuning conditions, making it difficult to maintain a high level of FoM. Furthermore, multi-stage feedback and bias circuits increase overall power consumption, resulting in a complex structure and large area, which is not conducive to the integration of high-density quantum control arrays.

[0005] In summary, existing cryogenic voltage-controlled oscillators (VCOs) for quantum computing suffer from multiple technical bottlenecks: traditional LC resonances and F-like topologies rely on a single inductor structure, limiting the frequency tuning range and failing to cover the full 4-8 GHz frequency band required for qubit control; at low temperatures, parasitic parameter drift leads to unstable resonance characteristics, phase noise degradation, and a lack of targeted frequency offset compensation design; simultaneously, multi-stage feedback and bias circuits result in high power consumption, and the complex structure hinders the integration of high-density quantum control arrays, making it difficult to meet the comprehensive requirements of quantum computing systems for wide coverage, low phase noise, low power consumption, and high stability.

[0006] Therefore, there is an urgent need for a low-temperature broadband VCO design that breaks through the above-mentioned bottlenecks through innovative circuit architecture. This design should not only use efficient topology to achieve current multiplexing and low power consumption, but also use dual-mode adjustable inductors and precise capacitors to compensate for the extended bandwidth and suppress low-temperature parameter drift, while ensuring low phase noise performance over a wide frequency range. This would be suitable for application scenarios with stringent requirements for signal quality and energy efficiency, such as quantum computing control, low-temperature RF communication, and high-precision frequency synthesis. Summary of the Invention

[0007] Based on the above-mentioned technical problems, this application discloses a low-temperature broadband CMOS voltage-controlled oscillator for quantum computing, including a Class-C dual-core push-pull cross-coupled amplifier circuit, a dual-mode resonant inductor network, a symmetrical inductor mode switching circuit, and a digitally controlled capacitor array, which constitute a complete oscillation system;

[0008] The differential output terminal of the Class-C dual-core push-pull cross-coupled amplifier circuit is electrically connected to the differential input terminal of the dual-mode resonant inductor network to form an oscillation circuit.

[0009] The symmetrical inductor mode switching circuit is electrically connected to the intermediate node of the dual-mode resonant inductor network. By controlling the MOS switch to turn on and off, the resonant current path is changed, and the equivalent value of the resonant inductor is switched, thereby realizing the switching between low-frequency mode and high-frequency mode.

[0010] The digitally controlled capacitor array is connected in parallel with the dual-mode resonant inductor network. Its control terminal receives digital control signals to adjust the conduction state of the parallel capacitor units in order to adjust the equivalent capacitance of the resonant circuit and compensate for the frequency shift caused by the change in inductance at low temperature.

[0011] The entire circuit has bias ports Vbias1 and Vbias2, differential resonant ports P1, P2, P3 and P4, and mode control ports HB and LB. The bias ports are used to provide bias current, the differential resonant ports are used to form an oscillation circuit, and the mode control ports are used for dual-mode switching.

[0012] Preferably, the Class-C dual-core push-pull cross-coupled amplifier circuit comprises symmetrical NMOS transistors and PMOS transistors, as well as capacitors C1, C2, C3, and C4, and resistors R1, R2, R3, and R4 for biasing and feedback.

[0013] The NMOS transistors are specifically M1 and M2, and the PMOS transistors are specifically M3 and M4. The NMOS transistors and PMOS transistors, which are symmetrically arranged vertically, share a common bias current and are alternately turned on in Class-C bias state to inject energy into the oscillation circuit formed by the dual-mode resonant inductor network in a push-pull drive manner.

[0014] The Class-C bias reduces conduction losses and suppresses phase noise by limiting the transistor to conduct only in the signal peak range; and the differential negative resistance is formed by the cross-coupling connection of capacitors C1 to C4 to compensate for the energy loss of the oscillation circuit and ensure stable start-up and continuous oscillation of the circuit.

[0015] Preferably, in the PMOS transistor branch of the Class-C dual-core push-pull cross-coupled amplifier circuit, one end of resistor R3 and one end of resistor R4 are connected together to form a bias port Vbias2, which is used to connect the bias current of the PMOS transistor.

[0016] The other end of resistor R3 and one end of capacitor C4 are connected to the gate of PMOS transistor M3.

[0017] The other end of capacitor C3 is connected to the differential resonant port P3 along with the drain of PMOS transistor M3, and the other end of capacitor C4 is connected to the differential resonant port P4 along with the drain of PMOS transistor M4. The sources of PMOS transistors M3 and M4 are both connected to the power supply voltage VDD, forming a complete signal path for the PMOS transistor branch.

[0018] Preferably, in the NMOS transistor branch of the Class-C dual-core push-pull cross-coupled amplifier circuit, one end of resistor R1 and one end of resistor R2 are connected together to form a bias port Vbias1, which is used to connect the bias current of the NMOS transistor.

[0019] The other end of resistor R1 and one end of capacitor C2 are connected to the gate of NMOS transistor M1, and the other end of resistor R2 and one end of capacitor C1 are connected to the gate of NMOS transistor M2.

[0020] The other end of capacitor C1 is connected to the drain of NMOS transistor M1 and then to the differential resonant port P1. The other end of capacitor C2 is connected to the drain of NMOS transistor M2 and then to the differential resonant port P2. The sources of NMOS transistors M1 and M2 are both grounded, forming a complete signal path for the NMOS transistor branch.

[0021] Preferably, the dual-mode resonant inductor network adopts a symmetrically arranged butterfly-shaped four-port differential inductor structure, with a layout that is symmetrical from left to right.

[0022] The left half is equipped with ports P1 and P3, and the right half is equipped with ports P2 and P4. Ports P1 to P4 are respectively connected to the corresponding differential nodes of the Class-C dual-core push-pull cross-coupled amplifier circuit, providing differential resonant paths in different modes.

[0023] By controlling the current path through a switching transistor connected to the middle node of the inductor, the inductor can exhibit different equivalent inductance values ​​under different switching states, corresponding to low-frequency mode and high-frequency mode.

[0024] Preferably, the symmetrical inductor mode switching circuit uses differentially symmetrically arranged NMOS transistors M5~M8, and switches the inductor current path by controlling their conduction and cutoff to achieve dual-mode oscillation frequency switching;

[0025] The switching transistors adopt a differential symmetrical layout, which allows their parasitic capacitances to cancel each other out under differential mode signal excitation, thereby reducing mode switching losses.

[0026] Preferably, the gates of NMOS transistor M5 and NMOS transistor M6 are connected to the low-frequency switching control port LB; the gates of NMOS transistor M7 and NMOS transistor M8 are connected to the high-frequency switching control port HB.

[0027] The drains of NMOS transistors M5 and M8 are both connected to the differential resonant port P3; the drains of NMOS transistors M6 and M7 are both connected to the differential resonant port P4; the sources of NMOS transistors M5 and M7 are both connected to the differential resonant port P1; and the sources of NMOS transistors M6 and M8 are both connected to the differential resonant port P2.

[0028] Preferably, the digitally controlled capacitor array consists of a digitally controlled capacitor bank and a varactor diode, including capacitors CT1 and CT2; capacitor CT1 is connected between differential resonant ports P1 and P2, and capacitor CT2 is connected between differential resonant ports P3 and P4.

[0029] The numerically controlled capacitor bank adopts a metal-oxide-metal (MOM) capacitor structure, which includes three switched capacitor units configured with binary weights. It achieves eight levels of discrete capacitance value adjustment through digital control signals for coarse frequency adjustment. The capacitance value of the varactor diode is continuously variable with the control voltage, which is used to achieve fine frequency adjustment in each discrete range.

[0030] Compared with the prior art, the technical solution of this application has the following technical effects:

[0031] This invention employs a Class-C dual-core push-pull cross-coupled amplification structure. The upper and lower symmetrical NMOS and PMOS are alternately turned on under Class-C bias and share the bias current, forming current multiplexing. At the same time, the push-pull method enables the upper and lower transistors to inject energy into the resonant circuit in a coordinated manner, realizing differential drive and improving output efficiency. While ensuring oscillation gain, it significantly reduces conduction time and power consumption. Moreover, Class-C conduction is limited to the signal peak region, where the signal amplitude is the largest and the noise has the least relative impact. The coordinated push-pull structure can effectively suppress phase noise and improve spectral purity over a wide frequency range.

[0032] The dual-mode resonant inductor network of this invention adopts a symmetrical butterfly four-port structure and is combined with a symmetrical inductor mode switching circuit. By controlling the current path, it achieves switching between low-frequency and high-frequency modes, thus covering a wide frequency range. This structure expands the tuning range and maintains a high resonance quality factor without increasing the layout area. The symmetrical layout allows parasitic capacitances to cancel each other out under differential-mode signals, achieving low-loss and low-distortion mode switching, effectively avoiding parasitic effects and additional noise problems in traditional multimode resonant structures.

[0033] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the preferred embodiments of this application are described in detail below with reference to the accompanying drawings.

[0034] The above and other objects, advantages and features of this application will become more apparent to those skilled in the art from the following detailed description of specific embodiments of this application in conjunction with the accompanying drawings. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In all drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0036] Based on the description of the figures and their corresponding technical content in the document, the titles of the figures are as follows:

[0037] Figure 1 This is a schematic diagram of the overall circuit structure of the low-temperature broadband push-pull Class-C dual-mode voltage-controlled oscillator of the present invention;

[0038] Figure 2 This is a schematic diagram showing the relationship between the oscillation frequency and the control voltage of the capacitor array in different modes of the present invention.

[0039] Figure 3 This is a schematic diagram illustrating the change of phase noise with frequency under two modes of the present invention; Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. In the following description, specific details such as specific configurations and components are provided merely to help fully understand the embodiments of this application. Therefore, those skilled in the art should understand that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application. In addition, for clarity and brevity, descriptions of known functions and structures are omitted in the embodiments.

[0041] It should be understood that the phrase "an embodiment" or "this embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "an embodiment" or "this embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0042] Furthermore, reference numerals and / or letters may be repeated in different examples within this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or settings discussed.

[0043] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, and A and B exist simultaneously. The term " / and" in this article describes another type of relationship between related objects, indicating that two relationships can exist. For example, A / and B can mean: A exists alone, and A and B exist alone. In addition, the character " / " in this article generally indicates that the related objects before and after it are in an "or" relationship.

[0044] In this article, the term "at least one" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, "at least one of A and B" can mean: A exists alone, A and B exist simultaneously, or B exists alone.

[0045] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion.

[0046] Example 1

[0047] This embodiment mainly describes a low-temperature broadband CMOS voltage-controlled oscillator for quantum computing, such as... Figure 1 As shown, the low-temperature broadband push-pull Class-C dual-mode voltage-controlled oscillator includes a Class-C dual-core push-pull cross-coupled amplifier circuit, a dual-mode resonant inductor network, a symmetrical inductor mode switching circuit, and a digitally controlled capacitor array.

[0048] The differential output of the Class-C dual-core push-pull cross-coupled amplifier circuit is electrically connected to the differential input of the dual-mode resonant inductor network to form an oscillation circuit.

[0049] The symmetrical inductor mode switching circuit is electrically connected to the intermediate node of the dual-mode resonant inductor network. By controlling the on and off states of the MOS switch, the resonant current path is changed, thereby switching the equivalent value of the resonant inductor and realizing the switching between low-frequency mode and high-frequency mode.

[0050] A digitally controlled capacitor array is connected in parallel with a dual-mode resonant inductor network. The control terminal of the capacitor array receives digital control signals to adjust the conduction state of the parallel capacitor units, thereby adjusting the equivalent capacitance of the resonant circuit and compensating for the frequency shift caused by inductance changes under low temperature conditions.

[0051] The entire circuit has a bias port V bias1 V bias2 The differential resonant ports are P1, P2, P3, and P4, and the mode control ports are HB and LB. The bias port is used to provide bias current, the differential resonant port is used to form an oscillation circuit, and the mode control port is used to switch between low-frequency mode and high-frequency mode.

[0052] Furthermore, the Class-C dual-core push-pull cross-coupled amplifier circuit consists of symmetrical NMOS transistors and PMOS transistors, as well as capacitors C1, C2, C3, and C4, and resistors R1, R2, R3, and R4 for bias and feedback.

[0053] The NMOS transistors are specifically M1 and M2, and the PMOS transistors are specifically M3 and M4. The NMOS transistors and PMOS transistors, which are symmetrically arranged vertically, share a common bias current and are alternately turned on in Class-C bias state to inject energy into the oscillation circuit formed by the dual-mode resonant inductor network in a push-pull drive manner.

[0054] The Class-C bias reduces conduction losses and suppresses phase noise by limiting the transistor to conduct only in the signal peak range; and the differential negative resistance is formed by the cross-coupling connection of capacitors C1 to C4 to compensate for the energy loss of the oscillation circuit and ensure stable start-up and continuous oscillation of the circuit.

[0055] Furthermore, in the PMOS transistor branch of the Class-C dual-core push-pull cross-coupled amplifier circuit, one end of resistor R3 and one end of resistor R4 are connected together to form a bias port Vbias2, which is used to connect the bias current of the PMOS transistor.

[0056] The other end of resistor R3 and one end of capacitor C4 are connected to the gate of PMOS transistor M3.

[0057] The other end of capacitor C3 is connected to the differential resonant port P3 along with the drain of PMOS transistor M3, and the other end of capacitor C4 is connected to the differential resonant port P4 along with the drain of PMOS transistor M4. The sources of PMOS transistors M3 and M4 are both connected to the power supply voltage VDD, forming a complete signal path for the PMOS transistor branch.

[0058] Furthermore, in the NMOS transistor branch of the Class-C dual-core push-pull cross-coupled amplifier circuit, one end of resistor R1 and one end of resistor R2 are connected together to form a bias port Vbias1, which is used to connect the bias current of the NMOS transistor.

[0059] The other end of resistor R1 and one end of capacitor C2 are connected to the gate of NMOS transistor M1, and the other end of resistor R2 and one end of capacitor C1 are connected to the gate of NMOS transistor M2.

[0060] The other end of capacitor C1 is connected to the drain of NMOS transistor M1 and then to the differential resonant port P1. The other end of capacitor C2 is connected to the drain of NMOS transistor M2 and then to the differential resonant port P2. The sources of NMOS transistors M1 and M2 are both grounded, forming a complete signal path for the NMOS transistor branch.

[0061] Furthermore, the dual-mode resonant inductor network adopts a symmetrically arranged butterfly four-port differential inductor structure. The inductor layout is symmetrically arranged from left to right. The switching transistor connected to the middle node of the inductor is used to control the current path, so that the inductor presents different equivalent inductance values ​​in different switching states, corresponding to low-frequency mode and high-frequency mode.

[0062] The dual-mode resonant inductor network has ports P1 and P3 on the left half and ports P2 and P4 on the right half. Ports P1, P2, P3, and P4 are connected to the corresponding differential nodes of the Class-C dual-core push-pull cross-coupled amplifier circuit to provide differential resonant paths in different modes.

[0063] Furthermore, the symmetrical inductor mode switching circuit uses differentially symmetrically arranged MOS switching transistors. By controlling their conduction and cutoff, the inductor current path is switched, thereby switching the oscillation frequency between the two modes. The switching transistors adopt a differentially symmetrical layout, so that their parasitic capacitances cancel each other out under differential mode signal excitation, reducing mode switching losses.

[0064] The symmetrical inductor mode switching circuit includes NMOS transistors M5, M6, M7, and M8.

[0065] The gates of NMOS transistors M5 and M6 are connected to the low-frequency switching control port LB; the gates of NMOS transistors M7 and M8 are connected to the high-frequency switching control port HB; the drains of NMOS transistors M5 and M8 are both connected to the differential resonant port P3; the drains of NMOS transistors M6 and M7 are both connected to the differential resonant port P4; the sources of NMOS transistors M5 and M7 are both connected to the differential resonant port P1; and the sources of NMOS transistors M6 and M8 are both connected to the differential resonant port P2.

[0066] Furthermore, the digitally controlled capacitor array consists of a digitally controlled capacitor bank and varactor diodes;

[0067] The numerically controlled capacitor bank adopts a metal-oxide-metal (MOM) capacitor structure, which includes three switched capacitor units configured with binary weights. It achieves eight levels of discrete capacitance value adjustment through digital control signals for coarse adjustment of the oscillation frequency.

[0068] The capacitance value of the varactor diode can be continuously varied with the control voltage, which is used to achieve fine frequency adjustment in each discrete range.

[0069] Digitally controlled capacitor array includes capacitor C T1 Capacitor C T2 Capacitor C T1 Connected between differential resonant ports P1 and P2; capacitor C T2 It is connected between the differential resonant ports P3 and P4.

[0070] This embodiment employs a Class-C structure to achieve current multiplexing, thereby reducing conduction time and static power consumption. The conduction characteristics of the Class-C structure are limited to the signal peak region, where the signal amplitude is maximum and the relative impact of noise is minimal. The amplification unit forms positive feedback through cross-coupled capacitors to enhance the start-up margin, and the push-pull symmetrical structure ensures differential output balance. The dual-mode resonant inductor network adopts a symmetrical butterfly four-port structure combined with an inductor mode switching circuit to achieve low-frequency and high-frequency mode switching and wide-range tuning. The symmetrical layout cancels parasitic capacitance and reduces additional noise. The digitally controlled capacitor array, by adjusting the parallel capacitor value, works in conjunction with the dual-mode inductor to achieve broadband high-resolution frequency tuning, while compensating for inductor drift at low temperatures, ensuring stable operation of the oscillator under low-temperature conditions.

[0071] Based on Example 1, this example provides an analysis of a frequency drift compensation technique for a low-temperature broadband CMOS voltage-controlled oscillator for quantum computing, as described in this application. Specifically:

[0072] Since passive components exhibit different characteristics at room temperature and low temperature, this is particularly evident in inductor design. Due to the low-temperature superconducting effect, the inductance of inductors made of metal wires decreases by approximately 5% from high-temperature to low-temperature environments. Therefore, certain technical designs are needed to compensate for the frequency shift. Electromagnetic simulations were performed on resonant inductor networks under both modes at low temperatures, and the simulation results are shown in Table 1.

[0073] Table 1 Electromagnetic simulation parameters of the dual-mode resonant inductor network

[0074] As shown in Table 1, by switching between the two modes, the equivalent inductance value required to cover the operating frequency of 4 GHz to 8.5 GHz at a low temperature of 4 K can be achieved, and the quality factor and equivalent impedance both have good results.

[0075] Under low-temperature conditions, when the circuit operates in low-frequency mode (4~6.7 GHz), ports P1 and P3, and P2 and P4 are connected respectively. Current flows from P1 and P3 through the intermediate line L2 to P2 and P4. The inductance in this mode is the sum of L1 and L2. As shown in Table 1, the inductance value is between 332.6 pH and 335.2, and the inductor's quality factor varies between 11.8 and 12.9. The resonant frequency at this time is... It can be represented as:

[0076]

[0077] in, For equivalent inductance, For a digitally controlled capacitor array, the coefficient 0.95 here reflects the change in inductance by 5% at low temperatures; this expression shows that when the inductance decreases, the resonant frequency increases accordingly.

[0078] Similarly, when the circuit operates in high-frequency mode (5.2~8.5 GHz) under low-temperature conditions, ports P1 and P4, and P2 and P3 are connected respectively; current flows from P3 to P2 and from P4 to P1, bypassing the intermediate line L2, resulting in a smaller inductance, including only L1. As shown in Table 1, the inductance value decreases to 213.6 pH~214.6 pH, and the inductor's quality factor varies between 12.3 and 13.6. The oscillation frequency at this point... for:

[0079]

[0080] Therefore, it can be seen that the decrease in inductance caused by low temperature will cause the entire operating frequency band to shift towards higher frequencies.

[0081] To compensate for this change, according to the above formula, the present invention selects an operating frequency slightly lower than the target operating range (4~8 GHz) at room temperature, so that when the temperature drops to 4 K, the frequency rise caused by the decrease in inductance is just enough to allow the VCO to cover the required full frequency band. Simultaneously, a digitally controlled capacitor array is added to the circuit to compensate for some uncertain random drift of the inductor value under low-temperature conditions, achieving a smooth frequency transition between the two modes. Through this predictive compensation design based on temperature-dependent inductance changes, the system can maintain stable oscillation within the target frequency range at low temperatures, ensuring that the wide bandwidth and high stability requirements for superconducting quantum bit driving are met.

[0082] Example 2

[0083] This embodiment details the implementation technology and effects of a low-temperature broadband CMOS voltage-controlled oscillator for quantum computing. Specifically, the oscillator adopts a Class-C dual-core push-pull cross-coupled structure. The upper and lower symmetrical NMOS and PMOS transistors alternately conduct under Class-C bias and share the bias current, forming current multiplexing to reduce conduction time and static power consumption. Simultaneously, the push-pull method allows the upper and lower transistors to collaboratively inject energy into the resonant circuit, improving energy transfer efficiency and differential output swing. Furthermore, Class-C conduction is limited to the signal peak region, where the signal amplitude is large and noise influence is small, thus exhibiting low phase noise characteristics. The amplification unit forms positive feedback through cross-coupling capacitors to enhance the start-up margin, while maintaining differential balance through the push-pull symmetrical structure.

[0084] A symmetrical butterfly-shaped four-port dual-mode resonant inductor network combined with an inductor mode switching circuit is used to switch between low-frequency and high-frequency modes by controlling the current path. The symmetrically arranged switching circuit can cancel parasitic capacitance to reduce additional noise. In addition, the circuit introduces a digitally controlled capacitor array, which adjusts the parallel capacitor value through control words. This works in conjunction with the dual-mode inductor to achieve continuously adjustable frequency control and compensate for frequency shifts caused by inductance changes at low temperatures, ensuring stable operation of the oscillator under different temperature and process conditions.

[0085] The low-temperature broadband push-pull Class-C dual-mode voltage-controlled oscillator of this invention is designed using TSMC 90nm CMOS technology, with a power supply voltage of 1.2 V and a power consumption of 10mW. Figure 1 The diagram shows the overall circuit structure of the low-temperature broadband push-pull Class-C dual-mode voltage-controlled oscillator of this invention. Key circuit parameters are: WM1=WM2=16 μm, WM3=WM4=32 μm, WM5=WM6=WM7=WM8=40 μm; R1=R2=R3=R4=15 KΩ, C1=C2=C3=C4=100 fF; the capacitor array is a standard binary array, CT1=CT2=110 fF×(1, 2, 4); the inductor layout has a linewidth of 10 μm, a total length of 197 μm, and a total width of 73 μm; bias voltages Vbias1 = 0.25 V, Vbias2 = 0.95 V.

[0086] The following are the relevant simulation results: Figure 2The diagram illustrates the variation of the circuit's operating frequency with the capacitor array control voltage when the resonant inductor network and capacitor array work together in two modes according to the present invention. The results show that by adjusting the capacitor array control voltage, the oscillation frequency can be continuously adjusted within the range of 4.0–5.8 GHz in low-frequency mode and within the range of 5.9–8.5 GHz in high-frequency mode. Within each mode, the digitally controlled capacitor array provides eight levels of discrete adjustment; the varactor diode provides continuous fine-tuning within each discrete level, achieving an organic combination of coarse and fine tuning. This allows the overall tuning range to cover 4.0–8.5 GHz, with a relative tuning range reaching 72%, meeting the wideband requirements for quantum bit control.

[0087] like Figure 3 As shown, the simulation results of the phase noise of the present invention as a function of frequency are presented. The figure shows that in both low-frequency mode (center frequency 5 GHz) and high-frequency mode (center frequency 7 GHz), the phase noise of the oscillator at a frequency offset of 1 MHz is approximately -115 dBc / Hz, and the phase noise at a frequency offset of 10 MHz is better than -135 dBc / Hz. In both modes, the phase noise gradually decreases with increasing frequency.

[0088] Table 2. Performance Comparison of the Invention with Existing Technologies

[0089] Note: ,in For phase noise, The oscillation frequency is... For frequency offset, This refers to power consumption.

[0090] Existing technologies disclose a low-temperature CMOS system for quantum computing. By integrating control and RF modules near the base temperature, it achieves close-range control and readout of qubit signals, verifying the feasibility of Cryo-CMOS operating at low temperatures. However, this oscillator uses traditional LC and F-like structures, relying on a fixed inductor network for tuning, resulting in a limited frequency range and difficulty in achieving wideband continuous tuning. At low temperatures, device parameter drift and parasitic effects lead to unstable resonance characteristics, limited phase noise suppression, and a significant decrease in FoM over a wide frequency range. Furthermore, its complex structure and high power consumption are unfavorable for high-density integration of quantum control systems. In contrast, this invention proposes a low-temperature push-pull Class-C dual-mode voltage-controlled oscillator. It achieves wide-frequency tuning through switchable inductors, expanding bandwidth while maintaining low phase noise. A dual-core current multiplexing structure reduces power consumption, and Class-C bias improves energy efficiency and stability. By optimizing inductor modeling and temperature compensation design, the oscillator maintains stable resonance and high FoM performance at low temperatures, achieving a comprehensive improvement in wideband coverage, low power consumption, and high stability.

[0091] This embodiment details a simulation experiment of a low-temperature broadband CMOS voltage-controlled oscillator for quantum computing. The simulation results show that the oscillator of this invention adopts a Class-C dual-core push-pull cross-coupled amplifier circuit. Through the synergistic optimization of the dual-mode resonant inductor network and the digitally controlled capacitor array, the frequency tuning range is significantly improved, the phase noise is reduced, and stable resonance and high FoM performance are maintained. It covers 4 GHz to 8.5 GHz at a low temperature of 4 K, achieving a 72% frequency tuning range, and maintaining a phase noise of -115 dBc / Hz@1 MHz offset in both high-frequency and low-frequency modes. This makes it an advantageous solution for low-temperature electronic systems, quantum control, and high-reliability radio frequency circuits.

[0092] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any changes, modifications, substitutions, integrations, and parameter changes made to these embodiments within the spirit and principles of the present invention, without departing from the principles and spirit of the present invention, through conventional substitutions or to achieve the same function, fall within the scope of protection of the present invention.

Claims

1. A low-temperature wideband CMOS voltage-controlled oscillator for quantum computing, characterized by, The complete oscillation system comprises a Class-C double-core push-pull cross-coupled amplification circuit, a double-mode resonant inductive network, a symmetrical inductive mode switching circuit and a digital control capacitor array. The differential output end of the Class-C double-core push-pull cross-coupled amplification circuit is electrically connected with the differential input end of the double-mode resonant inductive network, forming an oscillation loop. The symmetrical inductive mode switching circuit is electrically connected with the intermediate node of the double-mode resonant inductive network, and the resonant current path is changed by controlling the on and off of the MOS switch, the resonant inductance equivalent value is switched, and the switching between the low-frequency mode and the high-frequency mode is realized. The digital control capacitor array is connected in parallel with the double-mode resonant inductive network, and the control end thereof receives a digital control signal, the on state of the parallel capacitor unit is adjusted, the resonant loop equivalent capacitance is adjusted, and the frequency deviation caused by the inductance change at low temperature is compensated. The entire circuit is provided with bias ports Vbias1 and Vbias2, differential resonant ports P1, P2, P3 and P4, and mode control ports HB and LB; the bias ports are used for providing bias current, the differential resonant ports are used for forming an oscillation loop, and the mode control ports are used for double-mode switching.

2. The quantum-computing-oriented cryogenic wideband CMOS voltage-controlled oscillator of claim 1, wherein, The Class-C double-core push-pull cross-coupled amplification circuit comprises symmetrically-up-and-down NMOS tubes, PMOS tubes, and capacitors C1, C2, C3, C4, resistors R1, R2, R3 and R4 for biasing and feedback. The NMOS tubes are specifically M1 and M2, and the PMOS tubes are specifically M3 and M4; the symmetrically-up-and-down NMOS tubes and PMOS tubes share a bias current, and are alternately turned on in the Class-C bias state, so as to inject energy into the oscillation loop formed by the double-mode resonant inductive network in a push-pull driving mode. The Class-C biasing is realized by limiting the conduction of the transistors only in the signal peak interval, reducing the conduction loss and suppressing the phase noise; and the differential negative resistance is formed by the cross-coupled connection of the capacitors C1-C4, the energy loss of the oscillation loop is compensated, and the stable starting and continuous oscillation of the circuit is ensured.

3. The quantum-computing-oriented cryogenic wideband CMOS voltage-controlled oscillator of claim 2, wherein, In the PMOS tube branch of the Class-C double-core push-pull cross-coupled amplification circuit, one end of the resistor R3 and one end of the resistor R4 are commonly connected to form the bias port Vbias2, which is used for connecting the bias current of the PMOS tube. The other end of the resistor R3 and one end of the capacitor C4 are commonly connected to the gate of the PMOS tube M3, and the other end of the resistor R4 and one end of the capacitor C3 are commonly connected to the gate of the PMOS tube M4. The other end of the capacitor C3 and the drain of the PMOS tube M3 are commonly connected to the differential resonant port P3, and the other end of the capacitor C4 and the drain of the PMOS tube M4 are commonly connected to the differential resonant port P4; the sources of the PMOS tubes M3 and M4 are connected to the power supply voltage VDD, forming a complete signal path of the PMOS tube branch.

4. The quantum-computing-oriented cryogenic wideband CMOS voltage-controlled oscillator of claim 2, wherein, In the NMOS tube branch of the Class-C double-core push-pull cross-coupled amplification circuit, one end of the resistor R1 and one end of the resistor R2 are commonly connected to form the bias port Vbias1, which is used for connecting the bias current of the NMOS tube. The other end of the resistor R1 and one end of the capacitor C2 are commonly connected to the gate of the NMOS transistor M1, and the other end of the resistor R2 and one end of the capacitor C1 are commonly connected to the gate of the NMOS transistor M2; The other end of the capacitor C1 and the drain of the NMOS transistor M1 are commonly connected to the differential resonance port P1, and the other end of the capacitor C2 and the drain of the NMOS transistor M2 are commonly connected to the differential resonance port P2; the sources of the NMOS transistors M1 and M2 are both connected to the ground, forming a complete signal path of the NMOS transistor branch.

5. The quantum-computing-oriented cryogenic wideband CMOS voltage-controlled oscillator of claim 1, wherein, The double-mode resonant inductive network adopts a symmetrically arranged butterfly four-port differential inductive structure, and the layout is left-right symmetric; The left half part is provided with the ports P1 and P3, and the right half part is provided with the ports P2 and P4; the ports P1 to P4 are respectively connected to corresponding differential nodes of the Class-C double-core push-pull cross-coupled amplification circuit, and differential resonance paths in different modes are provided. The current path is controlled through the switching transistor connected to the inductive intermediate node, so that the inductor presents different equivalent inductance values in different switching states, corresponding to the low-frequency mode and the high-frequency mode.

6. The quantum-computing-oriented cryogenic wideband CMOS voltage-controlled oscillator of claim 1, wherein, The symmetric inductive mode switching circuit adopts the NMOS transistors M5 to M8 arranged in a differential symmetric mode, and the inductive current path is switched by controlling the conduction and cutoff of the NMOS transistors M5 to M8, so as to realize the switching of the double-mode oscillation frequency. The switching transistors are arranged in a differential symmetric mode, so that the parasitic capacitances of the switching transistors are mutually cancelled under the excitation of the differential mode signal, and the mode switching loss is reduced.

7. The quantum-computing-oriented cryogenic wideband CMOS voltage-controlled oscillator of claim 6, wherein, The gate of the NMOS transistor M5 and the gate of the NMOS transistor M6 are connected to the low-frequency switching control port LB; the gate of the NMOS transistor M7 and the gate of the NMOS transistor M8 are connected to the high-frequency switching control port HB. The drains of the NMOS transistors M5 and M8 are both connected to the differential resonance port P3; the drains of the NMOS transistors M6 and M7 are both connected to the differential resonance port P4; the sources of the NMOS transistors M5 and M7 are both connected to the differential resonance port P1; and the sources of the NMOS transistors M6 and M8 are both connected to the differential resonance port P2.

8. The quantum-computing-oriented cryogenic wideband CMOS voltage-controlled oscillator of claim 1, wherein, The digital control capacitor array is composed of a digital control capacitor group and a varactor diode, and includes capacitors CT1 and CT2; the capacitor CT1 is connected between the differential resonance ports P1 and P2, and the capacitor CT2 is connected between the differential resonance ports P3 and P4; The digital control capacitor group adopts a metal-oxide-metal (MOM) capacitor structure, contains three switching capacitor units configured according to binary weights, and realizes 8-level discrete capacitance value adjustment through a digital control signal, for frequency coarse adjustment; the capacitance value of the varactor diode is continuously variable with a control voltage, for realizing frequency fine adjustment in each discrete gear.

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