Multi-bus heterogeneous IP transmission system based on Rayleigh-core micro eight-core chip

Abstract

The invention relates to a multi-bus heterogeneous IP transmission system based on a Rayleigh-core micro eight-core chip, and belongs to the technical field of computer network communication. According to the multi-bus heterogeneous IP transmission system based on the Raycore micro eight-core chip, all components of the main board and the interface board are domestic devices, and 100% localization of the board-level components is achieved; the structural parts are all domestic products; meanwhile, RK3576 master control CPU unit software, RK3576 algorithm CPU unit software and MCU software are self-researched; hardware, software and the whole machine can be completely produced in China, so that the IP information transmission system is completely autonomous and controllable.

Description

Technical Field

[0001] This invention belongs to the field of computer network communication technology, and specifically relates to a multi-bus heterogeneous IP transmission system based on Rockchip octa-core chip. Background Technology

[0002] With IPv4 addresses becoming increasingly scarce and IPv6 becoming more widespread, IP addresses have evolved from mere "network locators" into critical data directly linked to user identity information, business topology, and even national security. Plaintext transmission of IP packets allows attackers to sniff, deeply correlate, and profil the source / destination addresses at any location within the backbone network, access network, or switching point. According to the ENISA 2024 annual report, over 73% of cross-border data breaches are related to address and traffic patterns. Currently, weaponry is rapidly developing towards miniaturization, lightweighting, and intelligence. However, communication between weapon systems carries the risk of IP information being eavesdropped on or tampered with, making the communication transmission methods between weapon systems particularly important.

[0003] Traditional address hiding schemes based on methods such as tunneling are difficult to defend against eavesdropping by attackers, and cannot meet the new user demand for "usable but invisible" addresses. In recent years, IP encrypted transmission technology has been proposed and implemented. By performing verifiable transmission encapsulation of IP information at the network layer, network devices can complete hop-by-hop routing and policy execution without decryption. During this process, any intermediate entity can only see unrelated encrypted addresses.

[0004] Currently, IP transmission methods only encrypt IP information at the transport or network layer. From a protocol stack perspective, encrypting IP information at the transport layer is an unauthorized act. The transport layer can only control the TCP / UDP header and payload. Encapsulating IP address information within the transport layer payload and encrypting it disrupts data transmission compatibility, poses a risk of transmission interruption, reduces throughput, and exacerbates data latency jitter. Furthermore, it cannot hide the outer IP header; timestamps, packet lengths, traffic patterns, and other information are still exposed, failing to achieve true anonymity. Encrypting IP information at the network layer is essentially a "re-encapsulation" process, which still does not isolate the IP transmission area from the encryption area, thus failing to meet the requirements of high security and high performance. Summary of the Invention

[0005] (a) Technical problems to be solved The technical problem to be solved by this invention is to propose a multi-bus heterogeneous IP transmission system to meet the requirements of high reliability and high security for encrypted transmission of IP information between weapons and equipment.

[0006] (II) Technical Solution To address the aforementioned technical problems, this invention provides a design method for a multi-bus heterogeneous IP transmission system based on a Rockchip octa-core chip. The system hardware includes a motherboard based on the Rockchip RK3576; the motherboard includes RK3576 main control CPU unit hardware, RK3576 algorithm CPU unit hardware, and integrates a power module and an LDO chip. The DC power supply is connected to the motherboard through an external interface. On the motherboard, the power module first converts it to 5V DC voltage, and then the LDO chip converts it to the voltage required by other hardware modules. The system software includes RK3576 main control CPU unit software, RK3576 algorithm CPU unit software, and MCU software. The RK3576 main control CPU unit software includes a main control update file, and the RK3576 algorithm CPU unit software includes an algorithm update file. The update includes: kernel, device tree, and file system; the motherboard power-on sequence is controlled by the MCU software. This system uses the FlexBus-RGMII-USB OTG heterogeneous bus to decouple the RK3576 main control CPU unit and the RK3576 algorithm CPU unit to achieve encrypted transmission of IP information; the RK3576 algorithm CPU unit performs IP information encoding, and the RK3576 main control CPU unit performs IP information transmission. The FlexBus interconnect enables data communication between two processing systems: SYS1 (RK3576 main control CPU unit hardware and software) and SYS2 (RK3576 algorithm CPU unit hardware and software). At the hardware level, the two ARM processor systems, namely the RK3576 main control CPU unit and the RK3576 algorithm CPU unit, are connected via the FlexBus bus, forming a distributed computing platform. Each processing system runs an independent Linux kernel, achieving data sharing and collaborative processing through the FlexBus bus. The FlexBus interconnect is configured in an asymmetric communication mode: the interconnect bus FlexBus0 of one processing system operates in DAC mode as the transmitter, while the FlexBus1 of the other processing system operates in ADC mode as the receiver. The transmitter and receiver are interconnected via the FlexBus interconnect bus. During transmission, the transmitter converts digital data into a signal sequence conforming to bus timing requirements using a built-in digital signal processing unit and achieves zero-copy data transmission through a DMA controller. The receiver performs the reverse process, sampling and reconstructing the signals on the FlexBus interconnect bus into a digital data stream.

[0007] The present invention also provides a system designed based on the method.

[0008] The present invention also provides an application of the method in the field of computer network communication technology.

[0009] The present invention also provides an application of the system in the field of computer network communication technology.

[0010] (III) Beneficial Effects The multi-bus heterogeneous IP transmission system based on Rockchip's octa-core chip of this invention uses domestically produced components for the motherboard and interface boards, achieving 100% domestic production of board-level components; structural components are all domestically produced products; at the same time, it has self-developed RK3576 main control CPU unit software, RK3576 algorithm CPU unit software and MCU software; thus achieving 100% domestic production of hardware, software and the whole machine, thereby realizing complete independent control of the IP information transmission system.

[0011] Furthermore, this invention meets the need for encrypted transmission of IP information between multiple devices, prevents IP information from being eavesdropped on or tampered with at the transport layer, ensures that data exists in encrypted form during transmission, and cannot be cracked even if intercepted, thus guaranteeing the reliability and security of data transmission.

[0012] Finally, this invention innovatively proposes a FlexBus-RGMII-USB OTG heterogeneous bus interconnection topology, which can realize multiple communication modes, enabling this invention to adapt to various application scenarios and network requirements. Attached Figure Description

[0013] Figure 1 This is a general block diagram of an IP transmission system. Figure 2 This is a hardware block diagram of a multi-bus heterogeneous IP transmission system based on a Rockchip octa-core chip. Figure 3 This is a block diagram of the motherboard power supply. Figure 4 Power-on sequence of the motherboard; Figure 5 The power supply architecture is RK3576+RK806S-5; Figure 6 Power-on sequence for RK3576+RK806S-5; Figure 7 FlexBus bus interconnect block diagram; Figure 8 Block diagram of RGMII interconnect bus; Figure 9 This is a block diagram of a USB OTG interconnect. Detailed Implementation

[0014] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0015] This invention relates to a multi-bus heterogeneous IP transmission system based on a Rockchip octa-core chip. Addressing the problems of current IP information encrypted transmission schemes, this invention, based on the Rockchip dual-path RK3576 platform, decouples the main control CPU unit and the algorithm CPU unit through a FlexBus-RGMII-USBOTG heterogeneous bus. This completely isolates the external network from the internal network at the data link layer, and transmits IP information in encrypted form using intelligent algorithms. This prevents IP information from being eavesdropped on or tampered with at the transport layer, ensuring the reliability and security of IP information transmission.

[0016] The system hardware includes: a motherboard based on Rockchip RK3576, an interface board, an input power supply, and structural components. The software includes RK3576 main control CPU unit software, RK3576 algorithm CPU unit software, and MCU software. This invention decouples the RK3576 main control CPU unit and the RK3576 algorithm CPU unit through an innovative FlexBus-RGMII-USB OTG heterogeneous bus. The RK3576 algorithm CPU unit handles the encrypted encoding of IP information, while the RK3576 main control CPU unit handles the transmission of IP information. Simultaneously, it completely physically isolates the external network from the internal network, preventing IP information from being eavesdropped on or tampered with at the transport layer. This fulfills the requirement for encrypted transmission of IP information between multiple devices, ensuring the reliability and security of IP information transmission. Under the innovative heterogeneous bus interconnection topology of this invention, multiple communication modes can be implemented, enabling the invention to adapt to various application scenarios and network requirements. A block diagram of the multi-bus heterogeneous IP transmission system based on the Rockchip octa-core chip is shown below. Figure 1 As shown.

[0017] To address the aforementioned technical problems, this invention provides a multi-bus heterogeneous IP transmission system based on a Rockchip octa-core chip, comprising system hardware and system software. The system hardware includes a motherboard, interface board, input power supply, and structural components based on Rockchip RK3576. The system software includes RK3576 main control CPU unit software, RK3576 algorithm CPU unit software, and MCU software; The motherboard integrates a Rockchip RK3576 processor, LPDDR4X memory chips, eMMC board-mount storage chips, network PHY chip, network card chip, microcontroller chip, RS232 converter chip, watchdog chip, power management chip, power module, LDO chip, clock chip, USB interface, and buttons. The interface board includes an indicator light board, a flexible board, and an aviation plug-in board; The input power supply includes a filter and a power input interface, used to provide power to the motherboard and the interface board; The structural components include a chassis, a front panel, a rear panel, and a cover plate; The LPDDR4X memory chips used are LPDDR4 chips from Shenzhen BIWIN, model BWMZCX32H2A-64GI-X; The eMMC board-mount storage chip used is Shenzhen BIWIN eMMC board-mount chip, with the specification model: BWEFMI064GN223; The network PHY chip used is the YT8531 chip from Yutai Microelectronics. The network card chip used is Beijing Netcom's WX1860AL2; The microcontroller chip selected is the QJ32L053C8T6 32-bit ultra-low power microprocessor circuit from the 58th Research Institute of China Electronics Technology Group Corporation. The RS232 conversion chip selected is the HCE3232SMG from Beijing Sevenstar Technology Co., Ltd. The watchdog chip selected is HCE706TM from Beijing Sevenstar Technology Co., Ltd. The power management chip selected is Rockchip's RK806-5S; The power module selected is WMG1A18H050N05R22 from Shanghai Juntao. The LDO chip selected is the HCE74401 from Beijing Sevenstar Technology Co., Ltd. The clock chip selected is the Aip8563 from AMEC. The USB interface and buttons are used for software burning and software upgrades. The indicator light board is used for network status indication, and the flexible board and the aviation plug-in board are used for 3-way gigabit network transmission; The RK3576 main control CPU unit software includes a main control update file, and the RK3576 algorithm CPU unit software includes an algorithm update file. The update includes: kernel, device tree, and file system; the MCU software includes power-on timing.

[0018] Based on the aforementioned Rockchip platform, the RK3576 main control CPU unit and the RK3576 algorithm CPU unit are decoupled through the FlexBus-RGMII-USB OTG heterogeneous bus to achieve encrypted transmission of IP information.

[0019] This invention also provides a FlexBus-RGMII-USB OTG heterogeneous bus mechanism.

[0020] This invention also provides an application of an IP information transmission method on the RK3576 dual-system platform.

[0021] Motherboard hardware design block diagram as follows Figure 2 As shown in the figure. The RK3576 algorithm CPU unit implements the encoding of IP information, and the RK3576 main control CPU unit implements the transmission of IP information.

[0022] Furthermore, the overall power management design of the motherboard is as follows: Figure 3 As shown, the DC power supply is connected to the motherboard through an external interface. To improve power conversion efficiency, the power module first converts the DC voltage to 5V in the motherboard, and then the LDO chip converts it to the voltage required by other hardware modules.

[0023] Furthermore, different functional modules within the motherboard have different power supply requirements. To avoid high loads and large currents that could cause power chip malfunctions when powered simultaneously, each power supply module adopts a staggered power supply design. This follows the principle of powering core modules first, then functional modules; powering low voltage modules first, then high voltage modules within the same module; and powering modules with the same voltage together. The motherboard power-on timing diagram is shown below. Figure 4 As shown. The motherboard power-on sequence is controlled by the MCU software.

[0024] Furthermore, the CPU power supply solution of this invention is a PMIC power supply solution using RK3576 and RK806S-5. A single PMIC reduces the complexity of hardware and PCB design, decreases the number of components and PCB layout space; moreover, the overall power consumption of a single PMIC is low, circuit design and debugging are relatively simple, and the development cycle is shortened. The PMIC chip selected is Rockchip's RK806S-5. The RK3576+RK806S-5 power architecture topology is as follows: Figure 5 As shown.

[0025] Furthermore, the power-on timing diagram for RK3576+RK806S-5 is as follows: Figure 6 As shown.

[0026] Furthermore, based on the aforementioned Rockchip hardware platform, the RK3576 main control CPU unit and the RK3576 algorithm CPU unit are decoupled through the FlexBus-RGMII-USB OTG heterogeneous bus to achieve encrypted transmission of IP information.

[0027] Furthermore, the RK3576 dual-system architecture, composed of the RK3576 main control CPU unit and the RK3576 algorithm CPU unit, adopts an innovative FlexBus bus interconnection scheme, namely a full-speed mode of 16-bit FlexBus0 + 16-bit FlexBus1, applicable to scenarios such as... Figure 7As shown, the FlexBus interconnect enables high-speed data communication between two independent processing systems (sys1 and sys2). Processing system SYS1 consists of the RK3576 main control CPU unit hardware and software, while processing system SYS2 consists of the RK3576 algorithm CPU unit hardware and software. At the hardware level, the two complete ARM processor systems (RK3576 main control CPU unit and RK3576 algorithm CPU unit hardware) are connected via a dedicated FlexBus bus, forming a distributed but tightly coupled computing platform. Each system runs an independent Linux kernel, but data sharing and collaborative processing are achieved through FlexBus. The core idea of ​​this invention's FlexBus interconnect is to configure FlexBus in an asymmetric communication mode: the interconnect bus FlexBus0 of one processing system operates in DAC (digital-to-analog conversion) mode as the transmitting end, while the FlexBus1 of the other processing system operates in ADC (analog-to-digital conversion) mode as the receiving end. The transmitting and receiving ends are interconnected via the FlexBus interconnect bus. This design ensures clear data flow, avoids bus conflicts, and guarantees the reliability of high-speed data transmission. As can be seen from the device tree configuration of SYS1 or SYS2 software, FlexBus supports a maximum operating frequency of 200MHz, and the data bit width can be configured to 4 bits, 8 bits, or 16 bits, providing flexible bandwidth adaptation capabilities. During transmission, the transmitting end (DAC mode) converts digital data into a signal sequence that meets the bus timing requirements through the built-in digital signal processing unit, and achieves efficient zero-copy data transmission through the DMA controller. The receiving end (ADC mode) performs the opposite process, sampling the signals on the FlexBus interconnect bus and reconstructing them into a digital data stream. The advantage of this design is that it bypasses the overhead of traditional network protocol stacks, implements data transmission directly at the hardware level, significantly reduces latency, and improves throughput.

[0028] The FlexBus interconnect system boasts a robust error handling mechanism. At the hardware level, the FlexBus controller can detect various anomalies such as DMA timeouts, data overflows / underflows, and bus errors, and promptly notify the software layer via interrupt mechanisms. At the software level, the driver implements a multi-level error recovery strategy: for transient errors, the system automatically retryes; for persistent errors, it triggers a link reset; and for critical errors, it enters an error state and notifies the upper-layer application for handling.

[0029] The handling of packet loss employs a sliding window and selective retransmission mechanism. The sender maintains a transmission queue to track the status of each packet; the receiver detects packet loss using sequence numbers and requests retransmission. This mechanism ensures data reliability while minimizing unnecessary retransmission overhead.

[0030] Furthermore, the RK3576 dual-system architecture employs the RGMII interconnect bus design. Compared to the traditional GMII interface, RGMII reduces the number of signal lines from 24 to 12, maintaining gigabit bandwidth by transmitting data on both the rising and falling edges of the clock using DDR technology. In the RK3576 dual-system architecture, the RGMII interconnect is achieved by directly connecting the Ethernet MAC controllers of the two systems, bypassing traditional network switch infrastructure and forming a point-to-point high-speed Ethernet link. The interconnect bus block diagram is shown below. Figure 8 As shown.

[0031] In the special scenario of direct connection between two RGMII systems, special consideration must be given to network topology and routing configuration. The two systems form a point-to-point link, requiring manual configuration of IP addresses and ensuring no conflicts with other networks. The `fixed-link` configuration item specifies the link parameter in the device tree: `speed =` <1000> This indicates a gigabit connection, and `full-duplex` specifies full-duplex mode. This configuration bypasses the normal PHY negotiation process and directly sets the link status to "up". Under this topology, various communication modes can be implemented: the simplest is static IP configuration, where the two systems are configured with different IP addresses within the same subnet; more complex configurations can achieve network bridging, providing services to the outside world as a single entity; routing protocols can also be configured, allowing one system to act as a gateway for the other, achieving complex network topologies. This flexible configuration capability enables the RK3576 dual-system platform to adapt to various application scenarios and network requirements.

[0032] Furthermore, the RK3576 dual-system architecture employs a USB OTG interconnect bus design. The implementation of USB interconnect involves complex hardware and software coordination mechanisms. During hardware initialization, the system first configures the operating modes of the Combo PHY and USBDP PHY, controlling the enabling status of each PHY module through the status attribute in the device tree. When set to "host," the controller acts as a USB host, responsible for bus management, device enumeration, and power distribution; when set to "device," the controller acts as a USB device, responding to commands and data requests from the host; and the "otg" mode allows for dynamic switching at runtime. The extcon framework provides external connector detection functionality, automatically selecting the appropriate operating mode by detecting the ID pin status of the USB connector, thus achieving true OTG functionality.

[0033] The implementation of the USB communication protocol stack involves coordination across multiple layers. At the physical layer, USB 3.0 employs differential signal transmission, including Super Speed ​​TX / RX differential pairs and traditional USB 2.0 D+ / D- signal lines, supporting full-duplex communication and a maximum data transfer rate of 5Gbps. The link layer implements 8b / 10b encoding, scrambling, and clock recovery functions to ensure signal integrity over long distances. The protocol layer handles packet encapsulation, flow control, error detection, and retransmission mechanisms. USB 3.0 introduces asynchronous communication, allowing multiple data streams to be transmitted concurrently, significantly improving bus efficiency. At the application layer, the Linux kernel's USB subsystem provides device enumeration, configuration management, and data transfer services through the USB host controller driver. USB communication between dual systems can be achieved in several ways: one is by using USB network adapter functionality (such as CDC-ECM or NCM protocols) to virtualize the USB connection as a network interface; another is by using the USB mass storage protocol to achieve file system-level data sharing; and yet another is by using custom USB device classes to directly exchange data through the standard USB API. The interconnect bus diagram is shown below. Figure 9 As shown.

[0034] Furthermore, the algorithm, driver, and system are all integrated into the update file and embedded into the eMMC of the RK3576 main control CPU unit and the RK3576 algorithm CPU unit via USB interface and button.

[0035] This invention is based on a dual-channel RK3576 hardware and software platform. By using a heterogeneous bus FlexBus-RGMII-USB OTG, the control unit and the algorithm unit are decoupled, enabling IP information to be transmitted between multiple devices in encrypted form. This prevents IP information from being eavesdropped on or tampered with at the transport layer, ensuring the reliability and security of IP information transmission.

[0036] This invention achieves high-performance, low-latency, and high-reliability inter-system communication through this multi-bus interconnected hardware and software collaborative architecture, providing a strong technical foundation for application scenarios such as distributed processing, load balancing, and real-time data exchange.

[0037] This invention, based on a dual-path Rockchip RK3576 hardware platform, innovatively proposes a FlexBus-RGMII-USB OTG heterogeneous bus interconnection topology. This heterogeneous bus completely isolates the external and internal networks at the data link layer, eliminating the direct encryption of IP information at the transport and network layers. Instead, a dedicated mechanism of the heterogeneous bus decouples the IP information transmission area from the algorithm encryption area. The main control CPU unit of the dual-path Rockchip RK3576 handles network transmission, while the algorithm CPU unit performs encryption. This partitioned processing of IP information transmission significantly improves the reliability and security of encrypted IP information transmission between weapon systems.

[0038] Meanwhile, the dedicated mechanism based on the FlexBus-RGMII-USB OTG heterogeneous bus enables multiple communication modes, allowing this invention to adapt to various application scenarios and network requirements. This mechanism provides complete packet management services, including ring buffers, sequence number management, error detection, error handling, and retransmission. It exposes hardware resources to the application layer in a user-friendly manner while maintaining kernel security and stability. Through the collaborative design of hardware and software, it provides a high-performance, highly reliable system communication foundation for encrypted IP information transmission.

[0039] Definitions: CPU: Central Processing Unit; FlexBus: FlexBus is a parallel bus interface introduced by Freescale. RGMII: Reduced Gigabit Media Independent Interface, a simplified interface standard specifically designed for Gigabit Ethernet; USB OTG: USB OTG (On-The-Go), USB OTG technology; RTC: Real Time Clock; eMMC: Embedded Multi Media Card; LDO: Low Drop-Out regulator; LPDDR: Low Power Double Data Rate Synchronous Dynamic Random Access Memory.

[0040] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A design method of a multi-bus heterogeneous IP transmission system based on a RunCore eight-core chip, characterized in that, The hardware of the system comprises a mainboard based on a Rockchip RK3576; the mainboard comprises an RK3576 master CPU unit hardware, an RK3576 algorithm CPU unit hardware, and an integrated power module and LDO chip; A DC power supply is connected to the mainboard through an external interface, and is first converted into a DC 5V voltage by the power module and then converted into a voltage required by each hardware module by the LDO chip; The software of the system comprises RK3576 master CPU unit software, RK3576 algorithm CPU unit software and MCU software; The RK3576 master CPU unit software comprises a master update file, the RK3576 algorithm CPU unit software comprises an algorithm update file, and the update comprises a kernel, a device tree and a file system; the power-on sequence of the mainboard is controlled by the MCU software; The system decouples the RK3576 master CPU unit and the RK3576 algorithm CPU unit through a FlexBus-RGMII-USB OTG heterogeneous bus to realize IP information ciphertext transmission; the RK3576 algorithm CPU unit realizes IP information encoding, and the RK3576 master CPU unit realizes IP information transmission; FlexBus bus interconnection realizes data communication between two processing systems, processing system SYS1: RK3576 master CPU unit hardware and software; processing system SYS2: RK3576 algorithm CPU unit hardware and software; at the hardware level, the two ARM processor systems, i.e., the RK3576 master CPU unit and the RK3576 algorithm CPU unit hardware, are connected through a FlexBus bus to form a distributed computing platform; each processing system runs an independent Linux kernel, and data sharing and collaborative processing are realized through the FlexBus bus; wherein, the FlexBus bus interconnection is configured as an asymmetric communication mode: one of the processing systems works in the DAC mode as the sending end, and the other works in the ADC mode as the receiving end; the sending end and the receiving end are interconnected through the FlexBus interconnection bus; during transmission, the sending end converts digital data into a signal sequence meeting the bus timing requirements through a built-in digital signal processing unit and realizes zero-copy data transmission through a DMA controller; the receiving end performs the opposite process to sample the signal on the FlexBus interconnection bus and reconstruct the digital data stream.

2. The method of claim 1, wherein, The sending end maintains a sending queue to track the state of each data packet; the receiving end detects packet loss through a serial number and requests retransmission.

3. The method of claim 1, wherein, The RK3576 dual-system composed of the two processing systems also adopts an RGMII interconnection bus design, and transmits data on the rising and falling edges of the clock through DDR technology to maintain a gigabit bandwidth; in the RK3576 dual-system architecture, the RGMII interconnection bus is realized by directly connecting the Ethernet MAC controllers of the two processor systems to form a point-to-point Ethernet link.

4. The method of claim 1, wherein, In the point-to-point Ethernet link formed by the two processor systems, the fixed-link configuration item specifies the link parameters in the device tree: speed = <1000> indicates a gigabit connection, and full-duplex specifies the full-duplex mode. This configuration bypasses the normal PHY negotiation process and directly sets the link state to up. In this topology, multiple communication modes can be implemented: static IP configuration, in which the two processor systems are respectively configured with different IP addresses of the same subnet; complex configuration, in which network bridging is implemented, and the RK3576 dual system is provided as a whole to provide services externally; and a routing protocol is also configured in the point-to-point Ethernet link, so that one processor system acts as a gateway for the other processor system.

5. The method of claim 1, wherein, The RK3576 dual system also adopts a USB OTG interconnection bus design, and the implementation of USB interconnection involves a hardware and software coordination mechanism. In the hardware initialization stage, the RK3576 dual system first configures the working mode of the Combo PHY and the USBDP PHY, and controls the enable state of the Combo PHY and the USBDP PHY through the status attribute in the device tree.

6. The method of claim 1, wherein, In the RK3576 dual system, the implementation of the USB communication protocol stack involves the coordination and cooperation of multiple levels; in the physical layer, USB 3.0 uses differential signal transmission, which is implemented through the Super Speed TX / RX differential pair and the USB 2.0 D+ / D- signal lines, supports full-duplex communication and a maximum data transmission rate of 5Gbps; the link layer implements 8b / 10b encoding, scrambling, and clock recovery functions; the protocol layer handles data packet encapsulation, flow control, error detection, and retransmission mechanisms, and USB 3.0 introduces an asynchronous communication mode that allows multiple data streams to be transmitted concurrently; In the application layer, the USB subsystem of the Linux kernel provides device enumeration, configuration management, and data transmission services through the USB host controller driver; USB communication between RK3576 dual systems is implemented in multiple ways: one is to use the USB network adapter function to virtualize the USB connection as a network interface; the other is to use the USB storage protocol to implement file system-level data sharing.

7. The method of claim 1, wherein, The update file integrates algorithms and drivers, and solidifies the algorithms and drivers into the eMMC of the RK3576 dual system through the USB interface and the key.

8. A system designed based on the method of any one of claims 1 to 7.

9. Application of the method of any one of claims 1 to 7 in the field of computer network communication technology.

10. Application of the system of claim 8 in the field of computer network communication technology.

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