Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The disclosure provides a semiconductor structure and a preparation method of the semiconductor structure, and relates to the technical field of semiconductors. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; stacking the substrate along a first direction to form a stacked structure, wherein the stacked structure comprises an active layer; forming an opening on at least one side of the active layer along a second direction, wherein the opening penetrates through the stacked structure and exposes the substrate; filling a metal material in the opening, and enabling the metal material to form a first protective layer with the exposed substrate; and removing the metal material; wherein the first direction intersects with the upper surface of the substrate and is perpendicular to the second direction. When the metal material fills the opening, the metal material can be adsorbed on the upper surface of the exposed substrate and react with the substrate to form the first protective layer in a self-aligned manner, thereby omitting the deposition and etching process steps, saving process costs, and enabling the first protective layer to be a metal silicide. The first protective layer can resist a wet etching solution, avoids damage to the substrate by the wet etching solution, and plays a role in protecting the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Technology

[0002] Dynamic Random Access Memory (DRAM), as a core device in the semiconductor memory field, is widely used in various electronic devices such as computers, servers, and mobile terminals. Existing memory cells are stacked in multiple layers along a direction perpendicular to the substrate, which can improve the integration density of memory cells without increasing the planar area.

[0003] To achieve vertical interconnection of memory cells, selective etching of the dielectric layer in the stacked structure is required using a side-cutting process. However, during silicon side-cutting, the etching solution directly contacts the exposed substrate surface, eroding the substrate and causing lattice damage and surface defects. This can lead to delamination or microcracks at the substrate-stacked interface, thus affecting the reliability of the semiconductor structure.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and a method for fabricating the semiconductor structure, which reduces substrate damage and achieves substrate protection.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to one aspect of this disclosure, a method for fabricating a semiconductor structure is provided, comprising the following steps: providing a substrate; stacking the substrate along a first direction to form a stacked structure, the stacked structure including an active layer; forming an opening on at least one side of the active layer along a second direction, the opening penetrating the stacked structure and exposing the substrate; filling the opening with a metal material and forming a first protective layer between the metal material and the exposed substrate; removing the metal material; wherein the first direction intersects the upper surface of the substrate and is perpendicular to the second direction.

[0008] In some embodiments, the stacked structure further includes a bottom dielectric layer and an interlayer dielectric layer. The bottom dielectric layer is located on the upper surface of the substrate, and the interlayer dielectric layer is located between the bottom dielectric layer and the active layer. The opening penetrates the bottom dielectric layer. After exposing the substrate, the structure further includes the following steps: removing the portion of the bottom dielectric layer surrounding the opening to form a gap between the substrate and the interlayer dielectric layer. The gap is circumferentially disposed around the opening and communicates with the opening. When a metal material is filled into the opening, the metal material can fill the gap and contact the substrate to form a second protective layer.

[0009] In some embodiments, the metallic material includes titanium, and the first protective layer and the second protective layer include titanium silicide.

[0010] In some embodiments, a high-temperature annealing process is used to form the first protective layer and the second protective layer.

[0011] In some embodiments, the depth of the opening along the first direction is greater than the height of the stacked structure along the first direction.

[0012] According to a second aspect of the present invention, embodiments of the present invention also provide a semiconductor structure, including a substrate, a stacked structure, and a first protective layer; the stacked structure is stacked on the substrate along a first direction, the stacked structure includes an active layer, and the active layer has a filling portion disposed on at least one side along a second direction, the filling portion penetrating the stacked structure; the first protective layer is disposed between the filling portion and the substrate and in contact with the substrate, the first protective layer including a metal silicide; wherein, the first direction intersects the upper surface of the substrate and is perpendicular to the second direction.

[0013] In some embodiments, the stacked structure further includes a bottom dielectric layer and an interlayer dielectric layer, the bottom dielectric layer being located on the upper surface of the substrate, the interlayer dielectric layer being located between the bottom dielectric layer and the active layer, and the filling portion penetrating the bottom dielectric layer; the semiconductor structure further includes a second protective layer, the second protective layer being located between the substrate and the interlayer dielectric layer, the second protective layer being disposed around the filling portion and between the first protective layer and the bottom dielectric layer.

[0014] In some embodiments, the second protective layer comprises titanium silicide.

[0015] In some embodiments, the first protective layer and the second protective layer are integrally formed.

[0016] In some embodiments, along the first direction, the lower surface of the filling portion is lower than the upper surface of the substrate.

[0017] One embodiment of the present invention has the following advantages or beneficial effects:

[0018] The semiconductor structure fabrication method provided in this disclosure involves creating openings in a stacked structure to expose the substrate. When a metal material fills the opening, it adheres to the exposed substrate surface, eliminating the need for additional photolithography and patterning steps. The metal material reacts with the substrate to form a self-aligned first protective layer, omitting deposition and etching processes and saving on process costs. Furthermore, the first protective layer formed by the reaction of the metal material and silicon atoms in the substrate is a metal silicide. Metal silicides are chemically stable, and the first protective layer resists wet etching solutions, preventing damage to the substrate and thus protecting it.

[0019] The semiconductor structure provided in this disclosure has the advantage that metal silicides have good resistance to wet etching solutions. Since wet etching solutions are difficult to remove metal silicides, the first protective layer formed by the metal silicide is located between the substrate and the stacked structure. In subsequent processes such as filling part forming and stacked structure patterning, the first protective layer can effectively block the direct contact between the wet etching solution and the substrate, thereby protecting the substrate and avoiding problems such as lattice damage and surface defects, thus improving the reliability of the semiconductor structure. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0021] Figure 1 The diagram shown is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0022] Figure 2 The diagram shown is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention;

[0023] Figure 3 The diagram shown is a schematic diagram of a method for fabricating a semiconductor structure according to an embodiment of the present invention, in which an opening is formed in the stacked structure;

[0024] Figure 4 The diagram shown illustrates a method for fabricating a semiconductor structure according to an embodiment of the present invention, in which a gap is formed between the substrate and the bottom dielectric layer.

[0025] Figure 5The diagram shown is a schematic diagram of a semiconductor structure fabrication method according to an embodiment of the present invention, in which a metal material is filled into the opening;

[0026] Figure 6 The diagram shown is a schematic diagram of a semiconductor structure fabrication method according to an embodiment of the present invention, in which a metal material reacts with a substrate to form a first protective layer and a second protective layer.

[0027] Figure 7 yes Figure 6 A magnified view of a portion at point A;

[0028] Figure 8 The diagram shown is a schematic diagram of a method for preparing a semiconductor structure according to an embodiment of the present invention, which involves removing residual metal material from the opening.

[0029] The reference numerals in the attached figures are explained as follows:

[0030] 1. Substrate; 2. Stacked structure; 3. Metallic material; 4. First protective layer; 5. Second protective layer; 6. Filler portion;

[0031] 21. Active layer; 22. Bottom dielectric layer; 23. Interlayer dielectric layer; 24. Insulating layer;

[0032] T, opening; P, gap. Detailed Implementation

[0033] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0034] The terms "first" and "second" used in this document are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly stated.

[0035] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0036] The following disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0037] It should be noted that, unless otherwise specified, the embodiments of the present invention and the technical features thereof can be combined with each other.

[0038] The following detailed description of this exemplary implementation method is provided in conjunction with the accompanying drawings and embodiments.

[0039] This embodiment provides a semiconductor structure, such as Figure 1 As shown, the semiconductor structure includes a substrate 1, a stacked structure 2, and a first protective layer 4. The stacked structure 2 is stacked on the substrate 1 along a first direction. The stacked structure 2 includes an active layer 21, and a filling portion 6 is provided on at least one side of the active layer 21 along a second direction, the filling portion 6 penetrating through the stacked structure 2. The first protective layer 4 is disposed between the filling portion 6 and the substrate 1 and is in contact with the substrate 1.

[0040] The first direction intersects the upper surface of substrate 1. This first direction can also be referred to as the stacking direction or the vertical direction. In some embodiments, the first direction may be a vertical direction. It should be noted that although some elements of the present invention are described as vertical or vertically oriented, the present invention is not limited thereto. For example, the first direction is perpendicular to the upper surface of substrate 1, and the second and third directions are two mutually perpendicular directions within the upper surface of substrate 1, i.e., the first, second, and third directions are mutually perpendicular to each other. The first direction is identified by D1, the second direction by D2, and the third direction by D3. The upper surface of substrate 1 is the surface of substrate 1 along the first direction and facing the stacked structure 2, and the lower surface of substrate 1 is the surface of substrate 1 along the first direction and away from the stacked structure 2.

[0041] The first protective layer 4 can also be called the bottom dielectric layer or the bottom passivation layer. The first protective layer 4 is located between the filling portion 6 and the substrate 1 and is used to isolate the filling portion 6 and the substrate 1.

[0042] The semiconductor structure provided in this embodiment has a stacked structure 2 stacked on a substrate 1 along a first direction. Without increasing the planar area, the number and integration scale of the active layers 21 are increased, thereby improving the storage density and integration level of the semiconductor structure. A first protective layer 4 is disposed between the filling portion 6 and the contact interface of the substrate 1. The first protective layer 4 serves as a barrier and protector, preventing the etching solution from directly contacting the substrate 1 in subsequent processes and reducing the possibility of damage to the substrate 1 in the interface region.

[0043] If the first protective layer 4 comprises silicon oxide, silicon oxide is easily removed by wet etching solution, making it difficult to protect the substrate 1. Therefore, in the semiconductor structure provided in this embodiment, the first protective layer 4 comprises a metal silicide. For example, the first protective layer 4 comprises titanium silicide, cobalt silicide, etc. This embodiment uses titanium silicide as an example.

[0044] Since metal silicides have good resistance to wet etching solutions, and wet etching solutions are difficult to remove metal silicides, the semiconductor structure provided in this embodiment has a first protective layer 4 formed by metal silicides located between the substrate 1 and the stacked structure 2. In subsequent processes such as the forming of the filling part 6 and the patterning of the stacked structure 2, the first protective layer 4 can effectively block the direct contact between the wet etching solution and the substrate 1, thereby protecting the substrate 1 and avoiding problems such as lattice damage and surface defects in the substrate 1. This prevents the substrate 1 from being damaged by the process and affecting the reliability of the semiconductor structure.

[0045] The substrate 1 is made of semiconductor materials, such as elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. Specifically, the substrate 1 provided in this disclosure is a silicon substrate.

[0046] The active layer 21 is made of elemental semiconductor materials such as silicon, for example, monocrystalline silicon, polycrystalline silicon, and oxide semiconductor materials (e.g., zinc tin oxide (ZnO)). x Sn y O, ZTO), indium zinc oxide (In) x Zn y O, IZO), zinc oxide (Zn) x O), Indium gallium zinc oxide (In xGa y Zn z One or more of O, IGZO and other similar materials.

[0047] An epitaxial growth process or a deposition process is used to stack a substrate 1 along a first direction to form a stacked structure 2. The deposition process may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), or low pressure chemical vapor deposition (LPCVD), etc.

[0048] In one embodiment, the filler portion 6 may be a conductor, including a bit line BL, which may also be referred to as a vertical conductor, a vertically oriented bit line, a vertically extending bit line, or a cylindrical bit line. The bit line BL is electrically connected to the active layer 21. The bit line BL may include a conductive material, and may include a silicon-based material, a metal-based material, or a combination thereof. The bit line BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The bit line BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line BL may include a stack of titanium nitride and tungsten (TiN / W).

[0049] In one embodiment, the filling portion 6 may be a data storage element, including a capacitor, such as a metal-insulator-metal (MIM) capacitor. The data storage element may be replaced with other data storage materials. For example, the data storage material may be a thyristor, a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material.

[0050] Specifically, the capacitor (not shown in the figure) includes a first electrode, a second electrode, and a dielectric layer, wherein the dielectric layer and the second electrode can be sequentially formed on the first electrode. The first electrode may include an internal space and multiple outer surfaces, and the internal space of the first electrode may include multiple inner surfaces. The outer surfaces of the first electrode may include a vertical outer surface and multiple horizontal outer surfaces. The vertical outer surface of the first electrode may extend vertically in a first direction, and the horizontal outer surfaces of the first electrode may extend horizontally in a second or third direction. The internal space of the first electrode may be three-dimensional. The dielectric layer may conformally cover the inner and outer surfaces of the first electrode or may be located on the inner and outer surfaces of the first electrode. The second electrode may be disposed on the dielectric layer within the internal space of the first electrode. Some outer surfaces of the first electrode may be electrically connected to the active layer 21.

[0051] The first electrode may have a cylindrical shape. The cylindrical shape of the first electrode may include an inner surface and an outer surface. Some outer surfaces of the first electrode's cylinder may be electrically connected to the active layer 21. A dielectric layer and a second electrode may be disposed on the inner surface of the cylindrical space of the first electrode. The second electrode may extend vertically in a first direction, and a first protective layer 4 is located between the second electrode and the substrate 1.

[0052] In one embodiment, such as Figure 1 As shown, along the first direction, the lower surface of the filling portion 6 is lower than the upper surface of the substrate 1. Specifically, the lower surface of the filling portion 6 is the surface of the filling portion 6 along the first direction and facing the substrate 1.

[0053] With this configuration, the filling portion 6 is at least partially embedded inside the substrate 1. Compared to the filling portion 6 being in contact with the upper surface of the substrate 1, the embedded contact between the filling portion 6 and the substrate 1 increases the contact area between them, preventing interlayer delamination, warping, or displacement of the filling portion 6 and the substrate 1, thus ensuring the integrity and reliability of the semiconductor structure. Simultaneously, increasing the contact area between the first protective layer 4 and the substrate 1 further enhances the protective effect on the substrate 1.

[0054] In one embodiment, such as Figure 1 As shown, the stacked structure 2 also includes a bottom dielectric layer 22 and an interlayer dielectric layer 23. The bottom dielectric layer 22 is located on the upper surface of the substrate 1, and the interlayer dielectric layer 23 is located between the bottom dielectric layer 22 and the active layer 21. The filling portion 6 penetrates the bottom dielectric layer 22.

[0055] The bottom dielectric layer 22 comprises silicon dioxide and covers the upper surface of the substrate 1. The bottom dielectric layer 22 effectively isolates the electrical signals between the substrate 1 and the upper stacked structure 2, preventing the random diffusion of charge carriers from the active layer 21 into the substrate 1, which could lead to leakage. The interlayer dielectric layer 23 further isolates the bottom dielectric layer 22 from the active layer 21, further reducing interlayer crosstalk.

[0056] In one embodiment, such as Figure 1 As shown, the stacked structure 2 also includes an insulating layer 24, which is disposed around the active layer 21 and located between the active layer 21 and the interlayer dielectric layer 23.

[0057] The insulating layer 24 comprises silicon oxide and surrounds the active layer 21. The insulating layer 24 isolates the active layer 21 from the interlayer dielectric layer 23. It prevents the random diffusion of charge carriers from the active layer 21 to the interlayer dielectric layer 23, thus avoiding charge loss and reduced read / write efficiency due to carrier leakage. Simultaneously, the insulating layer 24 also separates the functional regions of adjacent active layers 21, preventing signal crosstalk between adjacent active layers and ensuring the independence of the electrical signals of the active layer 21.

[0058] In one embodiment, such as Figure 1 As shown, the semiconductor structure also includes a second protective layer 5, which is located between the substrate 1 and the interlayer dielectric layer 23. The second protective layer 5 is arranged around the filling portion 6 and between the first protective layer 4 and the bottom dielectric layer 22.

[0059] The second protective layer 5 is arranged around the filling portion 6 and can connect the first protective layer 4 and the bottom dielectric layer 22 to protect the substrate 1, the sidewalls of the filling portion 6, and the connection area between the first protective layer 4 and the bottom dielectric layer 22. At the same time, since the first protective layer 4 directly contacts the substrate 1 and covers the contact area between the filling portion 6 and the substrate 1, the first protective layer 4 achieves directional protection of the contact area between the filling portion 6 and the substrate 1. Through the cooperation of the first protective layer 4 and the second protective layer 5, a dual protective structure of bottom contact protection and sidewall protection is formed, thereby eliminating the gap between the bottom of the filling portion 6 and the substrate 1, and the gap between the sidewall of the filling portion 6 and the bottom dielectric layer 22, preventing the etching solution from penetrating into the substrate 1 along the gaps, and further protecting the substrate 1.

[0060] In one embodiment, the second protective layer 5 comprises titanium silicide.

[0061] Because metal silicides have excellent resistance to wet etching solutions, they are difficult to remove using wet etching solutions. A second protective layer 5, formed of titanium silicide, is located between the substrate 1 and the interlayer dielectric layer 23, and around the filler portion 6. During processes such as filling portion 6 formation and stacked structure 2 patterning, the second protective layer 5 effectively prevents direct contact between the wet etching solution and the substrate 1, thus protecting the substrate 1 and preventing problems such as lattice damage and surface defects. This prevents the substrate 1 from being damaged by the process, thus ensuring the reliability of the semiconductor structure.

[0062] If the first protective layer 4 and the second protective layer 5 are separate structures, they are easily affected by factors such as deposition deviation and process fluctuation, which can easily cause gaps to form at the junction between the first protective layer 4 and the second protective layer 5. These gaps act as channels for the etching solution to penetrate and can easily damage the substrate 1.

[0063] Therefore, in the semiconductor structure provided in this embodiment, the first protective layer 4 and the second protective layer 5 are integrally formed.

[0064] This integrated molding structure prevents the etching solution from seeping through the gap between the first protective layer 4 and the second protective layer 5, achieving seamless protective coverage and reducing the risk of the etching solution damaging the substrate 1, thus further protecting the substrate 1. At the same time, the integrated molding structure of the first protective layer 4 and the second protective layer 5 saves molding time and reduces process costs.

[0065] The various semiconductor structures illustrated in this specific embodiment can be used in electronic devices with storage functions. These electronic devices can be terminal devices, such as mobile phones, tablets, and smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in these electronic devices can be implemented using the following types of memory: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).

[0066] This embodiment also provides a method for fabricating a semiconductor structure, such as... Figure 2 As shown, the method for fabricating this semiconductor structure includes the following steps:

[0067] S200, providing substrate 1;

[0068] S202, A stacked structure 2 is formed by stacking substrate 1 along a first direction, the stacked structure 2 including an active layer 21;

[0069] S204. An opening T is formed on at least one side of the active layer 21 along the second direction, the opening T penetrating the stacked structure 2 and exposing the substrate 1;

[0070] S206. Fill the opening T with metal material 3 and make the metal material 3 form a first protective layer 4 with the exposed substrate 1;

[0071] S208, Remove metal materials 3;

[0072] The first direction intersects the upper surface of the substrate 1 and is perpendicular to the second direction.

[0073] The semiconductor structure fabrication method provided in this disclosure involves creating an opening T in the stacked structure 2, which exposes the substrate 1. When a metal material 3 fills the opening T, the metal material 3 can adhere to the exposed surface of the substrate 1. Without requiring additional photolithography patterning steps, the metal material 3 can react with the substrate 1 to form a first protective layer 4 through self-alignment. Compared to existing protective layers that require deposition, patterning, and etching processes, this method eliminates these steps and reduces process costs.

[0074] Existing coating-type protective layers have problems such as easy peeling and poor adhesion. However, the first protective layer 4 provided in this disclosure is directly fused with the substrate 1. The film layer of the first protective layer 4 is dense and has strong adhesion, which ensures the stability of the first protective layer 4 and further improves the protective effect of the substrate 1.

[0075] Meanwhile, the first protective layer 4 formed by the reaction of the metal material 3 and silicon atoms in the substrate 1 is a metal silicide. Since the chemical properties of the metal silicide are relatively stable, the first protective layer 4 can resist the wet etching solution, prevent the wet etching solution from damaging the substrate 1, and play a role in protecting the substrate 1.

[0076] like Figure 3 As shown, a stacked structure 2 is formed on a substrate 1 along a first direction. The stacked structure 2 includes a bottom dielectric layer 22, an interlayer dielectric layer 23, and an active layer 21 stacked along the first direction, with the interlayer dielectric layer 23 and the active layer 21 alternately disposed. An opening T is formed on at least one side of the active layer 21 along a second direction, the opening T penetrating the stacked structure 2 and exposing the substrate 1.

[0077] Among them, such as Figure 3 As shown, the depth of the opening T along the first direction is greater than the height of the stacked structure 2 along the first direction.

[0078] With this configuration, the opening T penetrates the stacked structure 2 and extends into the substrate 1, so that the bottom of the opening T along the first direction and the sidewall along the second direction can expose the substrate 1. Then the first protective layer 4 can cover the bottom and sidewall of the opening T, increasing the contact area with the substrate 1 and further enhancing the protective effect on the substrate 1.

[0079] like Figure 4 As shown, after exposing substrate 1, the following steps are also included:

[0080] Remove the portion of the bottom dielectric layer 22 surrounding the opening T to form a gap P between the substrate 1 and the interlayer dielectric layer 23. The gap P is arranged in a ring around the opening T and communicates with the opening T.

[0081] After removing the bottom dielectric layer 22 around the opening T, the gap P formed is located between the substrate 1 and the bottom dielectric layer 22. The gap P is connected to the opening T and is arranged around the opening T, so that the gap P can also expose part of the substrate 1, that is, the part of the substrate 1 located in the gap P is exposed.

[0082] like Figure 5 As shown, when metal material 3 is filled into the opening T, the metal material 3 can fill the gap P, such as... Figure 6 As shown, the metal material 3 contacts the substrate 1 to form a second protective layer 5.

[0083] Since the gap P also exposes part of the substrate 1, the filling metal material 3 contacts and reacts with the exposed substrate 1 within the gap P. The metal material 3 does not react with the surrounding interlayer dielectric layer 23, thereby self-aligning to form a second protective layer 5 around the opening T. When the filling portion 6 is subsequently formed within the opening T, the second protective layer 5 around the opening T can prevent the etching solution from eroding the substrate 1 from the sidewall direction of the opening T. The second protective layer 5 can protect the portion of the substrate 1 located around the opening T, further reducing the risk of damage to the substrate 1.

[0084] like Figures 6-7 As shown, when the metal material 3 is filled into the opening T, a first protective layer 4 and a second protective layer 5 can be formed simultaneously. The first protective layer 4 and the second protective layer 5 are of the same layer structure, forming a structure of directional protection at the bottom of the opening T and surrounding protection around the sidewalls of the opening T, to cover the connection area between the substrate 1 and the opening T, and the interlayer dielectric layer 23. The first protective layer 4 can prevent the etching solution from vertically eroding the substrate 1 from the bottom of the opening T along the first direction, and the second protective layer 5 can prevent lateral penetration and erosion of the substrate 1 from the sidewalls of the opening T along the second direction. The first protective layer 4 and the second protective layer 5 form an isolation and protection structure to prevent the wet etching solution from penetrating into the interior of the substrate 1 along the bottom of the opening T along the first direction or the gap P between the substrate 1 and the bottom dielectric layer 22, thereby cutting off the erosion path of the wet etching solution and further improving the erosion resistance of the substrate 1.

[0085] In one embodiment, the metal material 3 includes titanium, and the first protective layer 4 and the second protective layer 5 include titanium silicide.

[0086] The first protective layer 4 and the second protective layer 5 formed by the in-situ reaction of metallic titanium and silicon in substrate 1 are titanium silicides. Compared with metal silicides such as cobalt silicides and nickel silicides, titanium silicides have better resistance to highly corrosive wet etching solutions, making the first protective layer 4 and the second protective layer 5 more difficult to be removed by wet etching solutions, thereby further protecting the substrate 1.

[0087] In one embodiment, a high-temperature annealing process is used to form the first protective layer 4 and the second protective layer 5.

[0088] Under high-temperature conditions, such as 600℃~900℃, titanium atoms in metal material 3 and silicon atoms in substrate 1 diffuse rapidly and combine fully to form dense, chemically stable titanium silicide, avoiding problems such as titanium residue or low crystallinity of titanium silicide caused by incomplete reaction at low temperatures. After the deposition of metallic titanium, a high-temperature annealing process is used to provide sufficient thermodynamic conditions for the reaction between metallic titanium and silicon in substrate 1, allowing the portion of substrate 1 exposed from the bottom of opening T and gap P to react with metallic titanium simultaneously, forming a continuous titanium silicide layer. That is, the first protective layer 4 and the second protective layer 5 are seamlessly fused, completely eliminating the gap between the two protective layers and preventing the etching solution from penetrating into substrate 1 along the gap.

[0089] like Figure 8 As shown, a wet etching process is used to remove the remaining metal material 3 using a wet etching solution. The wet etching solution is difficult to remove the first protective layer 4 and the second protective layer 5, so that the first protective layer 4 and the second protective layer 5 are retained and cover the substrate 1. The first protective layer 4 and the second protective layer 5 achieve isolation and protection for the substrate 1.

[0090] After removing the metal material 3, the opening T is filled with the filling part 6, forming as shown. Figure 1 The semiconductor structure shown. The filling portion 6 can be a bit line or the second electrode of a capacitor.

[0091] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0092] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0093] The semiconductor structure provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

[0094] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: Provide substrate; A stacked structure is formed by stacking the substrate along a first direction, the stacked structure including an active layer; An opening is formed on at least one side of the active layer along a second direction, the opening penetrating the stacked structure and exposing the substrate; The opening is filled with a metallic material, and the metallic material forms a first protective layer with the exposed substrate; Remove the metal material; Wherein, the first direction intersects the upper surface of the substrate and is perpendicular to the second direction; the stacked structure further includes a bottom dielectric layer and an interlayer dielectric layer, the bottom dielectric layer is located on the upper surface of the substrate, the interlayer dielectric layer is located between the bottom dielectric layer and the active layer, and the opening penetrates the bottom dielectric layer; After exposing the substrate, the following steps are also included: Remove the portion of the bottom dielectric layer surrounding the opening to form a gap between the substrate and the interlayer dielectric layer. The gap is arranged in a ring around the opening and communicates with the opening. When a metal material is filled into the opening, the metal material can fill the gap and contact the substrate to form a second protective layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The metallic material includes titanium, and the first protective layer and the second protective layer include titanium silicide.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first and second protective layers are formed by high-temperature annealing.

4. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The depth of the opening along the first direction is greater than the height of the stacked structure along the first direction.

5. A semiconductor structure, characterized in that, include: Substrate; A stacked structure is stacked on the substrate along a first direction. The stacked structure includes an active layer, and the active layer has a filling portion on at least one side along a second direction, the filling portion penetrating the stacked structure. A first protective layer is disposed between the filling portion and the substrate and in contact with the substrate, the first protective layer comprising a metal silicide; Wherein, the first direction intersects the upper surface of the substrate and is perpendicular to the second direction; the stacked structure further includes a bottom dielectric layer and an interlayer dielectric layer, the bottom dielectric layer is located on the upper surface of the substrate, the interlayer dielectric layer is located between the bottom dielectric layer and the active layer, and the filling portion penetrates the bottom dielectric layer; The semiconductor structure further includes a second protective layer located between the substrate and the interlayer dielectric layer, the second protective layer being disposed around the filling portion and between the first protective layer and the bottom dielectric layer.

6. The semiconductor structure according to claim 5, characterized in that, The second protective layer comprises titanium silicide.

7. The semiconductor structure according to claim 5, characterized in that, The first protective layer and the second protective layer are integrally formed.

8. The semiconductor structure according to any one of claims 5-7, characterized in that, Along the first direction, the lower surface of the filling portion is lower than the upper surface of the substrate.

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