A semiconductor device

Abstract

The application discloses a semiconductor device, which comprises a cell structure, the cell structure comprising an N+ substrate, an N-drift layer and a functional area; the N-drift layer is located on the N+ substrate; the functional area is embedded on the side of the N-drift layer away from the N+ substrate, and the functional area comprises two sub-units and a second N+ source area; the sub-unit comprises a P+ contact area, a P-type body area, a first N+ source area and a first trench gate structure; the first N+ source area is located on the P-type body area; the first trench is located between the P-type body area and the P+ contact area; a first gate oxide layer covers the inner wall of the first trench; the inner wall of the first gate oxide layer forms a first filling groove; a first gate is filled in the first filling groove; and the P+ shielding area of the P+ contact area covers the bottom of the first gate oxide layer. The first trench gate structures of the two sub-units have the second N+ source area therebetween. The device can improve the effective utilization rate of the channel, realize further reduction of the specific on-resistance, and optimize the long reverse recovery time.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Technology

[0002] Trench gate SiC MOSFET devices are highly competitive in the power device field due to their excellent specific on-resistance characteristics. However, the high electric field of the gate oxide at the bottom of the trench usually requires additional protection zones to mitigate the problem. The introduction of these protection zones either reduces the channel density or introduces a higher JFET resistance, resulting in low channel utilization, affecting further optimization of the specific on-resistance of the device, and causing a large reverse recovery voltage. Summary of the Invention

[0003] The present invention provides a semiconductor device that can improve the effective utilization of the channel, further reduce the overall specific on-resistance, and optimize the problem of long reverse recovery time caused by the large turn-on voltage drop of the enhancement trench gate device.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A semiconductor device includes at least one cell structure, the cell structure including an N+ substrate, an N- drift layer, at least one functional region, an interlayer dielectric layer, a source, and a drain;

[0006] The N-drift layer is located on the N+ substrate; the functional region is embedded in the N-drift layer on the side away from the N+ substrate, the functional region includes two sub-units and a second N+ source region, the sub-unit includes a P+ contact region, a P-type body region, a first N+ source region and a first trench gate structure, the first trench gate structure includes a first trench, a first gate oxide layer and a first gate;

[0007] In each of the sub-units, the first N+ source region is located on the surface of the P-type body region facing away from the N+ substrate. The first trench is located along a first direction between the P-type body region and the first N+ source region and the P+ contact region. The first gate oxide layer covers the inner wall of the first trench and contacts the P-type body region, the first N+ source region, the P+ contact region, and the N- drift layer. The inner wall of the first gate oxide layer forms a first filling trench. The first gate is filled in the first filling trench. The P+ contact region has a P+ shielding region, and the P+ shielding region covers the first gate oxide layer located at the bottom of the first trench. The two sub-units are arranged along a second direction, and a second N+ source region is located between the first trench gate structures of the two sub-units. The second direction is perpendicular to the first direction.

[0008] The source electrode is located on the side of the N-drift layer away from the N+ substrate and is in ohmic contact with the P+ contact region, the first N+ source region, and the second N+ source region; the interlayer dielectric layer is located between the N-drift layer and the source electrode to separate the first gate electrode from the source electrode; the drain electrode is located on the surface of the N+ substrate away from the N-drift layer.

[0009] This invention provides a semiconductor device comprising at least one cell structure, the cell structure including an N+ substrate, an N- drift layer, at least one functional region, an interlayer dielectric layer, a source, and a drain; the functional region includes two sub-units and a second N+ source region, the sub-units including a P+ contact region, a P-type body region, a first N+ source region, and a first trench gate structure; wherein the source, drain, N+ substrate, N- drift layer, sub-units, and interlayer dielectric layer can form an enhancement-mode trench gate device; and the source, drain, N+ substrate, N- drift layer, interlayer dielectric layer, the two first trench gate structures in the functional region, the P+ shielding region, and the second N+ source region can form a normally-off accumulation device. In the aforementioned semiconductor device, a normally off accumulator is embedded in an enhancement-mode trench gate device. The embedding of the accumulator avoids the influence of the P+ shielding region on the device, improves the effective utilization of the channel, and the high mobility of the accumulator channel further reduces the overall on-resistance of the device. In addition, the low electron barrier of the accumulator can serve as the electron current path when the enhancement-mode trench gate device is reverse-biased, thereby optimizing the problem of long reverse recovery time caused by the large diode turn-on voltage drop generated by the enhancement-mode trench gate device. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the structure of an enhancement-mode trench-gate SiC MOSFET device in the prior art;

[0011] Figure 2 This is a schematic diagram of a partial structure in a semiconductor device provided by an embodiment of the present invention;

[0012] Figure 3 For having Figure 2 A schematic cross-sectional view of a semiconductor device with a medium-sized structure along the first direction;

[0013] Figure 4 For having Figure 2 A schematic cross-sectional view of a semiconductor device with a mid-structure along the second direction;

[0014] Figure 5 This is a schematic diagram of a partial structure in another semiconductor device provided in an embodiment of the present invention;

[0015] Figure 6 For having Figure 5A schematic cross-sectional view of a semiconductor device with a mid-structure along the second direction;

[0016] Figure 7 This invention provides a diagram illustrating the operating state of an accumulation-type device in a semiconductor device according to an embodiment of the present invention.

[0017] Figure 8 Simulation data diagram of an accumulation device provided in an embodiment of the present invention;

[0018] Figure 9 Equivalent circuit diagram of a semiconductor device provided in an embodiment of the present invention;

[0019] Figure 10 A schematic cross-sectional view of a semiconductor device along a first direction, provided as an embodiment of the present invention;

[0020] Figure 11 A schematic cross-sectional view of a semiconductor device along a second direction, provided as an embodiment of the present invention;

[0021] Figure 12 A schematic diagram of the circuit structure of a semiconductor device provided in an embodiment of the present invention;

[0022] Figure 13 A schematic diagram of the circuit structure of another semiconductor device provided in an embodiment of the present invention;

[0023] Figure 14 A cross-sectional schematic diagram of another semiconductor device along a first direction provided in an embodiment of the present invention;

[0024] Figure 15 A schematic cross-sectional view of a semiconductor device along a second direction, provided as an embodiment of the present invention;

[0025] Figure 16 A flowchart illustrating the fabrication process of a semiconductor device provided in an embodiment of the present invention;

[0026] Figures 17 to 24 This is a fabrication state diagram of a semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] In related technologies, for enhancement-mode trench gate SiC MOSFET devices, taking the semi-enclosed trench scheme proposed by Infineon Technologies AG as an example, such as... Figure 1 As shown, the p-doped region 01 constitutes the enhancement-mode channel structure of the device, while the p+ region 02 both protects the oxide 03 at the bottom of the trench and grounds the p+ region 02. Although it has been optimized for trench gate oxide processes, its semi-enclosed p+ structure still significantly reduces the channel density, resulting in low effective channel utilization. This hinders further reductions in the device's specific on-resistance and also presents a large reverse recovery voltage.

[0029] To address the aforementioned technical problems, this invention provides a semiconductor device, please refer to... Figure 2 , Figure 3 and Figure 4 , Figure 2 This is a schematic diagram of a partial structure in a semiconductor device provided by an embodiment of the present invention. Figure 3 and Figure 4 They are respectively having Figure 1 A schematic cross-sectional view of a semiconductor device with a mid-structure along a first direction F1 and a second direction F2. Specifically, the semiconductor device includes at least one cell structure, which includes an N+ substrate 1, an N- drift layer 2, at least one functional region A, an interlayer dielectric layer 8, a source electrode S, and a drain electrode D.

[0030] The N-drift layer 2 is located on the N+ substrate 1; the functional region A is embedded in the side of the N-drift layer 2 away from the N+ substrate 1. The functional region A includes two sub-units b and a second N+ source region 9. The sub-unit b includes a P+ contact region 5, a P-type body region 3, a first N+ source region 4 and a first trench gate structure g1. The first trench gate structure g1 includes a first trench 6, a first gate oxide layer 7 and a first gate G1.

[0031] In each sub-unit b, the first N+ source region 4 is located on the surface of the P-type body region 3 facing away from the N+ substrate 1. The first trench 6 is located between the P-type body region 3, the first N+ source region 4, and the P+ contact region 5 along the first direction F1. The first gate oxide layer 7 covers the inner wall of the first trench 6 and contacts the P-type body region 3, the first N+ source region 4, the P+ contact region 5, and the N- drift layer 2. The inner wall of the first gate oxide layer 7 forms a first filling trench. The first gate G1 is filled in the first filling trench. The P+ contact region 5 has a P+ shielding region 51, which covers the first gate oxide layer 7 located at the bottom of the first trench 6. The two sub-units b are arranged along the second direction F2. The first trench gate structure g1 of the two sub-units b has a second N+ source region 9. The second direction F2 is perpendicular to the first direction F1.

[0032] The source S is located on the side of the N-drift layer 2 away from the N+ substrate 1 and is in ohmic contact with the P+ contact region 5, the first N+ source region 4 and the second N+ source region 9; the interlayer dielectric layer 8 is located between the N-drift layer 2 and the source S, and is used to separate the first gate G1 from the source S; the drain D is located on the surface of the N+ substrate 1 away from the N-drift layer 2.

[0033] The semiconductor device provided in this embodiment of the invention includes at least one cell structure, which includes an N+ substrate 1, an N- drift layer 2, at least one functional region A, an interlayer dielectric layer 8, a source S, and a drain D. Functional region A includes two sub-units b and a second N+ source region 9. Sub-unit b includes a P+ contact region 5, a P-type body region 3, a first N+ source region 4, and a first trench gate structure g1. The source S, drain D, N+ substrate 1, N- drift layer 2, sub-units b, and interlayer dielectric layer 8 can form an enhancement-mode trench gate device, such as... Figure 3 As shown; the source S, drain D, N+ substrate 1, N- drift layer 2, interlayer dielectric layer 8, and the two first trench gate structures g1, P+ shielding region 51, and second N+ source region 9 in functional region A can form a normally-off accumulation device, such as Figure 4 As shown, in the aforementioned semiconductor device, a normally-off accumulator is embedded within an enhancement-mode trench gate device. This embedding avoids the influence of the P+ shielding region on the device, improves the effective utilization of the channel, and the high mobility of the accumulator channel further reduces the overall device's on-resistance. Furthermore, the low electron barrier of the accumulator serves as the electron current path during reverse conduction of the enhancement-mode trench gate device, thus optimizing the problem of long reverse recovery time caused by the large diode turn-on voltage drop generated by the enhancement-mode trench gate device.

[0034] In the semiconductor device provided in this embodiment of the invention, the formed enhancement trench gate device can be an enhancement trench gate SiC MOSFET device, and the formed accumulation device can be a SiC accumulation field-effect transistor. Specifically, the N+ substrate 1 can be an N-type heavily doped silicon carbide (SiC) substrate. The N- drift layer 2 can be an N-type lightly doped silicon carbide region. The P+ contact region 5 can be a P-type heavily doped silicon carbide region. The P-type body region 3 can be a P-type doped silicon carbide region, and the first N+ source region 4 is an N-type heavily doped silicon carbide region. The materials of the first gate oxide layer 7 and the interlayer dielectric layer 8 can be silicon dioxide (SiO2). The material of the first gate G1 can be a P-type polycrystalline silicon material. The materials of the source S and drain D can be conductive metals, such as nickel (Ni) or titanium (Ti) / nickel (Ni / ) silver (Ag) stacks, etc. Specifically, the semiconductor device can be a structure of multiple identical cell structures connected in parallel. The number of cell structures is not limited here and depends on the actual situation.

[0035] Specifically, the two sub-units in functional area A may include a first sub-unit and a second sub-unit; such as Figure 2 and Figure 3 As shown, the cell structure may include at least two functional regions A arranged sequentially along the first direction F1. In two adjacent functional regions A along the first direction F1, the P+ contact region 5 of the first sub-unit in the preceding functional region contacts the P-type body region 3 and the first N+ source region 4 of the first sub-unit in the following functional region, and the P+ contact region 5 of the second sub-unit in the preceding functional region contacts the P-type body region 3 and the first N+ source region 4 of the second sub-unit in the following functional region. Specifically, the number of functional regions A in the cell structure of the above semiconductor device can be one or more, and there is no limitation here.

[0036] In the aforementioned semiconductor device, the cell structure can have at least two functional regions A. The source S, drain D, N+ substrate 1, N- drift layer 2, a row of sub-cells b arranged along the first direction F1, and interlayer dielectric layer 8 can form an enhancement-type trench gate device. The source S, drain D, N+ substrate 1, N- drift layer 2, interlayer dielectric layer 8, trench gate structure in functional region A, P+ shielding region 51, and second N+ source region 9 between the trench gate structure can form a normally-off accumulation device. This accumulation device is embedded in the enhancement-type trench gate device. The embedding of the accumulation device can improve the effective utilization rate of the device channel, further reduce the overall on-resistance of the device, and solve the problem of long reverse recovery time.

[0037] In the semiconductor device provided in this embodiment of the invention, each functional region A may further include a second trench gate structure g2 embedded on the side of the N-drift layer 2 facing away from the N+ substrate 1, such as... Figure 5 and Figure 6 As shown, Figure 5 This is a schematic diagram of a partial structure in another semiconductor device provided by an embodiment of the present invention. Figure 6 For having Figure 5 A schematic cross-sectional view of a semiconductor device with a medium-sized structure along the second direction F2, showing that... Figure 5 A cross-sectional schematic diagram of a semiconductor device with a medium structure along the first direction F1 can be shown as follows: Figure 3 As shown; the second trench gate structure g2 can be located between the first trench gate structure g1 of the two sub-units b. The second trench gate structure g2 includes a second trench 10, a second gate oxide layer 11, and a second gate G2. The second trench 10 is disposed on the N-drift layer 2. The second gate oxide layer 11 covers the inner wall of the second trench 10. The inner wall of the second gate oxide layer 11 forms a second filling trench. The second gate G2 is filled in the second filling trench.

[0038] Specifically, in functional region A, a second N+ source region 9 can be provided between adjacent first trench gate structure g1 and second trench gate structure g2; the first gate oxide layer 7 of the first trench gate structure g1 is in contact with the adjacent second N+ source region 9, and both sides of the second gate oxide layer 11 of the second trench gate structure g2 are in contact with the adjacent second N+ source region 9; the interlayer dielectric layer 8 is used to separate the second gate G2 from the source S, so that the second gate G2 is insulated from the source S.

[0039] In the aforementioned semiconductor device, each functional region A further includes a second trench gate structure g2 located between the first trench gate structures g1 of the two sub-units b. The source S, drain D, N+ substrate 1, N- drift layer 2, interlayer dielectric layer 8, the two first trench gate structures g1, the second trench gate structure g2, and the second N+ source region 9 of functional region A can form a normally-off accumulation device, such as... Figure 6 As shown, embedding the normally-off accumulator device into the enhancement-mode trench gate device improves the effective utilization of the device channel. Furthermore, the high mobility of the accumulator channel further reduces the overall on-resistance of the device, and the low electron barrier of the accumulator can serve as the electron current path when the enhancement-mode trench gate device is reverse-biased, thereby optimizing the problems of large diode turn-on voltage drop and long reverse recovery time caused by the enhancement-mode trench gate device.

[0040] Specifically, in each cell structure, there may be no second trench gate structure g2 between the two first trench gate structures g1 of each functional region A, and there is a second N+ source region 9 between the two first trench gate structures g1, such as... Figure 4 As shown; or, each functional area A may also have a second trench gate structure g2 between the two first trench gate structures g1, as shown. Figure 6 As shown.

[0041] Specifically, the second trench 10 of the second trench gate structure g2 can be etched simultaneously with the first trench 6 of the first trench gate structure g1; the second gate oxide layer 11 of the second trench gate structure g2 can be fabricated in the same layer as the first gate oxide layer 7 of the first trench gate structure g1, and the material of the second gate oxide layer 11 is the same as the material of the first gate oxide layer 7; the second gate G2 of the second trench gate structure g2 can be fabricated in the same layer as the first gate G1 of the first trench gate structure g1, and the material of the second gate G2 can be the same as the material of the first gate G1.

[0042] Specifically, the interlayer dielectric layer 8 is used to insulate the first gate G1 and the second gate G2 from the source phase S, such as... Figure 3 , Figure 4 and Figure 6As shown, the orthogonal projection of the interlayer dielectric layer 8 on the N+ substrate 1 can cover the orthogonal projections of the first trench gate structure g1 and the second trench gate structure g2 on the N+ substrate 1.

[0043] In the semiconductor device provided by the embodiments of the present invention, the enhancement trench gate device composed of the source S, drain D, N+ substrate 1, N- drift layer 2, a portion of the functional region A, and the interlayer dielectric layer 8 can be used as follows: Figure 3 As shown. In enhancement-mode trench gate devices, at zero gate-source voltage (V... GS When the gate voltage is 0V, it is in the off state (normally off), and a positive gate-source voltage (V) needs to be applied. GS A voltage greater than 0V is required for an N-channel device to turn on (conduct). When the voltage on the first gate G1 is zero, no conductive channel is formed below the first gate G1. The source (S) and drain (D) are separated by the P-type body region 3, forming a back-to-back PN junction, equivalent to two reverse-biased diodes connected in series. The device exhibits a high-resistance state, and the drain-source voltage V0 is zero. DS The PN junction, primarily located between the P-type body region 3 and the drain D, prevents current flow. However, a positive voltage (V) is applied to the first gate G1. GS When the voltage of the first gate G1 is greater than 0V, a negative charge is induced on the surface of the P-type body region 3 adjacent to the sidewall of the first trench 6 through the first gate oxide layer 7. GS Exceeding the threshold voltage V th At this time, the surface of the P-type body region 3 inverts, forming a vertical N-type conductive channel along the sidewall of the first trench 6. This vertical channel connects the source S and the N-drift layer 2. Electrons start from the source S, flow through the vertical channel into the N-drift layer 2, and then reach the drain D, forming a current (Id). D The P+ shielding region 51 covers the first gate oxide layer 7 located at the bottom of the first trench 6, which can shield the first gate oxide layer 7 at the bottom of the first trench 6, reduce its electric field strength, and improve long-term reliability. However, this will cause the single enhancement trench gate device to have problems such as low channel utilization, affecting further optimization of the device's specific on-resistance and large reverse recovery voltage.

[0044] By adding a second N+ source region and a second trench gate structure to the functional region of a semiconductor device, a normally-off accumulator device can be embedded in an enhancement-mode trench gate device. This accumulator device exhibits a very high accumulation layer mobility (150-200 cm² / vs). Specifically, in accumulator devices, such as... Figure 6 and Figure 7 As shown, when the voltage (V) applied to the first gate G1 and the second gate G2 GSWhen the voltage is zero, negative, or a low positive voltage, the band structure of the P-type polysilicon material (first gate G1 and second gate G2) and silicon carbide material (N-drift layer 2) can be used to deplete the N-type lightly doped silicon carbide region (N-drift layer 2) between two adjacent trench gate structures. This depleted region blocks the electron path from the source S through the N-drift layer 2 to the drain D, and the accumulation device is in the off state. However, when a sufficient positive gate voltage (V) is applied... GS When (exceeding the threshold voltage V) th The positive electric field on the first gate G1 and the second gate G2 strongly attracts electrons to the space between the two adjacent trench gate structures. Electrons that were originally repelled are also attracted back and their concentration is significantly increased, forming a highly conductive N-type accumulation layer 12. The N-type accumulation layer 12 formed on the trench sidewall is naturally connected to the second N+ source region 9 and the N- drift layer 2. At the same time, the N-type accumulation layer 12 at the bottom of the second trench 10 (the surface of the N- drift layer 2) further enhances the vertical conductivity. Therefore, a continuous, low-resistance N-type electron channel is established along the sidewall of the first trench 6, the sidewall of the second trench 10, and the bottom of the second trench 10, connecting the source S and the drain D. Electrons can flow smoothly from the source S, pass through the channel formed by the N-type accumulation layer 12, pass vertically downward through the N- drift layer 2, and finally reach the drain D. At this time, the device is in a low-resistance conducting state.

[0045] In the aforementioned semiconductor devices, not only can a channel be formed on the side of the first trench gate structure that contacts the P-type body region, but a channel is also formed in the region between the first trench gate structure and the second trench gate structure (or two adjacent first trench gate structures along the second direction), which can improve the effective utilization rate of the device trench. Furthermore, the channel of the accumulation type device has high mobility, which can further reduce the overall on-resistance of the device. In addition, the accumulation type device does not require reverse conduction to turn on and has a low electron barrier, which can become the electron current path when the enhancement trench gate device is reverse conducted, thereby optimizing the problem of long reverse recovery time caused by the large diode turn-on voltage drop generated by the enhancement trench gate device.

[0046] like Figure 8 The figure shows the band structure of the aforementioned accumulation device obtained through simulation under different channel widths, where the channel width W is... CH The horizontal spacing between two adjacent trench gates in an accumulation-type device is represented by the Y-axis, which points from the second N+ source region to the N+ substrate. Figure 8 The width W of the channel can be seen from this. CH The change in the band structure of a semiconductor device as the channel width W decreases from 0.6µm to 0.2µm. CHAs the channel narrows (from 0.6µm→0.4µm→0.2µm), the curvature of the conduction band (Ec), valence band (Ev), and Fermi level (Ef) in the central region of the channel increases dramatically, and the band slope (electric field) at the junction is significantly enhanced. This demonstrates the feasibility of the band distribution of P-type polycrystalline silicon and silicon carbide materials for the normally-off mode of the device.

[0047] Specifically, in the semiconductor device provided in the embodiments of this application, the equivalent circuit diagram of the cell structure during the reverse conduction process can be as follows: Figure 9 As shown in the diagram, the enhancement-mode trench gate device in the cell structure can be equivalent to an enhancement-mode trench gate device M11. The PN junction formed by the P-type body region 3 and the drain D in the enhancement-mode trench gate device M11 can be equivalent to the first equivalent diode D11. The source S of the enhancement-mode trench gate device M11 can be grounded. The normally-off accumulator embedded in the enhancement-mode trench gate device M11 can be equivalent to the second equivalent diode D12 connected in parallel with the enhancement-mode trench gate device M11. Because the accumulator has a low electron barrier height (<1.5eV), compared to a single silicon carbide body diode, more electrons participate in the reverse conduction process, thereby reducing the participation of minority carriers and reducing the reverse recovery time and loss of the device.

[0048] like Figure 10 and Figure 11 As shown, Figure 10 and Figure 11 These are schematic cross-sectional views along a first direction F1 and a second direction F2, respectively, of a semiconductor device provided in an embodiment of the present invention. In the semiconductor device provided in this embodiment, the cell structure may further include a metal contact portion 13 located on the side of the N-drift layer 2 facing away from the N+ substrate 1. The metal contact portion 13 makes ohmic contact with the P+ contact region 5, the first N+ source region 4, and the second N+ source region 9 of each functional region A. The source S makes ohmic contact with the P+ contact region 5, the first N+ source region 4, and the second N+ source region 9 of each functional region A through the metal contact portion 13. The metal contact portion 13 enables the formation of a low-resistance, stable ohmic contact.

[0049] Specifically, such as Figure 10 and Figure 11 As shown, the orthographic projection of the interlayer dielectric layer 8 onto the N+ substrate 1 can be non-overlapping with the orthographic projection of the metal contact portion 13 onto the N+ substrate 1. Specifically, the material of the metal contact portion 13 can be nickel metal, or it can be other materials, without limitation, depending on the actual situation.

[0050] In the semiconductor device provided in the embodiments of the present invention, such as Figure 12As shown, a cell structure may include a first device M21, a first P-type MOSFET M22, and a first diode D21. The first device M21 is a field-effect transistor and may include a first control electrode K1, a first electrode E1, and a second electrode E2. The first control electrode K1 is connected to all first gates G1 and second gates G2 in each cell structure. The first electrode E1 is connected to the source in each cell structure, and the second electrode E2 is connected to the drain in each cell structure. The source of the first P-type MOSFET M22 can be connected to the first electrode E1, which can be grounded. The drain of the first P-type MOSFET M22 can be connected to the first control electrode K1. The anode of the first diode D21 is connected to the gate of the first P-type MOSFET M22, and the cathode of the first diode D21 can be connected to the first control electrode K1.

[0051] Because the threshold voltage of the integrated accumulation device in the semiconductor device is low, there is a risk of the device being turned on accidentally. To address this risk, the semiconductor device can be equipped with a first P-type MOSFET M22 and a first diode D21. The gate G of the first P-type MOSFET M22 is the gate of the entire device. When a negative gate voltage is applied to the gate G, the first device M21 can be turned off through the first P-type MOSFET M22. The threshold voltage of the entire semiconductor device is the threshold voltage of the first device plus the voltage drop of the first diode D21, which can increase the threshold voltage of the device and avoid accidental turn-on.

[0052] Specifically, the first control electrode K1 can be fabricated in the same layer as the source electrode S of the cell structure. The first control electrode K1 is insulated from the source electrode S, which simplifies the fabrication process.

[0053] It should be noted that the aforementioned semiconductor devices can be integrated through layout design, including the first device M21, the first P-type MOSFET M22, and the first diode D21. Alternatively, the first P-type MOSFET and the first diode can be connected to the first device M21 via external circuitry.

[0054] In the semiconductor device provided in the embodiments of the present invention, such as Figure 13 As shown, it may include a second device M31, a second P-type MOS transistor M32, and a second diode D31; the second device M31 may also include a second control electrode K2, a third control electrode K3, a third electrode E3, a fourth electrode E4, and multiple identical cell structures; wherein, the second control electrode K2 is connected to all the first gates G1 in the cell structure, and the third control electrode K3 is connected to all the second gates G2 in the cell structure; or, the second control electrode K2 is connected to all the second gates G2 in the cell structure, and the third control electrode K3 is connected to all the first gates G1 in the cell structure; the third electrode E3 is connected to the source S in each cell structure, and the fourth electrode E4 is connected to the drain D in each cell structure.

[0055] Specifically, such as Figure 13 As shown, the source of the second P-type MOSFET M32 is connected to the third electrode E3, which can be grounded. The drain of the second P-type MOSFET M32 is connected to the third control electrode K3, and the gate of the second P-type MOSFET M32 is connected to the second control electrode K2. The anode of the second diode D31 is connected to the gate of the second P-type MOSFET M32, and the cathode of the second diode D31 is connected to the third control electrode K3.

[0056] Because the threshold voltage of the integrated accumulation device in the semiconductor device is low, there is a risk of the device being turned on erroneously. To address this risk, the semiconductor device can be equipped with a second P-type MOSFET M32 and a second diode D31. The gate G' of the second P-type MOSFET M32 is the gate of the semiconductor device. When a negative gate voltage is applied to the gate G', the second P-type MOSFET M32 can be used to turn off the second device M31. By adjusting the voltage drop of the second diode D31, the threshold voltage applied to the second control electrode K2 and the third control electrode K3 in the semiconductor device can be made consistent, thus avoiding the device being turned on erroneously.

[0057] It should be noted that the second device M31, the second P-type MOSFET M32, and the second diode D31 can be integrated into the above semiconductor device through layout design. Alternatively, the second P-type MOSFET and the second diode can be connected to the second device M31 through external circuitry.

[0058] like Figure 14 and Figure 15 As shown, Figure 14 and Figure 15 These are schematic cross-sectional views of a semiconductor device provided in an embodiment of the present invention along a first direction F1 and a second direction F2. In the semiconductor device provided in the embodiment of the present invention, the interlayer dielectric layer 8 may include a first interlayer dielectric layer 81 and a second interlayer dielectric layer 82; the cell structure may also include a first metal connection portion 141, a second metal connection portion 142, a third metal connection portion 143, a first metal interconnect portion and a second metal interconnect portion 15.

[0059] Specifically, the region of the first interlayer dielectric layer 81 opposite to the first gate G1 may have a first via, and the first metal connection portion 141 fills the first via; the region of the first interlayer dielectric layer 81 opposite to the P+ contact region 5 and the first N+ source region 4 may have a second via, and the region of the first interlayer dielectric layer 81 opposite to the second N+ source region 9 may have a third via, and the second metal connection portion 142 fills the second and third vias; the second interlayer dielectric layer 82 and the first interlayer dielectric layer 81 may have a through-hole fourth via, the fourth via being opposite to the second gate G2, and the third metal connection portion 143 filling the fourth via.

[0060] The first metal interconnect, the second metal interconnect 15, and the source electrode S are located on the side of the second interlayer dielectric layer 82 away from the first interlayer dielectric layer 81 and are insulated from each other. The first metal interconnect is connected to the first metal connection 141, the second metal interconnect 15 is connected to the third metal connection 143, the source electrode S is connected to the second metal connection 142, and the first metal interconnect and the second metal interconnect 15 are respectively connected to the second control electrode K2 and the third control electrode K3.

[0061] In the aforementioned semiconductor device, the first metal interconnect portion is connected to the first gate G1 via the first metal connection portion 141, and the second metal interconnect portion 15 is connected to the second gate G2 via the third metal connection portion 143. The first metal interconnect portion and the second metal interconnect portion 15 are respectively connected to the second control electrode K2 and the third control electrode K3. By using different first metal interconnect portions and second metal interconnect portions 15, the first gate G1 and the second gate G2 in the device can be isolated, which facilitates the connection of the first gate G1 and the second gate G2 to the second control electrode K2 and the third control electrode K3, respectively.

[0062] Specifically, the first metal interconnect portion and the second metal interconnect portion 15 can be fabricated in the same layer as the source electrode S, which simplifies the fabrication process; alternatively, the source electrode S can be located on the side of the first metal interconnect portion and the second metal interconnect portion 15 away from the N+ substrate 1, without limitation, depending on the actual situation. The materials of the first metal interconnect portion and the second metal interconnect portion 15 can be the same as or different from the material of the source electrode S, without limitation. The second control electrode K2, the third control electrode K3, the first metal interconnect portion, and the second metal interconnect portion 15 can be fabricated in the same layer or in different layers, without limitation.

[0063] Specifically, a metal contact portion 13 can be formed first in the second and third through holes, followed by a second metal connection portion 142. The source electrode S can achieve ohmic contact with the P+ contact region 5, the first N+ source region 4, and the second N+ source region 9 through the second metal connection portion 142 and the metal contact portion 13. The materials of the first metal connection portion 141, the second metal connection portion 142, and the third metal connection portion 143 can be the same or different; this is not limited here and depends on the actual situation.

[0064] This invention also provides a method for fabricating a semiconductor device, applicable to the fabrication of any of the semiconductor devices described in the above-mentioned technical solutions, such as... Figures 16 to 24 As shown, the specific steps of this manufacturing method include:

[0065] S1601: An N- drift layer is grown on an N+ substrate. Specifically, the N+ substrate can be an N-type heavily doped silicon carbide (SiC) substrate, and the N- drift layer can be an N-type lightly doped silicon carbide region.

[0066] S1602: P+ ions are implanted on the side of the N-drift layer away from the N+ substrate to form a P+ region. P+ ions are implanted on the side of the N-drift layer 2 away from the N+ substrate, i.e., P-type ion heavy doping is performed to form P+ region 501.

[0067] S1603: P-type ions are implanted on the side of the N-drift layer away from the N+ substrate to form a P-region. Specifically, P-type light doping is performed on one side of the P+ region 501 to form the P-region 301.

[0068] S1604: N+ ions are implanted into the N- drift layer on the side facing away from the N+ substrate to form an N+ region. For example... Figure 17 As shown, N-type heavy doping is performed on the side of P region 301 away from the N+ substrate to form N+ region 401.

[0069] S1605: Etching of the P+ region, P region, N+ region, and N- drift layer to form the P+ contact region, P-type body region, first N+ source region, second N+ source region, and first trench. For example... Figure 18 As shown, P+ region 501, P region 301, N+ region 401 and N- drift layer 2 are etched to form P+ contact region 5, P-type body region 3, first N+ source region 4 and first trench 6. The first trench 6 can be an independent block shape.

[0070] S1606: A first gate oxide layer is deposited on the inner wall of the first trench, and a first gate is filled in the first filling trench formed by the first gate oxide layer.

[0071] like Figure 5 As shown, a first gate oxide layer 7 can be deposited on the inner wall of the first trench 6 using a chemical vapor deposition process, and then a first gate G1 is filled in the first filling trench formed by the first gate oxide layer 7. The material of the first gate oxide layer 7 is silicon dioxide, and the material of the first gate is P-type polysilicon. Due to the band difference between P-type and N-type semiconductors, significant depletion occurs in the lightly doped N-type semiconductor. Therefore, significant depletion occurs at the interface between the first gate oxide layer and the N-drift layer.

[0072] S1607: An interlayer dielectric layer is deposited on the side of the N- drift layer away from the N+ substrate.

[0073] like Figure 19 and Figure 20As shown, a silicon dioxide layer can be deposited on the N-drift layer 2 using chemical vapor deposition (CVD). Then, the silicon dioxide layer is patterned using photolithography. After etching, the P+ contact region, the first N+ source region, and the SiC ohmic contact region of the second N+ source region are exposed, forming the interlayer dielectric layer 8. Figure 19 and Figure 20 These are cross-sectional views of a semiconductor device fabricated along a first direction and a second direction, respectively, according to embodiments of the present invention.

[0074] S1608: A source electrode is deposited on the side of the interlayer dielectric layer facing away from the N+ substrate, and a drain electrode is deposited on the side of the N+ substrate facing away from the N- drift layer. For example... Figure 10 and Figure 11 As shown, a source electrode S can be deposited on the side of the interlayer dielectric layer 8 facing away from the N+ substrate 1, and a drain electrode D can be deposited on the side of the N+ substrate 1 facing away from the N- drift layer 2. The source electrode S and the drain electrode D can be made of titanium or can be fabricated in a stacked form; there are no restrictions here. The source electrode S makes ohmic contact with the exposed SiC ohmic contact region.

[0075] In the semiconductor device fabrication method provided in this embodiment of the invention, the fabricated semiconductor device embeds a normally off accumulator device into an enhancement-mode trench gate device. The embedding of the accumulator device can improve the effective utilization rate of the channel of the enhancement-mode trench gate device. Furthermore, the high mobility of the accumulator device channel further reduces the overall on-resistance of the device, and the low electron barrier of the accumulator device can become the electron current path when the enhancement-mode trench gate device is reverse-biased, thereby solving the problems of large diode turn-on voltage drop and long reverse recovery time generated by the enhancement-mode trench gate device.

[0076] In the fabrication method provided by this embodiment of the invention, after etching the P+ region, P region, N+ region and N- drift layer in step S1605, the method may specifically include:

[0077] First, etching is performed to form the P+ contact region 5, the P-type body region 3, the first N+ source region 4, the second N+ source region 9, the first trench 6, and the second trench 10, as follows: Figure 18 As shown;

[0078] Then, a first gate oxide layer 7 is deposited on the inner wall of the first trench 6, and a second gate oxide layer 11 is deposited on the inner wall of the second trench 10; a first gate electrode G1 is filled in the first filling trench formed by the first gate oxide layer 7, and a second gate electrode G2 is filled in the second filling trench formed by the second gate oxide layer 11, as follows. Figure 5 As shown.

[0079] In the manufacturing method provided by the above embodiments of the invention, the first trench 6 and the second trench 10 are manufactured simultaneously, the first gate oxide layer 7 and the second gate oxide layer 11 are prepared in the same layer, and the first gate G1 and the second gate G2 are filled simultaneously, which can reduce the number of manufacturing steps and simplify the manufacturing process.

[0080] In the fabrication method provided in this embodiment of the invention, before depositing the source electrode on the side of the interlayer dielectric layer away from the N+ substrate in step S1608, the following steps may also be included:

[0081] A metal contact portion 13 is deposited on the side of the N-drift layer 2 facing away from the N+ substrate 1, such as... Figure 19 and Figure 20 As shown, after etching the interlayer dielectric layer 8, nickel metal is deposited in the exposed SiC ohmic contact region, and metal contact portion 13 is formed by rapid thermal annealing. This enables ohmic contact between metal contact portion 13 and the exposed P+ contact region 5, the first N+ source region 4, and the second N+ source region 9. The source S is connected to metal contact portion 13 to achieve ohmic contact with the exposed P+ contact region 5, the first N+ source region 4, and the second N+ source region 9.

[0082] In the fabrication method provided in this embodiment of the invention, step S1608, which involves depositing a source electrode on the side of the interlayer dielectric layer away from the N+ substrate, may further include the following steps:

[0083] A first control electrode is deposited on the side of the interlayer dielectric layer 8 facing away from the N+ substrate 1. The first control electrode is insulated from the source electrode. The first control electrode can be connected to the first gate and the second gate of the semiconductor device. The first control electrode is fabricated in the same layer as the source electrode, which has a simple structure, reduces fabrication steps, and simplifies the fabrication process.

[0084] In the fabrication method provided in this embodiment of the invention, step S1607, which involves depositing an interlayer dielectric layer on the side of the N- drift layer away from the N+ substrate, may further include the following steps:

[0085] First, a first interlayer dielectric layer 81 is deposited on the side of the N-drift layer 2 away from the N+ substrate 1.

[0086] Specifically, the first interlayer dielectric layer 81 can be formed by chemical vapor deposition, and the material of the first interlayer dielectric layer 81 can be silicon dioxide.

[0087] Then, the first interlayer dielectric layer 81 is etched to form a first via, a second via, a third via, and a first sub-via, with the first sub-via facing the second gate G2. Specifically, the first interlayer dielectric layer can be etched using photolithography to form the first via, the second via, the third via, and the first sub-via. Specifically, the second and third vias can be formed first using photolithography, with nickel metal deposited within them and rapidly thermally annealed to form metal contacts 13, achieving ohmic contact between the metal contacts and the P+ contact region, the first N+ source region, and the second N+ source region; then, the first sub-via and the first via are formed by photolithography.

[0088] Then, the first metal connecting portion 141 is filled into the first through hole, the second metal connecting portion 142 is filled into the second and third through holes, and the first metal portion 1431 is filled into the first sub-through hole, as follows. Figure 21 and Figure 22 As shown, Figure 21 and Figure 22 These are cross-sectional views of a semiconductor device fabricated along a first direction and a second direction, respectively, according to embodiments of the present invention. Specifically, a layer of titanium metal can be deposited first in the first through-hole, the second through-hole, the third through-hole, and the first sub-through-hole to achieve ohmic contact with the second gate G2; then, a tungsten plug filling process is performed to fill the first through-hole, the second through-hole, the third through-hole, and the first sub-through-hole to form a first metal connection portion 141, a second metal connection portion 142, and a first metal portion 1431, wherein the first metal portion 1431 achieves ohmic contact with the second gate G2.

[0089] Then, a second interlayer dielectric layer 82 is deposited on the side of the first interlayer dielectric layer 81 facing away from the N-drift layer 2. Specifically, the second interlayer dielectric layer can be formed by chemical vapor deposition, and the material of the second interlayer dielectric layer 82 can be silicon dioxide. The second interlayer dielectric layer 82 and the first interlayer dielectric layer 81 together constitute the interlayer dielectric layer 8.

[0090] Then, the second interlayer dielectric layer 82 is etched to form a second sub-via. The second sub-via is opposite to the first sub-via and together with the first sub-via forms a fourth via. Specifically, the second interlayer dielectric layer 82 can be etched using photolithography.

[0091] Next, a second metal portion is filled into the second through hole, and the second metal portion mates with the first metal portion 1431 to form a third metal connecting portion 143, such as... Figure 23 and Figure 24 As shown, Figure 23 and Figure 24 This is a cross-sectional view of a semiconductor device fabricated along a first direction and a second direction, provided for an embodiment of the present invention; specifically, a second metal portion can be formed by filling a second sub-via using a tungsten plug process.

[0092] Step S1608, which involves depositing the source electrode on the side of the interlayer dielectric layer facing away from the N+ substrate, may further include the following steps:

[0093] A first metal interconnect and a second metal interconnect 15 are formed on the side of the interlayer dielectric layer 8 facing away from the N+ substrate 1, such as Figure 14 and Figure 15 As shown. The first metal interconnect portion and the second metal interconnect portion are insulated from each other. The first metal interconnect portion can be connected to the first gate G1 through the first metal connection portion 141, and the second metal interconnect portion can be connected to the second gate G2 through the third metal connection portion 143.

[0094] In the manufacturing method provided by the above embodiments of the invention, the first gate and the second gate in the semiconductor device can be isolated by the provision of the first metal interconnect and the second metal interconnect. The first metal interconnect and the second metal interconnect are fabricated in the same layer as the source, which simplifies the manufacturing process.

[0095] Optionally, the first metal interconnect and the second metal interconnect can be disposed on different layers from the source electrode.

[0096] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the invention. Therefore, if these modifications and variations fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that, It includes at least one cellular structure, the cellular structure comprising an N+ substrate, an N- drift layer, at least one functional region, an interlayer dielectric layer, a source, and a drain; The N-drift layer is located on the N+ substrate; The functional region is embedded in the N-drift layer on the side away from the N+ substrate. The functional region includes two sub-units and a second N+ source region. The sub-units include a P+ contact region, a P-type body region, a first N+ source region, and a first trench gate structure. The first trench gate structure includes a first trench, a first gate oxide layer, and a first gate. In each of the sub-cells, the first N+ source region is located on the surface of the P-type body region away from the N+ substrate, the first trench is located along a first direction between the P-type body region and the first N+ source region and the P+ contact region, the first gate oxide layer covers the inner wall of the first trench and contacts the P-type body region, the first N+ source region, the P+ contact region and the N- drift layer, the inner wall of the first gate oxide layer forms a first filling trench, the first gate is filled in the first filling trench, the P+ contact region has a P+ shielding region, and the P+ shielding region covers the first gate oxide layer located at the bottom of the first trench; The two sub-units are arranged along a second direction, and a second N+ source region is located between the first trench gate structures of the two sub-units. The second direction is perpendicular to the first direction. The source electrode is located on the side of the N- drift layer away from the N+ substrate and is in ohmic contact with the P+ contact region, the first N+ source electrode region and the second N+ source electrode region; The interlayer dielectric layer is located between the N-drift layer and the source electrode, and is used to separate the first gate electrode from the source electrode; The drain is located on the surface of the N+ substrate away from the N- drift layer.

2. The semiconductor device according to claim 1, characterized in that, The functional area comprises two sub-units, namely a first sub-unit and a second sub-unit; The cell structure includes at least two functional regions arranged sequentially along the first direction. In two adjacent functional regions along the first direction, the P+ contact region of the first sub-unit in the preceding functional region is in contact with the P-type body region and the first N+ source region of the first sub-unit in the following functional region, and the P+ contact region of the second sub-unit in the preceding functional region is in contact with the P-type body region and the first N+ source region of the second sub-unit in the following functional region.

3. The semiconductor device according to claim 1, characterized in that, Each of the functional regions also includes a second trench gate structure embedded in the side of the N-drift layer facing away from the N+ substrate; The second trench gate structure is located between the first trench gate structures of the two sub-units. The second trench gate structure includes a second trench, a second gate oxide layer and a second gate. The second trench is disposed on the N-drift layer. The second gate oxide layer covers the inner wall of the second trench. The inner wall of the second gate oxide layer forms a second filling trench. The second gate is filled in the second filling trench. In the functional area, a second N+ source region is provided between adjacent first trench gate structures and second trench gate structures. The first gate oxide layer of the first trench gate structure is in contact with the adjacent second N+ source region, and both sides of the second gate oxide layer of the second trench gate structure are in contact with the adjacent second N+ source region. The interlayer dielectric layer is used to separate the second gate from the source.

4. The semiconductor device according to claim 3, characterized in that, The orthogonal projection of the interlayer dielectric layer on the N+ substrate covers the orthogonal projections of the first trench gate structure and the second trench gate structure on the N+ substrate.

5. The semiconductor device according to claim 3, characterized in that, The cell structure further includes a metal contact portion located on the side of the N- drift layer opposite to the N+ substrate. The metal contact portion makes ohmic contact with the P+ contact region, the first N+ source region and the second N+ source region of each functional region. The source makes ohmic contact with the P+ contact region, the first N+ source region and the second N+ source region of each functional region through the metal contact portion.

6. The semiconductor device according to any one of claims 3-5, characterized in that, Includes a first device, a first P-type MOSFET, and a first diode; The first device includes a first control electrode, a first electrode, a second electrode, and a plurality of identical cell structures. The first control electrode is connected to all first gates and second gates in each cell structure. The first electrode is connected to the source in each cell structure. The second electrode is connected to the drain in each cell structure. The source of the first P-type MOS transistor is connected to the first electrode, and the drain of the first P-type MOS transistor is connected to the first control electrode. The positive terminal of the first diode is connected to the gate of the first P-type MOS transistor, and the negative terminal of the first diode is connected to the first control electrode.

7. The semiconductor device according to claim 6, characterized in that, The first control electrode is fabricated in the same layer as the source electrode of the cell structure.

8. The semiconductor device according to claim 3 or 5, characterized in that, It includes a second device, a second P-type MOS transistor, and a second diode; the second device includes a second control electrode, a third control electrode, a third electrode, a fourth electrode, and multiple identical cell structures. The second control electrode is connected to all the first gates in each of the cell structures, and the third control electrode is connected to all the second gates in each of the cell structures; or, the second control electrode is connected to all the second gates in the cell structure, and the third control electrode is connected to all the first gates in the cell structure. The third electrode is connected to the source electrode in each of the cell structures, and the fourth electrode is connected to the drain electrode in each of the cell structures. The source of the second P-type MOS transistor is connected to the third electrode, the drain of the second P-type MOS transistor is connected to the third control electrode, and the gate of the second P-type MOS transistor is connected to the second control electrode; the anode of the second diode is connected to the gate of the second P-type MOS transistor, and the cathode of the second diode is connected to the third control electrode.

9. The semiconductor device according to claim 8, characterized in that, The interlayer dielectric layer includes a first interlayer dielectric layer and a second interlayer dielectric layer; The cellular structure further includes a first metal connection portion, a second metal connection portion, a third metal connection portion, a first metal interconnect portion, and a second metal interconnect portion; The region of the first interlayer dielectric layer opposite to the first gate has a first via, and the first metal connection portion fills the first via; The region of the first interlayer dielectric layer opposite to the P+ contact region and the first N+ source region has a second via, and the region of the first interlayer dielectric layer opposite to the second N+ source region has a third via. The second metal connection portion fills the second via and the third via. The second interlayer dielectric layer and the first interlayer dielectric layer have a through fourth via, the fourth via being opposite to the second gate, and the third metal connection portion filling the fourth via; The first metal interconnect, the second metal interconnect, and the source are located on the side of the second interlayer dielectric layer away from the first interlayer dielectric layer and are insulated from each other. The first metal interconnect is connected to the first metal connection, the second metal interconnect is connected to the third metal connection, the source is connected to the second metal connection, and the first metal interconnect and the second metal interconnect are respectively connected to the second control electrode and the third control electrode.

10. The semiconductor device according to claim 9, characterized in that, The first metal interconnect, the second metal interconnect, and the source electrode are fabricated in the same layer.

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