A topcon solar cell structure and a preparation method thereof

Abstract

The application relates to the technical field of batteries, in particular to a TOPCon solar cell structure and a preparation method thereof. The main body is an N-type silicon substrate. A boron diffusion doped region, an aluminum oxide passivation layer, a silicon nitride anti-reflection layer and an electrode are arranged on the front surface. The back surface is sequentially provided with a first tunneling oxide layer SiOx1 and a lightly doped poly-Si(n+)1. A second tunneling oxide layer SiOx2, a heavily doped poly-Si(n+)2 and a laser oxidation mask are arranged above the contact area. After alkali washing, the non-contact area poly-Si(n+)2 is removed, and the contact area double-layer poly (SiOx1 / poly-Si(n+)1 / SiOx2 / poly-Si(n+)2) is reserved, so that the contact resistance is reduced and the silver paste is prevented from being burnt through. The non-contact area is only provided with the lightly doped poly-Si(n+)1, and the parasitic absorption is reduced.

Description

Technical Field

[0001] This invention relates to the field of battery technology, and in particular to a TOPCon solar cell structure and its fabrication method. Background Technology

[0002] TOPCon (Tunnel Oxide Passivated Contact) cells, as a type of n-type crystalline silicon solar cell technology that has achieved high-efficiency mass production, have been widely used in the photovoltaic industry in recent years. To further improve its photoelectric conversion efficiency, the industry generally focuses on optimizing the back polycrystalline silicon (poly-Si) layer, among which the back poly-Si thinning process is considered an effective technical path.

[0003] In traditional TOPCon cells, the thickness of the back poly-Si layer typically exceeds 70 nm to ensure good metal contact performance and interface passivation. However, a thicker poly-Si layer can induce significant free-carrier absorption (FCA), reducing the short-circuit current density (Isc) and thus limiting efficiency improvements.

[0004] Currently, there are three main methods for reducing poly-Si thickness:

[0005] Direct deposition of thin poly-Si layers (e.g., ≤60nm): Although this method can reduce FCA and improve parallel resistance (Rsh) while shortening deposition time, excessively thin poly-Si layers can easily lead to an increased risk of metal burn-through, a decrease in interface passivation quality, and exacerbate metal-induced recombination, which may cause problems such as leakage and poor contact, thus having limited effect on overall efficiency improvement.

[0006] Laser-modified PSG-assisted alkaline washing for thinning in non-contact areas: The PSG in the non-contact area is made porous by laser, and the alkaline solution is used to etch and remove the underlying poly-Si, leaving only the thick poly structure in the contact area; the exposed silicon surface in the non-contact area needs to be passivated by additional deposition of alumina (Al2O3).

[0007] High-energy laser directly removes PSG and poly-Si in non-contact areas: High-energy lasers are used to ablate PSG and some poly-Si in non-contact areas, followed by chemical cleaning to remove residual materials. This also requires subsequent Al2O3 passivation.

[0008] However, the second and third methods mentioned above share a common problem: the second and third methods of thinning poly-Si, after back-side polishing to the silicon substrate, require alumina passivation. Alumina is negatively charged and forms a parasitic junction with the n-type substrate, causing current loss. Therefore, this method of poly-Si thinning is unlikely to effectively improve the efficiency of solar cells. The purpose of poly-Si thinning is to reduce parasitic absorption, thereby increasing current density and improving cell efficiency. However, the formation of parasitic junctions still results in current loss, making it difficult to improve cell efficiency.

[0009] In summary, existing poly-Si thinning technologies face a core contradiction: while thinning brings optical gains, it sacrifices electrical performance—either resulting in insufficient passivation / contact performance or the introduction of parasitic recombination mechanisms. Therefore, there is an urgent need for a new approach that can effectively thin the poly in the non-contact region to reduce parasitic absorption, while maintaining a highly doped, thick poly structure in the contact region to ensure low contact resistance and excellent passivation, thereby improving the overall efficiency of TOPCon cells. Summary of the Invention

[0010] This invention relates to a technique for patterned oxidation using lasers and for tunneling oxide layers to withstand alkaline washing. A patterned oxide layer was successfully fabricated using a high-precision green picosecond / femtosecond laser. Subsequently, a poly-finger structure was fabricated through the etching differential of alkaline washing, wherein the contact region employs a double-poly structure, while the non-contact region forms a thin, low-doped poly structure. This method is easier to implement than traditional patterned masks and mask / laser processes. Furthermore, the double-poly structure, with a highly doped outer layer and a low-doped inner layer, combines the advantages of both poly-finger and SE (selective emitter) technologies.

[0011] To achieve the above objectives, the main technical solutions adopted by the present invention include:

[0012] In a first aspect, this application provides a TOPCon solar cell structure, comprising: an N-type silicon substrate, a front structure, and a back structure, wherein the N-type silicon substrate serves as the main substrate of the cell;

[0013] The front structure is located on the front side of the N-type silicon substrate, and is arranged sequentially from the inside to the outside as follows:

[0014] The boron diffusion doping region includes a lightly doped region and a heavily doped region; wherein, the lightly doped region forms a shallow junction region, and the heavily doped region is used to reduce contact resistance.

[0015] An aluminum oxide layer serves as a passivation film on the front surface.

[0016] The front silicon nitride layer serves as an anti-reflective coating and protective layer.

[0017] The front electrode is made of a metallic material and is located above and in contact with the boron diffusion heavily doped region.

[0018] The back structure is located on the back side of the N-type silicon substrate, and is provided sequentially from the inside to the outside as follows:

[0019] The first tunneling oxide layer SiOx1 covers the back of the battery and is located between the N-type silicon substrate and the first n-type polycrystalline silicon layer poly-Si(n+)1, and is used for interface passivation.

[0020] The first n-type polycrystalline silicon layer, poly-Si(n+)1, covers the back of the cell. It is a lightly doped n-type polycrystalline silicon layer that provides good surface passivation.

[0021] The second tunneling oxide layer SiOx2 is disposed between the first n-type polycrystalline silicon layer poly-Si(n+)1 and the second n-type polycrystalline silicon layer poly-Si(n+)2 in the metal contact area, and is used to optimize the interface properties and help suppress the excessive penetration of metal slurry during the sintering process.

[0022] The second n-type polysilicon layer, poly-Si(n+)2, is a heavily doped n-type polysilicon layer and is disposed in the metal contact region to provide field passivation and reduce contact resistance.

[0023] The rear silicon nitride layer covers the back of the battery and serves as an anti-reflective film, a hydrogen passivation source, and a mechanical protective layer.

[0024] The rear electrode is located above the metal contact area and is in contact with the first n-type polycrystalline silicon layer poly-Si(n+)1.

[0025] In a further embodiment, the thickness of the first n-type polycrystalline silicon layer poly-Si(n+)1 is 10–80 nm, the thickness of the second n-type polycrystalline silicon layer poly-Si(n+)2 is 10–80 nm, the thickness of the first tunneling oxide layer SiOx1 is between 0.5 and 3 nm, and the thickness of the second tunneling oxide layer SiOx2 is between 0.5 and 3 nm.

[0026] In a further embodiment, the thickness of the first n-type polysilicon layer poly-Si(n+)1 (202) is 30-40 nm, and the thickness of the second n-type polysilicon layer poly-Si(n+)2 (204) is 50-60 nm.

[0027] In a further embodiment, the following steps are included:

[0028] Step S1

[0029] An N-type silicon substrate with a front electrode structure is provided, and a first tunneling oxide layer SiOx1 is formed on the back side of the N-type silicon substrate;

[0030] Step S2

[0031] A lightly doped n-type polysilicon layer is deposited on the first tunneling oxide layer to form a first n-type polysilicon layer poly-Si(n+)1 covering the entire back side, and a phosphosilicate glass layer is generated on its surface.

[0032] Step S3

[0033] A second tunneling oxide layer SiOx2 is formed on the first n-type polysilicon layer poly-Si(n+)1, followed by the deposition of a heavily doped second n-type polysilicon layer poly-Si(n+)2, and a mask oxide layer is deposited on the surface of poly-Si(n+)2, thereby constructing a stacked structure of SiOx1 / poly-Si(n+)1 / SiOx2 / poly-Si(n+)2 / mask oxide layer;

[0034] Step S4

[0035] The stacked structure is subjected to high-temperature annealing to crystallize the first n-type polycrystalline silicon layer poly-Si(n+)1 and the second n-type polycrystalline silicon layer poly-Si(n+)2.

[0036] Step S5

[0037] Remove the polycrystalline silicon and phosphosilicate glass layer on the front and sides of the silicon wafer, and selectively remove the phosphosilicate glass layer on the back side, while retaining the borosilicate glass on the front side.

[0038] Step S6

[0039] Laser oxidation is performed on the contact area on the back side to form a laser oxidation mask;

[0040] Specifically, using a picosecond or femtosecond ultraviolet laser, laser oxidation is performed on the contact area on the back side according to a preset metal electrode pattern. The laser spot (40-300μm) is used to generate silicon oxide, and a laser oxidation mask with a thickness of 3-15nm is formed in situ in the corresponding area of ​​the mask oxide layer, i.e., a silicon oxide mask.

[0041] Step S7

[0042] The first n-type polysilicon layer poly-Si(n+)2 and the underlying SiOx2 in the non-contact area are removed by alkaline washing and acid washing in a tank. The contact area is retained due to the protection of the silicon oxide mask, thereby forming a patterned back structure with a double-layer poly structure in the contact area and a single-layer poly-Si(n+)1 in the non-contact area.

[0043] Step S8

[0044] The TOPCon solar cell is fabricated by sequentially depositing alumina passivation film on the front or both sides, depositing an antireflection film on the front side, depositing a passivation film on the back side, printing front and back electrodes, and sintering at high temperature.

[0045] In a further embodiment, before forming the first tunneling oxide layer SiOx1 on the back side of the N-type silicon substrate, the following back side pretreatment step is further included:

[0046] The N-type silicon substrate is acid-washed on the back side, and hydrofluoric acid solution is used to remove the residual borosilicate glass formed on the back side due to the boron diffusion process on the front side.

[0047] Subsequently, alkaline polishing is performed on the back side using a mixed solution of KOH and polishing additives, treated under heating conditions to obtain a smooth and clean back surface.

[0048] Specifically, the N-type silicon substrate is subjected to chain-like back-side pickling using a hydrofluoric acid solution with a volume concentration of 20% to 60%.

[0049] During the frontal boron diffusion process, not only is P formed on the front... + This process generates a layer of borosilicate glass (BSG), a layer of boron and silicon oxide-containing glassy byproducts, across the entire silicon wafer surface (including the back side). If BSG remains on the back side, it can affect subsequent processes (such as back passivation, coating, and laser delamination), leading to: surface contamination; reduced passivation effectiveness; increased contact resistance; and decreased cell efficiency.

[0050] Therefore, the BSG on the back side should be removed selectively, while preserving as much of the BSG on the front side as possible. The front side should be facing up and the back side down; a spray head or wetting roller should be placed below to spray the HF solution only onto the back side, with a treatment time of 10–60 seconds.

[0051] Subsequently, alkaline polishing of the back side is performed using a tank-type process. KOH and polishing agent, preferably PS11 polishing additive, are mixed in an alkaline solution at a volume ratio of 2:1 to 5:1. The mixture is treated at 60-70°C for 3-5 minutes, controlling the single-sided thinning amount of the silicon wafer back side to be 0.15-0.4g and the tower base height to be 5-15μm, in order to obtain a flat and clean back side surface.

[0052] In a further embodiment, the step of providing an N-type silicon substrate with a front electrode structure includes:

[0053] Provide N-type silicon wafers as N-type silicon substrates;

[0054] The front side of the N-type silicon substrate is textured to form a light-trapping structure;

[0055] Boron diffusion is performed on the front side to form an initial p-type emitter, and a borosilicate glass layer is formed on the surface;

[0056] The predetermined electrode contact area of ​​the initial p-type emitter is subjected to laser propulsion processing, and the N-type silicon substrate after laser processing is subjected to post-oxidation processing to form a boron diffusion heavily doped region, while the non-contact region remains a boron diffusion lightly doped region.

[0057] An aluminum oxide layer and a front-side silicon nitride layer are deposited sequentially on the front side. Specifically, the steps of providing an N-type silicon substrate (100) with a front electrode structure and completing the back-side pretreatment include:

[0058] 1) Using N-type silicon wafers with a resistivity of 0.5-2 Ω·cm and a minority carrier lifetime greater than 10 ms, alkaline texturing is performed using an aqueous solution of KOH or NaOH and additives at a volume ratio of 2:1 to 5:1, preferably 3:1. The additive is preferably the texturing additive TS53V01. The treatment is carried out at 75-85℃, preferably 80℃, for 6-8 minutes, with the thinning amount controlled at 0.2-0.4g, and the front reflectance controlled at 9.0%-10.5%.

[0059] 2) High-temperature boron diffusion is performed on the front side of the texturized silicon wafer, using BCl3 or BBr3 as the boron source. The volume ratio of BCl3 to oxygen is 1:6 to 1:10, forming a junction depth of 0.2-0.5 μm, preferably 0.2±0.1 μm, with a doping peak concentration of 1-2×10⁻⁶. 20 atoms / cm 3 A p-type emitter with a sheet resistance of 130±5Ω / sq is used, and a borosilicate glass (BSG) layer is formed on the surface.

[0060] High-temperature boron diffusion employs a conventional process. The silicon wafer is heated to 810°C and subjected to initial oxidation at this temperature to create favorable interface conditions. A mixture of boron source gas and oxygen is introduced within the temperature range of 810°C to 960°C to deposit boron. The temperature is further increased to 985°C, and the high temperature propels boron atoms to diffuse into the silicon substrate. The furnace temperature is then raised to a maximum of 1045°C for the final post-oxidation treatment. Finally, the temperature is slowly reduced at a rate of 2-4°C from the maximum temperature of 1045°C to approximately 550°C, completing the entire boron diffusion process.

[0061] 3) Laser treatment of the pre-electrode region pushes surface PSG and shallow boron atoms into the silicon substrate, forming a selective emitter. This increases the junction depth, decreases the peak concentration, and reduces the sheet resistance in the laser-treated area; after SE, the peak concentration decreases to 1-2×10⁻⁶. 19 atoms / cm 3 The junction depth is increased to 1.2±0.22mm, and the sheet resistance is 100+5Ω / sq;

[0062] 4) Post-oxidation is performed on the laser-treated silicon wafer to further propel boron atoms into the substrate and form an oxide layer on the surface of the laser-treated area, ultimately obtaining a lightly doped boron region in the non-contact area and a heavily doped boron region in the contact area; the peak concentration of the p+ region after oxidation is 2-5 × 10⁻⁵. 18 atoms / cm 3 The junction depth was 0.75±0.05 μm, and the peak concentration in the p++ region was 3-8×10⁻⁸ μm. 18 atoms / cm 3 The junction depth is 1.4±0.2μm. The sheet resistance of the p+ region is 380±10Ω / sq, and the sheet resistance of the contact region p++ region is 240±5Ω / sq.

[0063] 5) Chain-type HF cleaning is used to remove BSG wrapping residue from the back and edges of the silicon wafer. The volume concentration of the HF solution is 20%-60%. Subsequently, tank-type alkaline polishing is performed on the back side using an aqueous solution of KOH or NaOH mixed with polishing agent at a volume ratio of 2:1 to 5:1. The solution is treated at 60-70℃ for about 3-5 minutes for rapid polishing, with the thinning amount controlled at 0.15~0.4g and the base thickness at 5-15um. The front side was not corroded because it was protected by BSG.

[0064] Subsequently, an aluminum oxide layer (103) is deposited sequentially on the front side as a front surface passivation film and a silicon nitride layer (104) is deposited on the front side as an anti-reflection film.

[0065] In a further embodiment, step S1, the step of forming a first tunneling oxide layer SiOx1 on the back side of the N-type silicon substrate, includes:

[0066] The back side of the N-type silicon substrate is thermally oxidized using nitrous oxide at a high temperature (430-450℃) for 10-200 seconds to form a first tunneling oxide layer SiOx1 with a thickness of 0.5-3nm.

[0067] In a further embodiment, step S2 includes: using chemical vapor deposition, with silane, phosphine and argon as the reaction gas, or a mixed gas consisting of silane, phosphine and hydrogen at a volume ratio of 2% as the reaction gas, to deposit a lightly doped n-type polycrystalline silicon layer on the first tunneling oxide layer, with a deposition time of 1-15 minutes, preferably 6-8 minutes, and a deposition time of 7 minutes, to form a first n-type polycrystalline silicon layer poly-Si(n+)1 with a thickness of 10-80 nm.

[0068] In a further embodiment, step S3 includes:

[0069] The second tunneling oxide layer SiOx2 is formed by in-situ oxidation using nitrous oxide, with an oxidation time of 10-200 seconds and a thickness of 0.5-3 nm.

[0070] The second n-type polycrystalline silicon layer, poly-Si(n+)2, is formed by chemical vapor deposition using silane, phosphine, and argon as reaction gases, or using a mixed gas consisting of silane, phosphine, and 2% hydrogen by volume as reaction gases. The heavily doped n-type polycrystalline silicon layer is deposited on the second tunneling oxide layer, SiOx2, with a deposition time of 1-15 minutes and a deposition thickness of 10-80 nm.

[0071] The mask oxide layer is formed by chemical vapor deposition of silane and nitrous oxide, with a deposition time of 30-600 seconds and a thickness of 3-60 nm.

[0072] In a further embodiment, the high-temperature annealing treatment in step S4 is performed under a nitrogen atmosphere, with an annealing pressure of 200-600 Pa, an annealing temperature of 880-930 °C, and an annealing time of 30-60 minutes. After annealing, the first n-type polycrystalline silicon layer poly-Si(n+)1 and the second n-type polycrystalline silicon layer poly-Si(n+)2 are crystallized, and their phosphorus doping peak concentrations both reach 1×10⁻⁶. 20 –8×10 20 atoms / cm 3 The inflection point concentration was 4.0 × 10⁻⁶. 18 –9.9×10 18 atoms / cm 3 The thickness of the phosphorus silicate glass layer formed on the surface is 10-30nm.

[0073] In a further embodiment, step S5 specifically involves the following steps:

[0074] A 5%-30% hydrofluoric acid solution is used to remove the phosphosilicate glass and the polycrystalline silicon wrapped around the front and sides of the silicon wafer through a single-sided chain cleaning process.

[0075] Alkaline polishing is performed by mixing potassium hydroxide or sodium hydroxide with polishing additives in a volume ratio of 3:1 to 5:1. The polishing temperature is controlled at 60–80℃ and the polishing time is 2–10 minutes.

[0076] The PSG layer on the back side is removed by either a tank-type hydrofluoric acid cleaning or a single-sided chain-type hydrofluoric acid cleaning, wherein:

[0077] If a tank cleaning method is used, an HF solution with a concentration of 10%-20% should be used, and the treatment time should be 20-180 seconds.

[0078] If a single-sided chain cleaning method is used, a 5% HF solution is used for 1-3 minutes, or a solution of 45-50% nitric acid, 30%-35% hydrofluoric acid, and the remainder water is used for 2-5 minutes.

[0079] The cleaning process preserves the borosilicate glass layer on the front side of the silicon wafer.

[0080] In a further embodiment, step S8 involves performing the following steps sequentially to complete the fabrication of the TOPCon solar cell:

[0081] The second n-type polycrystalline silicon layer poly-Si(n+)2 in the non-laser area on the back side is removed by alkaline washing in a tank. Then, the Si0x2 in the non-laser oxidation area, as well as the laser oxidation mask and BSG on the front side, are removed by hydrofluoric acid cleaning in a tank. Finally, RCA cleaning is used to improve the cleanliness of the front and back surfaces.

[0082] Alumina passivation film deposition:

[0083] In the atomic layer deposition chamber, TMA, nitrogen, and water are periodically introduced under vacuum conditions to deposit an aluminum oxide film on the front or both sides of the solar cell; the thickness of the aluminum oxide film is controlled between 1 and 10 nanometers.

[0084] Frontal antireflection film deposition:

[0085] Using plasma-enhanced chemical vapor deposition (PECVD), SiNx or at least one of SiOx, SiNx, and SiOxNy is sequentially deposited to form a multilayer antireflective film. The total film thickness should be maintained in the range of 70 to 90 nanometers, and the refractive index should be controlled between 1.9 and 2.1.

[0086] Backside passivation film deposition:

[0087] One or more passivation films composed of SiOxNy, SiOx, and SiNx are deposited on the back of a solar cell using the PECVD method. The total film thickness should be between 80 and 110 nanometers, and its refractive index should be set to 2.0 to 2.2.

[0088] Front and back electrode printing and high-temperature sintering:

[0089] The back electrode and back grid lines are printed, followed by the front electrode and grid lines. After printing, a high-temperature sintering process is performed, with the temperature controlled between 750°C and 850°C, to ensure good contact between the electrodes and the battery and improve battery performance.

[0090] Laser-enhanced passivated contacts and anti-photo-attenuation injection:

[0091] Laser-enhanced passivation contact treatment is performed through electrical or optical injection, and anti-photo-induced degradation injection is implemented to improve the conversion efficiency and long-term stability of solar cells.

[0092] Beneficial effects:

[0093] The TOPCon solar cell structure provided by this invention optimizes optical and electrical performance by constructing a local double-layer polycrystalline silicon contact region (poly-finger structure) on the back side. In the metal contact region, a complete SiOx1 / poly-Si(n+)1 / SiOx2 / poly-Si(n+)2 stacked structure is retained. The heavily doped poly-Si(n+)2 significantly reduces contact resistance, while SiOx2 acts as a barrier layer to effectively suppress silver paste burn-through and metal-induced recombination. In the non-contact region, only a lightly doped poly-Si(n+)1 layer is retained, significantly reducing parasitic absorption of free carriers caused by thick polycrystalline silicon and increasing short-circuit current density. Simultaneously, this structure avoids the parasitic junction problem caused by introducing negatively charged alumina passivation after exposing the silicon substrate in traditional thinning processes, maintaining excellent surface passivation quality without additional passivation media. On the front side, a boron-diffused selective emitter and an alumina / silicon nitride composite passivation anti-reflection system are employed to further reduce surface recombination and enhance light-harvesting capabilities. The overall structure balances low contact resistance, high passivation level and low optical loss, significantly improving the battery open-circuit voltage, short-circuit current and fill factor, thereby achieving higher photoelectric conversion efficiency. Attached Figure Description

[0094] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0095] Appendix Figure 1 This is a structural diagram of an N-type silicon wafer after alkaline texturing treatment;

[0096] Appendix Figure 2 This is a back-side structure diagram of an N-type silicon wafer after deposition of a SiOx1 / poly-Si(n+)1 / SiOx2 / poly-Si(n+)2 stacked structure and high-temperature annealing and crystallization.

[0097] Appendix Figure 3 To remove the front and back phosphorosilicate glass (PSG) and the structure after removing the front polycrystalline silicon, the SiOx1 / poly-Si(n+)1 / SiOx2 / poly-Si(n+)2 stacked structure on the back and the borosilicate glass (BSG) on the front were retained.

[0098] Appendix Figure 4 This is a laser oxidation mask formed after oxidation treatment of the back metal contact area using ultraviolet picosecond or femtosecond lasers. This mask covers the surface of the stacked structure and is used to protect the contact area in the subsequent alkaline washing process.

[0099] Appendix Figure 5 The back-side patterned structure is formed after alkaline washing and hydrofluoric acid cleaning in a tank. The poly-Si(n+)2 in the non-contact area is removed, and only the double-layer poly-Si structure in the contact area is retained to realize the poly-finger structure.

[0100] Appendix Figure 6 To complete the full structure of the TOPCon solar cell after electrode printing and high-temperature sintering.

[0101] Explanation of reference numerals in the attached figures:

[0102] 100: N-type silicon substrate (N-type silicon wafer); 101: Boron diffusion lightly doped region; 102: Boron diffusion heavily doped region; 103: Alumina layer; 104: Front silicon nitride layer; 105: Front electrode; 110: Borosilicate glass (BSG); 201: First tunneling oxide layer SiOx1; 202: First n-type polycrystalline silicon layer poly-Si(n+)1; 203: Second tunneling oxide layer SiOx2; 204: Second n-type polycrystalline silicon layer poly-Si(n+)2; 205: Back silicon nitride layer; 206: Back electrode; 210: Phosphosilicate glass (PSG); 211: Laser oxidation mask. Detailed Implementation

[0103] The embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to illustrate the principles of this application by way of example, but should not be used to limit the scope of this application. This application can be implemented in many different forms and is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

[0104] These embodiments are provided to make the application thorough and complete, and to fully express the scope of the application to those skilled in the art. It should be noted that, unless otherwise specifically stated, the relative arrangement of components and steps, material composition, numerical expressions, and values ​​illustrated in these embodiments should be interpreted as merely exemplary and not as limiting.

[0105] It should be noted that, in the description of this application, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicating orientation or positional relationship, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0106] Furthermore, the terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. "Vertical" is not strictly vertical, but within the permissible margin of error. "Parallel" is not strictly parallel, but within the permissible margin of error. Terms such as "including" or "contains" mean that the element preceding the word encompasses the element listed after it, and do not exclude the possibility of encompassing other elements as well.

[0107] All terms used in this application have the same meaning as understood by one of ordinary skill in the art to which this application pertains, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant art, and not as idealized or highly formalized, unless expressly defined herein.

[0108] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, they should be considered part of the specification.

[0109] All parameters not mentioned in the text refer to conventional processes.

[0110] The poly-finger structure is a back-side patterned polycrystalline silicon (poly-Si) electrode contact structure proposed in this invention. On the back side of the TOPCon solar cell, a thicker, highly doped double-layer polycrystalline silicon structure is retained only in the area where the metal electrode will be printed (i.e., the contact area), while the outer polycrystalline silicon layer is removed in the non-electrode area (i.e., the non-contact area), leaving only a thin layer of lightly doped inner polycrystalline silicon, thereby forming a highly doped poly region with a finger-like distribution—hence the name poly-finger (polycrystalline silicon finger structure).

[0111] In this application, the silicon substrate is oriented from the inside out towards the surface.

[0112] The thinning amount in this application refers to the mass loss of each 182mm×182mm×150μm N-type silicon wafer during the back-side alkaline polishing process. 0.15-0.4g corresponds to an average etching depth of approximately 0.3-0.8μm.

[0113] The front of the battery can use either an SE (Self-Contact) structure or a non-SE structure. The SE technology on the front is combined with LECO technology, resulting in a sheet resistance of 400-800 Ω / sq for the non-contact area and 80-300 Ω / sq for the contact area. The TOPCon layer on the back contact area uses a multilayer structure of SiOx1 / poly-Si(n+)1 / SiOx2 / poly-Si(n+)2, while the non-contact area uses a single-layer structure of SiOx1 / poly-Si(n+)1. The so-called tunneling oxide layer specifically refers to an oxide layer containing SiOx that enables the tunneling effect. Here, we refer to it as the first SiOx layer, or SiOx1, with a thickness between 0.5-3 nm. The contact area is further covered with a layer of SiOx on top of the poly-Si(n+), called the second SiOx layer, or SiOx2, with a thickness between 0.5-3 nm. Poly-Si(n+)1 serves as the first layer of poly-Si(n+), and poly-Si(n+)2 serves as the second layer of poly-Si(n+). This unique structure on the back of the n-TOPCon cell utilizes ultraviolet picosecond or femtosecond lasers to oxidize the poly-Si, forming a silicon dioxide protective film. The unoxidized poly-Si(n+)2 areas are then removed by alkaline washing, while the laser-oxidized areas, protected by silicon dioxide, remain unaffected, forming a unique poly-finger structure. Thinning the poly-Si layers in this stacked structure, and using a double-layer poly-Si structure in the non-contact areas, facilitates back-side passivation, improves contact, reduces metal-to-metal recombination, and removes some of the poly-Si in the non-contact areas through washing, achieving a poly-Si thinning effect and improving the efficiency of the solar cell.

[0114] This invention utilizes a SiOx1 / poly-Si(n+)1 / SiOx2 / poly-Si(n+)2 stacked structure, followed by a stripping and cleaning process to remove the SiOx1 / poly-Si(n+)1 / SiOx2 / poly-Si(n+)2 stacked structure on the front and four sides. Since the BSG is thicker and its alkali corrosion rate is lower than that of PSG, the back PSG protective film can be removed by a tank-type HF cleaning, while the front BSG is retained. Then, a laser is used to pattern an oxide mask (contact area). Finally, a tank-type alkaline cleaning thins the back poly-Si (outer poly layer removed). Retaining the SiOx1 / poly-Si(n+)1 / SiOx2 / poly-Si(n+)2 stacked structure in the gate area effectively reduces metal J0, while retaining the inner poly-Si(n+)1 in the non-contact area reduces parasitic absorption. In this invention, the non-metallic contact area on the back is thinned poly-Si, resulting in reduced parasitic absorption and increased current density. The metal contact region has a stacked poly-Si structure with a high doping concentration in the outer layer, which is beneficial for passivation and contact. Violet picosecond and femtosecond lasers are used, offering short wavelengths and minimal damage.

[0115] The first n-type polycrystalline silicon layer, poly-Si(n+)1, is abbreviated as poly-Si(n+)1, and the second n-type polycrystalline silicon layer, poly-Si(n+)1, is abbreviated as poly-Si(n+)2.

[0116] In this application, X and Y can be integers, such as 1, 2, 3, etc.

[0117] Appendix Figure 1-6 The accompanying drawings are preferably from Embodiment 1.

[0118] The process details not disclosed in this application are all conventional process technical parameters.

[0119] The specific implementation steps and key technical details will be elaborated below.

[0120] This invention primarily utilizes a purple laser to oxidize the poly-Si surface, generating an oxide layer resistant to alkaline corrosion during poly-plating removal. Then, alkaline washing removes the poly-Si (poly-Si(n)2) in the non-laser-treated areas down to the central SiO2 oxide layer. The laser-oxidized region retains the SiOx1 / poly-Si(n+)1 / SiOx2 / poly-Si(n+)2 structure, achieving a thin-thick poly-finger effect on the back side. This invention realizes a poly-finger structure on the back side of an N-type TOPCon cell. The SiOx2 in the contact area prevents silver paste burn-through, significantly reducing the metal recombination current density. The thin poly in the non-contact area is lightly doped, reducing parasitic absorption on the back side while ensuring lateral carrier transport. This cell structure significantly improves the photoelectric conversion efficiency of the cell.

[0121] There are slight deviations in the numerical values ​​between the embodiments in this application, all of which are within a controllable range. For example, in step 1, the thinning amount is controlled at about 0.25±0.03g; in step 2, the B diffusion junction depth is 0.22μm±0.1μm and the sheet resistance is 130±5Ω / sq; in step 3, the junction depth increases by 1.2μm±0.22μm and the sheet resistance is ±5Ω / sq; in step 4, the junction depth is 0.75μm±0.05um, 1.4μm±0.2μm, 380±10Ω / sq, and 240±5Ω / sq; in step 6, the thinning amount is controlled at 0.30±0.02g and the base thickness is 12±2um; in step 7, the thickness is about 1.6±0.2nm; the thickness is 42±2nm; the thickness is 70±3nm; in step 8, the thickness is 30±2nm and 50±3nm; in step 1, the thickness is 106±2nm, etc.

[0122] Example 1

[0123] Step 1 involves alkaline texturing of an N-type silicon wafer with a resistivity of 1.5 Ω·cm and a minority carrier lifetime of 12 ms to form a pyramid structure that traps light on the surface; rapid texturing is performed by using a mixed solution of KOH and additive (TS53V01) in a ratio of 3:1 at 80°C for 8 min, with the thinning amount controlled at 0.25 g and the reflectivity at 9.5%.

[0124] Step 2 involves high-temperature boron diffusion using BCl3, with a BCl3 to oxygen ratio of 1:6, a sheet resistance of 130 Ω / sq, forming a shallow junction, and a doping peak concentration of 1×10⁻⁶. 20 atom / cm 3 The depth of the first B diffusion junction is 0.22 μm.

[0125] Step 3: Laser SE forms a selective emitter; after SE, the peak concentration decreases to 1.4 × 10⁻⁶. 19 atoms / cm 3The junction depth is increased to 1.2 μm, and the sheet resistance is 100 Ω / sq.

[0126] A nanosecond pulsed laser with a wavelength of 532 nm and an energy density of 2.5 J / cm² was used. 2 The scanning speed was 500 mm / s, the spot diameter was 80 μm, and the overlap rate was 70%. The boron diffusion region was locally melted and advanced under a nitrogen atmosphere to form a selective emitter.

[0127] Step 4 involves post-oxidation, which further propels boron atoms into the substrate while simultaneously forming an oxide layer on the surface of the laser region. After oxidation, the peak concentration in the p+ region is 3.2 × 10⁻⁶. 18 atoms / cm 3 The junction depth was 0.75 μm, and the peak concentration in the p++ region was 5.4 × 10⁻⁶. 18 atoms / cm 3 The junction depth is 1.4 μm. The sheet resistance of the p+ region is 380 Ω / sq, and the sheet resistance of the contact region p++ is 240 Ω / sq.

[0128] Step 5 involves removing the BSG buildup around the back and sides using a chain-type HF cleaning process with an HF concentration of 40%.

[0129] Step 6 is groove-type back polishing. The front side, protected by BSG, did not react, while the rear, enlarged area was polished away. Polishing was performed using KOH:PS11 polishing compound in a 3:1 ratio, at a temperature of 65℃ for approximately 4 minutes, with a thinning amount controlled at 0.30g. After polishing, the side length of the pyramid base was 12μm. This resulted in a shape resembling... Figure 1 The structure shown.

[0130] Step 7 involves the fabrication of the SiOx1 / poly-Si(n+)1 / SiOx2 / poly-Si(n+)2 stacked structure: The SiOx1 layer was prepared by oxidation with nitrous oxide for 100 seconds, resulting in a thickness of approximately 1.6 nm; the poly-Si(n+)1 layer was prepared using a mixture of silane and phosphine with hydrogen (hydrogen volume ratio of 2%), a silane to phosphine volume ratio of 1:1, at a pressure of 200 Pa for 7 minutes, resulting in a thickness of 42 nm; the SiOx2 layer— Oxidation was performed using nitrous oxide for 100 seconds, resulting in a thickness of approximately 1.8 nm. A poly-Si(n+)2 layer was then deposited under the same gas conditions as the poly-Si(n+)1 layer for 12 minutes, achieving a thickness of 70 nm. A mask oxide layer was then deposited on the outer layer of SiOx1 / poly-Si(n+)1 / SiOx2 / poly-Si(n+)2 using silane (80 sccm) and nitrous oxide (1200 sccm) for 200 seconds, resulting in a thickness of 20 nm.

[0131] Then, the wafer undergoes step 8, high-temperature annealing and crystallization. Annealing is performed using nitrogen at a pressure of 400 Pa, with an annealing temperature of 910℃ and a time of 45 min. After annealing, the poly-Si(n+)1 layer thickness is reduced to 30 nm, and the poly-Si(n+)2 layer thickness is reduced to 50 nm. The peak concentration of the two poly-Si(n) layers is 3 × 10⁻⁶. 20 atoms / cmm 3 and 3.6×10 20 atoms / cmm 3 The film after step 8 is as follows Figure 2 As shown.

[0132] Step 9 involves removing the phosphosilicate glass (PSG) from the front surface and the polysilicon from the front side. The PSG on the front and sides is removed using a single-sided chain cleaning process with 20% hydrofluoric acid. Then, an alkaline polishing process is used, with potassium hydroxide and polishing additive in a 4:1 ratio, maintained at 70°C for approximately 6 minutes. Finally, the PSG on the back side is removed using a single-sided chain cleaning process with 5% hydrofluoric acid (HF). The structure after step 9 is as follows: Figure 3 As shown.

[0133] Step 10 is laser masking—using a purple laser with a spot size of 120 μm, laser oxidation is performed to generate silicon oxide. Figure 4 In this case, the silicon oxide mask thickness is 6 nm.

[0134] A 355nm ultraviolet nanosecond laser with an average power of 8W, a repetition rate of 200kHz, and a spot diameter of 120μm was used to scan at a speed of 300mm / s in an oxygen atmosphere (flow rate of 500sccm) to grow a local silicon oxide mask with a thickness of about 6nm in situ.

[0135] Step 11 involves alkaline washing in a tank to remove poly-Si(n+)2 from the non-laser-oxidized area on the back side, followed by hydrofluoric acid cleaning in a tank to remove SiOx2 from the non-laser-oxidized area, as well as the laser oxidation mask and BSG from the front side. Finally, RCA cleaning is used to improve the cleanliness of both the front and back surfaces. The structure after step 11 is as follows: Figure 5 As shown.

[0136] Using a 25wt% TMAH solution, the poly-Si(n+)2 layer not covered by the silicon oxide mask was selectively etched at 80℃ for 3 minutes. The etching selectivity ratio for SiO2 was greater than 50:1, ensuring that the poly structure of the laser oxidation region was preserved.

[0137] Step 12 involves front-side or double-sided alumina deposition. Under vacuum conditions within the ALD chamber, TMA, N2, and H2O are periodically introduced to deposit 3 nm of alumina on both sides. Step 13 involves front-side antireflection film deposition, using PECVD to sequentially deposit a multilayer structure of SiOx, SiNx, and SiOxNy, with a total film thickness of 80 nm and a refractive index of 2.0. Step 14 involves back-side passivation film deposition, using PECVD to deposit SiOxNy, SiOx, and SiNx, with a total film thickness of 100 nm and a refractive index of 2.2. Step 15 involves back-side electrode printing, back-side gate line printing, front-side electrode and gate line printing, followed by high-temperature sintering at 830°C. The structure after step 15 is shown below. Figure 6 As shown.

[0138] Step 16 involves laser-enhanced passivation of the LECO contact and anti-LID injection.

[0139] An infrared laser with a wavelength of 1064nm and a power of 40W is used, with a power density of 60kW / cm². 2 The scanning speed is 60 m / s, and a reverse voltage of 10-20 V is applied. Compared with traditional sintering processes, the sintering temperature can be reduced by 20-40℃, with 790℃ being optimal. Low-temperature sintering is beneficial for passivation. Laser irradiation of the solar cell, coupled with the application of a reverse voltage, creates a localized high current. This high current density generates hotspots, initiating sintering and causing silver-silicon interdiffusion to form a silver-silicon alloy, thus creating a good ohmic contact.

[0140] Example 2

[0141] This embodiment is the same as Embodiment 1, except that in step 7, the poly-Si(n+)1 layer is prepared in 10 minutes with a thickness of 58 nm, and in step 8, the thickness of poly-Si(n+)1 becomes 40 nm after crystallization, and the thickness of poly-Si(n+)2 layer is 50 nm.

[0142] Example 3

[0143] This embodiment is the same as Embodiment 1, except that in step 7, the poly-Si(n+)2 layer has a time of 15 minutes and a thickness of 87 nm, while in step 8, the thickness of the poly-Si(n+)2 layer becomes 60 nm, and the thickness of the poly-Si(n+)1 layer becomes 30 nm after crystallization.

[0144] Comparative Example 1

[0145] This embodiment is the same as Embodiment 1, except that...

[0146] 7) TOPCon layer fabrication: The tunneling oxide layer was oxidized using nitrous oxide for approximately 100 seconds, resulting in a thickness of 1.6 nm. The a-Si(n+) layer was deposited using a mixture of silane, phosphine, and hydrogen gas (2% H2, PH3) at a pressure of 200 Pa for approximately 19 minutes, resulting in a thickness of 120 nm. The mask oxide layer was deposited using silane and nitrous oxide for 200 seconds, resulting in a thickness of 20 nm.

[0147] 8) Annealing – Annealing is performed using nitrogen (N2) at a pressure of 400 Pa for approximately 45 minutes at a temperature of 910 °C. a-Si(n+) crystallizes into poly-Si(n+), reducing the thickness to 80 nm. After annealing, the peak concentration of poly-Si(n) is 3.4 × 10⁻⁶. 20 atoms / cm 3 .

[0148] Comparative Example 2

[0149] This embodiment is the same as embodiment 1, except that:

[0150] 7) TOPCon layer fabrication: tunneling oxide layer (SiOx1) 1.6 nm; a-Si(n+) layer thickness 100 nm (70 nm poly after annealing); no second poly or SiOx2 was deposited;

[0151] 8) Annealing: 910℃, 45min, to form thick poly-Si(n+);

[0152] 9) The front treatment is the same as in Example 1;

[0153] 10) Low-energy laser modification of PSG: using ultraviolet light at 355nm, with an energy density of 1.0J / cm². 2 Only the non-contact area of ​​PSG is scanned to make it loose and porous without damaging poly or SiOx1.

[0154] 11) Tank alkaline washing: Using 25% TMAH, 80°C, 5–8 min, the alkaline solution penetrates through the loose PSG and selectively corrodes the underlying poly-Si, only the non-contact poly is removed, and SiOx1 is retained; then HF is used to remove the PSG.

[0155] 13) Deposit Al2O3 (8nm) to passivate the exposed area; subsequent steps are the same as in Example 1.

[0156] Comparative Example 3

[0157] This embodiment is the same as Embodiment 1, except that in 7) the TOPCon layer is prepared, the tunneling oxide layer is oxidized with nitrous oxide for about 100 seconds, and the thickness is 1.6 nm; the a-Si(n+) layer is deposited with silane, phosphine mixed with hydrogen (2% H2, PH3) at a pressure of 200 Pa for about 8 minutes, and the thickness is 60 nm; the second tunneling oxide layer SiOx2, the second n-type polycrystalline silicon layer poly-Si(n+)2 and the mask oxide layer are not deposited, and the back structure is only a single layer of a-Si(n+) covering.

[0158] 8) Annealing – Annealing is performed using nitrogen gas at a pressure of 400 Pa for approximately 45 minutes at a temperature of 910 °C. This process crystallizes a-Si(n+) into poly-Si(n+), reducing the thickness to approximately 45 nm. The peak phosphorus doping concentration is 3.2 × 10⁻⁶. 20 atoms / cm 3 ;

[0159] 9) Remove the BSG and poly coatings from the front and sides (same as steps 5-6 in Example 1).

[0160] 10) High-energy green nanosecond laser (wavelength 532nm, energy density 4.0J / cm²) is used. 2 With a spot diameter of 80 μm, a scanning speed of 300 mm / s, and an overlap of 75%, high-energy ablation was performed on the non-contact area on the back side under a nitrogen atmosphere to completely remove the poly-Si(n+) layer and the underlying tunneling oxide layer (SiOx1) in the area, exposing the n-type silicon substrate; the poly-Si in the contact area remained intact.

[0161] 11) Subsequently, alkaline washing (TMAH 25wt%, 80℃, 3min) and HF cleaning (5%, room temperature, 2min) were performed to thoroughly remove ablation residue and poly residue on the sidewalls;

[0162] 12) Additional Al2O3 passivation layer: An 8 nm thick Al2O3 layer is deposited on the back side in the ALD chamber to passivate the exposed n-type silicon surface;

[0163] 13) Front passivation and antireflection film deposition (same as steps 12-13 in Example 1).

[0164] 14) The back passivation film is changed to: a layer of SiNx (PECVD, thickness 80nm, refractive index 2.0) is coated on Al2O3 as a protection and hydrogen source;

[0165] 15) Electrode printing and sintering (same as step 15 in Example 1);

[0166] 16) LECO and anti-LID treatment (same as step 16 in Example 1).

[0167] Comparative Example 4

[0168] This embodiment is the same as Embodiment 1, except that the steps are different.

[0169] 7) TOPCon layer fabrication: The tunneling oxide layer (SiOx1) was formed by thermal oxidation of nitrous oxide at 850°C for about 100 seconds, with a thickness of 1.6 nm; the a-Si(n+) layer was deposited by LPCVD at 200 Pa and 600°C using a mixture of silane, phosphine and 2% hydrogen gas for about 8 minutes, with a thickness of 60 nm; the second tunneling oxide layer (SiOx2), the second n-type polycrystalline silicon layer (poly-Si(n+)2) and the mask oxide layer were not deposited, and the back structure was only covered by a single layer of a-Si(n+);

[0170] 8) Annealing: The annealing process is carried out using nitrogen gas at a pressure of 400 Pa for about 45 minutes at a temperature of 910 °C. The a-Si(n+) crystallizes and transforms into poly-Si(n+), and the thickness shrinks to about 45 nm.

[0171] Comparative Example 5

[0172] This embodiment is the same as Embodiment 1, except that the steps are different.

[0173] 7) TOPCon layer preparation: SiOx1 layer was oxidized with nitrous oxide for 100 s, with a thickness of 1.6 nm; poly-Si(n+)1 layer was deposited for 4 min, with a deposited thickness of approximately 24 nm; SiOx2 layer was oxidized with nitrous oxide for 100 s, with a thickness of 1.8 nm; poly-Si(n+)2 layer was deposited for 6 min, with a deposited thickness of approximately 35 nm; mask oxide layer was prepared using silane / nitrous oxide for 200 s, with a thickness of 20 nm.

[0174] 8) Annealing: Nitrogen gas, 400 Pa, 910 °C, 45 min; after crystallization, the thickness of poly-Si(n+)1 is 18 nm; after crystallization, the thickness of poly-Si(n+)2 is 25 nm.

[0175] Comparative Example 6

[0176] This embodiment is the same as Embodiment 1, except that step 7) TOPCon layer preparation is different:

[0177] The SiOx1 layer was oxidized with nitrous oxide for 100 s, with a thickness of approximately 1.6 nm; the poly-Si(n+)1 layer was silane / phosphine / hydrogen (2%), at a pressure of 200 Pa, for 7 min, with a thickness of 42 nm; the SiOx2 layer was oxidized with nitrous oxide for 100 s, with a thickness of 1.8 nm; the poly-Si(n+)2 layer was deposited under the same gas conditions for 12 min, with a thickness of 70 nm; the SiOx3 layer was oxidized with nitrous oxide for 100 s, with a thickness of approximately 1.7 nm; the poly-Si(n+)3 layer was deposited under the same gas conditions for 8 min, with a thickness of 48 nm.

[0178] The mask oxide layer covers the outermost layer of poly-Si(n+)3), silane (80 sccm) + nitrous oxide (1200 sccm), deposited for 200 s, with a thickness of 20 nm;

[0179] 8) Annealing: Nitrogen gas, 400 Pa, 910 °C, 45 min; the thickness of poly-Si(n+)1 after crystallization is 30 nm; the thickness of poly-Si(n+)2 after crystallization is 50 nm; the thickness of poly-Si(n+)3 after crystallization is 35 nm; the peak phosphorus doping concentration of each layer is 3.0 × 10⁻⁶. 20 3.6×10 20 3.4×10 20 atoms / cm 3 .

[0180] Comparative Example 7

[0181] This embodiment is the same as Embodiment 1, except that step 7 skips the SiOx2 layer deposition step.

[0182] Comparative Example 8

[0183] This embodiment is the same as Embodiment 1, except that in step 7), the SiOx1 layer is oxidized with nitrous oxide for about 100 seconds, and the thickness is about 1.6 nm; the poly-Si(n+)1 layer is deposited with a mixture of silane and phosphine hydrogen gas (2% H2) at a pressure of 200 Pa for about 7 minutes, and the thickness is 42 nm.

[0184] A local mask was generated by laser oxidation on the surface of the poly-Si(n+)1 layer: a 355nm ultraviolet nanosecond laser with an average power of 8W, a repetition rate of 200kHz, and a spot diameter of 120μm was used to grow a silicon oxide mask with a thickness of about 6nm in situ under an oxygen atmosphere (500sccm) at a scanning speed of 300mm / s; then a SiOx2 layer (nitrous oxide oxidation, 100s, 1.8nm) and a poly-Si(n+)2 layer (same gas conditions, 12min, 70nm) were deposited to cover the entire back side (including the area of ​​the laser mask); no additional mask oxide layer was deposited on the outer layer.

[0185] 11) Tank alkaline washing: Use 25wt% TMAH solution, 80℃, soak for 3min; Since the poly-Si(n+)2 layer has no effective mask protection, the poly-Si(n+)2 on the entire back side is uniformly removed, and finally only the SiOx1 / poly-Si(n+)1 / SiOx2 structure is retained in both the contact area and the non-contact area.

[0186] Comparative Example 9

[0187] This comparative example is the same as Comparative Example 1. The difference is that in step 7, the deposition time of the poly-Si(n+)1 layer was extended from 7 min to 12 min, and the thickness of the deposited state was 70 nm.

[0188] In step 7, the poly-Si(n+)2 layer was prepared, and the deposition time was shortened from 12 min to 6 min, with a deposition thickness of approximately 38 nm.

[0189] After step 8, high-temperature annealing:

[0190] The thickness of poly-Si(n+)1 layer after crystallization is approximately 51 nm; the thickness of poly-Si(n+)2 layer after crystallization is approximately 32 nm.

[0191] The above-described embodiments and comparative data were tested accordingly, and the test data are shown in the table below.

[0192]

[0193] Comparative Example 1 uses a conventional single-layer thick poly-Si structure (80 nm thick after annealing) without introducing a double-layer poly or patterned thinning process. Its open-circuit voltage (UOC), fill factor (FF), and conversion efficiency (Eta) are all significantly lower than those of Examples 1–3. This indicates that although the excessively thick poly-Si layer ensures contact performance, it induces severe free carrier parasitic absorption (FCA), suppressing the increase in short-circuit current density (Isc). At the same time, the excessively high doping concentration may lead to increased interfacial recombination, thereby limiting the open-circuit voltage (UOC) and fill factor (FF).

[0194] Comparative Example 2 used laser-modified PSG-assisted alkaline washing to thin the non-contact poly layer, and then deposited an additional Al2O3 passivation layer on the exposed silicon surface. Although its fill factor (FF) was slightly higher than that of Comparative Example 1, its conversion efficiency (Eta) was still significantly lower. The reason is that Al2O3 is a negatively charged dielectric, which forms a parasitic junction on the back side of the n-type silicon, causing carrier transport to be hindered and triggering additional recombination losses, thus offsetting the optical gain brought about by poly thinning.

[0195] Comparative Example 3 uses a high-energy laser to directly ablate the non-contact poly layer and tunneling oxide layer, exposing the silicon substrate, and also relies on Al2O3 for passivation. Its performance further degrades. The high-energy laser not only destroys the integrity of the SiOx1 tunneling layer but may also introduce lattice damage, exacerbating the interface state density; subsequent Al2O3 passivation cannot completely repair this damage, and the parasitic junction effect persists. Although this approach achieves poly thinning, it comes at the cost of passivation quality and electrical performance, limiting the improvement in conversion efficiency (Eta).

[0196] Comparative Example 4 uses only a thin monolayer of poly-Si (approximately 45 nm after annealing), without any bilayer structure or patterning. Its conversion efficiency (Eta) is among the lowest of all comparative examples. Although the thin poly layer reduces free carrier parasitic absorption (FCA), the lack of a heavily doped contact layer increases the contact resistance between the metal electrode and the poly layer, leading to a decrease in the fill factor (FF). The lightly doped monolayer poly layer cannot effectively suppress metal-induced recombination in the contact region, and the open-circuit voltage (UOC) is also limited. This demonstrates that simply thinning the poly layer without optimizing the contact structure makes it difficult to achieve both low resistance and high passivation.

[0197] Although Comparative Example 5 constructed a bilayer poly structure, the thickness of each layer was significantly too thin (poly-Si(n+)1 was only 18 nm, and poly-Si(n+)2 was only 25 nm). Excessively thin poly layers are prone to discontinuities or pinholes during alkaline washing or sintering, affecting the tunneling passivation effect. Simultaneously, insufficient heavily doped layers lead to increased contact resistance, resulting in poor fill factor (FF) and open-circuit voltage (UOC) data. These results indicate that a balance needs to be struck between sufficiently thin poly layers to reduce absorption and sufficiently thick layers to ensure electrical performance; the ranges in the embodiments of this invention are more reasonable.

[0198] Comparative Example 6 attempted to introduce a three-layer poly structure (poly-Si(n+)1 / 2 / 3), but the structure was overly complex. Although the doping concentration of each layer met the requirements, the multilayer interface may introduce additional defect states, and the process control is difficult, leading to a deterioration in overall performance. Without a patterned selective retention mechanism, the entire back side is thick poly, and parasitic absorption is not effectively reduced. This approach deviates from the core idea of ​​this invention—thick contact areas and thin non-contact areas—and fails to achieve SE-like electrical optimization.

[0199] Comparative Example 7 omits the crucial second tunneling oxide layer SiOx2. Without SiOx2, the heavily doped poly-Si(n+)2 directly contacts the underlying poly-Si(n+)1, increasing the interface state density. More importantly, during high-temperature sintering, the silver paste easily penetrates the poly layer, causing direct metal-silicon contact, leading to severe recombination and significantly lowering the open-circuit voltage (UOC) and fill factor (FF).

[0200] Comparative Example 8 mistakenly placed the laser oxidation mask on the poly-Si(n+)1 surface, followed by the deposition of SiOx2 and poly-Si(n+)2 to cover the entire back side. Because the outer poly layer lacked effective mask protection, the entire poly-Si(n+)2 area was removed during alkaline washing, resulting in a convergence of structures between the contact and non-contact areas, thus losing the local advantages of the double-layer poly. Therefore, its performance was even lower than most comparative examples, demonstrating that the laser oxidation mask must be located on the outermost layer to selectively protect the contact area during alkaline washing. This is a crucial process sequence for achieving a poly-finger structure.

[0201] Although Comparative Example 9 retains the double-layer poly and patterning process, its electrical performance deteriorates. Because the poly-Si(n+)2 layer, serving as the key heavily doped layer in the metal contact region, is too thin, it is difficult to effectively reduce the contact resistance between the silver paste and the polysilicon, resulting in a significant decrease in the fill factor (FF). Furthermore, the excessively thin heavily doped layer cannot adequately prevent the silver paste from diffusing inwards during high-temperature sintering, increasing the risk of metal-induced recombination and thus slightly lowering the open-circuit voltage (UOC). The poly-Si(n+)1 layer retained in the non-contact region is too thick. Although it possesses good passivation capabilities, the strong free carrier absorption of the lightly doped polysilicon itself weakens the effect of thinning the poly layer to improve the short-circuit current.

[0202] The battery body of this application is an N-type silicon substrate. On the front side, a boron-diffused lightly doped region, a heavily doped region, an aluminum oxide passivation layer, a silicon nitride antireflection layer, and a front electrode are sequentially formed. The back side structure, from the inside out, is as follows: a first tunneling oxide layer SiOx1 covers the substrate and a first lightly doped poly-Si(n+)1 layer, the latter providing interface passivation; above the contact area, a second tunneling oxide layer SiOx2, a heavily doped poly-Si(n+)2 layer, and a laser oxidation mask are sequentially deposited. After alkaline washing, the poly-Si(n+)2 layer in the non-contact area is removed, retaining the double-layer poly structure (SiOx1 / poly-Si(n+)1 / SiOx2 / poly-Si(n+)2) in the contact area, which reduces contact resistance and prevents silver paste burn-through; only the lightly doped poly-Si(n+)1 layer remains in the non-contact area to reduce parasitic absorption of free carriers. The rear silicon nitride layer serves both antireflection and passivation purposes, and the rear electrode connects to the double-layer poly structure in the contact area. This structure leverages the local advantages of double-layer poly to balance low optical loss and high electrical performance, significantly improving battery efficiency.

[0203] The embodiments of this application have now been described in detail. To avoid obscuring the concept of this application, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0204] While specific embodiments of this application have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and are not intended to limit the scope of this application. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any manner.

Claims

1. A TOPCon solar cell structure, characterized in that, include: An N-type silicon substrate (100), a front structure, and a back structure, wherein the N-type silicon substrate (100) serves as the main substrate of the battery; The front structure is located on the front side of the N-type silicon substrate (100), and is provided sequentially from the inside to the outside as follows: The boron diffusion doping region includes a lightly doped region (101) and a heavily doped region (102); the boron diffusion doping region is in direct contact with the N-type silicon substrate. Alumina layer (103); Front silicon nitride layer (104); Front electrode (105); The back structure is located on the back side of the N-type silicon substrate (100), and is provided sequentially from the inside to the outside as follows: The first tunneling oxide layer SiOx1 (201) covers the back of the cell and is located between the N-type silicon substrate (100) and the first n-type polycrystalline silicon layer poly-Si(n+)1 (202); The first n-type polycrystalline silicon layer, poly-Si(n+)1 (202), covers the back of the battery and is a lightly doped n-type polycrystalline silicon. The second tunneling oxide layer SiOx2 (203) is disposed between the first n-type polycrystalline silicon layer poly-Si(n+)1 (202) and the second n-type polycrystalline silicon layer poly-Si(n+)2 (204) in the metal contact region; The second n-type polycrystalline silicon layer, poly-Si(n+)2(204), is a heavily doped n-type polycrystalline silicon. Rear silicon nitride layer (205); Rear electrode (206); The rear electrode is located above the metal contact area and is in contact with the first n-type polysilicon layer poly-Si(n+)1.

2. The TOPCon solar cell structure according to claim 1, characterized in that, The thickness of the first n-type polycrystalline silicon layer poly-Si(n+)1 (202) is 10-80 nm, and the thickness of the second n-type polycrystalline silicon layer poly-Si(n+)2 (204) is 10-80 nm; the thickness of the first tunneling oxide layer SiOx1 (201) and the second tunneling oxide layer SiOx2 (203) are each independently 0.5-3 nm.

3. The TOPCon solar cell structure according to claim 2, characterized in that, Preferably, the thickness of the first n-type polycrystalline silicon layer poly-Si(n+)1 (202) is 30-40 nm, and the thickness of the second n-type polycrystalline silicon layer poly-Si(n+)2 (204) is 50-60 nm.

4. A method for fabricating a TOPCon solar cell structure as described in any one of claims 1-3, characterized in that, Includes the following steps: Step S1 An N-type silicon substrate (100) with a completed front structure but without electrodes is provided, and a first tunneling oxide layer SiOx1 (201) is formed on the back side of the N-type silicon substrate (100). Step S2 A lightly doped n-type polysilicon layer is deposited on the first tunneling oxide layer (201) to form a first n-type polysilicon layer poly-Si(n+)1 (202) covering the entire back side. Step S3 A second tunneling oxide layer SiOx2 (203) is formed on the first n-type polysilicon layer poly-Si(n+)1 (202), and then a heavily doped second n-type polysilicon layer poly-Si(n+)2 (204) is deposited on it. A mask oxide layer is then deposited on the surface of the second n-type polysilicon layer poly-Si(n+)2 (204), thereby constructing a stacked structure of SiOx1 / poly-Si(n+)1 / SiOx2 / poly-Si(n+)2 / mask oxide layer. Step S4 The laminated structure is subjected to high-temperature annealing. Step S5 Remove the polycrystalline silicon and phosphosilicate glass layer on the front and sides of the silicon wafer, and selectively remove the phosphosilicate glass layer on the back side, while retaining the borosilicate glass on the front side. Step S6 Laser oxidation is performed on the contact area on the back side to form a laser oxidation mask (211). Step S7 Alkali washing and acid washing are performed to form a patterned back structure with a double-layer poly structure in the contact area and a single-layer first n-type polycrystalline silicon layer poly-Si(n+)1 (202) in the non-contact area; Step S8 The TOPCon solar cell is fabricated by sequentially depositing alumina passivation film on the front or both sides, depositing an antireflection film on the front side, depositing a passivation film on the back side, printing front and back electrodes, and sintering at high temperature.

5. The method for fabricating the TOPCon solar cell structure according to claim 4, characterized in that, Before forming the first tunneling oxide layer SiOx1 (201) on the back side of the N-type silicon substrate (100), the following back side pretreatment steps are also included: The N-type silicon substrate (100) is subjected to backside acid washing; Then, alkaline polishing is performed on the back side.

6. The method for fabricating the TOPCon solar cell structure according to claim 4, characterized in that, The step of providing an N-type silicon substrate (100) with a front electrode structure includes: Provides N-type silicon substrate (100); The front side of the N-type silicon substrate (100) is textured to form a light-trapping structure; Boron diffusion is performed on the front side to form an initial p-type emitter, and a borosilicate glass layer is formed on the surface; Laser propulsion processing is performed on the predetermined electrode contact area of ​​the initial p-type emitter, and post-oxidation processing is performed on the laser-processed N-type silicon substrate (100) to form a boron diffusion heavily doped region (102), and the non-contact region is a boron diffusion lightly doped region (101). An aluminum oxide layer (103) and a silicon nitride layer (104) are deposited sequentially on the front side.

7. The method for fabricating the TOPCon solar cell structure according to claim 4, characterized in that, In step S1, the step of forming a first tunneling oxide layer SiOx1 (201) on the back side of the N-type silicon substrate (100) includes: The back side of the N-type silicon substrate (100) is subjected to thermal oxidation for 10-200 seconds to form a first tunneling oxide layer SiOx1 (201).

8. The method for fabricating the TOPCon solar cell structure according to claim 4, characterized in that, Step S2 includes: depositing a lightly doped n-type polycrystalline silicon layer on the first tunneling oxide layer (201) using chemical vapor deposition for a deposition time of 1-15 min, preferably 6-8 min, to form a first n-type polycrystalline silicon layer poly-Si(n+)1 (202) with a thickness of 10-80 nm.

9. The method for fabricating the TOPCon solar cell structure according to claim 4, characterized in that, Step S3 includes: The second tunneling oxide layer SiOx2 (203) is formed by in-situ oxidation for 80-200 seconds and has a thickness of 0.5-3 nm. The second n-type polycrystalline silicon layer poly-Si(n+)2 (204) is formed by chemical vapor deposition. The heavily doped n-type polycrystalline silicon layer is deposited on the second tunneling oxide layer SiOx2 (203) for 1-15 minutes and the deposition thickness is 10-80 nm. The mask oxide layer is formed by chemical vapor deposition, with a deposition time of 30-600 seconds and a thickness of 3-60 nm.

10. The method for fabricating the TOPCon solar cell structure according to claim 4, characterized in that, The high-temperature annealing process in step S4 is carried out under a nitrogen atmosphere, with an annealing pressure of 200-600 Pa, an annealing temperature of 880-930 °C, and an annealing time of 30-60 minutes.

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