Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself, relating to the field of semiconductor technology. The method includes: providing a wafer, the wafer including a substrate, and a base layer disposed on the substrate; forming a hard mask layer on the base layer, the hard mask layer comprising, from bottom to top, a first silicon oxide layer, a polysilicon layer, a second silicon oxide layer, and a carbon layer; forming an anti-reflection layer and a photoresist layer with a preset pattern on the hard mask layer; etching the anti-reflection layer and the hard mask layer using the photoresist layer as a mask to transfer the preset pattern to the hard mask layer; and etching the base layer using the hard mask layer as a mask to form a target structure with the preset pattern in the base layer. This disclosure improves upon the problems of hard mask layer deformation and pattern failure in high aspect ratio etching processes, ensuring accurate transfer of the pattern to the base layer to fabricate a high-quality target structure and improve product performance.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] In semiconductor manufacturing, it is often necessary to fabricate structures with high aspect ratios, such as insulating trenches between memory cells.

[0003] In related technologies, to ensure the precision of the etching process, a relatively thick hard mask layer needs to be placed on the film to be etched. This hard mask layer typically employs a composite structure of a silicon oxide layer and a carbon layer. The silicon oxide layer, positioned above the film to be etched, has a significant thickness. This prevents excessive consumption of the silicon oxide layer during the etching process to form a high aspect ratio structure, thus protecting the integrity of the top of the film and the sidewalls of the internal etched structure. The carbon layer, also with a significant thickness, is positioned above the silicon oxide layer, protecting the integrity of its top and sidewalls when the silicon oxide layer is etched away.

[0004] However, due to the low hardness of the carbon layer itself and the decrease in its overall structural stability as the thickness increases, the bombardment of the carbon layer by the high-energy plasma during the etching process of opening the silicon oxide layer will cause deformation of the carbon layer, resulting in pattern failure, affecting the accuracy of subsequent structures and the performance of the final product. Summary of the Invention

[0005] This disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure, which at least partially improves the aforementioned pattern failure problem.

[0006] According to a first aspect of this disclosure, a method for fabricating a semiconductor structure is provided, comprising: providing a wafer, the wafer including a substrate, the substrate having a base layer disposed thereon; forming a hard mask layer on the base layer, the hard mask layer including, from bottom to top, a first silicon oxide layer, a polysilicon layer, a second silicon oxide layer, and a carbon layer; forming an anti-reflection layer and a photoresist layer having a preset pattern on the hard mask layer; etching the anti-reflection layer and the hard mask layer using the photoresist layer as a mask to transfer the preset pattern to the hard mask layer; and etching the base layer using the hard mask layer as a mask to form a target structure having the preset pattern in the base layer.

[0007] Optionally, at least a portion of the substrate is used as the base layer; or, an epitaxial layer is formed on the substrate, and the epitaxial layer is used as the base layer.

[0008] Optionally, etching the antireflective layer and the hard mask layer using the photoresist layer as a mask includes: etching the antireflective layer using the photoresist layer as a mask; etching the carbon layer using the antireflective layer as a mask; etching the second silicon oxide layer using the carbon layer as a mask; etching the polysilicon layer using the second silicon oxide layer as a mask; and etching the first silicon oxide layer using the polysilicon layer as a mask.

[0009] Optionally, the method further includes: after etching the first silicon oxide layer using the polysilicon layer as a mask, filling the grooves in the first silicon oxide layer and the remaining polysilicon layer with a filling material; removing the remaining polysilicon layer and the filling material in the remaining polysilicon layer to expose the first silicon oxide layer; and removing the filling material in the first silicon oxide layer.

[0010] Optionally, the filler material also covers the top of the remaining polysilicon layer; the removal of the remaining polysilicon layer and the filler material filling the remaining polysilicon layer includes the following steps: etching the filler material above the remaining polysilicon layer, and then etching the remaining polysilicon layer and the filler material filling the remaining polysilicon layer.

[0011] Optionally, etching the base layer using the hard mask layer as a mask includes etching the base layer using the first silicon oxide layer as a mask.

[0012] Optionally, the thicknesses of the first silicon oxide layer, the polycrystalline silicon layer, the second silicon oxide layer, and the carbon layer decrease sequentially.

[0013] Optionally, the thickness ratio of the first silicon oxide layer to the polycrystalline silicon layer is 1:1 to 8:1, the thickness ratio of the polycrystalline silicon layer to the second silicon oxide layer is 1:1 to 8:1, and the thickness ratio of the second silicon oxide layer to the carbon layer is 1:1 to 8:1.

[0014] Optionally, the target structure is a trench; the method further includes filling the trench with an isolation material to form an isolation trench between different semiconductor units.

[0015] According to a second aspect of this disclosure, a semiconductor structure is provided, said semiconductor structure being prepared by the method described in the first aspect.

[0016] According to a third aspect of this disclosure, a memory is provided, comprising the semiconductor structure described in the second aspect above.

[0017] The technical solution disclosed herein has the following beneficial effects:

[0018] On the one hand, in the etching process of target structures with high aspect ratios, a hard mask layer including a polysilicon layer is employed. The polysilicon layer provides a mask for the bottommost first silicon oxide layer in the hard mask layer. Compared with the carbon layer used in related technologies, the polysilicon layer has higher hardness and structural stability. During the etching of the first silicon oxide layer, the polysilicon layer is less prone to distortion under the bombardment of high-energy plasma. On the other hand, the hard mask layer is a multi-layered structure consisting of a first silicon oxide layer, a polysilicon layer, a second silicon oxide layer, and a carbon layer. This helps to reduce the thickness of the carbon layer, making it less prone to distortion during etching. Therefore, the problems of hard mask layer deformation and pattern failure in high aspect ratio etching processes are improved, ensuring the accurate transfer of the pattern in the photoresist layer to the base layer, thereby fabricating a high-quality target structure and improving the performance of the final product. Attached Figure Description

[0019] Figure 1 A schematic diagram of a semiconductor structure in the related art is shown.

[0020] Figure 2 A schematic diagram of a semiconductor structure in the related art is shown.

[0021] Figure 3 A schematic diagram of a semiconductor structure in the related art is shown.

[0022] Figure 4 A schematic diagram of a semiconductor structure in the related art is shown.

[0023] Figure 5 An electron microscope image of the deformation of the Kodiak layer in the related art is shown.

[0024] Figure 6 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure is shown.

[0025] Figure 7 A schematic diagram of a semiconductor structure according to an embodiment of the present disclosure is shown.

[0026] Figure 8 A schematic diagram of forming a hard mask layer is shown in an embodiment of this disclosure.

[0027] Figure 9 A schematic diagram of an embodiment of the present disclosure showing the formation of an anti-reflection layer and a photoresist layer on a hard mask layer is shown.

[0028] Figure 10 A flowchart illustrating an etching antireflective layer and a hard mask layer according to an embodiment of this disclosure is shown.

[0029] Figure 11A schematic diagram of a semiconductor structure after etching the anti-reflection layer and removing the photoresist layer is shown in an embodiment of this disclosure.

[0030] Figure 12 A schematic diagram of a semiconductor structure after etching a carbon layer is shown in an embodiment of this disclosure.

[0031] Figure 13 A schematic diagram of a semiconductor structure after etching a second silicon oxide layer is shown in an embodiment of this disclosure.

[0032] Figure 14 A schematic diagram of a semiconductor structure after etching a polysilicon layer is shown in an embodiment of this disclosure.

[0033] Figure 15 A schematic diagram of a semiconductor structure after etching a first silicon oxide layer is shown in an embodiment of this disclosure.

[0034] Figure 16 A schematic diagram of a deposition filler material according to an embodiment of the present disclosure is shown.

[0035] Figure 17 A schematic diagram of removing filler material over a polysilicon layer is shown in an embodiment of this disclosure.

[0036] Figure 18 A schematic diagram of removing the remaining polysilicon layer and filler material is shown in an embodiment of this disclosure.

[0037] Figure 19 A schematic diagram of removing residual filler material is shown in an embodiment of this disclosure.

[0038] Figure 20 A schematic diagram of a semiconductor structure after etching the base layer is shown in an embodiment of this disclosure.

[0039] The attached figures are labeled as follows:

[0040] 201: Substrate; 202: Base layer; 203: First silicon oxide layer; 204: Polycrystalline silicon layer; 205: Second silicon oxide layer; 206: Carbon layer; 207: Anti-reflective layer; 208: Photoresist layer; 209: Filler material. Detailed Implementation

[0041] Exemplary embodiments of this disclosure will be described more fully below with reference to the accompanying drawings.

[0042] The accompanying drawings are illustrative illustrations of this disclosure and are not necessarily drawn to scale. The technical solutions of this disclosure can be implemented in various forms and should not be construed as limited to the examples set forth herein. The features, structures, or characteristics described in this disclosure can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a sufficient description of embodiments of this disclosure. However, those skilled in the art will understand that one or more specific details may be omitted when implementing the technical solutions of this disclosure, or other methods, components, structures, etc., may be used to replace one or more specific details.

[0043] In semiconductor manufacturing, it is often necessary to fabricate structures with high aspect ratios, such as insulating trenches between memory cells.

[0044] In related technologies, in order to ensure the accuracy of the etching process, a relatively thick hard mask layer needs to be set on the film layer to be etched. Figure 1 A schematic diagram of a hard mask layer in the related technology is shown. An etched film layer 102 is disposed on a substrate 101, and a hard mask layer is disposed on the etched film layer 102. The hard mask layer includes a silicon oxide layer 103, a Kodiak (an amorphous carbon) layer 104, a silicon oxynitride layer 105, and a photoresist layer 106. The silicon oxide layer 103 and the Kodiak layer 104 have relatively large thicknesses. Figures 2 to 4 The etching process is illustrated, first transferring the pattern of the photoresist layer 106 to the Kodiak layer 104, then to the silicon oxide layer 103, and finally to the etched film layer 102. Figure 4 During the etching process shown, because high aspect ratio structures require high etching intensity, the silicon oxide layer 103 should have a large thickness to prevent it from being completely consumed before forming the high aspect ratio structure. Similarly, in Figure 3 During the etching process shown, since the silicon oxide layer 103 is relatively thick, the Kodiak layer 104 should also have a relatively large thickness to avoid the Kodiak layer 104 being consumed too early.

[0045] However, because the Kodiak 104 layer is made of carbon, its inherent hardness is relatively low. Furthermore, as the thickness increases, the internal stress increases, leading to a decrease in overall structural stability, such as... Figure 2As shown, after the Kodiak layer 104 is etched open, it has a large thickness but a small width, resulting in weak structural support in the width direction. During the etching process of opening the silicon oxide layer, the high-energy plasma bombards the Kodiak layer 104, causing it to wiggle. Furthermore, due to the increased density of semiconductor devices, the spacing between adjacent cells becomes smaller, causing the Kodiak layers 104 of adjacent cells to move closer together, increasing their mutual attraction and further exacerbating the deformation.

[0046] Figure 5 The TEM (transmission electron microscope) top view of the Kodiak layer 104 shows obvious distortion. This causes the pattern of the Kodiak layer 104 to fail. Subsequent transfer of this distorted pattern to the silicon oxide layer 103 and the etched film layer 102 affects the accuracy of the semiconductor structure, ultimately leading to a decrease in product performance or even failure.

[0047] In view of the above problems, this disclosure provides a method for preparing a semiconductor structure. Figure 6 The method flow is shown, including the following steps:

[0048] S110 provides a wafer, the wafer including a substrate, on which a base layer is disposed;

[0049] S120, a hard mask layer is formed on the base layer. The hard mask layer includes, from bottom to top, a first silicon oxide layer, a polysilicon layer, a second silicon oxide layer, and a carbon layer.

[0050] S130, an anti-reflection layer and a photoresist layer with a preset pattern are formed on the hard mask layer;

[0051] S140, using the photoresist layer as a mask to etch the anti-reflection layer and the hard mask layer, so as to transfer the preset pattern to the hard mask layer;

[0052] S150 uses a hard mask layer as a mask to etch the base layer, so as to form a target structure with a preset pattern in the base layer.

[0053] based on Figure 6The proposed method employs a hard mask layer comprising a polysilicon layer during the etching of high aspect ratio target structures. This polysilicon layer serves as a mask for the bottommost silicon oxide layer within the hard mask layer. Compared to the carbon layer used in related technologies, the polysilicon layer exhibits higher hardness and structural stability, making it less prone to distortion under the bombardment of high-energy plasma during the etching of the first silicon oxide layer. Furthermore, the hard mask layer is a multi-layered structure consisting of a first silicon oxide layer, a polysilicon layer, a second silicon oxide layer, and a carbon layer. This reduces the thickness of the carbon layer, further minimizing its distortion during etching. This approach improves upon the issues of hard mask layer deformation and pattern failure in high aspect ratio etching processes, ensuring precise transfer of the pattern from the photoresist layer to the base layer, thereby fabricating a high-quality target structure and enhancing the performance of the final product.

[0054] The following describes, in conjunction with one or more embodiments and related accompanying drawings, Figure 6 Each step is explained in detail.

[0055] In step S110, a wafer is provided, the wafer including a substrate, on which a base layer is disposed.

[0056] The wafer is the carrier for fabricating semiconductor devices. The wafer includes a substrate 201, which provides the base for the semiconductor device. The substrate 201 is typically monocrystalline silicon, but can also be other forms of silicon (such as polycrystalline silicon, amorphous silicon), or materials such as germanium, silicon-germanium compounds, or III-V compounds (such as gallium arsenide). The substrate 201 can have an epitaxial layer, or it can be a silicon-on-insulator substrate 201 (i.e., SOI substrate 201). This disclosure does not limit the specific structure of the substrate 201.

[0057] The base layer 202 is the film layer that needs to be etched to form the target structure. The target structure is a structure with a high aspect ratio. This disclosure does not limit the specific value or range of its aspect ratio. For example, the aspect ratio of the target structure can be greater than 10:1. The target structure includes, but is not limited to: trenches, vias, and contact holes.

[0058] The base layer 202 can be located inside or outside the substrate 201. In one embodiment, at least a portion of the substrate 201 can be used as the base layer 202. For example, if it is necessary to form isolation trenches or interconnects in the substrate 201, the substrate 201 can be used as the base layer 202 (or more specifically, the region in the substrate 201 where the isolation trench is to be formed can be used as the base layer 202). In another embodiment, an epitaxial layer is formed on the substrate 201, and the epitaxial layer can be used as the base layer 202. The epitaxial layer includes, but is not limited to, a silicon epitaxial layer, a germanium epitaxial layer, or a germanium-silicon epitaxial layer. Exemplarily, the epitaxial layer can be a silicon epitaxial layer and a germanium-silicon epitaxial layer (such as Si...).0.7 Ge 0.3 In the process of 3D DRAM (Dynamic Random Access Memory), the isolation trench between different memory cells is located in the epitaxial layer. Therefore, the epitaxial layer is used as the base layer 202, and a target structure with a high aspect ratio is subsequently formed in the epitaxial layer, thereby forming the isolation trench. Figure 7 A schematic diagram of a substrate 201 and a base layer 202 is shown. The base layer 202 is formed on the substrate 201 and includes a stacked structure of a silicon epitaxial layer and a germanium-silicon epitaxial layer.

[0059] Continue to refer to Figure 6 In step S120, a hard mask layer is formed on the base layer. The hard mask layer includes, from bottom to top, a first silicon oxide layer, a polysilicon layer, a second silicon oxide layer, and a carbon layer.

[0060] The hard mask layer is used to provide a mask for the etching process of the base layer 202. Figure 8 A schematic diagram of a hard mask layer is shown, formed on a base layer 202, comprising a first silicon oxide layer 203, a polysilicon layer 204, a second silicon oxide layer 205, and a carbon layer 206. The carbon layer 206 is located at the top of the entire hard mask layer and serves as a crucial intermediate mask for pattern transfer, exhibiting a high etch selectivity to the underlying second silicon oxide layer 205. In one embodiment, the carbon layer 206 may be an APF layer (Advanced Patterning Film, an amorphous carbon film). The second silicon oxide layer 205 is located below the carbon layer 206 and serves as an etch stop layer for etching the upper carbon layer 206, while also providing a mask during the etching of the underlying polysilicon layer 204. The polysilicon layer 204, located below the second silicon oxide layer 205, possesses high hardness. After patterning, it provides robust mechanical support for the entire hard mask layer structure and acts as a mask during the etching process of the first silicon oxide layer 203 below it, resisting deformation caused by high-energy plasma bombardment. The first silicon oxide layer 203, located at the bottom of the entire hard mask layer and in contact with the base layer 202, serves as a mask layer providing direct protection for the base layer 202. When the base layer 202 is a silicon layer or an epitaxial layer containing silicon and germanium, the silicon oxide material of the first silicon oxide layer 203 exhibits a high etching selectivity for the base layer 202.

[0061] In one embodiment, a chemical vapor deposition (CVD) process can be used to sequentially deposit a first silicon oxide layer 203, a polysilicon layer 204, a second silicon oxide layer 205, and a carbon layer 206 on a base layer 202 to form a hard mask layer with a composite structure. The process is relatively simple.

[0062] In one embodiment, the thicknesses of the first silicon oxide layer 203, the polysilicon layer 204, the second silicon oxide layer 205, and the carbon layer 206 decrease sequentially. During the etching of each layer in the hard mask layer, the layer above provides the masking effect, resulting in a high etch selectivity ratio between the two layers; that is, the etching rate of the current layer is lower than the thinning rate of the layer above. The thickness of the layer above can be lower than that of the current layer, ensuring that the layer above is not prematurely consumed during the etching of the current layer. Therefore, the thickness of each layer in the hard mask layer can decrease sequentially from bottom to top. This reduces the total thickness of the hard mask layer while ensuring sufficient masking effect, which is beneficial for controlling the focus depth in subsequent processes and may reduce the deposition cost of the hard mask layer. Furthermore, the sequential decrease in thickness of each layer in the hard mask layer from bottom to top results in a relatively thin carbon layer 206, which can improve the distortion and deformation problem of the carbon layer 206 and improve the pattern transfer accuracy.

[0063] In one embodiment, the thickness ratio of the first silicon oxide layer 203 to the polysilicon layer 204 is 1:1 to 8:1, the thickness ratio of the polysilicon layer 204 to the second silicon oxide layer 205 is 1:1 to 8:1, and the thickness ratio of the second silicon oxide layer 205 to the carbon layer 206 is 1:1 to 8:1. The thickness ratio between adjacent layers is determined based on factors such as etching selectivity, actual etching rate, mechanical properties of each layer, and stress conditions. The thickness of the first silicon oxide layer 203 can be determined first based on the material of the base layer 202 and the design depth of the target structure, then the thickness of the polysilicon layer 204 can be determined based on the thickness of the first silicon oxide layer 203, and so on, until the thickness of each subsequent layer is determined.

[0064] Taking the thickness ratio of the first silicon oxide layer 203 to the polysilicon layer 204 as an example, the larger the thickness ratio, the smaller the relative thickness of the polysilicon layer 204, and the less sufficient its masking effect. However, the process cost of forming the polysilicon layer 204 is usually lower. The smaller the thickness ratio, the larger the relative thickness of the polysilicon layer 204, and the more sufficient its masking effect. However, the process cost of forming the polysilicon layer 204 is usually higher. Therefore, considering both the masking effect and process cost, a suitable thickness ratio range is determined to be 1:1 to 8:1. That is, the thickness ratio of the polysilicon layer 204 to the first silicon oxide layer 203 is not less than 0.125 and not more than 1. The 0.125 ratio ensures that the polysilicon layer 204 will not be completely consumed before the etching of the first silicon oxide layer 203, leaving a certain margin to provide sufficient masking effect. The 1 ratio ensures that the thickness of the polysilicon layer 204 is not too large, resulting in a reasonable process cost for forming the polysilicon layer 204. Based on similar considerations, a suitable thickness ratio range of 1:1 to 8:1 can be determined for the polysilicon layer 204 and the second silicon oxide layer 205, and a suitable thickness ratio range of 1:1 to 8:1 for the second silicon oxide layer 205 and the carbon layer 206.

[0065] In one embodiment, the thickness ratio of the first silicon oxide layer 203, the polysilicon layer 204, the second silicon oxide layer 205, and the carbon layer 206 is 5:3:1:0.6. This is an optimal ratio determined through multiple experiments, which helps to reduce the preparation cost of the hard mask layer while ensuring the accurate completion of the etching process.

[0066] Continue to refer to Figure 6 In step S130, an anti-reflection layer and a photoresist layer with a preset pattern are formed on the hard mask layer.

[0067] The anti-reflection layer 207 is used to optimize photolithography imaging quality and reduce photoresist pattern distortion caused by reflection from the underlying structure or substrate 201. In one embodiment, the anti-reflection layer 207 can also be considered part of a hard mask layer, acting as a mask during the etching process of the underlying carbon layer 206. Exemplarily, the anti-reflection layer 207 can be a silicon oxynitride (SiON) layer. The preset pattern refers to a pattern designed for the target structure; for example, if the target structure is a trench, the preset pattern is the projection pattern of the trench onto a two-dimensional plane (i.e., the wafer plane). The photoresist layer 208 covers the area outside the target structure, leaving the area where the target structure is located empty, thereby defining the preset pattern that needs to be transferred to the base layer 202. Figure 9 A schematic diagram of forming an anti-reflection layer 207 and a photoresist layer 208 on a hard mask layer is shown. Silicon oxynitride can be coated on the hard mask layer as an anti-reflection layer 207 using a spin coating process, and photoresist can be coated on the hard mask layer. After exposure and development, the photoresist forms a photoresist layer 208 with a preset pattern.

[0068] In one embodiment, the thickness of the anti-reflective layer 207 is less than the thickness of the carbon layer 206, and the anti-reflective layer 207 can provide sufficient anti-reflection and hard masking effects even with a smaller thickness. In one embodiment, the thickness ratio of the carbon layer 206 to the anti-reflective layer 207 is 3:1 to 10:1. For example, the thickness ratio of the carbon layer 206 to the anti-reflective layer 207 can be 6:1.

[0069] In one embodiment, in the 3D DRAM process, the thickness of the first silicon oxide layer 203 is 0.5~3μm, the thickness of the polysilicon layer 204 is 62.5nm~3000nm, the thickness of the second silicon oxide layer 205 is 10nm~3000nm, the thickness of the carbon layer 206 is 1nm~1000nm, and the thickness of the anti-reflection layer 207 is 1nm~500nm. For example, the thickness of the first silicon oxide layer 203 is 1μm, the thickness of the polysilicon layer 204 is 500nm, the thickness of the second silicon oxide layer 205 is 200nm, the thickness of the carbon layer 206 is 60nm, and the thickness of the anti-reflection layer 207 is 20nm.

[0070] Continue to refer to Figure 6 In step S140, the anti-reflection layer and the hard mask layer are etched using the photoresist layer as a mask to transfer the preset pattern to the hard mask layer.

[0071] In this process, a series of etching processes are used to gradually and precisely transfer the preset pattern in the photoresist layer 208 into the anti-reflection layer 207 and the hard mask layer. In one embodiment, reference... Figure 10 As shown, etching the antireflection layer 207 and the hard mask layer using the photoresist layer 208 as a mask includes the following steps S1401 to S1405:

[0072] S1401, using a photoresist layer as a mask to etch the anti-reflection layer.

[0073] For example, the antireflective layer 207 is a SiON layer, and plasma dry etching is performed using fluorinated chemical gases (such as CF4, CHF3, SF6). This etching material has a high etching selectivity for both the antireflective layer 207 and the photoresist layer 208, resulting in a slower consumption rate of the photoresist layer 208 and ensuring sufficient masking effect. Furthermore, this etching material has a lower etching rate for the carbon layer 206, allowing the etching process to stop at the top of the carbon layer 206. Additionally, oxygen, argon, or other gases can be added to adjust the etching selectivity and physical bombardment composition. After etching the antireflective layer 207, the photoresist layer 208 can be removed using processes such as ashing or wet stripping, leaving only the patterned antireflective layer 207 as the mask for the next step. Figure 11 A schematic diagram of the semiconductor structure after etching the anti-reflection layer 207 and removing the photoresist layer 208 is shown.

[0074] S1402, carbon layer is etched using an anti-reflective layer as a mask.

[0075] For example, plasma dry etching is performed using oxygen as the primary etching material. This etching material has a high etching selectivity for the carbon layer 206 and the SiON layer, resulting in a slower thinning rate of the anti-reflection layer 207 and providing sufficient hard masking. Furthermore, this etching material has a lower etching rate for the second silicon oxide layer 205, allowing the etching process to stop at the top of the second silicon oxide layer 205. Additionally, hydrobromic acid and nitrogen can be added to improve sidewall passivation and contour control. Figure 12 A schematic diagram of the semiconductor structure after etching the carbon layer 206 is shown. During the etching process of the carbon layer 206, since the anti-reflective layer 207 is thinned slowly, it is usually not completely consumed. The remaining anti-reflective layer 207 does not affect the subsequent pattern transfer process, and it is not necessary to specifically remove the remaining anti-reflective layer 207.

[0076] S1403, using a carbon layer as a mask to etch the second silicon oxide layer.

[0077] For example, plasma dry etching using a fluorinated chemical gas can be performed. Compared to step S1401, the specific ratios and process parameters can be adjusted. This etching material has a high etching selectivity for the second silicon oxide layer 205 and the carbon layer 206, resulting in a slower thinning rate of the carbon layer 206 and providing sufficient hard masking. Furthermore, this etching material has a low etching rate for the polysilicon layer 204, allowing the etching process to stop at the top of the polysilicon layer 204. Figure 13 A schematic diagram of the semiconductor structure after etching the second silicon oxide layer 205 is shown. During the etching process of the second silicon oxide layer 205, since the carbon layer 206 thins out slowly, it is usually not completely consumed. The remaining carbon layer 206 can continue to serve as a hard mask layer to protect the non-patterned areas of the underlying film layer. Therefore, it is not necessary to specifically remove the remaining carbon layer 206.

[0078] S1404, using the second silicon oxide layer as a mask to etch the polysilicon layer.

[0079] For example, a mixed gas of hydrogen bromide, chlorine, etc., is used for plasma dry etching. Hydrogen bromide and chlorine are used for chemical etching of the polysilicon layer 204. This method has a high etching selectivity for the polysilicon layer 204 compared to silicon oxide, resulting in a slower thinning rate of the second silicon oxide layer 205 and providing sufficient masking. Furthermore, the etching material has a low etching rate for the first silicon oxide layer 203, allowing the etching process to stop at the top of the first silicon oxide layer 203. Additionally, oxygen can be added to form a passivation layer on the sidewalls, which is beneficial for controlling the profile and obtaining vertical sidewalls. After etching, the passivation polymer and residues on the sidewalls must be thoroughly removed. Figure 14A schematic diagram of the semiconductor structure after etching the polysilicon layer 204 is shown. During the etching process of the polysilicon layer 204, since the thinning rate of the second silicon oxide layer 205 is relatively slow, it is usually not completely consumed. The remaining second silicon oxide layer 205 can be used as a direct mask for etching the first silicon oxide layer 203, so there is no need to specifically remove the remaining second silicon oxide layer 205.

[0080] S1405, using a polysilicon layer as a mask to etch the first silicon oxide layer.

[0081] For example, plasma dry etching is performed using a fluorocarbon gas (such as CHF3 or C4F8, with oxygen added to adjust the etching selectivity). This etching material has a high etching selectivity for silicon oxide, polysilicon, and the base layer 202 (such as monocrystalline silicon, silicon epitaxial layer, silicon-germanium epitaxial layer, etc.). This results in a slower thinning rate of the polysilicon layer 204, providing sufficient masking, and the etching process can stop at the top of the base layer 202. Furthermore, argon gas can be added to provide physical bombardment. Figure 15 A schematic diagram of the semiconductor structure after etching the first silicon oxide layer 203 is shown. During the etching of the first silicon oxide layer 203, the polysilicon layer 204 is typically not completely consumed due to its slow thinning rate. In one embodiment, the remaining polysilicon layer 204 can be retained to provide a masking effect during the subsequent etching of the base layer 202. In another embodiment, the remaining polysilicon layer 204 can be removed to avoid adverse effects (such as collapse or contamination) during the subsequent etching of the base layer 202.

[0082] based on Figure 10 The process involves etching the anti-reflection layer 207 and the hard mask layer layer by layer in a multi-step etching manner, so that the preset pattern in the photoresist layer 208 can be transferred downwards accurately and stably, reducing pattern distortion and interlayer damage.

[0083] In one embodiment, the method for fabricating a semiconductor structure further includes the following steps:

[0084] After etching the first silicon oxide layer 203 using the polysilicon layer 204 as a mask, the grooves in the first silicon oxide layer 203 and the remaining polysilicon layer 204 are filled with filling material 209.

[0085] Remove the remaining polysilicon layer 204 and the filler material 209 filling the remaining polysilicon layer 204 to expose the first silicon oxide layer 203;

[0086] Remove the filler material 209 that fills the first silicon oxide layer 203.

[0087] As described above, after the etching of the first silicon oxide layer 203 is completed, a polysilicon layer 204 remains. The remaining polysilicon layer 204 is removed by backfilling with a filler material 209, which provides mechanical support during the process. The filler material 209 can be a spin-on hard mask (SOH) material, such as a silicon-based SOH material. For example, by spin-coating an SOH material, the grooves in the first silicon oxide layer 203 and the remaining polysilicon layer 204 are filled. Then, the remaining polysilicon layer 204 and the filler material 209 filling the remaining polysilicon layer 204 are removed using etching or other processes, exposing the top of the first silicon oxide layer 203. Finally, the filler material 209 filling the first silicon oxide layer 203 is removed using etching or other processes, resulting in a complete patterned first silicon oxide layer 203.

[0088] In one embodiment, the filler material 209 further covers the remaining polysilicon layer 204. The removal of the remaining polysilicon layer 204 and the filler material 209 within it includes the following steps:

[0089] The filler material 209 above the remaining polysilicon layer 204 is etched, and then the remaining polysilicon layer 204 and the filler material 209 filling the remaining polysilicon layer 204 are etched.

[0090] refer to Figures 16 to 19 As shown, after spin-coating the filler material 209, it fills the grooves in the first silicon oxide layer 203 and the remaining polysilicon layer 204, and covers the top of the remaining polysilicon layer 204. Then, the filler material 209 above the remaining polysilicon layer 204 is etched, exposing the top of the remaining polysilicon layer 204. The remaining polysilicon layer 204 and the filler material 209 within it are then etched. During this process, the etching rates of the polysilicon layer 204 and the filler material 209 can differ, with the complete etching of the polysilicon layer 204 as the etching endpoint. Thus, the remaining filler material 209 may be higher (in the case where the etching rate of the polysilicon layer 204 is greater than that of the filler material 209) or lower (in the case where the etching rate of the polysilicon layer 204 is less than that of the filler material 209) than the top of the first silicon oxide layer 203, without affecting subsequent processes. Finally, an ashing process is used to remove the filler material 209 filling the first silicon oxide layer 203.

[0091] Removing the polysilicon layer 204 in the above manner can ensure the integrity and stability of the first silicon oxide layer 203 structure and avoid the polysilicon layer 204 from having an adverse effect on the subsequent etching process of the base layer 202.

[0092] Continue to refer to Figure 6In step S150, the base layer is etched using a hard mask layer as a mask to form a target structure with a preset pattern in the base layer.

[0093] A patterned, structurally robust hard mask layer is used as the final mask to perform high aspect ratio etching on the base layer 202. Because the hard mask layer has a precise and stable pattern, it is possible to form high-quality target structures, such as deep trenches or holes, in the base layer 202.

[0094] In one embodiment, during the patterning process of the hard mask layer, only the patterned first silicon oxide layer 203 is ultimately retained through layer-by-layer etching. In step S150, the base layer 202 is etched using the first silicon oxide layer 203 as a mask. For example, plasma dry etching methods such as SF6, Cl2, and HBr can be used to etch the base layer 202, which contains silicon epitaxial layers and silicon-germanium epitaxial layers. Argon gas can be added to provide physical bombardment, and oxygen can be added to control the sidewall profile and improve the etching selectivity of the first silicon oxide layer 203. Figure 20 A schematic diagram of the semiconductor structure after etching the base layer 202 is shown. It should be understood that after etching the base layer 202, there may be residual first silicon oxide layer 203. The residual first silicon oxide layer 203 can be removed or retained according to the requirements of subsequent processes, and this disclosure does not limit this.

[0095] The embodiments disclosed herein can be used to fabricate different high aspect ratio structures in semiconductor processes. Examples are given below.

[0096] In one embodiment, the target structure is a trench. After forming a trench with a predetermined pattern, an isolation material can be filled into the trench to form an isolation trench between different semiconductor units. Exemplarily, a stacked structure of a silicon epitaxial layer and a silicon-germanium epitaxial layer is formed on substrate 201, which serves as the base layer 202. Figure 6 The fabrication method shown involves creating trenches with a predetermined pattern in the base layer 202, and then filling the trenches with an isolation material such as silicon oxide to form isolation trenches between laterally adjacent 1T1C cells (one transistor and one capacitor form one cell). This fabrication method can be applied to 3D DRAM processes as well as other semiconductor processes. Subsequently, transistor communication can be formed in the remaining base layer 202, for example, by selectively etching away the silicon-germanium epitaxial layer in the remaining base layer 202, retaining the silicon epitaxial layer as the channel for transistors (such as gate-all-around transistors).

[0097] In one implementation, the target structure is a word line via. Exemplarily, in a 3D DRAM process, a stacked structure of a silicon epitaxial layer and a silicon-germanium epitaxial layer is formed on substrate 201, which serves as the base layer 202. Figure 6The fabrication method shown creates holes with a predetermined pattern in the base layer 202, which can serve as word line holes. Subsequently, conductive material can be directly filled into the word line holes to form word lines. Alternatively, sacrificial material can be filled into the word line holes, and the remaining silicon-germanium epitaxial layer in the base layer 202 can be selectively etched away at an appropriate time. Then, the sacrificial material can be removed and conductive material filled at an appropriate time to form word lines.

[0098] In one embodiment, the target structure is a contact hole. After forming a contact hole with a preset pattern, conductive material can be filled into the contact hole to form a conductive pillar between the transistor and the capacitor. Exemplarily, a relatively thick interlayer dielectric layer (such as silicon nitride to achieve a higher etching selectivity than the first silicon oxide layer 203) is deposited on the substrate 201, serving as the base layer 202. Figure 6 The fabrication method shown creates contact holes with a preset pattern in the base layer 202. The contact holes can connect to transistor nodes. Then, conductive materials such as metals, alloys, and doped polysilicon are filled into the contact holes to form conductive pillars. These conductive pillars are used to connect the transistors to the capacitors subsequently formed on top.

[0099] It should be understood that the above is merely an exemplary description of the specific application of the target structure and the preparation method of the embodiments of this disclosure. The target structure can also be other high aspect ratio structures, and the preparation method of the embodiments of this disclosure can also be applied to other processes or steps. This disclosure does not limit it in this regard.

[0100] This disclosure also provides a semiconductor structure, which can be a semiconductor structure prepared by any of the preparation methods described in this disclosure, for example... Figure 20 The structure shown is a semiconductor structure with a high aspect ratio, which improves the hard mask layer deformation problem in high aspect ratio etching processes and is beneficial for realizing semiconductor devices with better performance.

[0101] This disclosure also provides a memory, which may include the semiconductor structure described in this disclosure. The memory may be a volatile memory, such as DRAM, or a non-volatile memory, such as NAND Flash. This memory incorporates a stable and accurate high aspect ratio structure, improving the hard mask layer deformation problem in high aspect ratio etching processes, and therefore exhibits superior performance.

[0102] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. This application is intended to cover any variations, uses, or adaptations of the technical solutions that follow the general principles of this disclosure and include common knowledge or customary technical means in the art not disclosed herein. The content of this specification is to be considered exemplary only, and the scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method of fabricating a semiconductor structure having a high aspect ratio, characterized in that, include: A wafer is provided, the wafer including a substrate on which a base layer is disposed; A hard mask layer is formed on the base layer, and the hard mask layer consists of a first silicon oxide layer, a polysilicon layer, a second silicon oxide layer, and a carbon layer from bottom to top; the thicknesses of the first silicon oxide layer, the polysilicon layer, the second silicon oxide layer, and the carbon layer decrease sequentially; the thickness ratio of the second silicon oxide layer to the carbon layer is 1:1 to 8:1, the thickness ratio of the first silicon oxide layer to the polysilicon layer is 1:1 to 8:1, and the thickness ratio of the polysilicon layer to the second silicon oxide layer is 1:1 to 8:

1. An anti-reflection layer and a photoresist layer with a preset pattern are formed on the hard mask layer; The anti-reflection layer and the hard mask layer are etched using the photoresist layer as a mask to transfer the preset pattern to the hard mask layer; The base layer is etched using the hard mask layer as a mask to form a target structure with the preset pattern in the base layer.

2. The method of claim 1, wherein, At least a portion of the substrate is used as the base layer; or, an epitaxial layer is formed on the substrate, and the epitaxial layer is used as the base layer.

3. The method according to claim 1, characterized in that, The etching of the antireflection layer and the hard mask layer using the photoresist layer as a mask includes: The antireflection layer is etched using the photoresist layer as a mask; The carbon layer is etched using the anti-reflective layer as a mask; The second silicon oxide layer is etched using the carbon layer as a mask; The polysilicon layer is etched using the second silicon oxide layer as a mask; The first silicon oxide layer is etched using the polysilicon layer as a mask.

4. The method according to claim 3, characterized in that, The method further includes: After etching the first silicon oxide layer using the polysilicon layer as a mask, the grooves in the first silicon oxide layer and the remaining polysilicon layer are filled with a filling material. Remove the remaining polysilicon layer and the filler material filling the remaining polysilicon layer to expose the first silicon oxide layer; Remove the filler material that filled the first silicon oxide layer.

5. The method according to claim 4, characterized in that, The filler material also covers the top of the remaining polysilicon layer; the removal of the remaining polysilicon layer and the filler material filling the remaining polysilicon layer includes the following steps: The filler material above the remaining polysilicon layer is etched, and then the remaining polysilicon layer and the filler material filling the remaining polysilicon layer are etched.

6. The method according to claim 3, characterized in that, The etching of the base layer using the hard mask layer as a mask includes: The base layer is etched using the first silicon oxide layer as a mask.

7. The method according to claim 1, characterized in that, The carbon layer is an APF layer.

8. The method according to any one of claims 1 to 7, characterized in that, The target structure is a trench; the method further includes: The trench is filled with an isolation material to form an isolation trench between different semiconductor units.

9. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method described in any one of claims 1 to 8.

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