Glass interposer stack substrate and semiconductor package structure

Abstract

The invention discloses a glass interposer stacked substrate and a semiconductor packaging structure, and the glass interposer stacked substrate is characterized in that a traditional single substrate is divided into independent glass sub-substrates made of different glass materials, and the glass sub-substrates are stacked through metal bonding and are filled with filling materials to form a multi-glass-material integrated interposer substrate; therefore, the sub-substrates can be processed in parallel, a multi-layer stacking process is simplified, alignment deviation and lamination defect risks are reduced, the manufacturing yield is remarkably improved, and the processing time is shortened; high-density integration is realized by stacking multiple layers of sub-substrates, and glass sub-substrates of different levels adopt glass substrates of different characteristics based on thermal-electric-mechanical characteristic differences of different chips in the AI module. The problems that in the prior art, a multi-layer process of a single glass material substrate is complex, heat-electricity-force requirements of multiple chips cannot be met, signal loss is high, heat dissipation is poor, and machining difficulty is large are solved.

Description

Technical Field

[0001] This invention relates to the field of advanced semiconductor packaging, and in particular to a glass interposer stacked substrate and a semiconductor packaging structure. Background Technology

[0002] With the surge in computing power demands from AI and high-performance computing chips, the thermal density and signal transmission rate of chips such as GPUs and HBMs have significantly increased. Traditional glass interposer substrates, using a single substrate material and a multi-layer RDL wiring structure, struggle to accommodate the differences in thermal, electrical, and mechanical characteristics among multiple chips, facing numerous challenges: low yield of multi-layer wiring, high processing costs, thermal stress mismatch, and signal transmission loss, failing to meet the higher-speed signal requirements between HBMs and GPUs. Multi-layer boards formed by multi-layer RDL wiring structures also face significant challenges in stacking alignment, dielectric thickness uniformity, interlayer interconnect precision control, and heat dissipation due to their extremely high lamination complexity. Any minute interlayer alignment deviation or lamination defect can lead to signal integrity issues or internal short circuits. Furthermore, the difficulty of via forming and electroplating processes increases exponentially, resulting in an overall manufacturing yield significantly lower than conventional boards. Therefore, technical solutions and approaches need further improvement.

[0003] The information disclosed in this background section was already known to the inventors prior to the implementation of this application or was acquired during the implementation of this disclosure. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the Invention

[0004] To address the aforementioned issues, this invention provides a glass interposer stacked substrate and a semiconductor packaging structure. By decomposing a single-layer substrate into independent sub-substrates of different glass materials, modularizing the sub-substrates design and parallel processing, and then stacking multiple sub-substrates, the invention solves the problems of complex multi-layer processes, inability to meet the thermal-electrical-power requirements of multiple chips, high signal loss, poor heat dissipation, and high processing difficulty of existing single-glass substrates.

[0005] According to one or more embodiments, a glass interposer stack substrate is provided, comprising: At least three glass sub-substrates disposed along the stacking direction, each of the glass sub-substrates comprising: A glass core board having a through-hole in the glass, wherein the through-hole is filled with a conductive material to form a conductive through-hole; Two redistribution structures are formed on opposite sides of the glass core board, corresponding to each other, and are electrically interconnected through the conductive vias; each redistribution structure has at least two redistribution layers, each redistribution layer including a dielectric layer, a metal wiring layer and a plurality of vias; the vias electrically connect the metal wiring layers of two adjacent redistribution layers; A metal bonding layer is disposed on the side of each redistribution structure opposite to the glass core board and is electrically connected to the redistribution structure; Along the stacking direction, the glass core of the top glass sub-substrate has a coefficient of thermal expansion of less than 5 ppm / ℃ and a thermal conductivity of 1.2 W / (m·K), and the glass sub-substrate uses silver metal wiring; the glass core of the bottom glass sub-substrate has a coefficient of thermal expansion of greater than 5 ppm / ℃, and the linewidth of the metal wiring layer of at least one wiring structure of the glass sub-substrate gradually widens from the conductive via to the metal bonding layer; the glass core of the glass sub-substrate located between the top and bottom layers has a dielectric constant of 4-7 and a dielectric loss of 0.007-0.009, and the glass sub-substrate uses silver metal wiring; Along the stacking direction, any two adjacent glass sub-substrates are stacked and bonded through the metal bonding layer, and the bonding gap between the two adjacent glass sub-substrates is filled with a filler material to form the glass interposer stacked substrate.

[0006] According to the glass interposer stacked substrate of the present invention, the traditional single-material substrate is first split into independent glass sub-substrates of different glass materials, which are then stacked by metal bonding and filled with filler material to form an interposer substrate integrating multiple glass materials. In this way, the sub-substrates can be processed in parallel, simplifying the multi-layer stacking process, reducing the risk of alignment deviation and lamination defects, significantly improving manufacturing yield and shortening processing time; high-density integration is achieved through multi-layer sub-substrate stacking.

[0007] Secondly, based on the differences in the thermal-electrical-mechanical characteristics of different chips in the AI ​​module, different glass sub-substrates of different layers adopt glass substrates with different characteristics to solve the defect that "a single substrate cannot meet the needs of multiple chips". For example, the top glass sub-substrate uses low CTE glass to match the silicon chip, reduce the thermal stress between the chip and the substrate, and the top glass sub-substrate has good thermal conductivity, which can solve the problem of local high heat after GPU / HBM flip-chip. Furthermore, the top glass sub-substrate uses silver metal wiring to reduce the loss of high-frequency signal transmission of the device and further improve the thermal conductivity of this layer of glass sub-substrate. The middle layer glass sub-substrate uses a low dielectric loss glass substrate, combined with silver metal wiring, to meet the integrity requirements of high-speed signal transmission of more than 2 Gbps between HBM and GPU, and avoid signal attenuation problems. The bottom glass sub-substrate uses medium CTE glass to alleviate the overall thermal stress after multi-layer stacking, avoid substrate warping after PCB mounting, and the gradual widening of the metal wiring layer of at least one wiring structure of the bottom glass sub-substrate can avoid metal fatigue caused by abrupt changes in linewidth.

[0008] Furthermore, filling the spaces between adjacent glass sub-substrates with a highly thermally conductive material eliminates air gaps at the bonding interface, improving heat dissipation efficiency and structural reliability, thus meeting the high-density integration and high thermal management requirements of AI chips. Independent testing and screening of sub-substrates avoids the failure of the entire substrate due to localized defects in traditional monolithic substrates, thereby reducing costs.

[0009] In addition, the glass interposer stacked substrate proposed according to the present invention may also have the following additional technical features: Optionally, at least one of the redistribution structures of the underlying glass sub-substrate has a first dielectric layer formed of a first dielectric material and a second dielectric layer formed of a second dielectric material, wherein the first dielectric layer is an epoxy resin material and is disposed adjacent to the glass core; the second dielectric layer is a siloxane film and is disposed on the outermost metal wiring layer of the redistribution structure.

[0010] Optionally, along the stacking direction, the linewidth of the metal wiring layer of the redistribution structure of the top glass sub-substrate is 2 μm and the line spacing is 2 μm; the linewidth of the redistribution structure of the bottom glass sub-substrate is 5 μm-10 μm and the line spacing is 5 μm-10 μm; the linewidth of the metal wiring layer of the redistribution structure of the glass sub-substrate located between the top and bottom layers is 3 μm-5 μm and the line spacing is 3 μm-5 μm; from the top glass sub-substrate to the bottom glass sub-substrate, the metal wiring layers of the redistribution structure are arranged from dense to sparse.

[0011] Optionally, the glass core of the top glass sub-substrate is borosilicate glass, in which Al2O3 thermally conductive particles are doped.

[0012] Optionally, the conductive vias and metal wiring layers of the top glass sub-substrate each have a seed layer and a conductive layer covering the seed layer, wherein the seed layer includes a titanium layer, or a titanium layer and a copper layer; and the conductive layer is a silver layer.

[0013] Optionally, the conductive vias and metal wiring layers of the glass sub-substrate located between the top and bottom layers each have a seed layer and a conductive layer covering the seed layer, wherein the seed layer includes a titanium layer, or a titanium layer and a copper layer; and the conductive layer is a silver layer.

[0014] Optionally, the metal bonding layer consists of a plurality of protrusions spaced apart on the side of the redistribution structure opposite to the glass core.

[0015] Furthermore, the bumps on one of the redistribution structures of the glass sub-substrate are solder balls or gold balls, and the bumps on the other redistribution structure are copper pillars.

[0016] Optionally, the filler material is LCM material, LMUF material, CUF material, thermally conductive adhesive, prepreg, or NCF film.

[0017] According to another aspect of one or more embodiments, a method for fabricating a glass interposer stacked substrate is provided, comprising the following steps: Provide at least three types of glass core boards with conductive through holes; A redistribution structure is provided on each of the opposite sides of each of the glass core boards; each redistribution structure has at least two redistribution layers; each redistribution layer includes a dielectric layer, a metal wiring layer, and a plurality of vias; the vias electrically connect the metal wiring layers of two adjacent redistribution layers; A metal bonding layer is provided on the side of each redistribution structure opposite to the glass core, and the wafer is cut to form at least three types of glass sub-substrates; The at least three types of glass sub-substrates are sequentially stacked and bonded along the stacking direction using the metal bonding layer, and the bonding gap between two adjacent glass sub-substrates is filled with filler material to form the glass interlayer stacked substrate. Along the stacking direction, the glass core of the top glass sub-substrate has a coefficient of thermal expansion of less than 5 ppm / ℃ and a thermal conductivity of 1.2 W / (m·K), and the glass sub-substrate uses silver metal wiring; the glass core of the bottom glass sub-substrate has a coefficient of thermal expansion of greater than 5 ppm / ℃, and the linewidth of the metal wiring layer of at least one wiring structure of the glass sub-substrate gradually widens from the conductive via to the metal bonding layer; the glass core of the glass sub-substrate located between the top and bottom layers has a dielectric constant of 4-7 and a dielectric loss of 0.007-0.009, and the glass sub-substrate uses silver metal wiring.

[0018] According to the present invention, a method for manufacturing a glass interposer stacked substrate, by separately manufacturing at least three types of glass sub-substrates and then stacking and bonding them, has the following advantages: the sub-substrate manufacturing process is independently controllable, and parallel processing can be performed to avoid the risk of lamination defects in traditional multilayer boards that are processed in one go, thus significantly shortening the overall process time; after cutting, each individual sub-substrate is independently inspected, and qualified products are selected for stacking, avoiding the scrapping of the entire board due to local defects in traditional monolithic substrates, thus significantly improving the yield; the functional modular design allows only the target sub-substrates to be replaced during product iteration, for example, by replacing the combination and stacking order of different glass sub-substrates according to different flip chips.

[0019] According to another aspect of one or more embodiments, a semiconductor packaging structure is provided, including the glass interposer stacked substrate described above, or the glass interposer stacked substrate prepared by the fabrication method described above. A semiconductor chip is flip-chip mounted on the glass interposer stack substrate and electrically connected to the metal bonding layer of the uppermost glass sub-substrate; and Bottom filler adhesive is used to fill the space between the semiconductor chip and the uppermost glass sub-substrate.

[0020] Optionally, the semiconductor chip includes a high-bandwidth memory (HBM) and a graphics processing unit (GPU) chip, both of which are flip-chip mounted on the uppermost glass sub-substrate; the side of the glass interposer stack substrate facing away from the semiconductor chip is connected to the PCB board to achieve electrical interconnection with external circuits.

[0021] By adopting the above solution, the present invention has the following advantages: 1. Manufacturing optimization: Multiple glass sub-substrates are processed in parallel to improve yield, shorten time, and achieve high-density integration; sub-substrates are independently inspected and screened to avoid local defects from causing the entire piece to fail and reduce costs.

[0022] 2. Performance Adaptation: The layered structure uses glass with different properties (low CTE / high thermal conductivity / silver wiring for the top layer, low dielectric loss for the middle layer, and medium CTE / gradient wiring for the bottom layer) to meet the thermal, electrical, and mechanical requirements of multiple chips and solve the problem that a single substrate cannot adapt to all chips. Attached Figure Description

[0023] Figure 1 This is a cross-sectional schematic diagram of a glass interposer stacked substrate according to an embodiment of the present invention; Figure 2 This is a schematic flowchart of a method for fabricating a glass interposer stacked substrate according to an embodiment of the present invention. Figures 3-19 This is a cross-sectional schematic diagram of the substrate for each step of the method for manufacturing a glass interposer stacked substrate according to an embodiment of the present invention. Figure 20 This is a cross-sectional schematic diagram of the semiconductor packaging structure according to an embodiment of the present invention; Figure 21 This is a warpage map of the glass interposer stacked substrate according to an embodiment of the present invention. Warpage: 82 μm; Figure 22 Warpage: 122 μm, representing the warp contour of a traditional multilayer board.

[0024] Label Explanation: Glass interlayer stacked substrate 1; The middle layer glass sub-substrate 10, the middle layer glass core board 110, the first side 110a, the second side 110b, the middle layer conductive via 111, the middle layer redistribution structure 120, the middle layer first redistribution structure 120a, the first redistribution layer 121a, the first dielectric layer 1211a, the first metal wiring layer 1212a, the first via 1213a, the middle layer second redistribution structure 120b, the second redistribution layer 121b, the second dielectric layer 1211b, the second metal wiring layer 1212b, the second via 1213b, the middle layer first metal bonding layer 130a, and the middle layer second metal bonding layer 130b; Top glass sub-substrate 20, top glass core board 210, top conductive via 211, top redistribution structure 220, top first redistribution structure 220a, third redistribution layer 221a, third dielectric layer 2211a, third metal wiring layer 2212a, third via 2213a, top second redistribution structure 220b, fourth redistribution layer 221b, fourth dielectric layer 2211b, fourth metal wiring layer 2212b, fourth via 2213b, top first metal bonding layer 230a, top second metal bonding layer 230b; Bottom glass sub-substrate 30, bottom glass core board 310, bottom conductive via 311, bottom redistribution structure 320, bottom first redistribution structure 320a, fifth redistribution layer 321a, fifth dielectric layer 3211a, fifth metal wiring layer 3212a, fifth via 3213a, bottom second redistribution structure 320b, sixth redistribution layer 321b, sixth dielectric layer 3211b, sixth metal wiring layer 3212b, sixth via 3213b, bottom first metal bonding layer 330a, bottom second metal bonding layer 330b; Filler material 40; High-bandwidth memory HBM 2; Graphics processing unit (GPU) chip 3. Detailed Implementation

[0025] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0026] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the invention to those skilled in the art.

[0027] It should be noted that, in this paper, the direction parallel to the main surface of the core board can be called the horizontal direction (X direction), and the direction perpendicular to both the horizontal direction (X direction) and the main surface of the core board can be called the vertical direction (Z direction), which is also the stacking direction.

[0028] This application is based on the inventor's considerations as follows: Glass packaging substrates, such as 24-layer substrates, face significant challenges in stacking alignment, dielectric uniformity, interlayer interconnect precision control, and heat dissipation due to their extremely high lamination complexity. Any minute interlayer alignment deviation or lamination defect can lead to signal integrity issues or inner layer short circuits. In addition, the difficulty of via forming and electroplating processes increases exponentially, resulting in a significantly lower overall manufacturing yield than conventional laminates. Furthermore, a single-material glass substrate cannot simultaneously meet the thermal, electrical, and mechanical requirements of multiple chips.

[0029] Therefore, according to one or more embodiments of the glass interposer stacked substrate, the traditional single-material substrate is first split into independent glass sub-substrates of different glass materials, which are then stacked by metal bonding and filled with filler material to form an interposer substrate integrating multiple glass materials; in this way, the sub-substrates can be processed in parallel, simplifying the multi-layer RDL structure stacking process, reducing the risk of alignment deviation and lamination defects, significantly improving manufacturing yield and shortening processing time; high-density integration is achieved through multi-layer sub-substrate stacking.

[0030] Secondly, based on the differences in the thermal-electrical-mechanical characteristics of different chips in the AI ​​module, different glass sub-substrates at different levels use glass substrates with different characteristics to solve the defect that "a single substrate cannot meet the needs of multiple chips". For example, the top glass sub-substrate uses low CTE glass to match the silicon chip, reducing thermal stress between the chip and the substrate. In addition, the top glass sub-substrate has good thermal conductivity, which can solve the problem of local high heat after GPU / HBM flip-chip. Furthermore, the top glass sub-substrate uses silver metal wiring to reduce the loss of high-frequency signal transmission of the device and further improve the thermal conductivity of this layer of glass sub-substrate. The middle glass sub-substrate uses a low dielectric loss glass substrate, combined with silver metal wiring, to meet the integrity requirements of high-speed signal transmission of more than 2 Gbps between HBM and GPU, avoiding signal attenuation problems. The bottom glass sub-substrate uses medium CTE glass to alleviate the overall thermal stress after multi-layer stacking, avoid substrate warping after PCB mounting, and the gradual widening of the metal wiring layer of at least one wiring structure of the bottom glass sub-substrate can avoid metal fatigue caused by abrupt changes in linewidth.

[0031] Furthermore, filling the spaces between adjacent glass sub-substrates with a highly thermally conductive material eliminates air gaps at the bonding interface, improving heat dissipation efficiency and structural reliability, thus meeting the high-density integration and high thermal management requirements of AI chips. Independent testing and screening of sub-substrates avoids the failure of the entire substrate due to localized defects in traditional monolithic substrates, thereby reducing costs.

[0032] Figure 1 A glass interposer stack substrate according to one or more embodiments is shown.

[0033] refer to Figure 1 The glass interposer stacked substrate 1 includes at least three glass sub-substrates disposed along the stacking direction. Each glass sub-substrate includes: a glass core plate having a through-hole filled with conductive material to form a conductive via; two redistribution structures formed on opposite sides of the glass core plate and electrically interconnected through the conductive via; each redistribution structure having at least two redistribution layers, each redistribution layer including a dielectric layer, a metal wiring layer, and multiple vias; the vias electrically connecting the metal wiring layers of two adjacent redistribution layers; and a metal bonding layer disposed on the side of each redistribution structure away from the glass core plate and electrically connected to the redistribution structure. Along the stacking direction, the glass core plate of the top glass sub-substrate has a coefficient of thermal expansion of less than 5 ppm / ℃ and a thermal conductivity of 1.2 W / (m·K), and the glass sub-substrate uses silver metal wiring; the glass core plate of the bottom glass sub-substrate has a coefficient of thermal expansion of greater than 5 ppm / ℃. The linewidth of the metal wiring layer of at least one wiring structure of the glass sub-substrate gradually widens from the conductive via to the metal bonding layer; the dielectric constant of the glass core plate of the glass sub-substrate located between the top and bottom layers is 4-7, the dielectric loss is 0.007-0.009, and the glass sub-substrate uses silver metal wiring; along the stacking direction, any two adjacent glass sub-substrates are stacked and bonded through the metal bonding layer, and the bonding gap between the two adjacent glass sub-substrates is filled with filler material to form a glass interlayer stacked substrate 1.

[0034] In other words, the glass interlayer stacked substrate 1 is formed by stacking and bonding at least three glass sub-substrates with different physical properties through metal bonding layers between adjacent glass sub-substrates; thus, a single-layer substrate is split into independent sub-substrates with different physical properties made of different glass materials, which are then stacked by metal bonding and filled with filler material to form an interlayer substrate integrating multiple glass materials. For example Figure 1The glass interposer stacked substrate 1 includes three types of glass sub-substrates: a middle glass sub-substrate 10, a top glass sub-substrate 20, and a bottom glass sub-substrate 30. These three types of glass sub-substrates have different physical characteristics. The top glass sub-substrate 20 is used for flip-chip bonding, requiring high heat dissipation performance and low high-frequency signal transmission loss. The middle glass sub-substrate 10 connects the top glass sub-substrate 20 and the bottom glass sub-substrate 30, requiring low high-frequency signal transmission loss. The bottom glass sub-substrate 30 connects to the PCB board, requiring good support performance and that the wiring disperses stress at the connection point with the PCB pads. Of course, according to other embodiments of the present invention, the glass sub-substrates of the glass interposer stacked substrate 1 are not limited to... Figure 1 It can have three layers, or four or more layers.

[0035] Specifically, the structures of each glass sub-substrate are roughly the same, with the middle glass sub-substrate 10 as an example. Please refer to... Figures 3-19 The middle glass sub-substrate 10 includes a middle glass core 110, two middle redistribution structures 120, and a middle metal bonding layer, such as 130a or 130b.

[0036] The intermediate glass core board 110 has a through-hole 111; that is, the intermediate glass core board 110 has a through-hole 111 that vertically penetrates the intermediate glass core board 110. A low-dielectric-loss glass material is used as the core board, such as borosilicate glass, with a dielectric constant of 4-7 and a dielectric loss of 0.007-0.009 selected. The glass allows for larger panel-level encapsulation, making parallel processing of each intermediate glass sub-substrate 10 possible, thus shortening processing time and reducing manufacturing costs.

[0037] A middle-layer conductive via 111 can be provided between two middle-layer redistribution structures 120, providing an electrical connection path between the two middle-layer redistribution structures 120. There can be one or more middle-layer conductive vias 111, each containing a conductive material within the via. This conductive material includes a seed layer and a conductive layer. The seed layer covers the inner wall of the glass via, and the conductive layer covers the seed layer. The seed layer can be a titanium layer and a copper layer, or a single titanium layer; the conductive layer can be a silver layer. Silver has a lower Young's modulus than copper, resulting in less thermal stress between the silver and the glass, thus preventing TGV cracking. Furthermore, silver has lower resistivity and higher thermal conductivity than copper, leading to better performance of the glass sub-substrate in high-frequency signal transmission and heat dissipation for high-power devices. The middle-layer conductive via 111 can have upper and lower surfaces spaced apart from each other in the vertical direction. The upper surface of the intermediate conductive via 111 can be coplanar with the first side 110a of the intermediate glass core board 110, and the lower surface of the intermediate conductive via 111 can be coplanar with the second side 110b of the intermediate glass core board 110. The upper surface of the intermediate conductive via 111 can be connected to the intermediate redistribution structure 120a of the first side 110a, and the lower surface of the intermediate conductive via 111 can be connected to the intermediate redistribution structure 120b of the second side 110b.

[0038] Additionally, each intermediate conductive via 111 can have any suitable shape, including, for example, a cylindrical shape. In one or more other embodiments, each intermediate conductive via 111 can have a vertically symmetrical tapered shape.

[0039] Two intermediate layer redistribution structures 120 are formed one-to-one on opposite sides of the intermediate glass core 110 (i.e., the first side 110a and the second side 110b) and are electrically interconnected through intermediate conductive vias 111. Each intermediate layer redistribution structure 120 has at least two redistribution layers, such as 121a or 121b. The redistribution structure on the first side 110a of the intermediate glass core 110 can be defined as the first intermediate layer redistribution structure 120a; the redistribution structure on the second side 110b of the intermediate glass core 110 can be defined as the second intermediate layer redistribution structure 120b.

[0040] The middle layer first redistribution structure 120a includes at least two first redistribution layers 121a. Each first redistribution layer 121a may include a first dielectric layer 1211a, a first metal wiring layer 1212a, and a plurality of first vias 1213a; each first via 1213a is electrically connected to the first metal wiring layer 1212a of two adjacent first redistribution layers 121a, and the first metal wiring layer 1212a and the first via 1213a may be included in or surrounded in the first dielectric layer 1211a.

[0041] The first dielectric layer 1211a may be stacked in the vertical direction. The first dielectric layer 1211a may include an insulating material, such as a photosensitive imaging dielectric resin prepared by combining an epoxy resin and a photoinitiator, and may further include photosensitive polyimide and / or inorganic fillers, but is not limited thereto. The first metal wiring layer 1212a and the first via 1213a may be provided as conductive patterns, and the conductive patterns may be positioned within the first dielectric layer 1211a. The first metal wiring layer 1212a may be provided to extend horizontally within the first dielectric layer 1211a. The first via 1213a may penetrate one or more of the first dielectric layers 1211a in the vertical direction, thereby contacting and electrically connecting with some wiring patterns in the first metal wiring layer 1212a. The first metal wiring layer 1212a has a minimum linewidth / spacing of 3 μm / 3 μm-5 μm / 5 μm and a metal thickness of 3 μm / 3 μm-5 μm / 5 μm. According to some specific embodiments, the first via 1213a can have any suitable shape, including, for example, a conical or cylindrical shape. The first metal wiring layer 1212a and the first via 1213a are made of conductive metal, which includes a seed layer and a conductive layer. The seed layer covers the surface of the glass core board or the first dielectric layer 1211a, and the conductive layer covers the seed layer; wherein the seed layer is a titanium layer and a copper layer, or a titanium layer alone; the conductive layer is a silver layer. Silver has a lower Young's modulus than copper, resulting in less thermal stress between silver and glass; furthermore, silver has lower resistivity and higher thermal conductivity than copper, enabling the glass sub-substrate to perform better in high-frequency signal transmission and heat dissipation for high-power devices.

[0042] The middle-layer second redistribution structure 120b includes at least two second redistribution layers 121b. Each second redistribution layer 121b may include a second dielectric layer 1211b, a second metal wiring layer 1212b, and a plurality of second vias 1213b; each second via 1213b electrically connects the second metal wiring layers 1212b of two adjacent second redistribution layers 121b, and the second metal wiring layers 1212b and the second vias 1213b may be included in or surrounded in the second dielectric layer 1211b. The second dielectric layers 1211b may be stacked in the vertical direction. The second dielectric layer 1211b may include an insulating material, such as a photosensitive imaging dielectric resin prepared by combining epoxy resin and a photoinitiator, and may further include photosensitive polyimide and / or inorganic fillers, but is not limited thereto. The second metal wiring layer 1212b and the second via 1213b may be provided as conductive patterns, and the conductive patterns may be positioned in the second dielectric layer 1211b. The second metal wiring layer 1212b may be provided to extend horizontally within the second dielectric layer 1211b. The second via 1213b may penetrate one or more of the second dielectric layers 1211b vertically to contact and electrically connect with some wiring patterns in the second metal wiring layer 1212b. The second metal wiring layer 1212b has a minimum linewidth / spacing of 3 μm / 3 μm-5 μm / 5 μm and a metal thickness of 3 μm / 3 μm-5 μm / 5 μm. According to some specific embodiments, the second via 1213b may have any suitable shape, including, for example, a tapered or cylindrical shape. The second metal wiring layer 1212b and the second via 1213b are made of a conductive metal comprising a seed layer and a conductive layer. The seed layer covers the surface of the glass core board or the first dielectric layer 1211a, and the conductive layer covers the seed layer; wherein the seed layer is a titanium layer and a copper layer, or a single titanium layer; and the conductive layer is a silver layer. Silver has a lower Young's modulus than copper, resulting in less thermal stress between the silver and glass. In addition, silver has lower resistivity and higher thermal conductivity than copper, which makes the glass sub-substrate perform better in high-frequency signal transmission and heat dissipation of high-power devices.

[0043] A middle-layer metal bonding layer (e.g., 130a or 130b) is disposed on the side of each middle-layer redistribution structure 120 opposite to the middle-layer glass core plate 110 and is electrically connected to the middle-layer redistribution structure 120. Along the stacking direction, any two adjacent glass sub-substrates are stacked and bonded by the metal bonding layer. That is, a metal bonding layer is disposed on the lower surface (the side opposite to the middle-layer glass core plate 110) of the first middle-layer redistribution structure 120a, which can be defined as the first middle-layer metal bonding layer 130a; a metal bonding layer is also disposed on the upper surface (the side opposite to the middle-layer glass core plate 110) of the second middle-layer redistribution structure 120b, which can be defined as the second middle-layer metal bonding layer 130b. Thus, the stacking of multiple glass sub-substrates can be achieved by bonding two vertically opposite metal bonding layers. In one or more embodiments, the intermediate metal bonding layer (e.g., 130a or 130b) consists of a plurality of protrusions spaced apart on the side of the intermediate redistribution structure 120 away from the intermediate glass core 110.

[0044] Specifically, the bumps, as a concrete implementation of the middle metal bonding layer (e.g., 130a or 130b), can adopt spherical or columnar structures. Spherical bumps include, but are not limited to, reflowable solderable materials such as solder balls and gold balls; columnar bumps are preferably copper column structures, and their height can be precisely controlled through electroplating. The spacing of the bump array must meet the alignment accuracy requirements when adjacent glass sub-substrates are stacked. The electrical connection between the bumps and the redistribution structure is achieved by fabricating a bump under-metal (UBM) layer on the outermost metal wiring layer of the redistribution structure, followed by forming the bump structure through ball placement or electroplating.

[0045] Thus, the spacing of the bumps effectively releases the thermal stress generated during the stacking process, avoiding interface delamination caused by differences in thermal expansion coefficients. Secondly, the bump structure can compensate for the flatness error between substrates through plastic deformation during bonding, improving the bonding yield. In addition, the air gaps formed by the bump array facilitate the full filling of the filling material 40, thereby improving the heat dissipation performance of the overall structure. Compared with traditional monolithic substrates that require the processing of multiple redistribution layers in one go, this embodiment utilizes the bonding of intermediate metal bonding layers (such as 130a or 130b) to significantly reduce the process difficulty of multi-layer stacking while ensuring the reliability of electrical interconnection.

[0046] In one or more specific embodiments, the bumps on one of the intermediate layer redistribution structures 120 of the intermediate layer glass sub-substrate 10 are solder balls or gold balls, and the bumps on the other intermediate layer redistribution structure 120 are copper pillars. For example, the bumps on the first intermediate layer redistribution structure 120a are copper pillars, and the bumps on the second intermediate layer redistribution structure 120b are solder balls or gold balls.

[0047] Specifically, when solder balls or gold balls are used as bump materials, their low melting point allows for interconnection of the middle metal bonding layers (e.g., 130a or 130b) during bonding via thermoforming or reflow soldering. When copper pillars are used as bump materials, their high mechanical strength and excellent conductivity enable them to withstand mechanical stress during stacking and ensure high-quality electrical signal transmission. Combining these two bump materials allows for differentiated bonding: solder balls or gold balls provide good wettability and interfacial bonding, while copper pillars provide structural support and current carrying capacity. As a preferred embodiment, the diameter of the solder balls can be controlled between 50-200 μm, the diameter of the gold balls between 50-100 μm, and the height of the copper pillars can be set to 50-150 μm, with a diameter matching that of the solder / gold balls.

[0048] The thickness of the intermediate glass sub-substrate 10 formed in this way can be ≥150 μm.

[0049] Similarly, the structure and principle of the top glass sub-substrate 20 are largely the same as those of the middle glass sub-substrate 10 described above. The difference lies in the fact that the top glass core plate 210 of the top glass sub-substrate 20 uses a glass material with a low coefficient of thermal expansion and a high thermal conductivity, such as borosilicate glass. This borosilicate glass is doped with Al2O3 thermally conductive particles. The doping with metal ions or metal oxides to improve the thermal conductivity of the material is a current technology and will not be described in detail here. Thus, the coefficient of thermal expansion of the top glass core plate 210 is less than 5 ppm / ℃. For example, a coefficient of thermal expansion of 3 ppm / ℃ and a thermal conductivity of 1.2 W / (m·K) are selected to ensure the heat dissipation effect of the top glass sub-substrate 20.

[0050] The top conductive via 211 and metal wiring layer of the top glass sub-substrate 20 also have a seed layer and a conductive layer covering the seed layer. The seed layer includes a titanium layer, or a titanium layer and a copper layer; the conductive layer is a silver layer. This enables the glass sub-substrate to have better performance in high-frequency signal transmission and heat dissipation of high-power devices.

[0051] Furthermore, each third redistribution layer 221a of the top-layer first redistribution structure 220a of the top-layer glass sub-substrate 20 includes a third dielectric layer 2211a, a third metal wiring layer 2212a, and a third via 2213a, wherein the minimum linewidth / spacing of the third metal wiring layer 2212a is 2 μm, and the metal thickness is 2 μm. Each fourth redistribution layer 221b of the top-layer second redistribution structure 220b of the top-layer glass sub-substrate 20 includes a fourth dielectric layer 2211b, a fourth metal wiring layer 2212b, and a fourth via 2213b, wherein the minimum linewidth / spacing of the fourth metal wiring layer 2212b is 2 μm, and the metal thickness is 2 μm.

[0052] Please refer to Figure 18The bottom glass sub-substrate 30 includes a bottom glass core 310, two bottom redistribution structures 320 and a bottom metal bonding layer (e.g., 330a or 330b).

[0053] The bottom glass core board 310 has a through-hole 311; that is, the bottom glass core board 310 has a through-hole 311 that vertically penetrates the bottom glass core board 310. A glass material with a medium coefficient of thermal expansion is used as the core board, such as soda lime glass. The CTE of this soda lime bottom glass core board 310 is greater than 5 ppm / ℃, for example, a CTE of 9 ppm / ℃ is chosen, which is between that of the top borosilicate glass and the PCB board, alleviating overall thermal stress after multilayer stacking and preventing substrate warping after PCB mounting.

[0054] A bottom conductive via 311 may be provided between two bottom redistribution structures 320, providing an electrical connection path between the two bottom redistribution structures 320. There may be one or more bottom conductive vias 311, each containing a conductive material within the via, which may be copper, aluminum, silver, gold, molybdenum, titanium, or a combination thereof. The bottom conductive via 311 may have an upper surface and a lower surface spaced apart from each other in a vertical direction. The upper surface of the bottom conductive via 311 may be connected to the bottom redistribution structure 320a, and the lower surface of the bottom conductive via 311 may be connected to the bottom redistribution structure 320b.

[0055] Additionally, each bottom conductive via 311 can have any suitable shape, including, for example, a cylindrical shape. In one or more other embodiments, each bottom conductive via 311 can have a vertically symmetrical tapered shape.

[0056] Two bottom redistribution structures 320 are formed one-to-one on opposite sides of the bottom glass core 310 and are electrically interconnected through bottom conductive vias 311; each bottom redistribution structure 320 has at least two redistribution layers (e.g., 321a or 321b). The redistribution structure on one side of the bottom glass core 310 can be defined as the bottom first redistribution structure 320a; the redistribution structure on the other side of the bottom glass core 310 can be defined as the bottom second redistribution structure 320b.

[0057] The bottom first redistribution structure 320a includes at least two fifth redistribution layers 321a. Each fifth redistribution layer 321a may include a fifth dielectric layer 3211a, a fifth metal wiring layer 3212a, and a plurality of fifth vias 3213a; each fifth via 3213a is electrically connected to the fifth metal wiring layer 3212a of two adjacent fifth redistribution layers 321a, and the fifth metal wiring layer 3212a and the fifth via 3213a may be included in or surrounded in the fifth dielectric layer 3211a.

[0058] The fifth dielectric layer 3211a can be stacked vertically. The underlying first super-wiring structure 320a includes a fifth dielectric layer 3211a made of at least two dielectric materials. For example, the first dielectric material is epoxy resin, disposed adjacent to the underlying glass core 310; the second dielectric material is a siloxane film, disposed on the outermost metal wiring layer of the underlying first super-wiring structure 320a. Thus, the first dielectric material has strong adhesion to the glass substrate, ensuring structural stability during reflow soldering of the underlying glass sub-substrate 30; while the second dielectric material, covering the outermost wiring surface, absorbs the thermal expansion difference stress between the wiring and the dielectric layer during thermal cycling, preventing the dielectric layer from cracking. Besides the first and second dielectric materials, the remaining fifth dielectric layers 3211a can also use photosensitive polyimide or other non-photosensitive materials. The fifth metal wiring layer 3212a and the fifth via 3213a can be provided as conductive patterns, and the conductive patterns can be positioned within the fifth dielectric layer 3211a. The fifth metal wiring layer 3212a may be provided to extend horizontally within the fifth dielectric layer 3211a. The fifth via 3213a may penetrate one or more of the fifth dielectric layers 3211a in the vertical direction, thereby contacting and electrically connecting with some wiring patterns in the fifth metal wiring layer 3212a. The fifth metal wiring layer 3212a, electrically connected to the bottom conductive via 311, has a minimum metal linewidth / spacing of 5 μm / 5 μm-10 μm / 10 μm and a metal thickness of 5 μm-10 μm. Moving towards the bottom first metal bonding layer 330a, the metal linewidth / spacing of the fifth metal wiring layer 3212a gradually increases. For example, the innermost layer (the one adjacent to and electrically connected to the bottom conductive via 311) has a minimum linewidth / spacing of 5 μm / 5 μm, the next innermost layer has a minimum linewidth / spacing of 7 μm / 7 μm, and so on, until the outermost layer (adjacent to the bottom first metal bonding layer 330a) has a minimum linewidth / spacing of 10 μm / 10 μm. μm; the metal linewidth / spacing of the gradually widening fifth metal wiring layer 3212a can be varied by changing the photoresist exposure size; thus, by setting the metal linewidth / spacing of the gradually widening fifth metal wiring layer 3212a, metal fatigue caused by abrupt linewidth changes can be avoided, reducing the wiring breakage rate after thermal cycling. According to some specific embodiments, the fifth via 3213a can have any suitable shape, including, for example, a conical or cylindrical shape. The fifth metal wiring layer 3212a and the fifth via 3213a are made of conductive metals, such as copper, aluminum, titanium, tantalum, molybdenum, and their alloys, but are not limited thereto.

[0059] The bottom second redistribution structure 320b includes at least two sixth redistribution layers 321b. Each sixth redistribution layer 321b may include a sixth dielectric layer 3211b, a sixth metal wiring layer 3212b, and a plurality of sixth vias 3213b; each sixth via 3213b electrically connects the sixth metal wiring layers 3212b of two adjacent sixth redistribution layers 321b, and the sixth metal wiring layers 3212b and the sixth vias 3213b may be included in or surrounded within the sixth dielectric layer 3211b. The sixth dielectric layers 3211b may be stacked in the vertical direction. The sixth dielectric layer 3211b may include an insulating material, such as a photosensitive imaging dielectric resin prepared by combining epoxy resin and a photoinitiator, and may further include photosensitive polyimide and / or inorganic fillers, and may also be similar to, but not limited to, the fifth dielectric layer 3211a described above. The sixth metal wiring layer 3212b and the sixth via 3213b may be provided as conductive patterns, and the conductive patterns may be positioned within the sixth dielectric layer 3211b. The sixth metal wiring layer 3212b may be provided to extend horizontally within the sixth dielectric layer 3211b. The sixth via 3213b may penetrate one or more of the sixth dielectric layers 3211b in the vertical direction, thereby contacting and electrically connecting with some wiring patterns in the sixth metal wiring layer 3212b. The sixth metal wiring layer 3212b, which is electrically connected to the underlying conductive via 311, has a minimum metal linewidth / spacing of 5 μm / 5 μm-10 μm / 10 μm and a metal thickness of 5 μm-10 μm. Preferably, towards the bottom second metal bonding layer 330b, the metal linewidth / spacing of the sixth metal wiring layer 3212b gradually increases. For example, the minimum linewidth / spacing of the sixth metal wiring layer 3212b in the innermost layer (i.e., the layer adjacent to and electrically connected to the bottom conductive via 311) is 5 μm / 5 μm, the minimum linewidth / spacing of the sixth metal wiring layer 3212b in the next innermost layer is 7 μm / 7 μm, and so on, until the minimum linewidth / spacing of the sixth metal wiring layer 3212b in the outermost layer (adjacent to the bottom second metal bonding layer 330b) is 10 μm / 10 μm. Of course, in other embodiments, the metal linewidth / spacing of the sixth metal wiring layer 3212b in each layer of the bottom second rewiring structure 320b can be the same. According to some specific embodiments, the sixth via 3213b can have any suitable shape, including, for example, a tapered or cylindrical shape. The sixth metal wiring layer 3212b and the sixth via 3213b are made of conductive metals, such as copper, aluminum, titanium, tantalum, molybdenum and their alloys, but not limited to these.

[0060] As can be seen from the above, along the stacking direction, from the top glass sub-substrate 20 to the bottom glass sub-substrate 30, the metal wiring layers of the redistribution structure are arranged from dense to sparse.

[0061] A bottom metal bonding layer (e.g., 330a or 330b) is disposed on the side of each bottom redistribution structure 320 facing away from the bottom glass core plate 310 and is electrically connected to the bottom redistribution structure 320; that is, a metal bonding layer is disposed on the lower surface (the side facing away from the bottom glass core plate 310) of the bottom first redistribution structure 320a, which can be defined as the bottom first metal bonding layer 330a; a metal bonding layer is also disposed on the upper surface (the side facing away from the bottom glass core plate 310) of the bottom second redistribution structure 320b, which can be defined as the bottom second metal bonding layer 330b. Thus, a multilayer glass sub-substrate can be stacked by bonding two metal bonding layers that are vertically opposite each other. In one or more embodiments, the bottom metal bonding layer (e.g., 330a or 330b) consists of a plurality of protrusions spaced apart on the side of the bottom redistribution structure 320 facing away from the bottom glass core plate 310.

[0062] Specifically, the bumps, as a concrete implementation of the underlying metal bonding layer (e.g., 330a or 330b), can adopt spherical or columnar structures. Spherical bumps include, but are not limited to, reflowable solderable materials such as solder balls or gold balls; columnar bumps are preferably copper column structures, and their height can be precisely controlled through electroplating. The spacing of the bump array must meet the alignment accuracy requirements when adjacent glass sub-substrates are stacked. The electrical connection between the bumps and the redistribution structure is achieved by fabricating a bump under-metal (UBM) layer on the outermost metal wiring layer of the redistribution structure, followed by forming the bump structure through ball placement or electroplating.

[0063] Thus, the spacing of the bumps effectively releases the thermal stress generated during the stacking process, avoiding interface delamination caused by differences in thermal expansion coefficients. Secondly, the bump structure can compensate for the flatness error between substrates through plastic deformation during bonding, improving the bonding yield. In addition, the air gaps formed by the bump array facilitate the full filling of the filling material 40, thereby improving the heat dissipation performance of the overall structure. Compared with traditional monolithic substrates that require the processing of multiple redistribution layers in one go, this embodiment utilizes the bonding of the bottom metal bonding layer (e.g., 330a or 330b) to significantly reduce the process difficulty of multi-layer stacking while ensuring the reliability of electrical interconnection.

[0064] In one or more specific embodiments, the bumps on one of the bottom redistribution structures 320 of the bottom glass sub-substrate 30 are solder balls or gold balls, and the bumps on the other bottom redistribution structure 320 are copper pillars. For example, the bumps on the first bottom redistribution structure 320a are copper pillars, and the bumps on the second bottom redistribution structure 320b are solder balls or gold balls.

[0065] Specifically, when solder balls or gold balls are used as bump materials, their low melting point allows for interconnection of the underlying metal bonding layers (e.g., 330a or 330b) during bonding via thermoforming or reflow soldering. When copper pillars are used as bump materials, their high mechanical strength and excellent conductivity enable them to withstand mechanical stress during stacking and ensure high-quality electrical signal transmission. Combining these two bump materials allows for differentiated bonding: solder balls or gold balls provide good wettability and interfacial bonding, while copper pillars provide structural support and current carrying capacity. As a preferred embodiment, the diameter of the solder balls can be controlled between 50-200 μm, the diameter of the gold balls between 50-100 μm, and the height of the copper pillars can be set to 50-150 μm, with a diameter matching that of the solder / gold balls.

[0066] The thickness of the bottom glass sub-substrate 30 formed in this way can be ≥150 μm. The thickness of the bottom glass sub-substrate 30 is set to 150 μm or more, mainly based on the following considerations: In a multilayer interposer stack structure, an excessively thin sub-substrate has insufficient mechanical strength, thermal stability, and processing yield. Insufficient thickness may cause the substrate to warp or crack during high-temperature bonding, affecting stacking accuracy and reliability.

[0067] The bonding gaps between two adjacent glass sub-substrates are filled with filler material 40 to form a glass interposer stack substrate 1. That is, after the multilayer glass sub-substrates are stacked and bonded, filler material 40 can be filled into the bonding gaps between every two adjacent glass sub-substrates. The filler material 40 is provided to be adjacent to and surrounding each bonding bump of the metal bonding layer. The filler material 40 can be LMUF (liquid molding underfill), CUF (post-fill underfill), high thermal conductivity filler, prepreg, or NCF film. Underfill is preferred, as it eliminates air gaps at the bonding interface, forming a vertical heat dissipation channel from the chip to the substrate, improving overall heat dissipation performance; it also releases thermal stress during the stacking process, preventing interface delamination. The total thickness of the bonded glass interposer stack substrate 1 is ≤1.4 mm, balancing structural thinness and mechanical stability.

[0068] It should be noted that the number of redistribution layers in the redistribution structure of each sub-substrate (middle glass sub-substrate 10, top glass sub-substrate 20, and bottom glass sub-substrate 30) of the glass interposer stacked substrate 1 can be customized as needed to ensure that the redistribution structure includes at least two redistribution layers; and the number of redistribution layers in the redistribution structure of different glass sub-substrates of the glass interposer stacked substrate 1 can be the same or different. For example, Figure 1The glass interposer stacked substrate 1 shown has three sub-substrates: upper, middle, and lower. The upper sub-substrate is the top glass sub-substrate 20, the middle sub-substrate is the middle glass sub-substrate 10, and the lower sub-substrate is the bottom glass sub-substrate 30. The top first rewiring structure 220a of the top glass sub-substrate 20 has two layers of third redistribution layers 221a, and the top second rewiring structure 220b has three layers of fourth redistribution layers 221b. Alternatively, the top first rewiring structure 220a may have three layers of third redistribution layers 221a, and the top second rewiring structure 220b may have two layers of fourth redistribution layers 221b. Or, the top first rewiring structure 220a may have three layers of third redistribution layers 221a, and the top second rewiring structure 220b may have three layers of fourth redistribution layers 221b. Similarly, the middle layer first redistribution structure 120a of the middle layer glass sub-substrate 10 has two first redistribution layers 121a, and the middle layer second redistribution structure 120b has three second redistribution layers 121b; alternatively, the middle layer first redistribution structure 120a may have three first redistribution layers 121a, and the middle layer second redistribution structure 120b may have two second redistribution layers 121b; alternatively, the middle layer first redistribution structure 120a may have three first redistribution layers 121a, and the middle layer second redistribution structure 120b may have three second redistribution layers 121b. Similarly, the number of redistribution layers in the bottom layer redistribution structure 320 of the bottom layer glass sub-substrate 30 can be the same as or different from that of the middle layer glass sub-substrate 10. Preferably, the number of redistribution layers in the redistribution structure of each sub-substrate does not exceed four layers.

[0069] Figure 2 A schematic flowchart illustrating a method for fabricating a glass interposer stacked substrate according to one or more embodiments is shown.

[0070] Please refer to Figure 2 This application proposes a method for fabricating a glass interposer stacked substrate, comprising the following steps: S1: Provide at least three types of glass core boards with conductive through holes; S2: A redistribution structure is provided on each of the opposite sides of each of the glass core boards; each redistribution structure has at least two redistribution layers; the redistribution layer includes a dielectric layer, a metal wiring layer and a plurality of vias; the vias electrically connect the metal wiring layers of two adjacent redistribution layers; S3: Provide a metal bonding layer on the side of each redistribution structure away from the glass core board, and cut the wafer to form at least three types of glass sub-substrates; S4: The at least three types of glass sub-substrates are sequentially stacked and bonded along the stacking direction using the metal bonding layer, and the bonding gap between two adjacent glass sub-substrates is filled with filler material to form the glass interlayer stacked substrate. Along the stacking direction, the glass core of the top glass sub-substrate has a coefficient of thermal expansion of less than 5 ppm / ℃ and a thermal conductivity of 1.2 W / (m·K), and the glass sub-substrate uses silver metal wiring; the glass core of the bottom glass sub-substrate has a coefficient of thermal expansion of greater than 5 ppm / ℃, and the linewidth of the metal wiring layer of at least one wiring structure of the glass sub-substrate gradually widens from the conductive via to the metal bonding layer; the glass core of the glass sub-substrate located between the top and bottom layers has a dielectric constant of 4-7 and a dielectric loss of 0.007-0.009, and the glass sub-substrate uses silver metal wiring.

[0071] In other words, this method enables large-scale mass production of sub-substrates by fabricating redistribution structures and metal bonding layers on large-size glass wafers of different materials, and then cutting them into various glass sub-substrates. After cutting into multiple glass sub-substrates, each sub-substrate can be independently inspected to select qualified sub-substrates for subsequent stacking. Process defects in a single sub-substrate only result in the scrapping of that sub-substrate, avoiding the failure of the entire wafer due to local defects in traditional monolithic substrates, thus improving yield. The functional modular design allows only the target sub-substrate to be replaced during product iteration. For example, different combinations and stacking orders of glass sub-substrates can be replaced according to different flip chips.

[0072] Figures 3-19 This diagram illustrates a cross-sectional view of a substrate showing the steps of a method for fabricating a glass interlayer stacked substrate according to one or more embodiments. For brevity, descriptions overlapping with the previous figures will be omitted, and the differences will be primarily described. The middle glass sub-substrate 10, top glass sub-substrate 20, and bottom glass sub-substrate 30 manufactured in the method described below can be or correspond to Figure 1 The middle glass sub-substrate 10, the top glass sub-substrate 20, and the bottom glass sub-substrate 30 shown herein, and therefore, can be used hereinafter. Figure 1 The same reference numerals are shown in the figures.

[0073] refer to Figures 3-10 First, the middle glass sub-substrate 10 is fabricated. For example... Figure 3 As shown, a middle glass core board 110 is provided. The thickness of the middle glass core board 110 is greater than 700 μm. The middle glass core board 110 is an 8-inch glass wafer. Then, the middle glass core board 110 is subjected to surface cleaning treatment.

[0074] refer to Figure 4The aforementioned intermediate glass core plate 110 is subjected to laser-induced wet etching to obtain TGV vias. Laser induction involves using a pulsed laser to create continuous modified regions on the glass. Compared to unmodified glass, modified glass has a faster etching rate in hydrofluoric acid or alkaline systems. Based on this phenomenon, through-holes, blind holes, or through-grooves and blind grooves can be fabricated on the glass. Specifically, one of nanosecond, picosecond, or femtosecond lasers is first used to create modified regions on the glass, and then the laser-treated glass is immersed in a hydrofluoric acid solution or alkaline solution for etching, resulting in highly uniform glass through-holes and blind holes. Subsequently, a metal material is filled into the TGV vias to form intermediate conductive through-holes 111. The metal material may include a seed layer and a conductive layer. The seed layer covers the inner wall of the glass through-hole, and the conductive layer covers the seed layer. The seed layer may be a titanium layer and a copper layer, or a titanium layer alone; the conductive layer may be a silver layer. The seed layer can be formed by PVD, and the conductive layer may be electroplated silver, chemically plated silver, or filled with silver paste. The upper surface of the intermediate conductive via 111 can be coplanar with the upper surface of the intermediate glass core 110. Specifically, a seed layer can be sputtered using PVD, followed by a conductive layer electroplated with metal, and finally surface CMP. In this embodiment, the intermediate conductive via 111 is fabricated by first forming a blind via, then forming a metal material within the blind via, and finally fabricating a single-sided redistribution structure. In other embodiments, the intermediate conductive via 111 can also be fabricated directly as a through-hole penetrating the first side 110a and the second side 110b of the intermediate glass core 110, followed by forming a metal material within the through-hole, and then simultaneously fabricating a double-sided redistribution structure.

[0075] refer to Figure 5 The first metal wiring layer 1212a may be provided on the first side 110a of the middle glass core 110 and cover one surface of the middle conductive via 111, so that the two are electrically connected.

[0076] refer to Figure 6 The first dielectric layer 1211a can be laminated on the first side 110a of the middle glass core 110 and the first metal wiring layer 1212a, and then a first via 1213a is formed in the first dielectric layer 1211a. One or more first vias 1213a can penetrate one or more first dielectric layers 1211a and contact the first metal wiring layer 1212a. Then, one or more stacked films (first dielectric layers) are laminated on the upper surface of the first dielectric layer 1211a, and the first metal wiring layer 1212a and the first via 1213a of each first redistribution layer 121a are fabricated accordingly to complete the fabrication of the middle layer first redistribution structure 120a. The first dielectric layer 1211a can be a wet film, a dry film, or a non-photosensitive material. The wet film is coated, baked, exposed, developed, and cured. The dry film is applied by roller or vacuum lamination, baked, exposed, developed, and cured. The non-photosensitive material is applied by roller or vacuum lamination, baked, and laser drilling.

[0077] Subsequently, a first metal bonding layer 130a is fabricated on the outer surface of the outermost first redistribution layer 121a of the first redistribution structure 120a. The fabrication of the first metal bonding layer 130a can involve forming a passivation layer, a metal under bump (UBM) layer, and a conductive layer on the first redistribution layer 121a, followed by forming bumps, such as solder balls or gold balls, on the conductive layer.

[0078] refer to Figure 7 Next, a temporary bonding adhesive is applied to the temporary carrier board and baked to temporarily bond it to the middle layer first metal bonding layer 130a of the aforementioned middle layer glass core board 110, so as to temporarily protect the middle layer first metal bonding layer 130a and the middle layer first rewiring structure 120a on that side.

[0079] refer to Figure 8 Then, the middle glass core plate 110 with the temporary carrier plate is flipped over, and the back of the middle glass core plate 110 is thinned to expose the middle conductive through hole 111.

[0080] Next, refer to Figure 9 A second rewiring structure 120b is fabricated on the second side 110b of the intermediate glass core board 110. Specifically, a second metal wiring layer 1212b is first provided on the second side 110b of the intermediate glass core board 110, covering one surface of the intermediate conductive via 111, thereby electrically connecting the two. Then, a second dielectric layer 1211b is laminated onto the second side 110b of the intermediate glass core board 110 and the second metal wiring layer 1212b, and subsequently, a second via 1213b is formed in the second dielectric layer 1211b. One or more second vias 1213b can penetrate one or more second dielectric layers 1211b and contact the second metal wiring layer 1212b. Subsequently, one or more stacked films (second dielectric layers) are laminated on the upper surface of the second dielectric layer 1211b, and correspondingly, the second metal wiring layer 1212b and the second via 1213b of the second redistribution layer 121b are fabricated to complete the fabrication of the middle layer second redistribution structure 120b. The second dielectric layer 1211b can be a wet film, a dry film, or a non-photosensitive material. The wet film process involves coating, baking, exposure, development, and curing; the dry film process involves roller or vacuum lamination, baking, exposure, development, and curing; and the non-photosensitive material process involves roller or vacuum lamination, baking, and laser drilling.

[0081] Then, a second metal bonding layer 130b is fabricated on the outer surface of the outermost second redistribution layer 121b of the second redistribution structure 120b. The fabrication of the second metal bonding layer 130b can be achieved by forming a passivation layer on the second redistribution layer 121b, followed by window electroplating to form bumps, such as copper pillars.

[0082] Then, refer to Figure 10 Laser debonding is used to remove the temporary carrier board, and then the wafer is cut to form multiple middle-layer glass sub-substrates 10.

[0083] The fabrication of the top glass sub-substrate 20 is the same as that of the middle glass sub-substrate 10 described above, and will not be repeated in detail here.

[0084] Similarly, refer to Figures 11-18 Fabricate the bottom glass sub-substrate 30. For example... Figure 11 As shown, a bottom glass core board 310 is provided. The thickness of the bottom glass core board 310 is greater than 700 μm. The bottom glass core board 310 is an 8-inch glass wafer. Then, the bottom glass core board 310 is subjected to surface cleaning treatment.

[0085] refer to Figure 12 The aforementioned bottom glass core plate 310 is subjected to laser-induced wet etching to obtain TGV holes. Laser induction involves using a pulsed laser to create continuous modified regions on the glass. Compared to unmodified glass, modified glass has a faster etching rate in hydrofluoric acid or alkaline systems. Based on this phenomenon, through-holes, blind holes, or through-grooves and blind grooves can be fabricated on the glass. Specifically, one of nanosecond lasers, picosecond lasers, or femtosecond lasers is first used to create modified regions on the glass, and then the laser-treated glass is immersed in a hydrofluoric acid solution or alkaline solution for etching, resulting in highly uniform glass through-holes and blind holes. Subsequently, metal material is filled into the TGV holes to form bottom conductive through-holes 311. The metal material can include, for example, copper, aluminum, silver, gold, molybdenum, titanium, and combinations thereof. The upper surface of the bottom conductive through-holes 311 can be coplanar with the upper surface of the bottom glass core plate 310. Specifically, a seed layer can be sputtered by PVD, followed by a conductive layer electroplated with metal, and finally CMP surface treatment. In this embodiment, the bottom conductive via 311 is fabricated by first forming a blind via, then forming a metal material within the blind via, and finally fabricating a single-sided redistribution structure. In other embodiments, the bottom conductive via 311 can also be fabricated by directly creating through-holes penetrating both opposite sides of the bottom glass core board 310, then forming a metal material within the through-holes, and finally fabricating a double-sided redistribution structure simultaneously.

[0086] refer to Figure 13 The fifth metal wiring layer 3212a may be provided on one side of the bottom glass core 310 and cover one surface of the bottom conductive via 311, so that the two are electrically connected.

[0087] refer to Figure 14The fifth dielectric layer 3211a can be laminated on one side of the bottom glass core board 310 and on the fifth metal wiring layer 3212a, and then a fifth via 3213a is formed in the fifth dielectric layer 3211a. One or more fifth vias 3213a can penetrate one or more fifth dielectric layers 3211a and contact the fifth metal wiring layer 3212a. Then, one or more stacked films (first dielectric layers) are laminated on the upper surface of the fifth dielectric layer 3211a, and the fifth metal wiring layer 3212a and the fifth via 3213a of the fifth redistribution layer 321a of each layer are fabricated accordingly to complete the fabrication of the bottom first redistribution structure 320a. In the bottom first wiring structure 320a, the linewidth of the fifth metal wiring layer 3212a gradually increases from the bottom conductive via 311 to the bottom first metal bonding layer 330a. The linewidth / spacing of this gradually widening fifth metal wiring layer 3212a can be varied by changing the photoresist exposure size. Different fifth dielectric layers 3211a can use different dielectric materials. Specifically, the innermost fifth dielectric layer 3211a (i.e., the one adjacent to the bottom glass core 310) is made of epoxy resin. The epoxy resin can be combined with a photoinitiator to form a photosensitive imaging dielectric resin, in the form of a dry film or a wet film. The wet film is prepared by coating, baking, exposure, development, and curing processes, while the dry film is prepared by roller or vacuum lamination, baking, exposure, development, and curing processes. The outermost layer (i.e., the fifth dielectric layer adjacent to the bottom metal bonding layer, such as 330a or 330b) 3211a is a siloxane film. The siloxane film is applied in dry film form using a coating, baking, exposure, development, and curing process. In addition to epoxy resin materials and siloxane films, the remaining fifth dielectric layers 3211a can also be made of photosensitive polyimide or other non-photosensitive materials. Non-photosensitive materials are applied using roller or vacuum lamination, baking, and laser drilling processes.

[0088] Subsequently, a first metal bonding layer 330a is fabricated on the outer surface of the fifth redistribution layer 321a, the outermost layer of the first redistribution structure 320a. The fabrication of the first metal bonding layer 330a can involve forming a passivation layer, a metal under bump (UBM) layer, and a conductive layer on the fifth redistribution layer 321a, followed by forming bumps, such as solder balls or gold balls, on the conductive layer.

[0089] refer to Figure 15 Next, a temporary bonding adhesive is applied to the temporary carrier board and baked to temporarily bond it to the bottom first metal bonding layer 330a of the bottom glass core board 310, so as to temporarily protect the bottom first metal bonding layer 330a and the bottom first rewiring structure 320a on that side.

[0090] refer to Figure 16Then, the bottom glass core plate 310 with the temporary carrier plate is flipped over, and the back side of the bottom glass core plate 310 is thinned to expose the bottom conductive through hole 311.

[0091] Next, refer to Figure 17 A second-layer redistribution structure 320b is fabricated on the second side 110b of the bottom glass core 310. Specifically, a sixth metal wiring layer 3212b is first provided on the bottom glass core 310, covering one surface of the bottom conductive via 311, thereby electrically connecting the two. Then, a sixth dielectric layer 3211b is laminated onto the bottom glass core 310 and the sixth metal wiring layer 3212b, followed by the formation of a sixth via 3213b in the sixth dielectric layer 3211b. One or more sixth vias 3213b can penetrate one or more sixth dielectric layers 3211b and contact the sixth metal wiring layer 3212b. Then, one or more laminated films (second dielectric layers) are laminated on the upper surface of the sixth dielectric layer 3211b, and the sixth metal wiring layer 3212b and sixth via 3213b of each sixth redistribution layer 321b are fabricated accordingly to complete the fabrication of the second-layer redistribution structure 320b. The sixth dielectric layer 3211b can be made of wet film, dry film, or non-photosensitive material. The wet film is made of coating, baking, exposure, and development process. The dry film is made of roller or vacuum lamination, baking, exposure, and development process. The non-photosensitive material is made of roller or vacuum lamination, baking, and laser drilling process.

[0092] Then, a second metal bonding layer 330b is fabricated on the outer surface of the sixth distribution layer 321b, the outermost layer of the second bottom wiring structure 320b. The fabrication of the second bottom metal bonding layer 330b can be achieved by forming a passivation layer on the sixth distribution layer 321b, followed by window electroplating to form bumps, such as copper pillars.

[0093] Then, refer to Figure 18 Laser debonding is used to remove the temporary carrier board, and then the wafer is cut to form multiple bottom glass sub-substrates 30.

[0094] Next, according to design requirements, the top glass sub-substrate 20, the middle glass sub-substrate 10, and the bottom glass sub-substrate 30 are aligned and thermo-bonded using metal bonding layers, thus completing the multi-layer stacking sequentially, for example... Figure 19 The middle first metal bonding layer 130a of the middle glass sub-substrate 10 and the bottom second metal bonding layer 330b of the bottom glass sub-substrate 30 are aligned and thermo-pressed together. Then, the middle second metal bonding layer 130b of the middle glass sub-substrate 10 is aligned and the top second metal bonding layer 230b of the top glass sub-substrate 20 are thermo-pressed together to form... Figure 19The stacked bodies. The hot-press bonding temperature is 250-300℃, the pressure is 5-10 MPa, and the time is 5-10 min.

[0095] In addition, the number of stacked layers can be designed according to actual needs.

[0096] Finally, refer to Figure 1 The bonding gap between two adjacent sub-substrates of the above-mentioned stack is filled with material 40 to form a glass interposer stack substrate 1. For example, a certain amount of adhesive is applied to the bottom edge of the substrate using the underfill method. After the adhesive fills the entire gap between the substrates under capillary action, it is thermo-cured to make the adhesive solid, thereby achieving the functions of bonding / supporting / protecting.

[0097] As can be seen from the above, the glass sub-substrates of the glass interposer stacked substrate 1 can be processed in parallel, shortening the process flow. Furthermore, each glass sub-substrate contains a glass core plate, which reduces the warpage of the overall structure. Adjacent sub-substrates are aligned and bonded through a metal bonding layer, improving product yield. In this glass interposer stacked substrate 1, when the CTE of the top glass core plate 210 is 3 ppm / ℃, the CTE of the middle glass core plate 110 is 6 ppm / ℃, and the CTE of the bottom glass core plate 310 is 9 ppm / ℃, if... Figure 21 As shown, the overall warpage of the glass interposer stacked substrate 1 after mounting is approximately 82 μm, while the overall warpage of a traditional multilayer board (i.e., fabrication of multiple RDLs on a single glass core board) after mounting is approximately 122 μm (reference). Figure 22 In this embodiment, the warpage of the glass interposer stack substrate 1 is significantly reduced.

[0098] refer to Figure 20 According to one or more embodiments of the present invention, a semiconductor packaging structure is also provided, comprising the aforementioned glass interposer stacked substrate 1 and a semiconductor chip. The semiconductor chip may include a high-bandwidth memory (HBM) 2 and a graphics processing unit (GPU) chip 3; both the HBM 2 and the GPU chip 3 are flip-chip mounted on the top glass sub-substrate 20. However, the embodiments are not limited to this, and semiconductor chips other than SOCs or HBMs may be provided, such as logic chips: central processing units (CPUs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), or memory chips: dynamic random access memory (DRAM) chips and NAND chips.

[0099] The high-bandwidth memory (HBM) 2 is a stacked multilayer chip, with an underfill between adjacent chip layers. Additionally, an underfill is also filled between the HBM 2 / GPU chip 3 and the glass interposer stack substrate 1. The underfill layer may include epoxy resin or a mixture of two or more silicon materials. The side of the glass interposer stack substrate 1 facing away from the semiconductor chips is connected to the PCB board, enabling electrical interconnection with external circuitry.

[0100] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0101] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0102] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0103] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0104] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0105] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A glass interposer stack substrate, characterized by, The application relates to a glass interposer stack substrate, comprising: at least three glass sub-substrates arranged along a stacking direction, each of the glass sub-substrates comprising: a glass core plate having a glass through-hole filled with a conductive material to form a conductive through-hole; two redistribution structures formed on opposite sides of the glass core plate and electrically interconnected through the conductive through-hole; each of the redistribution structures has at least two redistribution layers, the redistribution layers comprising dielectric layers, metal wiring layers and a plurality of vias electrically connecting the metal wiring layers of adjacent redistribution layers; a metal bonding layer arranged on a side of each of the redistribution structures away from the glass core plate and electrically connected with the redistribution structure; along the stacking direction, the glass core plate of the glass sub-substrate on the top layer has a thermal expansion coefficient less than 5 ppm / ℃ and a thermal conductivity of 1.2 W / (m·K), and the glass sub-substrate uses silver metal wiring; the glass core plate of the glass sub-substrate on the bottom layer has a thermal expansion coefficient greater than 5 ppm / ℃, and the line width of the metal wiring layer of at least one redistribution structure of the glass sub-substrate gradually increases from the conductive through-hole to the metal bonding layer; the glass core plate of the glass sub-substrate between the top layer and the bottom layer has a dielectric constant of 4-7 and a dielectric loss of 0.007-0.009, and the glass sub-substrate uses silver metal wiring; along the stacking direction, any two adjacent glass sub-substrates are stacked and bonded through the metal bonding layer, and the bonding gap between the two adjacent glass sub-substrates is filled with a filling material to form the glass interposer stack substrate.

2. The glass interposer stack substrate of claim 1, wherein, The at least one redistribution structure of the glass sub-substrate on the bottom layer has a first dielectric layer formed of a first dielectric material and a second dielectric layer formed of a second dielectric material, wherein the first dielectric layer is an epoxy material and is arranged adjacent to the glass core plate; and the second dielectric layer is a siloxane film and is arranged on the outermost metal wiring layer of the redistribution structure.

3. The glass interposer stack substrate of claim 1, wherein, Along the stacking direction, the line width of the metal wiring layer of the redistribution structure of the glass sub-substrate on the top layer is 2 microns, and the line spacing is 2 microns; the line width of the metal wiring layer of the redistribution structure of the glass sub-substrate on the bottom layer is 5-10 microns, and the line spacing is 5-10 microns; the line width of the metal wiring layer of the redistribution structure of the glass sub-substrate between the top layer and the bottom layer is 3-5 microns, and the line spacing is 3-5 microns; and the line width of the metal wiring layer of the redistribution structure gradually increases from the glass sub-substrate on the top layer to the glass sub-substrate on the bottom layer.

4. The glass interposer stack substrate of claim 1, wherein, The glass core plate of the glass sub-substrate on the top layer is borosilicate glass, and the borosilicate glass is doped with Al2O3 heat-conducting particles.

5. The glass interposer stack substrate of claim 1, wherein, The conductive through-hole and the metal wiring layer of the glass sub-substrate on the top layer each have a seed layer and a conductive layer covering the seed layer, the seed layer comprising a titanium layer or a titanium layer and a copper layer, and the conductive layer being a silver layer.

6. The glass interposer stack substrate of claim 1, wherein, The conductive through-hole and the metal wiring layer of the glass sub-substrate between the top layer and the bottom layer each have a seed layer and a conductive layer covering the seed layer, the seed layer comprising a titanium layer or a titanium layer and a copper layer, and the conductive layer being a silver layer.

7. The glass interposer stack substrate of claim 1, wherein, The metal bonding layer is a plurality of bumps arranged at intervals on a side of the redistribution structure away from the glass core plate.

8. The glass interposer stack substrate of claim 7, wherein, The bumps on one of the redistribution structures of the glass sub-substrate are tin balls or gold balls, and the bumps on the other redistribution structure are copper pillars.

9. The glass interposer stack substrate of claim 1, wherein, The filling material is an LCM material, an LMUF material, a CUF material, a thermal conductive adhesive, a prepreg, or an NCF film.

10. A method for fabricating a glass interposer stack substrate, the method comprising: The method comprises the following steps: Providing at least three glass core plates with conductive vias; Providing a redistribution structure on each side of each glass core plate; each redistribution structure has at least two redistribution layers; the redistribution layers include dielectric layers, metal wiring layers, and a plurality of vias; the vias electrically connect the metal wiring layers of adjacent redistribution layers; Providing a metal bonding layer on a side of each redistribution structure away from the glass core plate, and cutting the wafer to form at least three glass sub-substrates; Sequentially stacking and bonding the at least three glass sub-substrates in a stacking direction using the metal bonding layer, and filling a filling material in the bonding gap between adjacent glass sub-substrates to form the glass interposer stack substrate; In the stacking direction, the glass core plate of the top glass sub-substrate has a coefficient of thermal expansion less than 5 ppm / °C and a thermal conductivity of 1.2 W / (m·K), and the glass sub-substrate uses silver metal wiring; the glass core plate of the bottom glass sub-substrate has a coefficient of thermal expansion greater than 5 ppm / °C, and the metal wiring layer of at least one redistribution structure of the glass sub-substrate gradually widens from the conductive via to the metal bonding layer; the glass core plate of the glass sub-substrate between the top and bottom layers has a dielectric constant of 4-7 and a dielectric loss of 0.007-0.009, and the glass sub-substrate uses silver metal wiring.

11. The method of making a glass interposer stack substrate of claim 10, wherein, The filling material is an LCM material, an LMUF material, a CUF material, a thermal conductive adhesive, a prepreg, or an NCF film.

12. The method of making a glass interposer stack substrate of claim 10, wherein, The metal bonding layer is provided by providing a plurality of bumps arranged at intervals on a side of the redistribution structure away from the glass core plate and electrically connected to the redistribution structure.

13. A semiconductor package structure, comprising: The glass interposer stack substrate prepared by the method of any one of claims 1-9, or the method of any one of claims 10-12; A semiconductor chip flip-chip mounted on the glass interposer stack substrate and electrically connected to the metal bonding layer of the top glass sub-substrate; and A bottom filling adhesive filled between the semiconductor chip and the top glass sub-substrate. The semiconductor chip includes a high-bandwidth memory (HBM) and a graphics processing unit (GPU) chip, both of which are flip-chip mounted on the top glass sub-substrate; and the side of the glass interposer stack substrate away from the semiconductor chip is connected to a PCB board to achieve electrical interconnection with external circuits.

14. The semiconductor package structure of claim 13, wherein, The semiconductor chip includes a high-bandwidth memory (HBM) and a graphics processing unit (GPU) chip, both of which are flip-chip mounted on the top glass sub-substrate; and the side of the glass interposer stack substrate away from the semiconductor chip is connected to a PCB board to achieve electrical interconnection with external circuits.

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