Solid film electrolyte chip structure, preparation method, test method and test system

Abstract

The invention relates to the technical field, in particular to a solid film electrolyte chip structure, a preparation method, a test method and a test system. According to the invention, a substrate is provided, the substrate comprises a test area formed by a plurality of cell areas arranged in an array, and the edge of the test area comprises front conductive contacts and back conductive contacts with the same number as the cell areas; a test unit formed by stacking a bottom electrode, a solid electrolyte film layer and a top electrode in sequence is formed on each cell area; a conductive hole is formed in the position, corresponding to each bottom electrode, of the face, away from the test unit, of the substrate, the bottom electrodes are connected to the back face conductive contacts of the test area through the conductive holes and wires, and the top electrodes are directly connected to the corresponding front face conductive contacts of the substrate through wires. According to the technical scheme, double-face wiring of the substrate is achieved, and the problems of lead crowding, short circuit and signal crosstalk in a high-density array in existing single-face wiring are solved.

Description

Technical Field

[0001] This invention relates to the field of high-throughput technology, and in particular to a solid-state thin-film electrolyte chip structure, preparation method, testing method, and testing system. Background Technology

[0002] In the development of solid-state batteries, obtaining solid electrolyte materials with high ionic conductivity, excellent chemical stability, and good mechanical properties requires the preparation and testing of a large number of samples with different compositions, ratios, and synthesis processes. Traditional testing methods can only characterize one sample at a time, resulting in low efficiency, long development cycles, and high costs. Therefore, developing high-throughput screening technologies capable of testing multiple micro-electrolyte units in parallel is crucial for accelerating the discovery and optimization of new materials.

[0003] Current high-throughput testing typically involves integrating multiple electrolyte samples onto a single substrate and constructing a corresponding test array. However, existing integration schemes usually employ a single-sided wiring method. When dealing with hundreds of electrolyte samples, this single-sided wiring structure leads to an increase in the number of leads, resulting in complex and congested wiring paths. This makes the leads prone to mutual interference, affecting the accuracy and reliability of the test. Summary of the Invention

[0004] To address the aforementioned problems, this invention provides a solid-state thin-film electrolyte chip structure, its fabrication method, testing method, and testing system.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a solid-state thin-film electrolyte chip structure, comprising the following steps: providing a substrate, the substrate comprising a test area formed by a plurality of cell regions arranged in an array, the edge of the test area comprising a front conductive contact and a back conductive contact equal in number to the cell regions; on each cell region, a bottom electrode, a solid electrolyte thin film layer and a top electrode are sequentially formed to obtain a test unit formed by the bottom electrode, the solid electrolyte thin film layer and the top electrode being stacked sequentially; and forming a conductive hole on the side of the substrate opposite to the test unit at a position corresponding to each bottom electrode, connecting the bottom electrode to the back conductive contact of the test area through the conductive hole and a wire, and directly connecting the top electrode to the corresponding front conductive contact of the substrate through a wire.

[0006] Preferably, a bottom electrode, a solid electrolyte film layer, and a top electrode are sequentially formed on each cell region to obtain a test unit formed by the sequential stacking of the bottom electrode, the solid electrolyte film layer, and the top electrode. Specifically, this includes the following steps: depositing a Pt layer as a bottom electrode on each cell region using DC sputtering or electron beam evaporation deposition; depositing a solid electrolyte film layer on the bottom electrode using any one of radio frequency sputtering, pulsed laser deposition, and spin coating-annealing techniques; and depositing or placing a Pt layer or a Li layer on the solid electrolyte film layer as a top electrode, so that the bottom electrode, the solid electrolyte film layer, and the top electrode on each cell region are sequentially stacked to form a test unit.

[0007] Preferably, depositing or placing a Pt layer or a Li layer as a top electrode on the solid electrolyte film layer specifically includes the following steps: depositing a Pt layer or a Li layer as a top electrode on the solid electrolyte film layer by DC sputtering technology or electron beam evaporation deposition technology; or transferring a pre-fabricated Pt layer or a pre-fabricated Li layer onto the solid electrolyte film layer to form a top electrode by metal sheet transfer technology.

[0008] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a solid-state thin-film electrolyte chip structure, which is prepared by any of the above-described methods for preparing solid-state thin-film electrolyte chip structures; the solid-state thin-film electrolyte chip structure includes a substrate and test units arranged in an array on the substrate, each test unit consisting of a bottom electrode, a solid-state electrolyte thin film layer, and a top electrode stacked sequentially; a conductive hole is provided on the side of the substrate facing away from the test unit at a position corresponding to each bottom electrode, the bottom electrode being connected to a back conductive contact of the test area through the conductive hole, and the top electrode being directly connected to a corresponding front conductive contact of the substrate.

[0009] Preferably, the proportions of each material in the solid electrolyte thin film layer of the plurality of test units are the same or different.

[0010] Preferably, the substrate further includes a pad area surrounding the test area, the pad area including a front pad and a back pad with the same number as the test units, the front conductive contacts being wired in a one-to-one correspondence with the front pads, and the back conductive contacts being wired in a one-to-one correspondence with the back pads.

[0011] Preferably, all conductors on the substrate between the test area and the pad area are arranged radially with the test area as the center.

[0012] Preferably, a Ti layer and a Cu layer are sequentially disposed on the wall of the conductive hole, and the two ends of the Cu layer are respectively connected to the bottom electrode of the test unit and the wire on the side of the substrate opposite to the test unit.

[0013] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a testing method for a solid-state thin-film electrolyte chip structure, applied to any of the solid-state thin-film electrolyte chip structures described above, comprising the following steps: providing a test fixture; the test fixture includes multiple sets of probe groups, each set of probes including a front probe and a back probe; loading the solid-state thin-film electrolyte chip structure into the test fixture; the solid-state thin-film electrolyte chip structure includes a substrate and test units disposed on each unit area of ​​the substrate, each test unit consisting of a bottom electrode, a solid-state electrolyte thin film layer, and a top electrode stacked sequentially; a conductive hole is provided on the side of the substrate facing away from the test unit at a position corresponding to each bottom electrode, the bottom electrode being connected to a back conductive contact of the test area through the conductive hole, and the top electrode being directly connected to the corresponding front conductive contact of the substrate; through the front probe group of each probe group... A front probe contacts the front conductive contact corresponding to the top electrode in one of the test units, and a back probe in the probe group contacts the bottom electrode, leading out the back conductive contact from a conductive hole on the side of the substrate opposite to the test unit. A test fixture is connected to a detection device, which detects the solid electrolyte film layer in each test unit of the solid-state thin-film electrolyte chip structure to obtain the ionic conductivity and / or electrochemical window corresponding to the solid electrolyte film layer in each test unit. The current signal output by the detection device sequentially passes through the front probe, the top electrode, the solid electrolyte film layer, the bottom electrode, the conductive hole, and the back probe, finally returning to the detection device. The solid electrolyte film layers in all test units of the solid-state thin-film electrolyte chip structure are screened based on the ionic conductivity and / or electrochemical window.

[0014] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a testing system for a solid-state thin-film electrolyte chip structure, applied to the testing method for the solid-state thin-film electrolyte chip structure as described above, comprising: a solid-state thin-film electrolyte chip structure, the solid-state thin-film electrolyte chip structure including a substrate and test units disposed on each unit region of the substrate, each test unit being composed of a bottom electrode, a solid electrolyte thin film layer and a top electrode stacked sequentially; a conductive hole is disposed on the side of the substrate opposite to the test unit at a position corresponding to each bottom electrode, the bottom electrode being connected to a back conductive contact of the test area through the conductive hole, and the top electrode being directly connected to a corresponding front conductive contact of the substrate; a test fixture, the test fixture including multiple sets of probe groups, each set of probes including a front probe and a back probe, the front probe in each set of probes contacting a... The top electrode in each of the test units is connected to the front conductive contact, and the back probe contacts the bottom electrode, which is led out from the conductive hole on the side of the substrate opposite to the test unit and connected to the back conductive contact; a detection device, connected to the test fixture, is used to detect the solid electrolyte thin film layer in each test unit of the solid thin film electrolyte chip structure to obtain the ionic conductivity and / or electrochemical window corresponding to the solid electrolyte thin film layer in each test unit; wherein, the current signal output by the detection device passes sequentially through the front probe, the top electrode, the solid electrolyte thin film layer, the bottom electrode, the conductive hole, and the back probe, and finally returns to the detection device; and a screening device is used to screen the solid electrolyte thin film layers in all test units of the solid thin film electrolyte chip structure based on the ionic conductivity and / or electrochemical window.

[0015] Compared with the prior art, the solid-state thin-film electrolyte chip structure, preparation method, testing method, and testing system provided by the present invention have the following beneficial effects: 1. This invention provides a method for fabricating a solid-state thin-film electrolyte chip structure. By designing a substrate containing an array of test areas, and sequentially stacking a bottom electrode, a solid-state electrolyte thin film layer, and a top electrode on each cell to form an independent test unit, high-density integration of test units on the chip is achieved. Simultaneously, conductive vias are provided on the back of the substrate to lead the bottom electrode to the back conductive contact, while the top electrode is directly connected to the front conductive contact, forming a double-sided lead structure on the substrate. This achieves double-sided wiring on the substrate. This double-sided wiring design separates the unavoidable cross-leads in traditional single-sided wiring to two different planes, thereby solving the problems of lead congestion, short circuits, and signal crosstalk in high-density arrays of existing single-sided wiring. It provides an independent and clear electrical test path for each test unit, improving the integration density, test reliability, and manufacturability of test units in the solid-state thin-film electrolyte chip structure. This is more conducive to subsequent high-throughput and parallel electrochemical testing of multiple test units in the solid-state thin-film electrolyte chip structure.

[0016] 2. This invention provides differentiated fabrication processes for different functional layers in a solid-state thin-film electrolyte chip structure. For the bottom electrode, DC sputtering or electron beam evaporation deposition is used. For the solid electrolyte thin film layer, three options are provided: radio frequency sputtering, pulsed laser deposition, and spin-coating-annealing. For the top electrode, both deposition and placement methods are supported. This layered design provides optimal fabrication paths for the material properties of each functional layer, ensuring process standardization and repeatability while significantly improving the flexibility and adaptability of the fabrication method. It can meet the fabrication needs of various solid-state electrolyte materials, from oxides and sulfides to polymers.

[0017] 3. In this embodiment of the invention, the top electrode is formed on the solid electrolyte thin film layer by DC sputtering, electron beam evaporation deposition or metal sheet transfer technology. The metal sheet transfer technology avoids the potential damage to the temperature-sensitive solid electrolyte thin film layer and its interface caused by thermal evaporation or plasma processes, and can form a pristine and clean electrode / electrolyte interface, thereby improving the accuracy and reliability of test data for fragile material systems.

[0018] 4. This invention provides a solid-state thin-film electrolyte chip structure, obtained using the aforementioned method for fabricating solid-state thin-film electrolyte chip structures. In this solid-state thin-film electrolyte chip structure, the bottom electrode of each test unit is connected to a back conductive contact through a conductive via, and the top electrode is directly connected to a front conductive contact, forming a double-sided lead-out electrical architecture. This structure distributes the leads of the high-density test array to both the front and back planes of the substrate, resulting in ample wiring space, effectively reducing the lead density in a single plane, and completely avoiding lead crossing and the resulting short-circuit risk. This provides a reliable test environment for achieving high-reliability, crosstalk-free parallel electrical testing of hundreds of test units.

[0019] 5. In this embodiment of the invention, the solid electrolyte thin film layers in multiple test units have the same or different material proportions: When the solid electrolyte thin film layers in multiple test units use the same material and the same proportion, the stability verification of the performance of the same solid electrolyte can be achieved under completely consistent preparation and testing conditions, so as to effectively evaluate the repeatability of the material preparation and the reliability of the test results corresponding to the current solid electrolyte thin film layer; while when multiple test units use different material proportions, it is convenient to screen the performance of different solid electrolyte components in parallel on a solid thin film electrolyte chip structure.

[0020] 6. In this embodiment of the invention, a pad area is provided on the substrate surrounding the test area. This pad area includes front pads and back pads, the same number as the test units, and the front and back conductive contacts are connected by corresponding wiring. The pad area provides a contact interface for the test fixture to be tested later, facilitating the alignment and electrical connection between the solid-state thin-film electrolyte chip structure and the test fixture, thereby ensuring the consistency and stability of subsequent test connections.

[0021] 7. In this embodiment of the invention, a pad area surrounding the test area is set on the substrate, including front pads and back pads with the same number as the test units. The front and back conductive contacts are connected by one-to-one wiring, and the pad area is combined with radial wiring so that the conductive lines of each test unit maintain an independent path. This effectively increases the physical spacing between adjacent conductive lines, thereby preventing signal crosstalk, reducing distributed capacitance and electromagnetic interference between lines, and providing a highly independent test environment for each test unit. This ensures the accuracy and reliability of electrochemical measurement results and is suitable for high-precision, high-throughput screening scenarios.

[0022] 8. In this embodiment of the invention, a Ti layer and a Cu layer are sequentially disposed on the wall of the conductive hole. The Ti layer serves as an adhesion layer to enhance bonding strength, while the Cu layer serves as a conductive layer to ensure excellent conductivity. This double-layer metallization structure ensures the stability and electrical reliability of the electrical connection between the vertical interconnect bottom electrode and the conductive lines on the back of the substrate. It ensures the achievement of a stable double-sided interconnect and guarantees smooth current transmission, thus improving the long-term stability and yield of the chip.

[0023] 9. This invention also provides a testing method for solid-state thin-film electrolyte chip structures. By providing a test fixture with multiple sets of front and back probes, it precisely connects to the double-sided solder joint structure of the solid-state thin-film electrolyte chip structure, constructing an independent and isolated test circuit for each test unit. Furthermore, this testing method clearly defines the complete path of the current signal during testing, sequentially flowing through the front probe, top electrode, solid-state electrolyte thin-film layer, bottom electrode, conductive via, and back probe, ensuring that the measurement target accurately points to the solid-state electrolyte thin-film layer itself, effectively eliminating parallel interference that is difficult to avoid in traditional single-sided wiring. In addition, this testing method integrates high-throughput fabrication methods, facilitating the fabrication and screening of key performance parameters for dozens to hundreds of samples.

[0024] 10. This invention provides a testing system for solid-state thin-film electrolyte chip structures, integrating a dedicated double-sided wiring solid-state thin-film electrolyte chip structure, a test fixture including multiple sets of probes, a detection device, and a screening device. The solid-state thin-film electrolyte chip structure solves the lead crosstalk problem, the test fixture enables rapid and reliable connection, the detection device acquires accurate ionic conductivity and electrochemical window data, and the screening device performs data evaluation, thus forming a complete testing system. This system optimizes the entire process from sample preparation to performance screening, providing a complete technical platform for high-throughput, high-reliability screening of solid-state electrolyte materials. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a flowchart of the steps in the preparation method of the solid-state thin-film electrolyte chip structure provided in the first embodiment of the present invention.

[0027] Figure 2 This is a flowchart illustrating the specific steps of step S2 in the method for preparing a solid-state thin-film electrolyte chip structure according to the first embodiment of the present invention.

[0028] Figure 3 This is a flowchart illustrating the specific steps of step S3 in the first optional implementation of the method for fabricating a solid-state thin-film electrolyte chip structure provided in the first embodiment of the present invention.

[0029] Figure 4 This is a flowchart illustrating the specific steps of step S3 in the method for fabricating a solid-state thin-film electrolyte chip structure provided in the first embodiment of the present invention.

[0030] Figure 5 This is a top front view of the solid-state thin-film electrolyte chip structure provided in the second embodiment of the present invention.

[0031] Figure 6 This is a top view of the back of the solid-state thin-film electrolyte chip structure provided in the second embodiment of the present invention.

[0032] Figure 7 This is a wiring diagram of a single test unit of the solid-state thin-film electrolyte chip structure provided in the second embodiment of the present invention.

[0033] Figure 8 This is a top view of the pad area of ​​the solid-state thin-film electrolyte chip structure provided in the second embodiment of the present invention.

[0034] Figure 9 This is a top view of the back of the pad area of ​​the solid-state thin-film electrolyte chip structure provided in the second embodiment of the present invention.

[0035] Figure 10 This is a schematic diagram of the conductive holes in the solid-state thin-film electrolyte chip structure provided in the second embodiment of the present invention.

[0036] Figure 11 This is a schematic diagram of a single test unit of the solid-state thin-film electrolyte chip structure provided in the third embodiment of the present invention.

[0037] Figure 12 This is a flowchart of the testing method for a solid-state thin-film electrolyte chip structure provided in the fourth embodiment of the present invention.

[0038] Figure 13 This is a block diagram of a test system for a solid-state thin-film electrolyte chip structure provided in the fifth embodiment of the present invention.

[0039] Explanation of reference numerals in the attached diagram: 1. Solid-state thin-film electrolyte chip structure; 2. Test fixture; 3. Detection device; 4. Screening device; 5. Test system for solid-state thin-film electrolyte chip structure; 11. Substrate; 12. Test unit; 21. Probe group; 101. First substrate; 102. Second substrate; 111. Test area; 112. Pad area; 113. Conductive via; 114. Front conductive contact; 115. Back conductive contact; 116. Wire; 121. Bottom electrode; 122. Solid electrolyte film layer; 123. Top electrode; 211. Front probe; 212. Back probe; 1121, Front pad; 1122, Back pad; 1130, Hole wall; 1131, Ti layer; 1132, Cu layer. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0041] In the embodiments provided by this invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0042] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also recognize that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to the invention.

[0043] In various embodiments of the present invention, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0044] The flowcharts and block diagrams in the accompanying drawings illustrate methods and possible architectures, functions, and operations according to various embodiments of this application. In this regard, each block in the flowchart or block diagram may represent part of a step. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved.

[0045] Please see Figure 1 The first embodiment of the present invention provides a method for fabricating a solid-state thin-film electrolyte chip structure, comprising the following steps: Step S1: Provide a substrate, the substrate including a test area formed by a plurality of cell regions arranged in an array, the edge of the test area including front conductive contacts and back conductive contacts in the same number as the cell regions; Step S2: On each cell region, a bottom electrode, a solid electrolyte film layer, and a top electrode are sequentially formed to obtain a test unit formed by the sequential stacking of the bottom electrode, the solid electrolyte film layer, and the top electrode; and Step S3: Form conductive holes at positions corresponding to each bottom electrode on the side of the substrate opposite to the test unit, connect the bottom electrode to the back conductive contact of the test area through the conductive holes and wires, and connect the top electrode directly to the front conductive contact of the substrate through wires.

[0046] Specifically, step S1 provides a substrate with multiple cell regions arranged in an array to form a test area, which establishes a basic platform for subsequent high-throughput testing. The substrate material selection needs to consider thermal stability, insulation, and mechanical strength. In this embodiment, the substrate can be a single-crystal silicon wafer with a thickness ranging from 200µm to 1000µm, 300µm to 900µm, or 500µm to 750µm. A SiO2 layer with a thickness of approximately 300nm to 700nm, 400nm to 600nm, or 500nm is formed on the surface of the single-crystal silicon wafer through thermal oxidation as an insulating layer to enhance wiring stability. The array arrangement of the multiple cell regions in the test area determines the array arrangement of the subsequent test units. Therefore, before actually fabricating the test units, the spacing between each cell region needs to be reasonably set to ensure that the spacing between the subsequently fabricated test units is not too large or too small, thus affecting the arrangement of conductive lines. Furthermore, one front conductive contact on the substrate is used to connect the top electrode of a test unit; and one back conductive contact is used to connect the bottom electrode of a test unit. That is, corresponding conductive contacts are provided on the substrate for the bottom and top electrodes of a test unit, respectively. Since the front and back conductive contacts are located on different surfaces of the substrate, the top and bottom electrodes of each test unit are led to the front and back conductive contacts on different surfaces of the substrate, achieving different lead paths and completely isolating the two lead paths on two different physical planes, thus providing an interface guarantee for subsequent double-sided wiring.

[0047] Specifically, in step S2, during the test unit construction process, the bottom electrode, solid electrolyte thin film layer, and top electrode sequentially formed on each cell region constitute a complete micro solid-state battery structure. Furthermore, the arrangement of multiple test units is the same as the arrangement of the cell regions, all exhibiting an array arrangement. This results in high integration and good repeatability, making it suitable for the simultaneous fabrication and testing of multiple solid electrolyte materials with different compositions. The bottom electrode, as the current collection layer, needs to possess good conductivity and interface stability. Different deposition processes can be selected for the solid electrolyte thin film layer depending on the material properties. The top electrode can be an inert electrode or an active electrode, depending on the testing requirements. This stacked structure ensures the structural consistency of each test unit, providing a reliable basis for subsequent performance comparisons of the solid electrolyte thin film layer. In addition, the array structure design of the chip gives it high integration and good repeatability, making it suitable for the simultaneous fabrication and testing of multiple solid electrolyte materials with different compositions.

[0048] More specifically, corresponding conductive contacts are provided on the substrate for the bottom and top electrodes of each test unit. The front and back conductive contacts are located on different surfaces of the substrate. Therefore, the top and bottom electrodes of each test unit are led to the front and back conductive contacts on different surfaces of the substrate, achieving different lead paths. Specifically, in step S3, conductive vias are fabricated on the back of the substrate, so that the top electrode of each test unit on the substrate is connected to a front conductive contact, and the bottom electrode is connected to a back conductive contact on a different surface from the front conductive contact through the conductive vias. This solves the unavoidable lead crossing problem in traditional single-sided wiring.

[0049] It should be noted that the order of steps S2 and S3 can be interchanged. Test units can be fabricated on the substrate in step S2, and then conductive holes can be fabricated on the substrate in step S3; alternatively, conductive holes can be fabricated on the substrate in step S3 first, and then test units can be fabricated on the substrate in step S2. The appropriate fabrication order can be selected according to the actual situation. This embodiment does not limit this, as long as each conductive hole fabricated in the end corresponds to the bottom electrode of the corresponding test unit and is electrically conductive.

[0050] Understandably, the formation of conductive vias requires precise etching and metallization processes to ensure good electrical connectivity. The wiring on both the front and back sides employs a reasonable line width and spacing design, ensuring signal transmission quality while avoiding mutual interference between lines.

[0051] Understandably, in this embodiment of the double-sided wiring scheme, with conductive lines led out from both the front and back sides of the substrate, the front side of the substrate can be defined as the side where test units are located, and the back side of the substrate is the side opposite to the front side. This achieves complete electrical independence for each test unit in the high-density array on the substrate. Compared to traditional single-sided wiring schemes, where the lead density increases dramatically when dealing with dozens or even hundreds of test units, leading to line crossing, signal crosstalk, and decreased test accuracy, this embodiment effectively reduces wiring density and establishes a clear test loop for each test unit by separating the top and bottom electrode leads in each test unit to two different planes. In addition, double-sided wiring can improve test reliability and also enhance the integration density and manufacturability of multiple test units on the substrate.

[0052] Please see Figure 2 Furthermore, step S2 specifically includes the following steps: Step S21: Deposit a Pt layer as a bottom electrode on each of the cell regions using DC sputtering or electron beam evaporation deposition techniques; Step S22: Deposit a solid electrolyte thin film layer on the bottom electrode using any one of the following techniques: radio frequency sputtering, pulsed laser deposition, and spin coating-annealing; and Step S23: Deposit or place a Pt layer or Li layer as a top electrode on the solid electrolyte film layer, so that the bottom electrode, the solid electrolyte film layer and the top electrode on each cell area are stacked in sequence to form a test cell.

[0053] Specifically, during the formation of the bottom electrode, solid electrolyte thin film layer, and top electrode of the test unit, differentiated thin film deposition techniques are employed based on the material properties and process requirements of different functional layers. In the bottom electrode formation process of step S21, either DC sputtering or electron beam evaporation deposition can be used to deposit a Pt layer on each cell region. Both DC sputtering and electron beam evaporation deposition techniques can produce dense, uniform, and highly conductive Pt thin films.

[0054] DC sputtering technology involves filling a vacuum chamber with argon gas, applying a DC voltage to generate plasma, and bombarding a Pt target with argon ions to sputter and deposit Pt atoms onto the substrate surface to form a dense Pt thin film, also known as a Pt layer. The operating parameters of DC sputtering technology can be adjusted according to the actual sputtering conditions; this embodiment does not impose any limitations on this. DC sputtering technology features fast film formation rate and strong adhesion, making it particularly suitable for large-scale preparation.

[0055] Electron beam evaporation deposition technology operates in a high vacuum environment (gas pressure ≤ 10). -By bombarding the Pt source material with a high-energy electron beam emitted from an electron gun (³Pa), the Pt source material is locally melted and evaporated, then condensed on the substrate surface to form a film, resulting in a Pt thin film with higher purity. Both techniques can produce dense, uniform, and highly conductive bottom electrodes, providing a reliable current collection layer for subsequent electrochemical testing. In this embodiment, either DC sputtering or electron beam evaporation deposition can be used to deposit the Pt layer as the bottom electrode, depending on the actual situation; this embodiment does not impose any restrictions on this. Understandably, Pt is chosen as the bottom electrode material because of its excellent chemical stability, high conductivity, and good interfacial compatibility with most solid electrolyte materials, which provides a reliable current collection layer for subsequent electrochemical testing. The thickness of the Pt layer prepared by DC sputtering or electron beam evaporation deposition can be 100nm-300nm, 150nm-250nm, or 200nm.

[0056] More specifically, in step S22, the radio frequency sputtering technology is applicable to oxide electrolyte systems. Specifically, multiple targets for preparing solid electrolyte thin films are installed on a radio frequency sputtering device, a reaction gas is introduced under a preset vacuum, radio frequency power is applied to generate glow discharge, and multiple targets are deposited onto a Pt layer by controlling parameters such as sputtering power, working gas pressure and substrate temperature to obtain a dense solid electrolyte thin film.

[0057] Pulsed laser deposition technology is suitable for electrolytes with complex compositions. Specifically, a target material with a precise composition ratio is placed in a vacuum chamber, and a high-energy laser pulse is used to bombard the target material in a certain atmosphere to deposit a solid electrolyte thin film layer with a stoichiometric ratio on a Pt layer on a heated substrate.

[0058] Spin-coating-annealing technology is suitable for solution-based electrolyte systems. Specifically, the required precursor material for the solid electrolyte film layer to be prepared is dissolved in a stoichiometric ratio to prepare a solution. A uniform liquid film is formed on the Pt layer on the substrate through a step-by-step spin-coating process. After preliminary drying and subsequent annealing, a solid electrolyte film layer is formed.

[0059] In this embodiment, the corresponding preparation technology and target material can be flexibly selected according to the required material properties of the solid electrolyte thin film layer to be prepared, so as to ensure that a high-quality solid electrolyte thin film layer is obtained. The final thickness of the prepared solid electrolyte thin film layer is in the range of 50nm-1200nm, 100nm-1000nm, or 200nm-800nm. For example, Li7La3Zr2O can be prepared. 12 When preparing LiPON, a target containing Li, La, and Zr is required; when preparing Li3PS4 and other solid electrolyte thin films, a target containing Li, P, and S is required.

[0060] More specifically, after the solid electrolyte thin film layer is prepared, a Pt layer or Li layer can be deposited or placed on the solid electrolyte thin film layer as a top electrode in step S23, so that the bottom electrode, solid electrolyte thin film layer and top electrode in each cell region are stacked sequentially to form a test cell. The thickness of the top electrode can be 50nm-800nm, 100nm-500nm or 200nm-300nm.

[0061] It should be noted that when using a Pt layer as the top electrode, Pt, as an inert electrode, can provide a stable electrochemical interface, which can be used to evaluate the ionic conductivity and intrinsic electrochemical stability window of the solid electrolyte material itself, avoiding the interference of electrode side reactions on the test results. Using Li as the active electrode can be used to simulate the working state of a real solid battery. In this embodiment, the corresponding material can be selected to form the top electrode according to the specific detection conditions, which is more conducive to meeting different screening requirements of users.

[0062] Understandably, by designing differentiated fabrication processes for different functional layers in the solid-state thin-film electrolyte chip structure, DC sputtering or electron beam evaporation deposition techniques are used for the bottom electrode, while three options are provided for the solid electrolyte thin film layer: radio frequency sputtering, pulsed laser deposition, and spin coating-annealing. For the top electrode, two implementation methods are supported: deposition or placement. This layered design process system provides the optimal fabrication path for the material properties of each functional layer, ensuring both process standardization and repeatability, while significantly improving the flexibility and adaptability of the fabrication method, and meeting the fabrication needs of various solid-state electrolyte materials, from oxides and sulfides to polymers.

[0063] In one optional implementation, step S23 specifically includes the following steps: Step S231: Deposit a Pt layer or a Li layer as a top electrode on the solid electrolyte thin film layer using DC sputtering or electron beam evaporation deposition technology.

[0064] Understandably, the top electrode can be prepared using the same method as the bottom electrode. Specifically, it can be prepared by directly depositing a Pt or Li layer on the solid electrolyte film layer using DC sputtering or electron beam evaporation deposition. Both of these deposition techniques can produce a top electrode with good interfacial contact with the solid electrolyte film layer, providing a reliable electrode interface for electrochemical testing.

[0065] In one optional implementation, step S23 specifically includes the following steps: Step S232: Transfer the pre-fabricated Pt layer or pre-fabricated Li layer onto the solid electrolyte film layer using metal sheet transfer technology to form the top electrode.

[0066] Understandably, metal transfer technology involves precisely mechanically bonding a pre-fabricated Pt or Li layer to a solid electrolyte film layer in a protective atmosphere to achieve close contact and form a stable electrode / electrolyte interface. Metal transfer technology avoids thermal damage and interfacial reactions during deposition, preserving the original properties of the electrode material, and is particularly suitable for temperature-sensitive electrolyte material systems.

[0067] It should be noted that either deposition or transfer methods can be chosen to fabricate the top electrode based on different testing objectives and material properties. Deposition is suitable for large-scale, standardized electrode fabrication, allowing for precise control of electrode patterns and dimensions through a mask. Transfer methods offer unique advantages in protecting sensitive materials and interfaces, enabling the formation of an electrode / electrolyte interface that most closely resembles the actual application state. These two implementation methods provide flexible options for top electrode fabrication, allowing users to choose the most suitable method based on specific material properties, testing objectives, and process conditions.

[0068] Understandably, by providing both deposition and transfer techniques for top electrode fabrication, both the feasibility and standardization of the process are ensured, as well as the accuracy and reliability of the test results. Furthermore, the choice of different fabrication methods allows the final top electrode to be adapted to different needs. The thickness of the final top electrode can also be adjusted within an appropriate range according to testing requirements to meet various electrochemical testing requirements.

[0069] Please see Figure 3 In the first optional implementation of step S3, the specific process of preparing the conductive hole in step S3 can be as follows: Step S31: Conductive holes are formed in the substrate and insulating layer using a dry etching process; Precise control of etching parameters ensures the verticality of the conductive hole walls and the uniformity of the hole diameter, laying the foundation for subsequent metallization processes. Step S32: After completing the preparation of the conductive hole, metallization treatment is performed inside the conductive hole, and a double layer of metal, consisting of a titanium layer and a copper layer, is deposited sequentially on the hole wall as a conductive medium. The titanium layer acts as an adhesion layer, enhancing the bond between the metal and the insulating hole walls; the copper layer, as the primary conductive layer, provides an excellent current conduction path. This double-layer metal structure ensures both the reliability of the mechanical connections and the stability of the electrical performance. Step S33: After depositing the titanium and copper layers, perform back copper wiring on the substrate.

[0070] Understandably, the wiring pattern is defined using photolithography, and then the copper traces on the back side are formed using wet etching or electroplating. Wet etching is suitable for simpler wiring patterns, while electroplating is suitable for higher precision circuit control. In this embodiment, the choice can be made according to the actual wiring situation. During the wiring process, the line width and spacing can be controlled to ensure electrical isolation between each signal path.

[0071] Understandably, steps S31-S33 ensure that all back-side wiring is accurately connected to the corresponding back-side solder joints of the substrate, forming a complete bottom electrode lead-out path. This conductive via formation process, through a dry etching-metallization-patterned wiring technique, achieves reliable transmission of bottom electrode signals from the front to the back of the solid-state thin-film electrolyte chip structure. Together with the top electrode leads on the front side, it forms a complete double-sided interconnect architecture, providing crucial process assurance for independent testing of high-density test cell arrays.

[0072] Please see Figure 4 In a second optional implementation of step S3, the specific process of preparing the conductive hole in step S3 can be as follows: Step S31': Two substrates are used. Test units and corresponding bottom electrodes are set on the first substrate. Conductive holes are formed by dry etching process. Wiring is performed on the back side of the first substrate so that the wiring extends from the conductive holes to the conductive contacts on the back side of the substrate. Step S32': Etch a reserved space for wiring corresponding to the wiring lines on the back side of the first substrate on one side of the second substrate; and Step S33': Stack the first substrate and the second substrate together so that the second substrate covers the back wiring lines of the first substrate, while the conductive contacts on the first substrate are exposed from the edge of the joint between the first substrate and the second substrate.

[0073] Understandably, this embodiment adopts a dual-substrate stacked structure. By combining the back wiring of the first substrate with the protective coverage of the second substrate, the mechanical strength and wiring protection capability of the solid-state thin-film electrolyte chip structure are enhanced, effectively preventing damage to the circuit from the external environment. It is suitable for continuous testing and high-power application scenarios.

[0074] It should be noted that the single-substrate solution has a compact structure, mature technology, and lower cost, making it suitable for conventional testing scenarios and applications sensitive to chip thickness and cost. While the dual-substrate solution has higher process complexity, it excels in reliability, maintainability, and heat dissipation performance, making it suitable for long-term continuous testing, high-density wiring, and scenarios with high stability requirements. Users can choose the appropriate solution based on specific testing needs, environmental conditions, and resource constraints; this embodiment does not impose any restrictions in this regard.

[0075] Please see Figures 5-7The second embodiment of the present invention provides a solid-state thin-film electrolyte chip structure 1, which is prepared by any one of the preparation methods of the solid-state thin-film electrolyte chip structure 1 in the first embodiment. The solid-state thin-film electrolyte chip structure 1 includes a substrate 11 and test units 12 disposed on each unit region of the substrate 11. Each test unit 12 is composed of a bottom electrode 121, a solid electrolyte thin film layer 122 and a top electrode 123 stacked in sequence. A conductive hole 113 is provided on the side of the substrate 11 facing away from the test unit 12 at a position corresponding to each bottom electrode 121. The bottom electrode 121 is connected to the back conductive contact 115 of the test area 111 through the conductive hole 113, and the top electrode 123 is directly connected to the front conductive contact 114 of the substrate 11.

[0076] Specifically, the substrate 11 can be a single-crystal silicon wafer with a thickness ranging from 200µm to 1000µm, 300µm to 900µm, or 500µm to 750µm. A SiO2 layer with a thickness of approximately 300nm to 700nm, 400nm to 600nm, or 500nm is formed on the surface of the single-crystal silicon wafer through thermal oxidation. This SiO2 layer can serve as an insulating layer to enhance wiring stability. The size of the test area 111 can range from 3cm×3cm to 10cm×10cm, or from 4cm×4cm to 8cm×8cm, or from 4cm×4cm to 6cm×6cm, preferably 5.4cm×5.4cm.

[0077] Specifically, the shape of each test unit 12 is not limited and can be square, circular, rectangular, triangular, etc., and can be selected according to the actual situation. In this embodiment, it is preferred that the test unit 12 is square, with a side length of 1mm-8mm, 2mm-3mm, or 2mm-5mm. More preferably, the side length of each test unit 12 is 3cm. Furthermore, the unit spacing between any two adjacent test units 12 is greater than or equal to 2mm, which provides sufficient space for wiring on the substrate 11, ensuring the width and spacing of the traces, and further preventing electrical short circuits or signal coupling caused by excessively close traces. At the same time, this unit spacing also provides process margin during the fabrication process, reducing manufacturing difficulty, improving chip yield, and enhancing the performance independence of each test unit 12.

[0078] Specifically, multiple test units 12 can be arranged in a square array. For example, if there are 100 test units 12, they can be arranged in a 10-row × 10-column array. Each test unit 12 consists of a bottom electrode 121, a solid electrolyte film layer 122, and a top electrode 123 stacked sequentially. That is, the bottom electrode 121 is in direct contact with the substrate 11, and the solid electrolyte film layer 122 is sandwiched between the bottom electrode 121 and the top electrode 123, so that each test unit 12 can be used as an independent micro solid-state battery. The bottom electrode 121 of each test unit 12 is vertically connected to the back side of the substrate 11 through a conductive hole 113 with a diameter in the range of 10µm-100µm, 20µm-80µm, or 30µm-50µm. Specifically, the side of the substrate 11 that is directly opposite to where the test unit 12 is located can be defined as the back side of the substrate 11. Copper wiring is connected to the back conductive contact 115 on the back side of the substrate 11. The top electrode 123 is directly connected to the corresponding front conductive contact 114 of the substrate 11 through the front metal trace. The trace width can be 20µm-150µm, 30-120µm, or 50µm-100µm, and the spacing between the traces must be ≥100µm to avoid signal interference.

[0079] Understandably, the bottom electrode 121 of each test unit 12 is connected to the back conductive contact 115 through a conductive hole 113, and the top electrode 123 is directly connected to the front conductive contact 114, forming a double-sided lead-out electrical architecture. This structure distributes the leads of the high-density test array formed by multiple test units 12 to both the front and back planes of the substrate 11, resulting in ample wiring space, effectively reducing the lead density in a single plane, and completely avoiding lead crossing and the resulting short-circuit risk. This provides a reliable test environment for achieving highly reliable, crosstalk-free parallel electrical testing of hundreds of test units 12.

[0080] Furthermore, the proportions of each material in the solid electrolyte thin film layer 122 in the multiple test units 12 may be the same or different.

[0081] Understandably, the solid electrolyte thin film layers 122 in multiple test units 12 can be flexibly configured according to different research and development objectives. When the solid electrolyte thin film layers 122 in multiple test units 12 use the same material and the same proportion, the stability verification of the performance of the same solid electrolyte can be achieved under completely consistent preparation and testing conditions, so as to effectively evaluate the repeatability of the material preparation and the reliability of the test results corresponding to the current solid electrolyte thin film layer 122; while when multiple test units 12 use different material proportions, it is convenient to screen the performance of solid electrolytes with different components in parallel on a solid thin film electrolyte chip structure 1.

[0082] Please see Figure 8 and Figure 9 Furthermore, the substrate 11 also includes a pad area 112 surrounding the test area 111. The pad area 112 includes a front pad 1121 and a back pad 1122, which are the same number as the test units 12. The front conductive contacts 114 are wired to the front pads 1121 one by one, and the back conductive contacts 115 are wired to the back pads 1122 one by one.

[0083] Understandably, a dedicated pad area 112 for external connection testing can be provided at the edge of the substrate 11. This area includes an array of front pads 1121 and a array of back pads 1122 arranged in a preset manner. The number of front pads 1121 matches the total number of test units 12. Each front pad 1121 is connected to a front conductive contact 114 led out from the top electrode 123 of the corresponding test unit 12 via an independent metal trace. The number of back pads 1122 also matches the total number of test units 12. Each back pad 1122 is connected to a back conductive contact 115 led out from the bottom electrode 121 of the corresponding test unit 12 via a conductive via a conductive hole 113 via a dedicated wiring path. This one-to-one connection between the front conductive solder points and the front pads 1121, and between the back conductive solder points and the back pads 1122, ensures that each test unit 12 has a completely independent electrical connection path, effectively avoiding mutual interference between signals. The arrangement of the front pads 1121 and back pads 1122 on the pad area 112 can match the probe array of the test fixture, providing a reliable interface guarantee for subsequent testing. In addition, the design of the front pads 1121 and back pads 1122 in the pad area 112 standardizes the connection interface of high-density wiring into an ordered pad array, solving the risks of lead crossover and short circuits in traditional solutions, improving the stability and repeatability of test connections, and enabling the solid-state thin-film electrolyte chip structure 1 to quickly and accurately interface with the test system, which is more conducive to high-throughput and parallel electrochemical performance testing.

[0084] Please continue reading. Figure 8 and Figure 9 Furthermore, all the wires 116 between the test area 111 and the pad area 112 on the substrate 11 are arranged radially with the test area 111 as the center.

[0085] Understandably, the wiring scheme radiating from the test area 111 to the pad area 112 is adopted, so that all conductors 116 are arranged radially. The spacing between adjacent conductors 116 gradually increases along the direction from the test area 111 to the pad area 112, avoiding long-distance parallel routing between lines, thereby preventing signal crosstalk, reducing distributed capacitance and electromagnetic interference between lines, providing a highly independent test environment for each test unit 12, ensuring the accuracy and reliability of electrochemical measurement results, and is suitable for high-precision, high-throughput screening scenarios.

[0086] Please see Figure 10 Furthermore, a Ti layer 1131 and a Cu layer 1132 are sequentially disposed on the hole wall 1130 of the conductive hole 113. The Cu layer 1132 fills the entire conductive hole 113, so that the two ends of the Cu layer 1132 are connected to the bottom electrode 121 of the test unit 12 and the wire 116 on the side of the substrate 11 away from the test unit 12, respectively.

[0087] Understandably, the Ti layer 1131, acting as an adhesion layer, enhances the bonding force between the metal and the insulating via wall 1130; the Cu layer 1132, acting as the main conductive layer, provides an excellent current conduction path. This double-layer metallization structure ensures the stability and electrical reliability of the electrical connection between the vertical interconnect bottom electrode 121 and the conductor 116 on the back of the substrate 11. This ensures the achievement of a robust double-sided interconnect and guarantees smooth current transmission, improving the long-term stability and yield of the chip.

[0088] Please see Figure 11 The third embodiment of the present invention provides a solid thin film electrolyte chip structure 1. The difference from the second embodiment is that the conductive hole 113 in this embodiment can be prepared by steps S31'-S33' in the first embodiment. The structure of the substrate 11 and the conductive hole 113 on the substrate 11 in this embodiment is different from the structure of the second embodiment, while the rest of the structure remains the same.

[0089] In this embodiment, two first substrates 101 and second substrates 102 are stacked together. The first substrate 101 is provided with a test unit 12 and a corresponding bottom electrode 121, and the corresponding bottom electrode 121 forms a first conductive hole 113. Wiring is performed on the back side of the first substrate 101, so that the wiring extends from the first conductive hole 113 to the back conductive contact 115 of the substrate 11. One side of the second substrate 102 is etched with a reserved space for wiring corresponding to the wiring on the back side of the first substrate 101. When the first substrate 101 and the second substrate 102 are stacked together, the second substrate 102 covers the wiring on the back side of the first substrate 101, while the conductive contact on the first substrate 101 is exposed from the edge of the junction of the two first substrates 101 and the second substrate 102.

[0090] Understandably, this embodiment adopts a stacked structure of dual substrates. By combining the back wiring of the first substrate 101 with the protective coverage of the second substrate 102, the mechanical strength and wiring protection capability of the solid thin film electrolyte chip structure 1 are enhanced, effectively preventing damage to the circuit from the external environment. It is suitable for continuous testing and high-power application scenarios.

[0091] Please see Figure 12The fourth embodiment of the present invention provides a testing method for a solid-state thin-film electrolyte chip structure, applicable to the solid-state thin-film electrolyte chip structure of any one of the second and third embodiments, comprising the following steps: Step S100: Provide a test fixture; the test fixture includes multiple sets of probes, each set of probes including a front probe and a back probe; Step S200: Load the solid-state thin-film electrolyte chip structure into the test fixture; Step S300: Contact the front conductive contact corresponding to the top electrode in the test unit through the front probe in each probe group, and lead out the connected back conductive contact from the conductive hole on the side of the substrate away from the test unit through the back probe in the probe group. Step S400: Connect the test fixture to the detection device, and use the detection device to detect the solid electrolyte thin film layer in each test unit of the solid thin film electrolyte chip structure to obtain the ionic conductivity and / or electrochemical window corresponding to the solid electrolyte thin film layer in each test unit; wherein, the current signal output by the detection device passes sequentially through the front probe, the top electrode, the solid electrolyte thin film layer, the bottom electrode, the conductive hole, and the back probe, and finally returns to the detection device; and Step S500: Screen the solid electrolyte film layers in all test units of the solid thin film electrolyte chip structure based on ionic conductivity and / or electrochemical window.

[0092] Specifically, the testing method provided in this embodiment utilizes the advantages of the double-sided wiring design of the solid-state thin-film electrolyte chip structure, and achieves independent and accurate measurement of each test unit through a designed test fixture. Multiple sets of probes in the test fixture correspond one-to-one with the conductive contacts on the front and back sides of the chip, ensuring that each test unit can establish an independent test circuit. After the conductive contacts on the front and back sides of the solid-state thin-film electrolyte chip structure are connected one-to-one with the front and back probes in the test fixture, and the test fixture is also connected to the detection device, during the test, the current signal output by the detection device is transmitted along a specific path: sequentially passing through the front probe, top electrode, solid-state electrolyte thin film layer, bottom electrode, conductive hole, and finally returning to the detection device through the back probe, forming a complete test circuit, ensuring accurate transmission of the test signal and reliability of the measurement results.

[0093] It should be noted that this embodiment employs a double-sided contact measurement method. By establishing independent test circuits on both the front and back sides, complete electrical isolation can be achieved for each test unit in a high-density array. Traditional single-sided testing methods cannot avoid signal crosstalk and measurement errors when dealing with dozens or even hundreds of test units. This embodiment, however, completely separates the positive and negative measurement paths of each test unit through double-sided probe contact, effectively eliminating mutual interference between units, improving test accuracy, and facilitating high-throughput parallel testing.

[0094] Specifically, in the ionic conductivity test, electrochemical impedance spectroscopy can be used, and the detection device can be an impedance analyzer. The specific detection process is as follows: First, pre-test calibration is performed, including impedance calibration of the probe circuit of each test unit using a standard resistor to eliminate contact resistance interference; at the same time, the electrolyte film thickness of each unit is accurately measured using a profilometer, the thickness data is recorded and bound to the test unit and the corresponding unit number; Load the solid-state thin-film electrolyte chip structure into the test fixture, ensuring that the top and bottom electrodes of the solid-state thin-film electrolyte chip structure are connected to the impedance analyzer via the corresponding front and back probes. By applying a small-amplitude AC signal to each test unit, its impedance response at different frequencies is measured. Simultaneous testing was conducted under ambient temperature and multiple temperature rise conditions, and impedance data at different temperatures were recorded. Conductivity-temperature correlation analysis was achieved through multi-temperature point testing. The impedance spectrum is fitted using an equivalent circuit model, and the total impedance is obtained by extracting the real part of the impedance crossover points. Finally, based on the thickness data, temperature data, and impedance fitting results of each test unit, the conductivity formula is automatically substituted to output the ionic conductivity of the corresponding test unit, thereby achieving full automation of the testing-calculation-output process.

[0095] The formula for calculating ionic conductivity is:

[0096] Where σ is the conductivity (S / cm), L is the electrolyte thickness (cm), R is the resistance (Ω), and A is the effective electrode area (cm²).

[0097] Understandably, in ionic conductivity testing, the introduction of a dual calibration mechanism involving impedance and thickness calibration effectively eliminates the problem of contact resistance being mistakenly included in electrolyte resistance in traditional testing, significantly reducing the testing error from ±10% to ±2%. Furthermore, the establishment of a multi-temperature point synchronous testing scheme allows for the acquisition of the conductivity variation patterns of materials at different temperatures. Moreover, by achieving in-depth correlation analysis between conductivity and temperature, materials that maintain excellent performance even at low temperatures can be screened more accurately.

[0098] In electrochemical window testing, linear scanning voltammetry is used, and the detection device can be a potentiometer. The specific detection process is as follows: Pt is selected as the counter electrode to construct a Pt|solid electrolyte thin film layer|Pt symmetrical structure; if the top electrode is Li, a Li|solid electrolyte thin film layer|Pt structure test cathode window can be constructed. Use a potential scanner to perform a forward scan in the range of 0V-6V; A sweep rate gradient optimization scheme is adopted, such as using three sweep rates of 1mV / s, 5mV / s, and 10mV / s to test the solid electrolyte thin film layer, and taking the average value of the current change potential as the decomposition potential to determine the electrolyte decomposition starting point. Store the complete LSV curve data corresponding to the unit number of each test unit, automatically label the decomposition start point and decomposition peak point, and generate a "unit number-curve-window value" associated database.

[0099] Understandably, in electrochemical window testing, by setting an optimized scan rate gradient scheme to achieve the average value of multiple scan rate tests, false positive results that may be caused by a single scan rate can be effectively avoided, and the test error can be precisely controlled within ±0.05V from ±0.2V. Furthermore, the complete LSV curve not only records the decomposition potential but also establishes a comprehensive database linking "unit number - curve - window value," which can be used for subsequent materials mechanism research and the construction of a materials genome database.

[0100] Understandably, after testing, the ionic conductivity value of each test unit can be compared with the preset threshold and electrochemical window range screening criteria, based on these criteria. Simultaneously, its electrochemical window is evaluated to determine if it meets the requirements. For test units that simultaneously meet both high ionic conductivity and a wide electrochemical window, the system automatically marks them as preferred materials; for units that only meet a single criterion, they are categorized and stored according to their characteristics; and materials that do not meet the criteria are excluded.

[0101] Furthermore, in step S300, the front probe in each probe group contacts the top electrode of one of the test units, leading to the front conductive contact, and then to the front pad in the front pad area. Similarly, the back probe in the probe group contacts the bottom electrode, leading to the back conductive contact through a conductive hole, and then to the back pad in the back pad area. The pad area expands the range of external device connections for the bottom and top electrodes, facilitating the connection of the front and back probes in the test fixture to the front and back pads respectively. This enables rapid and accurate automated docking, improving testing efficiency. Compared to directly connecting conductive contacts, the corresponding connection between the pads and probes better protects the test area in the solid-state thin-film electrolyte chip structure, avoiding damage to the conductive contacts from repeated testing, extending chip lifespan, and providing reliable technical support for high-throughput screening. Additionally, the spacing between adjacent pads on the same surface is greater than the distance between adjacent solder joints on the same surface, effectively reducing mutual interference between test units during testing.

[0102] Please see Figure 13 The fifth embodiment of the present invention provides a testing system 5 for a solid-state thin-film electrolyte chip structure, applied to the testing method for the solid-state thin-film electrolyte chip structure described in the fourth embodiment, comprising: Combination Figure 7 or Figure 11 As shown, a solid-state thin-film electrolyte chip structure 1 includes a substrate 11 and test units 12 disposed on each unit region of the substrate 11. Each test unit 12 is composed of a bottom electrode 121, a solid electrolyte thin film layer 122, and a top electrode 123 stacked sequentially. A conductive hole 113 is provided on the side of the substrate 11 facing away from the test unit 12, corresponding to each bottom electrode 121. The bottom electrode 121 is connected to the back conductive contact 115 of the test area 111 through the conductive hole 113, and the top electrode 123 is directly connected to the corresponding front conductive contact 114 of the substrate 11.

[0103] like Figure 13 As shown, the test fixture 2 includes multiple sets of probe groups 21. Each set of probe groups 21 includes a front probe 211 and a back probe 212. The front probe 211 in each set of probes 21 contacts the front conductive contact 114 corresponding to the top electrode 123 in the test unit 12. The back probe 212 contacts the back conductive contact 115 connected to the bottom electrode 121, which is led out from the conductive hole 113 on the side of the substrate 11 away from the test unit 12. The detection device 3, connected to the test fixture 2, is used to detect the solid electrolyte thin film layer 122 in each test unit 12 of the solid thin film electrolyte chip structure 1, and obtain the ionic conductivity and / or electrochemical window corresponding to the solid electrolyte thin film layer 122 in each test unit 12; wherein, the current signal output by the detection device 3 passes sequentially through the front probe 211, the top electrode 123, the solid electrolyte thin film layer 122, the bottom electrode 121, the conductive hole 113, the back probe 212, and finally returns to the detection device 3; The screening device 4 is used to screen the solid electrolyte thin film layer 122 in all test units 12 of the solid thin film electrolyte chip structure 1 based on ionic conductivity and / or electrochemical window.

[0104] Understandably, this embodiment integrates a dedicated double-sided wiring solid-state thin-film electrolyte chip structure 1, a test fixture 2 including multiple sets of probes, a detection device 3, and a screening device 4. For the specific structure of the solid-state thin-film electrolyte chip structure 1, please refer to [reference needed]. Figures 6-11 The lead crosstalk problem can be solved by the solid-state thin-film electrolyte chip structure 1, the test fixture 2 can achieve fast and reliable connection, the detection device 3 can obtain accurate ionic conductivity and electrochemical window data, and finally the screening device 4 completes the data evaluation, thus forming a complete testing system. This system optimizes the entire process from sample preparation to performance screening and provides a complete technical platform for high-throughput and high-reliability screening of solid-state electrolyte materials.

[0105] The foregoing has provided a detailed description of the solid-state thin-film electrolyte chip structure, preparation method, testing method, and testing system disclosed in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention. Any modifications, equivalent substitutions, and improvements made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a solid-state thin-film electrolyte chip structure, characterized in that: Includes the following steps: A substrate is provided, the substrate including a test area formed by a plurality of cell regions arranged in an array, the edges of the test area including front conductive contacts and back conductive contacts in the same number as the cell regions; In each cell region, a bottom electrode, a solid electrolyte film layer, and a top electrode are formed sequentially to obtain a test unit formed by the bottom electrode, the solid electrolyte film layer, and the top electrode stacked sequentially. as well as Conductive holes are formed on the side of the substrate opposite to the test unit at positions corresponding to each bottom electrode. The bottom electrodes are connected to the back conductive contacts of the test area through the conductive holes and wires, and the top electrodes are directly connected to the front conductive contacts of the substrate through wires.

2. The method for fabricating a solid-state thin-film electrolyte chip structure as described in claim 1, characterized in that: In each cell region, a bottom electrode, a solid electrolyte film layer, and a top electrode are sequentially formed to obtain a test unit formed by the sequential stacking of the bottom electrode, the solid electrolyte film layer, and the top electrode. This process specifically includes the following steps: A Pt layer is deposited as a bottom electrode on each of the cell regions using DC sputtering or electron beam evaporation deposition techniques. A solid electrolyte film layer is deposited on the bottom electrode using any one of the following techniques: radio frequency sputtering, pulsed laser deposition, and spin coating-annealing. A Pt layer or Li layer is deposited or placed on the solid electrolyte film layer as a top electrode, and the bottom electrode, the solid electrolyte film layer and the top electrode in each cell region are stacked in sequence to form a test cell.

3. The method for fabricating a solid-state thin-film electrolyte chip structure as described in claim 2, characterized in that: Depositing or placing a Pt layer or a Li layer as a top electrode on the solid electrolyte thin film layer specifically includes the following steps: A Pt or Li layer is deposited on the solid electrolyte film layer as a top electrode using DC sputtering or electron beam evaporation deposition; or a pre-fabricated Pt or Li layer is transferred onto the solid electrolyte film layer to form a top electrode using metal sheet transfer technology.

4. A solid-state thin-film electrolyte chip structure, characterized in that: The solid-state thin-film electrolyte chip structure is prepared by the fabrication method of any one of claims 1-3; the solid-state thin-film electrolyte chip structure includes a substrate and test units arranged in an array on the substrate, each of the test units being composed of a bottom electrode, a solid electrolyte thin film layer and a top electrode stacked sequentially; A conductive hole is provided on the side of the substrate facing away from the test unit, corresponding to each bottom electrode. The bottom electrode is connected to the back conductive contact of the test area through the conductive hole, and the top electrode is directly connected to the front conductive contact of the substrate.

5. The solid-state thin-film electrolyte chip structure as described in claim 4, characterized in that: The proportions of each material in the solid electrolyte thin film layer in the multiple test units may be the same or different.

6. The solid-state thin-film electrolyte chip structure as described in claim 4, characterized in that: The substrate also includes a pad area surrounding the test area. The pad area includes a front pad and a back pad, which are the same number as the test units. The front conductive contacts are wired in a one-to-one correspondence with the front pads, and the back conductive contacts are wired in a one-to-one correspondence with the back pads.

7. The solid-state thin-film electrolyte chip structure as described in claim 6, characterized in that: All conductors on the substrate between the test area and the pad area are arranged radially with the test area as the center.

8. The solid-state thin-film electrolyte chip structure as described in claim 4, characterized in that: Ti layer and Cu layer are sequentially disposed on the wall of the conductive hole. The two ends of the Cu layer are respectively connected to the bottom electrode of the test unit and the wire on the side of the substrate away from the test unit.

9. A test method for a solid-state thin-film electrolyte chip structure, applied to the solid-state thin-film electrolyte chip structure as described in any one of claims 3-8, characterized in that: Includes the following steps: A test fixture is provided; the test fixture includes multiple sets of probes, each set of probes including a front probe and a back probe; The solid-state thin-film electrolyte chip structure is mounted in a test fixture; The solid-state thin-film electrolyte chip structure includes a substrate and test units disposed on each unit region of the substrate. Each test unit is composed of a bottom electrode, a solid-state electrolyte thin film layer and a top electrode stacked in sequence. A conductive hole is disposed on the side of the substrate opposite to the test unit at a position corresponding to each bottom electrode. The bottom electrode is connected to the back conductive contact of the test area through the conductive hole, and the top electrode is directly connected to the corresponding front conductive contact of the substrate. The front probe in each probe group contacts the front conductive contact corresponding to the top electrode in the test unit, and the back conductive contact is led out from the conductive hole on the side of the substrate opposite to the test unit by the back probe in the probe group. The test fixture is connected to the detection device, and the solid electrolyte thin film layer in each test unit of the solid thin film electrolyte chip structure is detected by the detection device to obtain the ionic conductivity and / or electrochemical window corresponding to the solid electrolyte thin film layer in each test unit; wherein, the current signal output by the detection device passes sequentially through the front probe, the top electrode, the solid electrolyte thin film layer, the bottom electrode, the conductive hole, the back probe, and finally returns to the detection device; The solid electrolyte film layers in all test units of the solid thin film electrolyte chip structure are screened based on ionic conductivity and / or electrochemical windows.

10. A testing system for a solid-state thin-film electrolyte chip structure, applied to the testing method for the solid-state thin-film electrolyte chip structure as described in claim 9, characterized in that: include: A solid-state thin-film electrolyte chip structure includes a substrate and test units disposed on each unit region of the substrate. Each test unit consists of a bottom electrode, a solid-state electrolyte thin film layer, and a top electrode stacked sequentially. A conductive hole is disposed on the side of the substrate opposite to the test unit at a position corresponding to each bottom electrode. The bottom electrode is connected to a back conductive contact of the test area through the conductive hole, and the top electrode is directly connected to a corresponding front conductive contact of the substrate. The test fixture includes multiple sets of probes, each set of probes including a front probe and a back probe. The front probe in each set of probes contacts a front conductive contact corresponding to the top electrode in the test unit, and the back probe contacts the back conductive contact connected to the bottom electrode through a conductive hole on the side of the substrate opposite to the test unit. A detection device, connected to the test fixture, is used to detect the solid electrolyte thin film layer in each test unit of the solid thin film electrolyte chip structure, and obtain the ionic conductivity and / or electrochemical window corresponding to the solid electrolyte thin film layer in each test unit; wherein, the current signal output by the detection device passes sequentially through the front probe, the top electrode, the solid electrolyte thin film layer, the bottom electrode, the conductive hole, the back probe, and finally returns to the detection device; as well as A screening device for screening solid electrolyte film layers in all test units of the solid thin film electrolyte chip structure based on ionic conductivity and / or electrochemical windows.

Images