Clock signal processing system and clock signal processing method

Abstract

The embodiment of the invention provides a clock signal processing system and a clock signal processing method. The processing system comprises a control module, a register module, a state machine module, a clock source generation module, a clock control module, a reset module and a function module. The clock source generation module is used for generating a functional clock signal; the state machine module is used for detecting whether the function clock signal is changed or not, and if the function clock signal is changed, a clock gating signal is sent to the clock control module and a reset control signal is sent to the reset module; the clock control module is used for determining whether to send a functional clock signal to each functional module or not according to the clock gating signal; the reset module is used for resetting clock signals of all the function modules, frequency division control words are controlled in real time through a state machine, gating and reset control signals are generated, the problems of burrs and overclocking of a clock are reasonably solved, and meanwhile the requirement for clock phase alignment required by the system is met.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more specifically, to a clock signal processing system and a clock signal processing method. Background Technology

[0002] In digital electronic circuits, sequential devices such as flip-flops cannot reach a stable state within a specified time, exhibiting a metastable state. This means that the setup time or hold time of the input signal violates the timing requirements of the register. When a flip-flop enters a metastable state, it is impossible to predict the output level of the unit or when the output will stabilize at a correct level. During this period, the flip-flop may output some intermediate levels or be in an oscillating state. This useless output level can propagate along the cascaded flip-flops in the signal path. Metastability can lead to system logic confusion and errors. Due to the existence of metastability, the output of the register may be glitches, oscillations, or a fixed voltage value before it stabilizes. Metastability in signal transmission can cause other connected digital components to make different judgments, potentially leading to system crashes or logic errors. Therefore, it is crucial to understand how to use digital methods to reasonably avoid clock glitches or overclocking when they occur, eliminating glitch clock signals to prevent impact on subsequent digital circuits. Summary of the Invention

[0003] The purpose of some embodiments of this application is to provide a clock signal processing system and a clock signal processing method. According to the technical solution of the embodiments of this application, the processing system includes: a control module, a register module, a state machine module, a clock source generation module, a clock control module, a reset module, and functional modules. The control module is connected to the register module, the register module is connected to the clock source generation module, the reset module, and the state machine module, the state machine module is connected to the clock source generation module, the clock control module, and the reset module, and the clock control module and the reset module are connected to each of the functional modules. The clock source generation module is used to generate a functional clock signal based on the frequency division control word sent by the state machine module. The state machine module is used to detect whether the functional clock signal has changed. If the functional clock signal has changed, ... The clock control module sends a clock gating signal; the reset control module sends a reset control signal; and the clock source generation module sends the frequency division control word. The clock control module determines whether to send the functional clock signal to each functional module based on the clock gating signal. The reset module resets the clock signals of each functional module based on the reset control signal sent by the state machine module. In this embodiment, during normal operation, when the system requires real-time changes to the clock source frequency division control word, causing clock overclocking or glitches, the state machine (FSM) is used to control the frequency division control word and generate gating and reset control signals in real time without affecting the normal operation of the system. This reasonably avoids clock glitches and overclocking problems, while ensuring the system's required clock phase alignment, improving the accuracy of glitches handling, and avoiding impact on subsequent digital circuits.

[0004] In a first aspect, some embodiments of this application provide a clock signal processing system. The processing system includes: a control module, a register module, a state machine module, a clock source generation module, a clock control module, a reset module, and functional modules. The control module is connected to the register module, the register module is connected to the clock source generation module, the reset module, and the state machine module, the state machine module is connected to the clock source generation module, the clock control module, and the reset module, and the clock control module and the reset module are connected to each of the functional modules. The clock source generation module is used to generate a functional clock signal based on the frequency division control word sent by the state machine module; The state machine module is used to detect whether the functional clock signal has changed. If the functional clock signal has changed, it sends a clock gating signal to the clock control module, a reset control signal to the reset module, and the frequency division control word to the clock source generation module. The clock control module is used to determine whether to send the functional clock signal to each functional module based on the clock gating signal; The reset module is used to reset the clock signals of each functional module according to the reset control signal sent by the state machine module.

[0005] Some embodiments of this application, when clock overclocking or glitches occur during normal operation due to real-time changes in the clock source divider control word caused by system requirements, utilize a state machine (FSM) to control the divider control word in real time and generate gating and reset control signals without affecting the normal operation of the system. This reasonably avoids clock glitches and overclocking problems, while ensuring the clock phase alignment required by the system, improving the accuracy of glitch handling, and avoiding impact on subsequent digital circuits.

[0006] Optionally, the state machine module is used to receive the first state word sent by the register, generate a second state word according to the first state word under the control of the enable signal, and send the second state word as the target state word to the clock source generation module. Some embodiments of this application, by setting up a state machine module, utilize the state machine (FSM) to control the frequency division control word in real time and generate gating and reset control signals, reasonably avoid clock glitches and overclocking issues, while ensuring the clock phase alignment requirements of the system. The state machine module is used to generate real-time control signals to control the clock source generation module to complete the switching of the clock frequency division control word, and output cgc_en_fsm and rst_en_fsm to control the clk_gen module and rst_gen module to avoid glitches or overclocking, respectively.

[0007] Optionally, the clock source generation module is used to modify the clock frequency of the generated functional clock signal according to the target status word. Some embodiments of this application allow the clock frequency of the generated functional clock signal to be modified according to different target words by setting a clock source generation module.

[0008] Optionally, the register module and the state machine module share the same clock.

[0009] In some embodiments of this application, to avoid metastability issues caused by asynchronous clock domain signal processing, the software needs to switch the register clock source to the same clock source as the FSM module before changing the frequency division control word signalC. When the software rewrites signalA, the signal change and the working clock of the FSM module belong to the same clock domain.

[0010] Optionally, the state machine module is configured to generate the clock gating signal cgc_en_fsm at the first clock edge of the preset clock signal before the target state word modification is completed, and to generate the reset signal rst_en_fsm at the second clock edge.

[0011] In some embodiments of this application, clock clk_free 1, 2, 3, 4, 5 correspond to five clock edges respectively. The hardware only needs two clk_free clock cycles to complete the clock switching, that is, from clock edge 1 to clock edge 5. The clock switching is completed quickly and avoids overclocking or glitches caused by clk_source during the period, which has high real-time performance.

[0012] Optionally, the clock control module is used to stop sending clock signals to the various functional modules when the clock gating signal is off.

[0013] Optionally, the clock control module is used to send corresponding clock signals to each functional module when the clock gating signal is enabled.

[0014] Some embodiments of this application use an FSM module to automatically generate relevant control signals to switch the clock source and reasonably avoid the process of clock overclocking or glitches during control word switching.

[0015] Optionally, The reset module is used to generate an asynchronous reset signal rst_n_clk at the second clock edge of the preset clock signal. The asynchronous reset signal is used to control the clock control module to perform reset processing on each functional module.

[0016] Optionally, The reset module is used to control the clock signals of each functional module to perform reset processing if the asynchronous reset signal is 0.

[0017] In some embodiments of this application, by disabling the cgc_en_fsm and rst_en_fsm signals, all clk_source divider registers are processed. Even if glitches or overclocking occur in clk_source due to changes in signalC timing, the digital signal will not be affected.

[0018] Optionally, the clock source generation module is an analog control circuit, and the analog control circuit is a phase-locked loop circuit.

[0019] Optionally, the register module is used to configure the state machine module, clock source generation module, clock control module, and reset module.

[0020] Secondly, some embodiments of this application provide a clock signal processing method applied to the clock signal processing system as described in the first aspect, the method comprising: Based on the frequency division control word sent by the state machine module, a functional clock signal is generated; The system detects whether the functional clock signal has changed; if the functional clock signal has changed, it sends a clock gating signal to the clock control module. Based on the clock gating signal, determine whether to send the functional clock signal to each functional module; The clock signals of each functional module and the register module are reset according to the reset control signal sent by the state machine module. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of some embodiments of this application, the accompanying drawings used in some embodiments of this application will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A schematic diagram of the structure of a clock signal processing system provided in an embodiment of this application; Figure 2 A circuit diagram of a clock signal processing system provided in an embodiment of this application; Figure 3 This is a timing diagram illustrating the processing of clock signals provided in an embodiment of this application. Detailed Implementation

[0023] The technical solutions of some embodiments of this application will now be described with reference to the accompanying drawings.

[0024] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] Metastability refers to a state in digital circuits where sequential devices such as flip-flops fail to reach a definite state within a specified time. This occurs when the setup or hold time of the input signal violates the timing requirements of the register. When a flip-flop enters a metastable state, it is impossible to predict its output level or when it will stabilize at a correct level. During this period, the flip-flop may output intermediate levels or oscillate, and this useless output level can propagate along the cascaded flip-flops in the signal path.

[0026] Metastability can lead to system logic confusion and errors. Due to the presence of metastability, the output of a register may exhibit glitches, oscillations, or a fixed voltage value before stabilizing. Metastability in signal transmission can cause other connected digital components to make different judgments, potentially leading to system crashes or logical errors.

[0027] In digital design systems, the clock, as a key element of the flip-flop, has strict timing requirements with the data and reset signals. Any timing violation will lead to metastability in the flip-flop output, causing immeasurable damage to the entire data link. The clock module is responsible for providing the necessary clock signals for the system, and while meeting various functional requirements, it must also ensure the robustness of the design.

[0028] As process nodes advance, the upper limit of supported clock frequencies also increases to some extent. To pursue chip performance and complete various complex calculations, at a certain process node, the design and constraints often push the clock frequency to the maximum possible limit. If the clock frequency exceeds the limit during system operation, timing violations will occur. Typically, during system initialization, the clock frequencies of various functional modules are allocated reasonably. Depending on different application scenarios, the clock frequencies of different functional modules may be adjusted dynamically or in a time-sharing manner. Therefore, depending on the requirements, sometimes it is necessary to rewrite the control word of the clock source to change the clock frequency at the source, and sometimes it is necessary to adjust the clock frequency of each module through a digital frequency divider while keeping the clock source frequency fixed. Regardless of the method used to change the clock frequency, overclocking (clock frequency exceeding the maximum constrained frequency, including overclocking caused by changes in clock duty cycle when using positive and negative edge designs) must not occur at any time during the process, otherwise timing violations will occur.

[0029] Besides the aforementioned clock overclocking causing metastability issues, other causes include: asynchronous clock domain signal processing, clock pulses not meeting the minimum pulse width (clock glitches), and timing discrepancies between the clock and reset signals.

[0030] To address the various causes of metastability, current solutions primarily target digital issues such as overclocking or glitches in digital circuits. Overclocking refers to the clock frequency exceeding the maximum frequency guaranteed by the design and constraints for safe operation. Designs typically have a margin of safety, theoretically allowing for higher frequencies. However, timing convergence may not reach the maximum frequency supported by the design. Therefore, the final clock frequency often depends on the maximum frequency constrained by timing constraints. For example, a design might support a maximum clock frequency of 200MHz, but considering limitations such as area, timing, and power consumption, the final timing convergence might only reach 180MHz. During system operation, as long as the clock frequency does not exceed 180MHz, timing is guaranteed; that is, the entire system will not experience timing violations, and all functions can operate safely. However, when the clock frequency exceeds 180MHz, timing convergence cannot be guaranteed, leading to timing violations. The outputs of triggers may not respond correctly, causing the chip to malfunction. In fact, a robust design does not allow system clock overclocking. During the timing constraint phase, if timing cannot converge to a certain frequency, a frequency reduction method is typically used to converge the timing.

[0031] For processing asynchronous signals, synchronous clocks or data signals can typically be used for synchronous processing.

[0032] Using a synchronous clock: In a synchronous system, if the interaction of signals is in the same clock domain, as long as the frequency is not overclocked, it falls within the scope of timing constraints. That is, all paths under the same clock domain, once the timing is completely converged, can meet the timing requirements of the register, and therefore metastability will not occur.

[0033] Data signal synchronization: For signals transmitted across clock domains, where data exchange occurs between one or more clock domains, the phases of the two clock domains are arbitrary. Therefore, when a signal from clock domain A is sampled by clock domain B, there is a certain probability of timing violations. For such cross-clock domain signals, digital intermediate circuits cannot achieve timing convergence by setting constraints. Therefore, for cross-clock domain signal processing, it is necessary to design a system that guarantees functional correctness. Common methods include signal synchronization techniques such as using dual-flip-flop synchronizers or asynchronous FIFOs, hardware handshaking mechanisms, and setting multiple cycles to ensure that the signal meets timing requirements during transmission, thereby avoiding metastability.

[0034] Synchronized Asynchronous Reset is a design technique that combines the fast response of asynchronous reset with the timing stability of synchronous release. It is primarily used to eliminate the metastability risk caused by the release of the reset signal, while retaining the low-power characteristics of asynchronous reset. Asynchronous reset means that the reset signal is independent of the clock and can immediately reset the circuit whenever it is valid; synchronous release ensures that the removal of the reset signal is synchronized with the clock, guaranteeing that the reset release does not lead to metastability.

[0035] Flip-flops typically have an asynchronous reset port, and the asynchronous reset has a higher priority. When the asynchronous reset is active, the flip-flop output is directly pulled to the reset value. At this point, even if the input data changes, it will not be reflected back to the output. Generally, each clock domain requires a separate synchronizer to generate a local synchronous reset signal to avoid timing conflicts across clock domains. For example, the 30MHz and 50MHz clock domains need to use independent synchronizers to ensure that the reset release is aligned with their respective clock edges.

[0036] In summary, because asynchronous reset is clock-independent, the reset activation time can be arbitrary. Even if a timing violation occurs between the reset and the clock at the reset activation time, the high priority of the reset forces the flip-flop to a fixed state, thus the timing at the reset activation time does not affect normal function. However, when the reset is withdrawn, if the withdrawal time and clock phase are also arbitrary, a timing violation may occur. In this case, because the reset is withdrawn, it no longer has the highest priority, meaning the timing between the clock and the reset will be checked normally. If a timing violation occurs, the flip-flop will output a metastable state. Typically, to increase design robustness, the reset signal is synchronously released, synchronized to the current clock domain via two stages of synchronizers. This ensures that signal processing within the same clock domain is guaranteed by timing constraints. After clock synchronization, the reset signal serves as the reset source for other flip-flops. The first stage of the synchronizer may have metastability, which will recover in the next clock cycle. Therefore, the output of the second stage of the synchronizer is used as the reset signal (if the clock frequency is high and more stages of synchronizers are needed to eliminate metastability, the output of the last stage synchronizer is used as the reset signal). This can avoid the metastability problem.

[0037] Another issue related to clock glitches is that the pulse width of the high-level clock signal is less than the agreed-upon pulse width. For example, a 100MHz clock with a period of 10ns and a duty cycle of 50% has a high-level pulse width of 5ns. Therefore, any high-level pulse width less than 5ns can be considered a clock glitch. For flip-flops, there are minimum pulse width requirements. These requirements vary depending on the process node and the specific cornerstone. If the clock pulse width is less than the minimum pulse width of the flip-flop, the timing of the flip-flop cannot be met, leading to abnormal output.

[0038] Clock glitches are likely caused by narrow pulses introduced during clock switching, or by narrow pulses generated by changes in the control word of the clock source.

[0039] One of the reasons for the aforementioned clock glitches is the switching between two clock sources. When using combinational logic (such as a MUX) to switch asynchronous clock sources, the control signal is out of phase with the clock, resulting in narrow pulses at the output. Additionally, for asynchronous signal operations, the unsynchronized clock selection signal (such as CLK_SEL) changes at any time, potentially truncating the current clock cycle or superimposing different clock edges.

[0040] Another combinational logic delay discrepancy, namely the path delay mismatch of the enable signal (EN) in the gated clock, causes a brief failure of the clock gating signal. Therefore, for switching asynchronous clock sources, a common practice is to choose a glitch-free clock switching method. That is, the design ensures that the old clock is completely turned off before the new clock is turned on, guaranteeing that there are no glitches between the old and new clocks.

[0041] Regarding the second cause of clock glitches mentioned above, which involves changing the clock source frequency, a Clock Gating Cell (CGC) is typically used. This is implemented using latches and specific logic gates. For the latch, the enable signal must be stable during the CLK low level to meet the latch setup time. By adding a logic gate (e.g., an AND gate) to the clock path and controlling it with an enable signal, when the enable signal is valid, the AND gate allows the clock signal to pass through, and the module works normally; when the enable signal is invalid, the clock signal is blocked, and the flip-flops and cells inside the module stop toggling. The design must ensure that the gating logic itself does not introduce timing problems. The control signal can come from software control registers or hardware logic. A latch is inserted in the enable signal path, utilizing its level-holding characteristic to filter glitches.

[0042] Based on the above issues, in normal applications, considering low-power design, Clock Gating Units (CGCs) are widely used in systems. When a module does not need to operate, the CGC can be used to turn off the module's clock, thereby reducing clock tree flips and lowering power consumption. When the module needs to operate normally, the CGC needs to be used to turn on the module's clock. Therefore, when a module does not need to operate, its clock can be turned off. In this way, even if the clock source produces glitches or overclocking for some reason, the module clock cannot be transmitted to the internal flip-flops because it is turned off, thus not affecting the flip-flops. However, when a module is operating normally, if a clock source glitches or overclocking occurs, because the CGC is turned on, the clock glitches or overclocking will be directly transmitted to the module's internal flip-flops, causing timing violations in the internal flip-flops, and thus causing the module to malfunction.

[0043] Typically, before a chip can operate normally, the software initializes various modules in the system, including enabling module clocks and configuring them. Switching between different application scenarios also involves software clock switching. For complex applications, these switching often require high real-time performance, especially for interactions between multiple modules, which have clock phase requirements and timely response demands. For example, in ADC design, some designs require that the clock connection not be interrupted for extended periods during ADC sampling and conversion; that is, the clock cannot be without toggle for a prolonged period. Therefore, if module clocks are switched on and off via software to avoid glitches or overclocking—that is, the module clock is turned off for a period and then turned on again after the clock source glitches or overclocking issues disappear—this process is often too time-consuming and cannot meet real-time requirements.

[0044] In view of this, some embodiments of this application provide a clock signal processing system, which includes: a control module, a register module, a state machine module, a clock source generation module, a clock control module, a reset module, and functional modules. The control module is connected to the register module, the register module is connected to the clock source generation module, the reset module, and the state machine module, the state machine module is connected to the clock source generation module, the clock control module, and the reset module, and the clock control module and the reset module are connected to their respective functional modules. The clock source generation module generates a functional clock signal based on a frequency division control word sent by the state machine module. The state machine module detects whether the functional clock signal has changed; if the functional clock signal has changed, it sends a clock gating signal to the clock control module and to the reset module. The module sends a reset control signal and the frequency division control word to the clock source generation module; the clock control module is used to determine whether to send a functional clock signal to each functional module according to the clock gating signal; the reset module is used to reset the clock signal of each functional module according to the reset control signal sent by the state machine module. In this embodiment, during normal operation, when the clock overclocking or glitches are caused by the real-time change of the clock source frequency division control word due to system requirements, the state machine (FSM) is used to control the frequency division control word and generate gating and reset control signals in real time without affecting the normal operation of the system, so as to reasonably avoid clock glitches and overclocking problems, while ensuring the clock phase alignment requirements of the system, improving the accuracy of glitches, and avoiding the impact on subsequent digital circuits.

[0045] like Figure 1 As shown, an embodiment of this application provides a clock signal processing system, which includes: a control module 101, a register module 102, a state machine module 103, a clock source generation module 105, a clock control module 104, a reset module 106, and functional modules. The control module 101 is connected to the register module 102, the register module 102 is connected to the clock source generation module 105, the reset module 106, and the state machine module 103, the state machine module 103 is connected to the clock source generation module 105, the clock control module 104, and the reset module 106, and the clock control module 104 and the reset module 106 are connected to the respective functional modules. The clock source generation module 105 is used to generate a functional clock signal based on the frequency division control word sent by the state machine module; The state machine module 103 is used to detect whether the functional clock signal has changed. If the functional clock signal has changed, it sends a clock gating signal to the clock control module, a reset control signal to the reset module, and the frequency division control word to the clock source generation module. The clock control module 104 is used to determine whether to send a functional clock signal to each functional module based on the clock gating signal; The reset module 106 is used to reset the clock signals of each functional module and the related triggers according to the reset control signal sent by the state machine module.

[0046] Specifically, Figure 2 A circuit diagram of a clock signal processing system provided in an embodiment of this application is shown below. Figure 2 As shown, it includes the following modules: The control module 101, i.e., the CPU or processor, mainly performs software operations; Register module 102: Responsible for controlling system-related registers and configuring various functional modules; The state machine module 103, also known as the FSM module, is used to generate real-time control signals to control the clock source generation module to complete the clock division control word switching. At the same time, it outputs cgc_en_fsm and rst_en_fsm to control the clk_gen module and rst_gen module to avoid glitches or overclocking, respectively. Clock source generation module 105: Provides the design of the clock source for the system, which is built from analog circuits, such as phase-locked loops (PLLs). Clock control module 104, also known as clk_gen module, is used to generate the clocks required by various modules of the system; Reset module 106, also known as the rst_gen module, is used to generate the resets required by various modules of the system. Functional modules, namely module1 / 2 / N: These are the various functional modules in the system.

[0047] Before sending the functional clock signal to each functional module, the state machine module 103 detects whether the functional clock signal has changed. If the functional clock signal has changed, it sends a clock gating signal to the clock control module and a reset control signal to the reset module, and controls the frequency division control word of the clock source generation module in real time. The clock control module 104 determines whether to send the functional clock signal to each functional module based on the clock gating signal. In this way, glitches generated in the line can be eliminated in advance, and the signal is clean before reaching each functional module.

[0048] Some embodiments of this application, when clock overclocking or glitches occur during normal operation due to real-time changes in the clock source divider control word caused by system requirements, utilize a state machine (FSM) to control the divider control word in real time and generate gating and reset control signals without affecting the normal operation of the system. This reasonably avoids clock glitches and overclocking problems, while ensuring the clock phase alignment required by the system, improving the accuracy of glitch handling, and avoiding impact on subsequent digital circuits.

[0049] Another embodiment of this application further supplements the description of the clock signal processing system provided in the above embodiments.

[0050] based on Figure 2 The signals generated are shown below: sel_fsm: From register, used to control whether the clock divider control word comes from the FSM module or the register module. When it is 0, the control signal output by the register module is selected to go to the clock source generation module. When it is 1, the control signal output by the FSM module is selected to go to the clock source generation module. signalA: From the register module, clock divider control word, used to adjust the clock frequency of the clock source generation module. This control word is also transmitted to the FSM module for the initialization configuration of the FSM module. signalB: From the FSM module, clock divider control word, used to adjust the clock frequency of the clock source generation module; signalC: MUX for register module output and FSM module output, clock divider control word, used to adjust the clock frequency of the clock source generation module; fsm_en: From the register module, the FSM module is enabled. When this signal is 1, the FSM module is enabled, and when it is 0, the FSM module is disabled. clk_free: This comes from another clock source in the system. This clock has a fixed frequency and phase, and its frequency and phase remain unchanged during system operation. cgc_en_fsm: From the FSM module, output to the clk_gen module, used for real-time control of CGC to avoid clock overclocking or glitches; cgc_en_reg: Originates from the register module and outputs to the clk_gen module for real-time control of CGC, avoiding clock overclocking or glitches; rst_n_fsm: From rst_gen, for resetting the FSM module; rst_en_fsm: from the FSM module, output to rst_gen, used to generate rsg_n_clk, to ensure the clock phase of clk_gen remains aligned after avoiding clock glitches or overclocking; rst_en_reg: from the register module, output to rst_gen, used to generate rsg_n_clk, to ensure the clock phase of clk_gen remains aligned after avoiding clock glitches or overclocking; clk_source: This comes from the clock source generation module and is the source of the system clock. It usually comes from analog circuits. This clock will change with the frequency division control word and may be overclocked or have glitches. clk_1 / 2 / N: These are derived from clk_gen, divided by clk_source, and output to their respective modules as clocks. rst_n_clk: From rst_gen, after avoiding clock glitches or overclocking, it fulfills the clock phase alignment requirement generated by clk_gen; rst_n_1 / 2 / N: These are from rst_gen and are output to the corresponding modules as resets for those modules. This application embodiment, as an optional implementation method, namely a hardware control scheme, uses the FSM module to automatically generate relevant control signals to switch the clock source and reasonably avoids clock overclocking or glitches during control word switching. This scheme requires software to set sel_fsm to 1. At this time, cgc_en in the timing diagram is cgc_en_fsm, rst_en is rst_en_fsm, and signalC comes from signalB output by the FSM module. By automatically updating the frequency division control word of the clock source by hardware logic, it has high real-time performance.

[0051] Optionally, the state machine module receives the first state word sent by the register, generates a second state word based on the first state word under the control of the enable signal, and sends the second state word as the target state word to the clock source generation module. Some embodiments of this application, by setting up a state machine module, utilize the state machine (FSM) to control the frequency division control word in real time and generate gating and reset control signals, reasonably avoid clock glitches and overclocking issues, while ensuring the clock phase alignment requirements of the system. The state machine module is used to generate real-time control signals to control the clock source generation module to complete the switching of the clock frequency division control word, and output cgc_en_fsm and rst_en_fsm to control the clk_gen module and rst_gen module to avoid glitches or overclocking, respectively.

[0052] Optionally, the clock source generation module is used to modify the clock frequency of the generated functional clock signal according to the target status word.

[0053] Specifically, since a hardware control scheme was chosen, the actual software-modified register is signalA. This signal is transmitted to the FSM module in real time for processing and is displayed at clock edge 3 (e.g., ...). Figure 3 As shown), the signalC output is passed to the clock source generation module. This module changes the frequency of clk_source based on the value of signalC, which may cause brief clock glitches or overclocking issues, such as... Figure 3 The red arrow points to clk_source.

[0054] Some embodiments of this application allow the clock frequency of the generated functional clock signal to be modified according to different target words by setting a clock source generation module.

[0055] Optionally, the register module and the state machine module share the same clock. like Figure 3 As shown, it is known that when the clock source frequency is switched, i.e., when the frequency division control word signalC is changed, the software can rewrite signalA at any time according to system requirements. signalA is processed by the state machine module to generate signalC. When signalC is rewritten, the clock clk_source output by the clock source generation module will experience overclocking or glitches, such as... Figure 3 At the red arrow, since the clock of the register module and the clock of the FSM module are from different clock sources, in order to avoid metastability problems caused by asynchronous clock domain signal processing, the software needs to switch the register clock source to the same clock source as the FSM module before changing the frequency division control word signalA. In this way, when the software rewrites signalA, the signal change and the working clock of the FSM module belong to the same clock domain.

[0056] In some embodiments of this application, to avoid metastability issues caused by asynchronous clock domain signal processing, the software needs to switch the register clock source to the same clock source as the FSM module before changing the frequency division control word signalC. When the software rewrites signalA, the signal change and the working clock of the FSM module belong to the same clock domain.

[0057] Optionally, the state machine is used to generate a clock gating signal cgc_en_fsm at the first clock edge of the preset clock signal before the target state word modification is completed, and to generate a reset signal rst_en_fsm at the second clock edge.

[0058] In some embodiments of this application, clock clk_free 1, 2, 3, 4, 5 correspond to five clock edges respectively. The hardware only needs two clk_free clock cycles to complete the clock switching, that is, from clock edge 1 to clock edge 5. The clock switching is completed quickly and avoids overclocking or glitches caused by clk_source during the period, which has high real-time performance.

[0059] Optionally, the clock control module is used to stop sending clock signals to each functional module when the clock gating signal is off.

[0060] Optionally, the clock control module is used to send corresponding clock signals to each functional module when the clock gating signal is enabled.

[0061] Specifically, since all triggers in the system are sensitive to glitches or overclocking, the FSM module generates `cgc_en_fsm` on clock edge 1 and `rst_en_fsm` on clock edge 2 before controlling the `signalC` change. `cgc_en_fsm` controls the gating of all trigger clocks under the `clk_source` clock domain, ensuring that all gating under the `clk_source` clock domain is disabled before clock glitches or overclocking signals arrive. For example, `clk_internal` is a temporary clock variable inside the `clk_gen` module, which serves as the frequency divider for the entire system clock.

[0062] Therefore, when cgc_en_fsm is disabled, the clk_internal clock seen by the system clock is a clean clock, meaning there is no clock overclocking or glitches. Thus, clocks obtained by dividing clk_internal, such as clk_1 / clk_2 / clk_N, are all clean clocks.

[0063] When the software modifies signalA, the hardware logic automatically generates a change in cgc_en_fsm. Specifically, cgc_en_fsm is pulled low at clock edge 1 to disable clock gating. To avoid metastability issues, cgc_en_fsm is synchronized by clk_internal, ensuring that the clk_internal clock is properly shut down. When the clk_internal clock is turned off, all the division clocks clk_1 / 2 / N of clk_internal are paused, either at level 0 or at level 1.

[0064] Some embodiments of this application use an FSM module to automatically generate relevant control signals to switch the clock source and reasonably avoid the process of clock overclocking or glitches during control word switching.

[0065] Optionally, the reset module is used to generate an asynchronous reset signal rst_n_clk at the second clock edge of the preset clock signal. The asynchronous reset signal is used to control the clock control module to perform reset processing on each functional module.

[0066] Optionally, the reset module is used to control the clock signals of each functional module to perform reset processing if the asynchronous reset signal is 0.

[0067] Specifically, due to the phase alignment requirements of the system clock, such as Figure 3 As shown in the timing diagram, clk1 / 2 / N, etc., need to toggle to a high level on the same clock edge at the dashed line. However, when clk_internal is turned off, clk1 / 2 / N may be turned off to level 0 or level 1. For example, clk_1 toggles to a high level on the clock edge before clk_internal is about to be turned off, and it will not toggle again until a new clock edge appears in clk_internal. Therefore, if no special processing is done on clk_1 / 2 / N during the clock shutdown period, clk_1 may toggle to level 0 and clk_2 / N may toggle to level 1 at the dashed line. This would make it impossible to guarantee the phase alignment requirement of all clocks at the dashed line. Therefore, the FSM module automatically generates the rst_en signal at clock edge 2, which in turn generates the asynchronous reset signal rst_n_clk. This signal is used to control all the frequency divider clock registers of clk_internal. When rst_n_clk is pulled low, i.e. when the asynchronous reset is active, all clk_1 / 2 / N are pulled to level 0. For example, the clk_1 signal itself is at level 1 when clk_internal is turned off, but it is reset to level 0 by the reset signal rst_n_clk at the green arrow. Without rst_en control, clk_1 will remain at level 1 at the green arrow and will remain there until it flips to 0 at the dashed line.

[0068] After all clk_source divider registers have been processed by disabling the cgc_en_fsm and rst_en_fsm signals, the system will not be affected even if the clk_source experiences glitches or overclocking as indicated by the red arrow due to changes in signalC timing.

[0069] like Figure 3As shown, after avoiding clock glitches or overclocking, i.e., after completing the clock frequency switching of the clock source, the system clock needs to be restored to the new clock frequency. Therefore, at clock edge 5, the FSM module first pulls cgc_en_fsm high to enable clock gating, and then pulls rst_en_fsm low at clock edge 6 to release the reset signal. The reason for enabling cgc_en_fsm first and then releasing rst_en_fsm is to avoid timing issues between the timing of cgc_en_fsm changes and the clock signal. That is, when cgc_en_fsm is at a fixed level when clk changes, the timing of the gating circuit can be guaranteed. At the same time, in order to avoid metastability issues between the clock and the reset signal, rst_n_clk needs to be released synchronously. Therefore, when rst_n_clk goes high, clk_internal clock is released normally, and clk_1 / 2 / N obtained by dividing clk_internal flips to high level at the same time, ensuring the phase alignment requirement.

[0070] In some embodiments of this application, by disabling the cgc_en_fsm and rst_en_fsm signals, all clk_source divider registers are processed. Even if glitches or overclocking occur in clk_source due to changes in signalC timing, the digital signal will not be affected.

[0071] Optionally, the clock source generation module is an analog control circuit, and the analog control circuit is a phase-locked loop circuit.

[0072] Optionally, the register module is used to configure the state machine module, clock source generation module, clock control module, and reset module.

[0073] This application embodiment addresses the issue of clock source overclocking or glitches during normal module operation. Considering both system real-time requirements and the need for flexible system configuration in complex applications, this embodiment provides a clock signal processing system. During normal operation, when real-time changes to the clock source divider control word cause clock overclocking or glitches, a Finite State Machine (FSM) is used to control the divider control word in real-time and generate gating and reset control signals without affecting normal system operation. This effectively avoids clock glitches and overclocking while ensuring the required clock phase alignment. Furthermore, considering system configuration flexibility and increasing design robustness, this embodiment does not have high real-time requirements but requires flexible configuration to avoid clock overclocking or glitches. Frequency switching can be performed by finding suitable time points. It should be noted that each of the implementable methods in this embodiment can be implemented individually or in any combination without conflict. This application does not limit this.

[0074] Another embodiment of this application provides a clock signal processing method applied to the aforementioned clock signal processing system, the method comprising: Based on the frequency division control word sent by the state machine module, a functional clock signal is generated; The system detects whether the functional clock signal has changed; if the functional clock signal has changed, it sends a clock gating signal to the clock control module. Based on the clock gating signal, determine whether to send the functional clock signal to each functional module; The clock signals of each functional module and the register module are reset according to the reset control signal sent by the state machine module.

[0075] In addition to the hardware control scheme described above, this application embodiment can also employ a software control scheme, where the control module needs to set sel_fsm to 0 via software. In this case, the timing... Figure 3 In this context, `cgc_en` is equivalent to `cgc_en_reg`, and `rst_en` is equivalent to `rst_en_reg`. `signalC` directly originates from the software-configured `signalA` signal. As mentioned above, when `signalC` changes, `clk_source` may experience glitches or overclocking. To avoid clock glitches or overclocking, additional software-controlled registers for `cgc_en_reg` and `rst_en_reg` are needed. When rewriting `signalA`, the software first pulls `cgc_en_reg` low to disable clock gating, then pulls `rst_en_reg` high for asynchronous reset, and then rewrites `signalA`. After rewriting `signalA`, i.e., avoiding clock glitches, the software first configures `cgc_en_reg` to 1 to enable gating, and then configures `rst_en_reg` to 0 to release the reset. Because the software process lacks high real-time performance, the time required for the software to complete the above configuration process far exceeds that of the hardware solution, failing to meet real-time requirements. However, the software solution offers greater flexibility, allowing for frequency switching at appropriate times based on different application needs. Therefore, this approach can serve as a supplement to the hardware solution, further enhancing the robustness of the design.

[0076] In this embodiment, during normal operation, when the clock source divider control word is changed in real time due to system requirements, resulting in clock overclocking or glitches, a state machine (FSM) is used to control the divider control word in real time and generate gating and reset control signals, without affecting the normal operation of the system. This effectively avoids clock glitches and overclocking problems while ensuring the clock phase alignment required by the system. Furthermore, a software control scheme is supported, allowing for flexible software configuration to fulfill the corresponding functional requirements, further increasing the robustness of the design.

[0077] This application provides a digital method to avoid clock glitches or overclocking issues. Especially for complex application systems, it allows for the selection of flexible software configuration schemes and hardware schemes with high real-time requirements, fulfilling various clock frequency switching needs, perfectly avoiding clock glitches or overclocking issues, while preserving the integrity and correctness of system operation.

[0078] Regarding the apparatus in this embodiment, the specific manner in which each module performs its operations has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0079] The above are merely embodiments of this application and are not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0080] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0081] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A clock signal processing system, characterized in that, The processing system includes: a control module, a register module, a state machine module, a clock source generation module, a clock control module, a reset module, and functional modules. The control module is connected to the register module, the register module is connected to the clock source generation module, the reset module, and the state machine module, the state machine module is connected to the clock source generation module, the clock control module, and the reset module, and the clock control module and the reset module are connected to each of the functional modules. The clock source generation module is used to generate a functional clock signal based on the frequency division control word sent by the state machine module; The state machine module is used to detect whether the functional clock signal has changed. If the functional clock signal has changed, it sends a clock gating signal to the clock control module, a reset control signal to the reset module, and the frequency division control word to the clock source generation module. The clock control module is used to determine whether to send the functional clock signal to each functional module based on the clock gating signal; The reset module is used to reset the clock signals of each functional module according to the reset control signal sent by the state machine module.

2. The clock signal processing system according to claim 1, characterized in that, The state machine module is used to receive the first state word sent by the register, and under the control of the enable signal, generate a second state word according to the first state word, and send the second state word as the target state word to the clock source generation module.

3. The clock signal processing system according to claim 2, characterized in that, The clock source generation module is used to modify the clock frequency of the generated functional clock signal according to the target status word.

4. The clock signal processing system according to claim 1, characterized in that, The register module and the state machine module share the same clock.

5. The clock signal processing system according to claim 3, characterized in that, The state machine module is used to generate the clock gating signal at the first clock edge of the preset clock signal before the target state word modification is completed, and to generate a reset signal at the second clock edge.

6. The clock signal processing system according to claim 1, characterized in that, The clock control module is used to stop sending clock signals to each functional module when the clock gating signal is off.

7. The clock signal processing system according to claim 1, characterized in that, The clock control module is used to send corresponding clock signals to each functional module when the clock gating signal is enabled.

8. The clock signal processing system according to claim 5, characterized in that, The reset module is used to generate an asynchronous reset signal at the second clock edge of the preset clock signal. The asynchronous reset signal is used to control the clock control module to perform reset processing on each functional module.

9. The clock signal processing system according to claim 8, characterized in that, The reset module is used to control the clock signals of each functional module to perform reset processing if the asynchronous reset signal is 0.

10. The clock signal processing system according to claim 1, characterized in that, The clock source generation module is an analog control circuit, and the analog control circuit is a phase-locked loop circuit.

11. The clock signal processing system according to claim 1, characterized in that, The register module is used to configure the state machine module, clock source generation module, clock control module, and reset module.

12. A clock signal processing method, characterized in that, The method, applied to a clock signal processing system as described in any one of claims 1-11, comprises: Based on the frequency division control word sent by the state machine module, a functional clock signal is generated; The system detects whether the functional clock signal has changed. If the functional clock signal has changed, a clock gating signal is sent to the clock control module. Based on the clock gating signal, determine whether to send the functional clock signal to each functional module; The clock signals of each functional module and the register module are reset according to the reset control signal sent by the state machine module.

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