Audio data synchronization method and device, computer equipment, medium and product

Abstract

The invention relates to an audio data synchronization method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the steps of determining a first frequency division coefficient of an audio playing clock based on a reference frequency division coefficient in response to the situation that an accumulated value of absolute values of differences between playing ending moments of multiple pieces of historical audio data and a system time sequence clock reaches a preset threshold value; adjusting a mapping reference value based on the first frequency division coefficient and the reference frequency division coefficient; determining a second frequency division coefficient of the audio playing clock according to the adjusted mapping reference value; and controlling the next segment of audio data to play based on the second frequency division coefficient. By adopting the method, synchronization between the playing time of the audio data and the system time sequence clock can be realized, so that the playing effect is improved.

Description

Technical Field

[0001] This application relates to the field of audio control technology, and in particular to a method, apparatus, computer device, computer-readable storage medium, and computer program product for synchronizing audio data. Background Technology

[0002] In the MPEG-2 system layer specification, audio synchronization and system clock recovery time stamps are located at three layers: Elementary Stream (ES), Packetized Elementary Stream (PES), and Transport Stream (TS). At the ES layer, synchronization is primarily related to the Video Buffer Verifier (VBV), used to prevent buffer overflow or underflow in the decoder. At the PES layer, synchronization is mainly related to the Presentation Time Stamp (PTS) and Decoding Time Stamp (DTS) in the PES header. At the TS layer, the TS header contains the Program Clock Reference (PCR), used to recover the System Time Clock (STC). The STC is the audio synchronization reference; it is a series of 27MHz pulses that trigger a counter to form a binary time reference. Time stamps such as PCR, PTS, and DTS are obtained by sampling this STC. Therefore, synchronization between audio data and the STC is crucial.

[0003] In related technologies, when the playback time of audio data is not synchronized with STC, it affects the continuity of audio playback, such as playback being unsmooth, audio interruptions or skipping, resulting in poor audio data playback quality. Summary of the Invention

[0004] Therefore, it is necessary to provide an audio data synchronization method, apparatus, computer device, computer-readable storage medium, and computer program product that can achieve synchronization between the playback time of audio data and the system timing clock, in order to address the above-mentioned technical problems.

[0005] Firstly, this application provides a method for synchronizing audio data, including:

[0006] In response to the cumulative value of the absolute value of the difference between the playback end time of multiple historical audio data and the system timing clock reaching a preset threshold, the first frequency division coefficient of the audio playback clock is determined based on the reference frequency division coefficient;

[0007] Adjust the mapping reference value based on the first frequency division coefficient and the reference frequency division coefficient;

[0008] The second frequency division coefficient of the audio playback clock is determined based on the adjusted mapping reference value;

[0009] The playback of the next segment of audio data is controlled based on the second frequency division coefficient.

[0010] In one embodiment, adjusting the mapping reference value based on the first frequency division coefficient and the reference frequency division coefficient includes:

[0011] In response to the first division factor being greater than the reference division factor, the mapping reference value is reduced to obtain the adjusted mapping reference value;

[0012] In response to the first division factor being less than the reference division factor, the mapping reference value is increased to obtain the adjusted mapping reference value.

[0013] In one embodiment, determining the second frequency division coefficient of the audio playback clock based on the adjusted mapping reference value includes:

[0014] Based on the preset mapping relationship and the adjusted mapping reference value, the selection signal and the target playback clock cycle corresponding to the selection signal are determined, wherein the preset mapping relationship includes the correspondence between the selection signal, the mapping reference value and at least one playback clock cycle in each group of playback clock cycles;

[0015] The reference division coefficient is adjusted according to the selection signal to obtain the second division coefficient within the target playback clock cycle corresponding to the selection signal.

[0016] In one embodiment, adjusting the reference division coefficient according to the selection signal to obtain the second division coefficient within the target playback clock cycle corresponding to the selection signal includes:

[0017] In response to the first division factor being greater than the reference division factor, the reference division factor is increased to obtain the second division factor within the target playback clock cycle corresponding to the selection signal;

[0018] In response to the first division factor being less than the reference division factor, the reference division factor is reduced to obtain the second division factor within the target playback clock cycle corresponding to the selection signal.

[0019] In one embodiment, controlling the playback of the next segment of audio data based on the second frequency division coefficient includes: determining the target frequency of the audio playback clock according to the preset frequency of the audio playback clock and the second frequency division coefficient, and controlling the playback of the next segment of audio data according to the target frequency.

[0020] In one embodiment, determining the first frequency division factor of the audio playback clock based on the reference frequency division factor includes:

[0021] In response to the difference being greater than a first value, the reference frequency division factor is increased to obtain a first frequency division factor;

[0022] In response to the difference being less than a first value, the reference frequency division coefficient is reduced to obtain a first frequency division coefficient.

[0023] Secondly, this application also provides an audio data synchronization device, comprising:

[0024] The first determining module is used to determine the first frequency division coefficient of the audio playback clock based on the reference frequency division coefficient when the cumulative value of the absolute value of the difference between the playback end time of multiple historical audio data and the system timing clock reaches a preset threshold.

[0025] The second determining module is used to adjust the mapping reference value based on the first frequency division coefficient and the reference frequency division coefficient;

[0026] The third determining module is used to determine the second frequency division of the audio playback clock based on the adjusted mapping reference value;

[0027] The control module is used to control the playback of the next segment of audio data based on the second frequency division coefficient.

[0028] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method proposed in the first aspect of the embodiments of this application.

[0029] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method proposed in the first aspect of the embodiments of this application.

[0030] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the method proposed in the first aspect of the embodiments of this application.

[0031] The aforementioned audio data synchronization method, apparatus, computer device, computer-readable storage medium, and computer program product, in response to the cumulative absolute value of the difference between the playback end time of multiple historical audio data and the system timing clock reaching a preset threshold, determine a first frequency division coefficient for the audio playback clock based on a reference frequency division coefficient. Then, adjust a mapping reference value based on the first frequency division coefficient and the reference frequency division coefficient. A second frequency division coefficient for the audio playback clock is determined based on the adjusted mapping reference value. Finally, the playback of the next segment of audio data is controlled based on the second frequency division coefficient. In other words, by adjusting the frequency division coefficient, the playback clock is adjusted, thereby changing the playback speed of the next segment of audio data, which enables synchronization between the playback time of the audio data and the system timing clock, thus improving the playback effect of the audio data. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a diagram illustrating the application environment of an audio data synchronization method in one embodiment.

[0034] Figure 2 This is a flowchart illustrating an audio data synchronization method in one embodiment;

[0035] Figure 3 This is a schematic diagram of the signal connection between the audio playback module and the clock adjustment module in one embodiment;

[0036] Figure 4 for Figure 2 A flowchart illustrating step 203;

[0037] Figure 5 This is a schematic diagram of the signal connection between a 3-to-1 selector and a 2-to-1 selector in one embodiment;

[0038] Figure 6 for Figure 2 A flowchart illustrating step 204 in the middle section;

[0039] Figure 7 This is a flowchart illustrating an audio data synchronization method in a specific example.

[0040] Figure 8 This is a flowchart illustrating the audio data synchronization method in another specific example;

[0041] Figure 9This is a structural block diagram of an audio data synchronization device in one embodiment;

[0042] Figure 10 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0044] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0045] Synchronization is essential for correct audio playback. In digital television, due to the use of buffers to store signals during compression encoding, the time axis of the signal in the multiplexer is variable. Furthermore, the compression ratio varies depending on the amount of data redundancy, resulting in significant time axis fluctuations. All of these factors can lead to audio data desynchronization, meaning the playback time of the audio data is inconsistent with or out of sync with the STC (Synchronous Transmission Time). Currently, there is a lack of synchronization solutions in relevant technologies to address audio data desynchronization.

[0046] Therefore, this application proposes an audio data synchronization method that can synchronize audio data playback with the system timing clock, thereby improving playback performance.

[0047] The audio data synchronization method provided in this application embodiment can be applied to, for example, Figure 1 In the application environment shown, terminal 102 communicates with server 104 via a network. A data storage system can store the data that server 104 needs to process. The data storage system can be integrated onto server 104, or it can be located in the cloud or on other network servers. Terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, smart TVs, tablets, drones, low-altitude aircraft, IoT devices, and portable wearable devices. Server 104 can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services.

[0048] In one exemplary embodiment, such as Figure 2 As shown, an audio data synchronization method is provided, which can be applied to... Figure 1 Taking terminal 102 as an example, the explanation includes the following steps 201 to 204. Wherein:

[0049] Step 201: In response to the cumulative value of the absolute value of the difference between the playback end time of multiple historical audio data and the system timing clock reaching a preset threshold, the first frequency division coefficient of the audio playback clock is determined based on the reference frequency division coefficient.

[0050] The end time of playback for multiple historical audio data is determined at the end of playback for each historical audio data. When this end time is inconsistent with the corresponding system timing clock, a difference exists; therefore, each historical audio data corresponds to a difference. The reference division factor comes from a register and represents the division factor of the audio playback clock when the audio data is normal (synchronized).

[0051] For example, after the playback of multiple historical audio data segments ends, the absolute values ​​of all differences are summed to obtain an accumulated value. When this accumulated value reaches a preset threshold, it will cause the playback time of the next audio data segment to be out of sync with the system timing clock, thus requiring synchronization of the next audio data segment. First, a frequency division factor for the audio playback clock is determined based on a reference frequency division factor, referred to as the first frequency division factor. Optionally, the reference frequency division factor can be adjusted, such as by increasing, decreasing, stepwise increasing, or stepwise decreasing, or by performing addition, subtraction, multiplication, or division calculations on the reference frequency division factor to obtain an updated frequency division factor, which is the first frequency division factor.

[0052] Step 202: Adjust the mapping reference value based on the first frequency division coefficient and the reference frequency division coefficient.

[0053] The mapping reference value refers to the reference value used to generate the second frequency division coefficient. This reference value is specifically used for subsequent mapping, and its initial value is a certain value, such as the initial value 16.

[0054] For example, the first frequency division coefficient and the reference frequency division coefficient can be compared, and the mapping reference value can be adjusted according to the comparison result. Alternatively, the difference between the first frequency division coefficient and the reference frequency division coefficient can be calculated, and the mapping reference value can be adjusted according to the magnitude of the difference. The mapping reference value can be adjusted by operations such as addition, subtraction, multiplication, and division to obtain the adjusted mapping reference value. The specific setting depends on actual needs and experience. For example, if the difference between the two coefficients is greater than a preset difference, it indicates a large difference, and the playback clock needs to be slowed down. Therefore, the mapping reference value is reduced, and the specific reduction amount can be preset according to actual needs.

[0055] Step 203: Determine the second frequency division coefficient of the audio playback clock based on the adjusted mapping reference value.

[0056] For example, the adjusted mapping reference value can be further adjusted to the reference frequency division coefficient, such as by performing addition, subtraction, multiplication, and division operations to obtain a second frequency division coefficient, which is called the second frequency division coefficient. This adjustment step can be the same as or different from the adjustment in step 201.

[0057] Step 204: Control the playback of the next segment of audio data based on the second frequency division coefficient.

[0058] For example, after obtaining the second frequency division factor, the audio playback clock can be controlled according to the second frequency division factor to synchronize the playback time of the next audio data segment with the system timing clock. The frequency division factor mentioned above can be a frequency division factor used to control the phase-locked loop.

[0059] In the aforementioned audio data synchronization method, firstly, in response to the cumulative absolute value of the difference between the playback end time of multiple historical audio data and the system timing clock reaching a preset threshold, a first frequency division coefficient of the audio playback clock is determined based on a reference frequency division coefficient. Then, a mapping reference value is adjusted based on the first frequency division coefficient and the reference frequency division coefficient. A second frequency division coefficient of the audio playback clock is determined based on the adjusted mapping reference value. Finally, the playback of the next segment of audio data is controlled based on the second frequency division coefficient, thus synchronizing the playback time of the next segment of audio data with the system timing clock. In other words, this embodiment of the application, by adjusting the frequency division coefficient and thus the playback clock, changes the playback speed of the next segment of audio data, enabling synchronization between the playback time of the audio data and the system timing clock, thereby improving the playback effect of the audio data.

[0060] In an exemplary embodiment, the first frequency division coefficient of the audio playback clock determined based on the reference frequency division coefficient in step 201 above may include: increasing the reference frequency division coefficient to obtain the first frequency division coefficient in response to the difference being greater than a first value; and decreasing the reference frequency division coefficient to obtain the first frequency division coefficient in response to the difference being less than the first value.

[0061] The first value can be a pre-set value used to determine the playback speed of audio data, such as 0.

[0062] For example, such as Figure 3As shown, the audio playback terminal may include an audio playback module 301 and a clock adjustment module 302. The audio playback module 301 includes a comparison unit 311 and a generation unit 312. First, the comparison unit 311 compares the playback end time of each historical audio data with the system timing clock. When the two are inconsistent, and the absolute value of the difference between all playback end times and the system timing clock accumulates to a preset threshold, it further determines the relationship between each difference and a first value, such as 0. If the difference is greater than 0, it outputs a first flag signal over_th as a second value (such as 1) and a second flag signal under_th as a third value (different from the second value, such as 0), indicating that the audio playback clock needs to be slowed down. If the difference is less than 0, it outputs a first flag signal over_th as 0 and a second flag signal under_th as 1, indicating that the audio playback clock needs to be sped up. The comparison unit 311 outputs the first flag signal and the second flag signal to the generation unit 312. The generation unit 312 generates a first frequency division coefficient pll_cntl_scale based on the first and second flag signals and the reference frequency division coefficient r_global_scale. Optionally, when over_th is 1 and under_th is 0, r_global_scale is increased by a first preset value to obtain pll_cntl_scale; when over_th is 0 and under_th is 1, r_global_scale is decreased by a first preset value to obtain pll_cntl_scale. That is, the first division coefficient is different in the two cases. Then, the generation unit 312 outputs pll_cntl_scale to the clock adjustment module 302 for further adjustment of the division coefficient.

[0063] Therefore, when the audio playback ends ahead of or behind the system timing clock, a first frequency division coefficient is generated for adjusting the playback speed of the audio playback clock, which improves the reliability and specificity of the adjustment.

[0064] Next, step 202 is executed to adjust the mapping reference value based on the first frequency division coefficient and the reference frequency division coefficient.

[0065] In an exemplary embodiment, step 202 includes: in response to a first division factor being greater than a reference division factor, decreasing the mapping reference value to obtain an adjusted mapping reference value; and in response to a first division factor being less than a reference division factor, increasing the mapping reference value to obtain an adjusted mapping reference value.

[0066] For example, after obtaining the first division coefficient pll_cntl_scale and the reference division coefficient r_global_scale, the clock adjustment module 302 compares the two to determine their magnitude relationship. If pll_cntl_scale > r_global_scale, indicating that the clock needs to be slowed down, the third flag signal level_cond, indicating whether the clock needs to be slowed down or sped up, is assigned a fourth value (e.g., 01). If pll_cntl_scale < r_global_scale, indicating that the clock needs to be sped up, the level_cond signal is assigned a fifth value (different from the fourth value, e.g., 10). When level_cond is 01, the mapping reference value cur_level is decreased by a second preset value; when level_cond is 10, the mapping reference value cur_level is increased by a second preset value. The initial value of cur_level is 16.

[0067] The second preset value can be a value given in advance by the software, such as 1 or 2. The second preset value may be the same as or different from the first preset value.

[0068] Thus, by increasing or decreasing the second preset value of the mapping reference value, the mapping reference value is adjusted, ensuring the reliability of the adjustment and enabling it to represent whether the clock needs to be slowed down or sped up.

[0069] In one exemplary embodiment, such as Figure 4 As shown, step 203, which involves determining the second frequency division coefficient of the audio playback clock based on the adjusted mapping reference value, includes steps 401 and 402. Wherein:

[0070] Step 401: Determine the selection signal and the target playback clock cycle corresponding to the selection signal based on the preset mapping relationship and the adjusted mapping reference value.

[0071] The selection signal refers to the signal that indicates whether the audio playback clock needs to be slowed down or sped up. The specific value is set and stored in advance, and can be obtained when needed through the mapping relationship.

[0072] The preset mapping relationship includes the correspondence between the selection signal, the mapping reference value, and at least one playback clock cycle in each set of playback clock cycles. The selection signal has two distinct values, such as 10 (indicating slower playback speed) and 01 (indicating faster playback speed). Each selection signal value corresponds to a mapping reference value and at least one playback clock cycle. `Cur_level` is updated every preset period `vco_pll_latch`. Within the interval where the `cur_level` signal is not updated, multiple sets of playback clock cycles are included, each set containing multiple playback clock cycles, for example, 16 playback clock cycles per set. These multiple sets of playback clock cycles are counted using a counter. Optionally, the preset mapping relationship can be in the form of a table as shown in Table 1. Referring to Table 1, cul_level determines the corresponding selection signal pre_sel when the counter counts to which number (i.e., which playback clock cycle). For example, if cul_level=19, within each playback clock cycle, when the counter counts to the 4th, 9th, and 14th playback clock cycles, pre_sel=10, indicating that the playback clock needs to be sped up; when the counter counts to other values, pre_sel=00, indicating that the playback clock remains unchanged.

[0073] Table 1 Preset Mapping Relationship Table

[0074]

[0075] The preset period vco_pll_latch can be set in advance based on requirements and experience, and configured through software. Optionally, taking a playback clock of 24.576MHz as an example, the counter will generate the total period based on the playback clock of 128 clock cycles and the corresponding ratio set by the software, thus obtaining vco_pll_cntl_latch.

[0076] For example, the adjusted mapping reference value Cur_level is used to find the corresponding selection signal pre_sel and the target playback clock cycle corresponding to pre_sel in Table 1. For instance, when Cur_level is adjusted to 17, the corresponding pre_sel is 10 and the target clock cycle is 8, which means that within the range where Cur_level remains unchanged, the playback clock needs to be sped up in the 8th clock cycle of each set of playback clock cycles within that range, while remaining unchanged in other clock cycles.

[0077] In other words, a selection signal pre_sel is obtained by mapping Cur_level to the playback clock cycle. When the first division factor is greater than the reference division factor, the selection signal is the sixth value, such as 01; when the first division factor is less than the reference division factor, the selection signal is the seventh value, such as 10.

[0078] Step 402: Adjust the reference division coefficient according to the selection signal to obtain the second division coefficient within the target playback clock cycle corresponding to the selection signal.

[0079] Further, the step includes: in response to the first division factor being greater than the reference division factor, increasing the reference division factor to obtain a second division factor within the target playback clock cycle corresponding to the selection signal; and in response to the first division factor being less than the reference division factor, decreasing the reference division factor to obtain a second division factor within the target playback clock cycle corresponding to the selection signal.

[0080] For example, for each target playback clock cycle, the reference division coefficient r_global_scale is calculated by adding or subtracting based on the selection signal pre_sel to obtain the second division coefficient for that target playback clock cycle. Optionally, as... Figure 5 As shown, the clock adjustment module 302 includes a 3-to-1 selector 501 and a 2-to-1 selector 502. The selection signal pre_sel is used as the selection terminal of the 3-to-1 selector 501. When pre_sel=00, the 3-to-1 selector 501 outputs r_global_scale, which is the default value of the frequency division coefficient of the audio playback clock. When pre_sel=10, r_global_scale is subtracted by a fixed value minus (usually 1) and then output to the output terminal of the selector 501. This fixed value is configured in advance by software. When pre_sel=01, r_global_scale is added by a fixed value plus and then output to the output terminal of the selector 501. This fixed value is configured in advance by software.

[0081] Reference Figure 5 The second division factor output by the three-to-one selector 501 and the reference division factor r_global_scale are then passed through a two-to-one selector 502. The start_up signal of the selector indicates whether the synchronization function is enabled. Its value can be 0 or 1. 0 means that the synchronization function is not enabled, so r_global_scale is output; 1 means that the synchronization function is enabled, so the second division factor is output, i.e. r_global_scale+plus or r_global_scale+minus.

[0082] Therefore, this example demonstrates how to increase or decrease the reference division factor in steps based on the selection signal within each target playback clock cycle. This ensures the reliability and accuracy of the division factor, avoiding poor synchronization caused by inaccurate division factors. Furthermore, by using a 3-to-1 selector and a 2-to-1 selector, not only is the division factor generated, but flexibility is also improved, allowing the synchronization function to be promptly disabled when synchronization is not appropriate.

[0083] After obtaining the second division factor (r_global_scale+plus or r_global_scale+minus), the next segment of audio data is controlled based on it to synchronize the playback of the audio data.

[0084] In one exemplary embodiment, such as Figure 6 As shown, step 204 controls the playback of the next segment of audio data based on the second frequency division coefficient, including step 601:

[0085] Step 601: Determine the target frequency of the audio playback clock based on the preset frequency and the second frequency division coefficient, and control the playback of the next segment of audio data based on the target frequency.

[0086] For example, the clock adjustment module obtains a preset frequency, divides it by a second frequency division factor to obtain a target frequency, that is, the ratio of the preset frequency to the second frequency division factor is used as the target frequency of the audio playback clock, and outputs it to the audio playback module so that it plays the next segment of audio data according to the target frequency.

[0087] Therefore, by using historical audio data, the playback time of the next audio segment is synchronized with the system clock, thus eliminating the bad user experience caused by audio desynchronization.

[0088] The methods of this application are described below through two specific examples.

[0089] In a specific example, such as Figure 7 As shown, when the playback of historical audio data precedes the system timing clock, the audio data synchronization method includes the following steps:

[0090] Step 701: In response to the fact that the sum of the absolute values ​​of the differences between the playback end time of multiple historical audio data and the system timing clock reaches a preset threshold and the difference is greater than 0, the reference frequency division coefficient r_global_scale is increased by a first preset value to obtain the first frequency division coefficient pll_cntl_scale.

[0091] Step 702: In response to pll_cntl_scale being greater than r_global_scale, the mapping baseline value is reduced by the second preset value to obtain the adjusted mapping baseline value cur_level;

[0092] Step 703: Determine the selection signal pre_sel and the target playback clock cycle corresponding to pre_sel based on the preset mapping relationship and cur_level;

[0093] Step 704: In response to the first division factor being greater than the reference division factor, increase r_global_scale by a fixed value to obtain the second division factor within the target playback clock cycle corresponding to pre_sel;

[0094] Step 705: The ratio of the preset frequency to the second frequency division coefficient within the target playback clock cycle is used as the target frequency of the audio playback clock, and the playback of the next segment of audio data is controlled according to the target frequency to slow down the playback speed.

[0095] In another specific example, such as Figure 8 As shown, when the playback of historical audio data lags behind the system timing clock, the audio data synchronization method includes the following steps:

[0096] Step 801: In response to the fact that the sum of the absolute values ​​of the differences between the playback end time of multiple historical audio data and the system timing clock reaches a preset threshold and the difference is less than 0, the reference frequency division coefficient r_global_scale is reduced by a first preset value to obtain the first frequency division coefficient pll_cntl_scale.

[0097] Step 802: In response to pll_cntl_scale being less than r_global_scale, the mapping reference value is increased by the second preset value to obtain the adjusted mapping reference value cur_level;

[0098] Step 803: Determine the selection signal pre_sel and the target playback clock cycle corresponding to pre_sel based on the preset mapping relationship and cur_level;

[0099] Step 804: In response to the first division factor being less than the reference division factor, r_global_scale is reduced by a fixed value to obtain the second division factor within the target playback clock cycle corresponding to pre_sel;

[0100] Step 805: The ratio of the preset frequency to the second frequency division coefficient within the target playback clock cycle is used as the target frequency of the audio playback clock, and the playback of the next segment of audio data is controlled according to the target frequency to speed up the playback.

[0101] The above method can be implemented using devices such as chips and chip modules, and can be applied to smart TVs. This technical solution remains consistent across different product types.

[0102] In summary, the embodiments of this application enable the setting of an audio data synchronization scheme in a smart TV. By adjusting the division factor of the audio playback clock, the playback speed of the audio data is adjusted. When playback is too fast, the playback speed is increased by adjusting the division factor; when playback is too slow, the playback speed is decreased by adjusting the division factor. This achieves audio data synchronization, solves the problem of audio data desynchronization, improves audio playback quality, and enhances the user experience.

[0103] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0104] Based on the same inventive concept, this application also provides an audio data synchronization device for implementing the audio data synchronization method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more audio data synchronization device embodiments provided below can be found in the limitations of the audio data synchronization method described above, and will not be repeated here.

[0105] In one exemplary embodiment, such as Figure 9 As shown, an audio data synchronization device is provided, comprising: a first determining module 901, a second determining module 902, a third determining module 903, and a control module 904, wherein:

[0106] The first determining module 901 is used to determine the first frequency division coefficient of the audio playback clock based on the reference frequency division coefficient when the cumulative value of the absolute value of the difference between the playback end time of multiple historical audio data and the system timing clock reaches a preset threshold.

[0107] The second determining module 902 is used to adjust the mapping reference value based on the first frequency division coefficient and the reference frequency division coefficient;

[0108] The third determining module 903 is used to determine the second frequency division of the audio playback clock based on the adjusted mapping reference value;

[0109] The control module 904 is used to control the playback of the next segment of audio data based on the second frequency division coefficient.

[0110] In one embodiment, the second determining module 902 includes a first increasing unit and a first decreasing unit, wherein:

[0111] The first reduction unit is configured to reduce the mapping reference value to obtain an adjusted mapping reference value in response to the first frequency division coefficient being greater than the reference frequency division coefficient.

[0112] The first amplification unit is used to increase the mapping reference value to obtain an adjusted mapping reference value in response to the first division coefficient being less than the reference division coefficient.

[0113] In one embodiment, the third determining module 903 includes a determining unit and an adjusting unit, wherein:

[0114] The determining unit is configured to determine the selection signal and the target playback clock cycle corresponding to the selection signal based on the preset mapping relationship and the adjusted mapping reference value, wherein the preset mapping relationship includes the correspondence between the selection signal, the mapping reference value and at least one playback clock cycle in each group of playback clock cycles;

[0115] An adjustment unit is used to adjust the reference frequency division coefficient according to the selection signal to obtain a second frequency division coefficient within the target playback clock cycle corresponding to the selection signal.

[0116] Furthermore, the adjustment unit is specifically used for:

[0117] In response to the first division factor being greater than the reference division factor, the reference division factor is increased to obtain the second division factor within the target playback clock cycle corresponding to the selection signal;

[0118] In response to the first division factor being less than the reference division factor, the reference division factor is reduced to obtain the second division factor within the target playback clock cycle corresponding to the selection signal.

[0119] In one embodiment, the control module 904 is specifically configured to: determine the target frequency of the audio playback clock based on the preset frequency of the audio playback clock and the second frequency division coefficient, and control the playback of the next segment of audio data based on the target frequency.

[0120] In one embodiment, the first determining module 901 includes a second increasing unit and a second decreasing unit, wherein:

[0121] The second amplification unit is used to increase the reference frequency division coefficient to obtain the first frequency division coefficient in response to the difference being greater than the first value.

[0122] The first reduction unit is used to reduce the reference frequency division coefficient to obtain a first frequency division coefficient in response to the difference being less than a first value.

[0123] The aforementioned device can take the form of a chip, chip module, or other similar product, and can be applied to smart TVs. This technical solution remains consistent regardless of the type of product it is applied to.

[0124] Each module in the aforementioned audio data synchronization device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0125] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0126] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 10As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores data required for audio data synchronization. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When executed by the processor, the computer program implements an audio data synchronization method.

[0127] Those skilled in the art will understand that Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0128] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the audio data synchronization method proposed in the above embodiments of this application.

[0129] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the audio data synchronization method proposed in the above embodiments of this application.

[0130] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the audio data synchronization method proposed in the above embodiments of this application.

[0131] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0132] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0133] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method of synchronizing audio data, characterized by, The method comprises: in response to an accumulated value of absolute values of differences between ending time of playing of a plurality of historical audio data and a system timing clock reaching a preset threshold, determining a first frequency division coefficient of an audio playing clock based on a reference frequency division coefficient; adjusting a mapping reference value based on the first frequency division coefficient and the reference frequency division coefficient; determining a second frequency division coefficient of the audio playing clock according to the adjusted mapping reference value; controlling playing of next audio data based on the second frequency division coefficient.

2. The method of claim 1, wherein, The adjusting of the mapping reference value based on the first frequency division coefficient and the reference frequency division coefficient comprises: in response to the first frequency division coefficient being greater than the reference frequency division coefficient, decreasing the mapping reference value to obtain an adjusted mapping reference value; in response to the first frequency division coefficient being less than the reference frequency division coefficient, increasing the mapping reference value to obtain an adjusted mapping reference value.

3. The method of claim 1, wherein, The determining of the second frequency division coefficient of the audio playing clock according to the adjusted mapping reference value comprises: determining a selection signal and a target playing clock period corresponding to the selection signal according to a preset mapping relationship and the adjusted mapping reference value, wherein the preset mapping relationship comprises a corresponding relationship between the selection signal, the mapping reference value and at least one playing clock period in each group of playing clock periods; adjusting the reference frequency division coefficient according to the selection signal to obtain the second frequency division coefficient in the target playing clock period corresponding to the selection signal.

4. The method of claim 3, wherein, The adjusting of the reference frequency division coefficient according to the selection signal to obtain the second frequency division coefficient in the target playing clock period corresponding to the selection signal comprises: in response to the first frequency division coefficient being greater than the reference frequency division coefficient, increasing the reference frequency division coefficient to obtain the second frequency division coefficient in the target playing clock period corresponding to the selection signal; in response to the first frequency division coefficient being less than the reference frequency division coefficient, decreasing the reference frequency division coefficient to obtain the second frequency division coefficient in the target playing clock period corresponding to the selection signal.

5. The method according to any one of claims 1 to 4, characterized in that, The controlling of the playing of next audio data based on the second frequency division coefficient comprises: determining a target frequency of the audio playing clock according to a preset frequency of the audio playing clock and the second frequency division coefficient, and controlling the playing of next audio data according to the target frequency.

6. The method according to claims 1-4, characterized in that, The determining of the first frequency division coefficient of the audio playing clock based on the reference frequency division coefficient comprises: in response to the difference being greater than a first value, increasing the reference frequency division coefficient to obtain the first frequency division coefficient; in response to the difference being less than the first value, decreasing the reference frequency division coefficient to obtain the first frequency division coefficient.

7. An apparatus for synchronizing audio data, characterized by comprising: The device comprises: a first determining module configured to determine a first frequency division coefficient of an audio playing clock based on a reference frequency division coefficient in response to an accumulated value of absolute values of differences between ending time of playing of a plurality of historical audio data and a system timing clock reaching a preset threshold; a second determining module configured to adjust a mapping reference value based on the first frequency division coefficient and the reference frequency division coefficient; a third determining module configured to determine a second frequency division of the audio playing clock according to the adjusted mapping reference value; a control module configured to control playing of next audio data based on the second frequency division coefficient.

8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 6.

9. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 6.

10. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 6.

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