Optical module access method and device and storage medium

Abstract

The invention discloses an optical module access method and device and a storage medium, and the method comprises the steps: distributing an address for each optical module, and synchronizing the address distributed by each module to a connected processor; the receiving processor determines an operation instruction based on the in-place state and the address of each optical module, and analyzes the operation instruction to obtain a target optical module and operation information; and screening out a target IIC interface connected with the target optical module from the shared IIC interfaces, and sending the operation information to the target optical module through the target IIC interface so as to access the target optical module. An optical module assembly comprising a plurality of optical modules is in matrix interconnection with a CPLD (Complex Programmable Logic Device) through a shared IIC (Inter-Integrated Circuit) interface, an operation instruction sent by a processor is analyzed through the CPLD to determine a target module needing to be accessed and operation information, and the operation information is sent to the target module, so that fewer IIC interfaces are adopted to access a plurality of target modules, and the access efficiency is improved. And the material cost of the IIC interface and the IO resources of the CPLD are reduced.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a method, apparatus and storage medium for accessing an optical module. Background Technology

[0002] With the rapid development of communication technology, interface chips are facing increasingly higher requirements for speed, efficiency, and miniaturization, leading to a higher utilization rate of optical modules. The Inter-Integrated Circuit (IIC) interface, as the management interface for optical modules, is responsible for information querying and parameter configuration. Processors typically access optical modules through the IIC interface. Currently, optical modules of the same model from the same manufacturer share the same IIC address, making it impossible to achieve multi-module access communication via the IIC bus.

[0003] To address the aforementioned issues, existing technologies have proposed adding an IIC interface chip to enable direct processor access to multiple optical modules. However, this approach increases material costs and printed circuit board layout space. Another approach involves adding a Complex Programmable Logic Device (CPLD), through which the processor achieves point-to-point optical module access. However, this method wastes a significant amount of CPLD I / O resources. Summary of the Invention

[0004] This invention provides a method, apparatus, device, and storage medium for accessing optical modules, enabling access to optical modules while saving material costs and CPLD I / O resources.

[0005] According to a first aspect of this invention, a method for accessing an optical module is provided, applied to a complex programmable logic device (CPLD), the method comprising:

[0006] The on-site status of each optical module in the optical module network is saved to a local register. The optical module network is interconnected with the CPLD in a matrix manner through a shared IIC interface, and the number of shared IIC interfaces is less than the number of optical modules in the optical module network.

[0007] An address is assigned to each optical module, and the address assigned to each module is synchronized to the connected processor;

[0008] The receiving processor determines the operation instruction based on the presence status and address of each optical module, and parses the operation instruction to obtain the target optical module and operation information;

[0009] Filtering a target IIC interface connecting the target optical module from the shared IIC interfaces, and sending the operation information to the target optical module through the target IIC interface to access the target optical module.

[0010] According to another aspect of the present application, there is provided an access device of an optical module, comprising: an in-place state saving module for saving in-place states of optical modules in an optical module network into local registers, wherein the optical module network is interconnected with a CPLD in a matrix manner through shared IIC interfaces, and the number of the shared IIC interfaces is less than the number of the optical modules in the optical module network;

[0011] An address allocation module for allocating an address to each of the optical modules and synchronizing the allocated addresses of the modules to the connected processor;

[0012] An operation instruction analysis module for receiving an operation instruction determined by the processor based on the in-place states and the addresses of the optical modules, and analyzing the operation instruction to obtain a target optical module and operation information;

[0013] An optical module access module for filtering a target IIC interface connecting the target optical module from the shared IIC interfaces, and sending the operation information to the target optical module through the target IIC interface to access the target optical module.

[0014] According to another aspect of the present application, there is provided a terminal device, comprising: one or more processors;

[0015] A storage device for storing one or more programs,

[0016] When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any of the embodiments of the present application.

[0017] According to another aspect of the present application, there is provided a storage medium of computer executable instructions, which stores a computer program, and the program is executed by a processor to implement the method according to any of the embodiments of the present application.

[0018] The technical solution of the present application connects an optical module assembly comprising a plurality of optical modules with a CPLD in a matrix manner through shared IIC interfaces, synchronizes related information of the optical modules to a processor through the CPLD, analyzes an operation instruction sent by the processor to determine a target module to be accessed and operation information, sends the operation information to the target module through a target IIC interface determined from the shared IIC interfaces, thereby achieving access to a plurality of target modules using fewer IIC interfaces, and reducing the material cost of the IIC interfaces and the IO resources of the CPLD.

[0019] It should be understood that the matters described in this detailed description are intended to be illustrative and are not intended to limit or restrict the scope of the embodiments of the present application. Other characteristics, features and advantages of the present application will become apparent from the following detailed description, from the appended claims, and from the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0021] Figure 1 is a flow chart of an access method of an optical module according to the first embodiment of the present application;

[0022] Figure 2 is a schematic diagram of an access application scenario of an optical module according to the first embodiment of the present application;

[0023] Figure 3 is a flow chart of an access method of an optical module according to the second embodiment of the present application;

[0024] Figure 4 is a structural schematic diagram of an access device of an optical module according to the third embodiment of the present application;

[0025] Figure 5 is a structural block diagram of a terminal device according to the fourth embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the technical personnel in the art better understand the present application scheme, the technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0027] It is to be understood that the terminology "first", "second" and the like used throughout this specification and the annexed drawings is merely intended to distinguish between similar objects and not to imply a specific order or sequence. It is to be understood that the data used herein can be interchanged, where appropriate, without departing from the scope of the embodiments of the application described herein. Furthermore, "including", "containing" and "having" and any variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, product or terminal device that comprises, includes or has a list of steps or units is not necessarily limited to those specifically listed and can include other steps or units not expressly listed or inherent to such process, method, article, product or terminal device.

[0028] Embodiment one

[0029] Figure 1 A flowchart of an access method of an optical module is provided for an embodiment of the application. The embodiment can be applied to the case of accessing an optical module. The method can be executed by an access device of an optical module. The device can be realized in the form of hardware and / or software. The device can be integrated into a terminal device. As shown in Figure 1 the method comprises:

[0030] In step S101, the in-situ states of the optical modules in the optical module network are saved into the local register.

[0031] Optionally, saving the in-situ states of the optical modules in the optical module network into the local register comprises: obtaining the in-situ states of the optical modules through the in-situ interfaces corresponding to the optical modules, wherein the in-situ states include in-situ or not in-situ; selecting the local register for recording the in-situ states from the current chip, and obtaining the available capacity of the local register and the occupied capacity of the in-situ states of all the optical modules; when the occupied capacity is less than the available capacity, the in-situ states of the optical modules in the optical module network are saved into the local register.

[0032] In step S102, the in-situ states of the optical modules in the optical module network are saved into the local register. Figure 2An access application scenario diagram of the optical module provided by the embodiment is shown. As shown in the figure, the processor CPU in the embodiment is connected to the CPLD through the IIC interface, which specifically includes a data line (Serial Data, SDA) and a clock line (Serial Clock Line, SCL). A plurality of optical modules form an optical module network. In the embodiment, 16 optical modules are taken as an example for description, and the optical module network is in the form of a grid. Each optical module is a node in the grid. Of course, the embodiment is only taken as an example for description, and the specific form of the optical module network is not limited. Figure 2 The IIC interface includes four data lines SDA1-SDA4 and four clock lines SCL1-SCL2, and the data lines and the clock lines are used as shared IIC interfaces. Each shared interface is specifically composed of one data line and one clock line. Since the actual shared IIC interfaces are only four, the connection between the CPLD and the plurality of optical modules can be achieved through different combinations of internal data lines and clock lines. For example, the IIC interface obtained by combining SCL1 and SDA1 can achieve the connection between the CPLD and the optical module 1, and the IIC interface obtained by combining SCL2 and SDA1 can achieve the connection between the CPLD and the optical module 2. Therefore, only four shared IIC interfaces are needed in the embodiment to achieve the connection with 16 optical modules. Compared with the 16 IIC interfaces required by the point-to-point IIC communication of the CPLD in the prior art, the number of IIC interfaces is obviously reduced. Only one IIC interface is needed between the processor and the CPLD to interconnect with the CPLD, so that the processor can access different optical modules. Therefore, the total number of IIC interface chips and the physical cost are significantly reduced. Of course, the embodiment is only taken as an example for description, and the number of optical modules included in the optical module network and the number of IIC interfaces used when the optical module network is interconnected with the CPLD in a matrix form are not limited. As long as the number of shared IIC interfaces is less than the number of optical modules, it is within the protection scope of the application.

[0033] Specifically, each optical module in the optical module networking will also be connected with the CPLD through the in-place interface, and when the optical module is connected, the in-place signal will be sent to the CPLD through the in-place interface, and the CPLD determines the in-place state of the optical module based on the in-place signal. For example, for optical module 1, when the in-place signal sent by the optical module 1 through the in-place interface is determined, the in-place state of the optical module is updated to in-place, and is recorded in the local register, such as SFP_Present[0:15]. When the in-place signal sent by the optical module 1 is not received, the in-place state of the optical module 1 is always recorded in the local register as not in place, and when the optical module is offline, the offline signal will be automatically triggered to be sent to the CPLD through the connected in-place port, so that the CPLD updates the in-place state of the optical module to not in place. Therefore, through the in-place interface, the CPLD can realize real-time acquisition and update of the in-place state of each optical module. Of course, in the present embodiment, only the in-place state of the optical module recorded in the local register is taken as an example for description, and the recording method of the in-place state of other optical modules is substantially the same. Therefore, the present embodiment will not be described in detail.

[0034] Optionally, the method further comprises: when the occupied capacity is greater than the available capacity, determining a replacement register from the current chip, wherein the replacement register is a reserved available register in the chip; and saving the in-place state of each optical module in the optical module networking into the replacement register.

[0035] It should be noted that since the current chip includes a plurality of registers, and a certain memory is occupied to record the state of each optical module, in the present embodiment, the available capacity of each register in the chip is obtained, and the occupied capacity of the optical module in-place state is compared with the available capacity. Any optical module with available capacity greater than occupied capacity is selected as the local register for recording the in-place state of the optical module. Of course, in the present embodiment, only an example is given, and the selection method of the local register is not limited. In the present embodiment, a register with a very large available capacity is selected as a replacement register. The replacement register is usually not used for other tasks, but in the case where the occupied capacity of the current chip is greater than the available capacity, the in-place state is saved to the replacement register. Of course, in the present embodiment, only an example is given, and the specific storage location of the in-place state is not limited.

[0036] Step S102, allocate an address for each optical module, and synchronize the address allocated to each module to the connected processor.

[0037] Optionally, after synchronizing the addresses of the modules to the connected processor, the method further comprises: receiving a state reading instruction sent by the processor, wherein the state reading instruction comprises a target address; determining the target optical module according to the target address, and querying the in-place state of the target optical module from the local register; feeding back the in-place state of the target optical module to the processor, and displaying the in-place state on the human-computer interaction interface through the processor, so that the processor receives operation information input by a user based on the in-place state.

[0038] Specifically, since the original addresses of optical modules of the same type from the same manufacturer are the same and cannot be effectively identified, the CPLD allocates new addresses to each optical module in the optical module network, and the addresses allocated to the optical modules are different, so that effective identification of the optical modules can be achieved based on the addresses. In addition, after completing the address allocation of the optical modules, the CPLD synchronizes the addresses of the allocated optical modules to the processor, so that the processor records the addresses of the optical modules.

[0039] It should be noted that, before accessing the optical modules in the optical module network, the processor needs to determine whether the accessed optical module is in place, so as to avoid invalid occupation of analysis and calculation resources caused by sending operation instructions but the access object not existing. Therefore, when the processor needs to access a target optical module, a state reading instruction is generated. Since the target address of the accessed target optical module is included in the state reading instruction, the CPLD queries the in-place state of the target optical module from the local register or the above-mentioned alternative register according to the target address after receiving the state reading instruction. When the in-place state of the target optical module is determined, the in-place state is directly fed back to the processor, and the in-place state is displayed on the human-computer interaction interface through the processor. When the in-place state is not in place, the processor directly suspends the subsequent access process of the target optical module. When the in-place state is in place, the processor continues to perform the subsequent access process of the target optical module.

[0040] In step S103, the processor determines an operation instruction based on the in-place state and the address of each optical module, and analyzes the operation instruction to obtain a target optical module and operation information.

[0041] Optionally, analyzing the operation instruction to obtain a target optical module and operation information comprises: extracting a target address and operation information contained in the operation instruction; querying the target optical module from the local register according to the target address.

[0042] Specifically, in the case that the in-place state of the target optical module is determined to exist, the processor receives operation information input by a user when the user accesses the target optical module, wherein the operation information can include write information, read information, or query information, and the specific content of the operation information is not limited in the embodiment. Since the addresses allocated to the modules have been synchronized to the processor, the processor combines the target address of the target module and the operation information to generate an operation instruction, and sends the operation instruction to the CPLD. The operation instruction can be encoded and encrypted in a predetermined manner after being obtained, and is sent through a wired or wireless manner, so as to ensure the security of the operation instruction in the transmission process. Of course, the embodiment only illustrates the operation instruction obtaining manner and sending manner, and the specific operation instruction obtaining manner and sending manner are not limited.

[0043] It should be noted that the CPLD receives the operation instruction and analyzes the operation instruction as a processor agent. The specific operation includes decryption, decoding, and extraction, for example, the operation instruction is decrypted in a predetermined decryption manner, and the decrypted operation instruction is decoded to obtain the plaintext operation instruction generated by the processor initially. At this time, the target address and the operation information are restored by extracting information from the operation instruction. Since the addresses allocated to the optical modules are saved in the local register of the CPLD, the CPLD can query the target address from the local register to obtain the target optical module to be accessed, for example, the target optical module is optical module 1, and the serial number of the target optical module is not limited in the embodiment. The extracted operation information is read information, that is, the data saved in the target optical module is read.

[0044] Step S104: filtering out a target IIC interface connected to the target optical module from the shared IIC interface, and sending the operation information to the target optical module through the target IIC interface to access the target optical module.

[0045] Optionally, filtering out the target IIC interface connected to the target optical module from the shared IIC interface includes: filtering out a target data line and a target clock line directly connected to the target optical module from the shared IIC interface; and taking the target data line and the target clock as the target IIC interface.

[0046] It should be noted that after the target optical module is determined and the operation information is determined in the embodiment, the operation information is sent to the target optical module. Since the CPLD is connected to the optical module network in a matrix manner through a plurality of shared IIC interfaces, the CPLD and each module in the optical module network are connected through different IIC interfaces. Therefore, in the embodiment, the target IIC interface is determined according to the structure of the optical module network and the matrix connection relationship of the shared IIC interfaces.

[0047] In one specific implementation, when the target optical module is the optical module 1, the operation information is sent to the optical module 1 through the target IIC interface according to Figure 2 It can be learned that the data line connected to the optical module 1 by the CPLD is SDA1, and the clock line is SCL1. Therefore, the IIC interface formed by the data line SDA1 and the clock line SCL1 is used as the target IIC interface. The operation information is sent to the optical module 1 through the target IIC interface, so as to read the data in the optical module 1. After the data in the optical module 1 is read, the CPLD feeds back the access data to the processor as a proxy. Before the feedback, the CPLD encodes and encrypts the access data to ensure the safety of the data transmission process. The encoding and encryption methods are the same as those of the processor, which will not be described herein. When the target optical module is the optical module 5, the operation information is sent to the optical module 5 through the target IIC interface according to Figure 2 It can be learned that the data line connected to the optical module 5 by the CPLD is SDA1, and the clock line is SCL2. Therefore, the IIC interface formed by the data line SDA1 and the clock line SCL2 is used as the target IIC interface. It can be learned that the same data line is used when the CPLD sends the operation information to the optical module 1 and the optical module 2 as a proxy, that is, the data line is shared by different optical modules in the optical module network. Similarly, the clock line is also shared by different optical modules in the optical module network. For the optical modules using the same shared IIC interface, the CPLD sends the operation information in time sequence to avoid sending conflicts. For example, when the optical module 1 and the optical module 5 are the target optical modules at the same time, the operation information is sent to the optical module 1 first and then to the optical module 5. Of course, the sending time sequence is only used as an example in the embodiment, and is not limited.

[0048] In the embodiment, the programmable logic device CPLD is used to manage a plurality of optical modules without adding an IIC interface expansion device. Compared with the point-to-point management scheme, the hardware and IO resources are saved, and the advantage is more obvious as the number of optical modules increases. Therefore, the I2C interface is expanded through the CPLD IO matrix interconnection, without adding an IIC expansion interface material, thereby saving the material cost. Compared with the existing point-to-point scheme, the CPLD IO resources are saved through the CPLD IO matrix interconnection.

[0049] The technical scheme of the embodiment of the application realizes the matrix interconnection of the optical module assembly containing multiple optical modules through the shared IIC interface and the CPLD, synchronizes the related information of the optical modules to the processor through the CPLD, analyzes the operation instruction sent by the processor to determine the target module and the operation information that need to be accessed, and sends the operation information to the target module through the target IIC interface determined from the shared IIC interface, so that the access of multiple target modules is realized by using fewer IIC interfaces, and the material cost of the IIC interface and the IO resource of the CPLD are reduced.

[0050] Embodiment two

[0051] Figure 3 is a flowchart of an optical module access method provided by the embodiment of the application, and the embodiment is based on the above-described embodiment and further includes the following steps after the target IIC interface connected to the target optical module is screened out from the shared IIC interface: acquiring the remaining shared IIC interfaces after screening, and setting the working state of the remaining shared IIC interfaces to the high configuration to block the access of the processor to the remaining optical modules in the optical module networking. The method includes the following steps.

[0052] In step S201, the in-place states of the optical modules in the optical module networking are saved into the local register.

[0053] Optionally, the saving of the in-place states of the optical modules in the optical module networking into the local register includes the following steps: acquiring the in-place states of the optical modules through the in-place interfaces corresponding to the optical modules, wherein the in-place state includes in place or not in place; screening out the local register used to record the in-place states from the current chip, and acquiring the available capacity of the local register and the occupied capacity of the in-place states of all the optical modules; when the occupied capacity is less than the available capacity, the in-place states of the optical modules in the optical module networking are saved into the local register.

[0054] Optionally, the method further includes the following steps: when the occupied capacity is greater than the available capacity, a replacement register is determined from the current chip, wherein the replacement register is a reserved available register in the chip; and the in-place states of the optical modules in the optical module networking are saved into the replacement register.

[0055] In step S202, an address is allocated to each optical module, and the addresses allocated to the modules are synchronized to the connected processor.

[0056] Optionally, after synchronizing the addresses of the modules to the connected processor, the method further comprises: receiving a state reading instruction sent by the processor, wherein the state reading instruction comprises a target address; determining a target optical module according to the target address, and querying the in-place state of the target optical module from the local register; feeding back the in-place state of the target optical module to the processor, and displaying the in-place state on a human-computer interaction interface through the processor, so that the processor receives operation information input by a user based on the in-place state.

[0057] In step S203, the processor determines an operation instruction based on the in-place state and the address of each optical module, and parses the operation instruction to obtain a target optical module and operation information.

[0058] Optionally, parsing the operation instruction to obtain the target optical module and the operation information comprises: extracting the target address and the operation information contained in the operation instruction; and querying the target optical module from the local register according to the target address.

[0059] In step S204, a target IIC interface connected to the target optical module is filtered out from the shared IIC interfaces, and the operation information is sent to the target optical module through the target IIC interface to access the target optical module.

[0060] Optionally, filtering out the target IIC interface connected to the target optical module from the shared IIC interfaces comprises: filtering out a target data line and a target clock line directly connected to the target optical module from the shared IIC interfaces; and taking the target data line and the target clock as the target IIC interface.

[0061] In step S205, the remaining shared IIC interfaces are obtained, and the working state of the remaining shared IIC interfaces is set to a high state to block the processor from accessing the remaining optical modules in the optical module network.

[0062] Specifically, in the embodiment, after the target IIC interface connected to the target optical module is determined, there are still shared IIC interfaces that do not need to perform data transmission in the shared IIC interfaces. In order to avoid the operation information sent to the target optical module being sent to other optical modules in the optical module network, the working state of the remaining shared IIC interfaces can be set to a high impedance state. The shared IIC interfaces in the high state no longer perform information transmission, and the power consumption is reduced, so that the operation information sent to the target optical module can only be transmitted through the target IIC interface, and the remaining shared IIC interfaces are in a blocked information state, thereby ensuring that the power consumption is reduced while the accurate transmission of the operation information is realized.

[0063] It is worth mentioning that, in the embodiment, when the CPLD receives the access information fed back by the target optical module, it is determined that the access to the target optical module is ended, at which time the working state of the remaining shared IIC interface is switched to the non-high configuration, thereby ensuring the accurate sending of subsequent operation information.

[0064] It should be noted that, in the case of access failure, for example, the access information received by the CPLD is incorrect, at which time the CPLD generates an access failure prompt and feeds back the access failure prompt to each processor through the IIC interface, and the processor re-sends the operation instruction, and when the number of access failures exceeds a specified value, an alarm prompt is generated to prompt the user that the current access is abnormal, thereby facilitating the user to detect the hardware device or software unit in time, repair according to the detection result, and save the repair log locally, so that when the same fault occurs again subsequently, automatic repair can be performed based on the repair strategy saved in the repair log, thereby improving the efficiency and accuracy of fault repair.

[0065] The technical scheme of the embodiment of the application realizes the matrix interconnection of the optical module assembly containing a plurality of optical modules with the CPLD through the shared IIC interface, synchronizes the related information of the optical module to the processor through the CPLD, determines the target module and operation information to be accessed by analyzing the operation instruction sent by the processor, and sends the operation information to the target module through the target IIC interface determined from the shared IIC interface, thereby realizing the access of a plurality of target modules using fewer IIC interfaces, and reducing the material cost of the IIC interface and the IO resource of the CPLD.

[0066] Embodiment three

[0067] Figure 4 A structure diagram of an optical module access device provided by the embodiment of the application is shown in FIG. 1. Figure 4 As shown in the figure, the device includes an in-place state saving module 310, an address allocation module 320, an operation instruction analysis module 330, and an optical module access module 340.

[0068] The in-place state saving module 310 is configured to save the in-place state of each optical module in the optical module network to a local register, wherein the optical module network is interconnected with the CPLD in a matrix manner through a shared IIC interface, and the number of shared IIC interfaces is less than the number of optical modules in the optical module network.

[0069] The address allocation module 320 is configured to allocate an address to each optical module and synchronize the allocated address of each module to the connected processor.

[0070] The operation instruction analysis module 330 is configured to receive an operation instruction determined by the processor based on the in-position state and the address of each optical module, and analyze the operation instruction to obtain a target optical module and operation information;

[0071] The optical module access module 340 is configured to filter a target IIC interface connected to the target optical module from the shared IIC interface, and send the operation information to the target optical module through the target IIC interface to access the target optical module.

[0072] Optionally, the in-position state saving module is configured to obtain the in-position state of each optical module through an in-position interface corresponding to each optical module, wherein the in-position state includes in-position or out-of-position.

[0073] The local register used to record the in-position state is filtered from the current chip, and the available capacity of the local register and the occupied capacity of the in-position state of all optical modules are obtained.

[0074] When the occupied capacity is less than the available capacity, the in-position state of each optical module in the optical module network is saved in the local register.

[0075] Optionally, the in-position state saving module is further configured to determine a replacement register from the current chip when the occupied capacity is greater than the available capacity, wherein the replacement register is a reserved available register in the chip.

[0076] The in-position state of each optical module in the optical module network is saved in the replacement register.

[0077] Optionally, the device further includes an in-position state reading module configured to receive a state reading instruction sent by the processor, wherein the state reading instruction includes a target address.

[0078] The target optical module is determined according to the target address, and the in-position state of the target optical module is queried from the local register.

[0079] The in-position state of the target optical module is fed back to the processor, and the in-position state is displayed on a human-computer interaction interface through the processor, so that the processor receives operation information input by a user based on the in-position state.

[0080] Optionally, the operation instruction analysis module is configured to extract the target address and the operation information contained in the operation instruction.

[0081] The target optical module is obtained by querying the local register according to the target address.

[0082] Optionally, the optical module access module is configured to filter a target data line and a target clock line directly connected to the target optical module from the shared IIC interface.

[0083] The target data line and the target clock are taken as a target IIC interface.

[0084] Optionally, the device further comprises an IIC interface setting module for obtaining the remaining shared IIC interface after the screening.

[0085] The working state of the remaining shared IIC interface is set as a high configuration to block the access of the processor to the remaining optical modules in the optical module networking.

[0086] The access device of the optical module provided in the embodiments of the present application can execute the access method of the optical module provided in any of the embodiments of the present application, and has the corresponding function modules and beneficial effects of the execution method.

[0087] Embodiment four

[0088] Figure 5 A structural schematic diagram of a terminal device 10 that can be used to implement embodiments of the present application is shown. The terminal device is intended to represent various forms of digital computers, such as laptops, desktops, tablets, servers, blade servers, mainframes, and other appropriate computers. The terminal device can also represent various forms of mobile devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not intended to limit implementations of the applications described and / or claimed in this document.

[0089] The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not intended to limit implementations of the applications described and / or claimed in this document.

[0090] As Figure 5 shown, the terminal device 10 includes at least one processor 11, and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., which is communicatively connected to the at least one processor 11, wherein the memory stores a computer program that can be executed by the at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the terminal device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0091] A plurality of components in the terminal device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the terminal device 10 to exchange information / data with other terminal devices through a computer network, such as the Internet, and / or various telecommunication networks.

[0092] The processor 11 can be various general and / or special-purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs various methods and processes described above, such as the access method of the optical module.

[0093] In some embodiments, the access method of the optical module can be implemented as a computer program tangibly embodied in a computer readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed onto the terminal device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded onto the RAM 13 and executed by the processor 11, one or more steps of the access method of the optical module described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to perform the access method of the optical module by any other appropriate means, such as by means of firmware.

[0094] Various implementations of the apparatuses and techniques described above herein can be realized in digital electronic circuit apparatuses, integrated circuit apparatuses, field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system on a chip (SOCs), complex programmable logic terminal devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable apparatus including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage apparatus, at least one input apparatus, and at least one output apparatus.

[0095] A computer program for implementing the access method of the optical module of the present application can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the computer program, when executed by the processor, implements the functions / operations specified in the flowcharts and / or block diagrams. The computer program can be executed in whole on the machine, partially on the machine, partially on the machine as a stand-alone software package, or completely on a remote machine or server.

[0096] In the context of the present application, a computer-readable storage medium can be a tangible medium that can contain or store the computer program for use by or in connection with an instruction execution device, apparatus, or terminal device. A computer-readable storage medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or terminal device, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of a machine-readable storage medium will include one or more lines of a program of instructions in a transitory signal form, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage terminal device, a magnetic storage terminal device, or any suitable combination of the foregoing.

[0097] To provide for interaction with a user, the devices and techniques described here can be implemented on a terminal device having a display device (e.g., a touch screen) for displaying information to the user and a keyboard, a mouse, or a touch screen by which the user can provide input to the terminal device. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0098] It should be understood that the various forms of flow shown above can be re-ordered, added to, or deleted from without departing from the spirit of the present application. For example, the steps recited in the present application can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present application are achieved, which are not limited herein.

[0099] The above detailed description does not limit the scope of the application. Various modifications, combinations, sub-combinations and alternatives can be made to the detailed description. Any modification, equivalent replacement and improvement etc. made within the spirit and principle of the application shall be included in the scope of the application.

Claims

1. A method for accessing an optical module, characterized in that, The method, applied to complex programmable logic devices (CPLDs), includes: The on-site status of each optical module in the optical module network is saved to a local register. The optical module network is interconnected with the CPLD in a matrix manner through a shared IIC interface, and the number of shared IIC interfaces is less than the number of optical modules in the optical module network. An address is assigned to each optical module, and the address assigned to each module is synchronized to the connected processor; The receiving processor determines the operation instruction based on the presence status and address of each optical module, and parses the operation instruction to obtain the target optical module and operation information; The target IIC interface connected to the target optical module is selected from the shared IIC interfaces, and the operation information is sent to the target optical module through the target IIC interface to access the target optical module.

2. The method according to claim 1, characterized in that, The step of saving the on-site status of each optical module in the optical module network to a local register includes: The presence status of each optical module is obtained through the presence interface corresponding to each optical module, wherein the presence status includes whether it is in place or not in place; Select the local registers from the current chip to record the in-situ status, and obtain the available capacity of the local registers and the occupied capacity of all optical modules in-situ status. When the occupied capacity is less than the available capacity, the on-site status of each optical module in the optical module network is saved to the local register.

3. The method according to claim 2, characterized in that, The method further includes: When the occupied capacity is greater than the available capacity, a replacement register is determined from the current chip, wherein the replacement register is an available register that is pre-set and reserved in the chip; The in-situ status of each optical module in the optical module network is saved to the replacement register.

4. The method according to claim 1, characterized in that, After synchronizing the addresses allocated to each module to the connected processor, the process further includes: Receive a status read instruction sent by the processor, wherein the status read instruction includes a target address; The target optical module is determined based on the target address, and the on-site status of the target optical module is queried from the local register; The in-situ status of the target optical module is fed back to the processor, and the in-situ status is displayed on the human-computer interaction interface by the processor, so that the processor can receive the operation information input by the user based on the in-situ status.

5. The method according to claim 1, characterized in that, The step of parsing the operation command to obtain the target optical module and operation information includes: Extract the target address and operation information contained in the operation instruction; The target optical module is obtained by querying the local register based on the target address.

6. The method according to claim 1, characterized in that, The step of selecting the target IIC interface for connecting the target optical module from the shared IIC interfaces includes: Target data lines and target clock lines that are directly connected to the target optical module are selected from the shared IIC interface; The target data line and the target clock are used as the target IIC interface.

7. The method according to claim 1, characterized in that, After selecting the target IIC interface for connecting the target optical module from the shared IIC interfaces, the process further includes: Retrieve the remaining shared IIC interfaces after filtering; The remaining shared IIC interfaces are configured to operate in a high state to block the processor from accessing the remaining optical modules in the optical module network.

8. An access device for an optical module, characterized in that, The device includes: The in-situ status saving module is used to save the in-situ status of each optical module in the optical module network to a local register. The optical module network is interconnected with the CPLD in a matrix manner through a shared IIC interface, and the number of shared IIC interfaces is less than the number of optical modules in the optical module network. The address allocation module is used to allocate an address to each optical module and synchronize the address allocated to each module to the connected processor; The operation instruction parsing module is used to receive the operation instruction determined by the processor based on the on-site status and address of each optical module, and to parse the operation instruction to obtain the target optical module and operation information. The optical module access module is used to filter out the target IIC interface connected to the target optical module from the shared IIC interfaces, and send the operation information to the target optical module through the target IIC interface to access the target optical module.

9. A terminal device, characterized in that, The terminal device includes: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1-7.

10. A storage medium for computer-executable instructions, wherein a computer program is stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1-7.

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