Vertical interconnection structure defect analysis method and computer equipment

Abstract

The invention discloses a vertical interconnection structure defect analysis method and computer equipment. The method comprises the following steps: establishing a defect-free model of a vertical interconnection structure and a defect-containing model containing a cavity defect; an electricity-heat-force multi-physics field coupling environment is constructed; setting electric, thermal and mechanical boundary conditions of the model, setting a virtual buffer layer which has high thermal conductivity and is only used for heat conduction on the top surface of the substrate, and applying a generalized heat source on the buffer layer; establishing a coupling relationship among electric-thermal-force multi-physics fields, and executing multi-physics field coupling solution; performing third-order analysis; comparing global key indexes of the defect-containing model and the defect-free model; analyzing physical quantity distribution on a key interface between the metal filler of the vertical interconnection structure and the substrate; the physical quantity distribution on a longitudinal cross-sectional line passing through the center of the defect is analyzed. According to the method, comprehensive, quantitative and multi-scale evaluation on the influence of the internal micro-nano cavity defect of the vertical interconnection structure under the electro-thermal-mechanical coupling field can be realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of interconnection structure reliability, and particularly relates to a vertical interconnection structure defect analysis method and a computer device. BACKGROUND

[0002] With Moore's Law approaching the physical limit, advanced packaging technology centered on Chiplet has become a key path to continue the development of the semiconductor industry. Among them, through silicon via (TSV) and through glass via (TGV) are the core technologies to realize three-dimensional stacking and high-density interconnection. These vertical interconnection technologies realize high-performance electrical connection between chips and chips, chips and substrates by manufacturing conductive vias in silicon substrates or glass substrates, and are the research focus in the current advanced packaging field. However, in the practical application of TSV / TGV technology, micro-nano cavity defects inside the interconnection structure are ubiquitous, which seriously restricts the reliability evaluation of the device and the improvement of the process quality. Accurate and efficient analysis of the influence of these defects on the reliability of the interconnection structure is of great significance to guide process optimization and improve product yield.

[0003] At present, research teams at home and abroad mainly use the method combining experimental characterization and finite element simulation to analyze the stress and strain behavior of TSV / TGV structure under thermal load and the influence of single defects on the performance of the structure. Although some progress has been made, there are still significant shortcomings in analyzing the dynamic influence of TSV / TGV internal defects, such as high cost, low efficiency, and single analysis state, which makes it difficult to systematically, efficiently and low-costly evaluate the multi-physical field coupling effect of TSV / TGV internal micro-nano cavity defects under real working environment. SUMMARY

[0004] The purpose of the present application is to provide a vertical interconnection structure defect analysis method, a computer device, a computer readable storage medium and a computer program product, which can realize comprehensive, quantitative and multi-scale evaluation of the influence of micro-nano cavity defects inside the vertical interconnection structure under the electric-thermal-mechanical coupling field.

[0005] In order to achieve the above-mentioned purpose, one aspect of the present application provides a vertical interconnection structure defect analysis method, comprising: Step S1, a three-dimensional model containing a vertical interconnection structure and a substrate where the vertical interconnection structure is located is established as a defect-free model, and one or more micro-nano scale cavity defects are created inside the metal filler of the vertical interconnection structure in the defect-free model to obtain a defect-containing model; Step S2, the electrical, thermal and mechanical properties of the three-dimensional model are set to build an electric-thermal-mechanical multi-physical field coupling environment; Step S3, setting the electrical boundary condition, thermal boundary condition and mechanical boundary condition of the three-dimensional model, wherein setting the thermal boundary condition includes setting a virtual buffer layer with high thermal conductivity and only for heat conduction on the top surface of the substrate, and applying a generalized heat source on the buffer layer for simulating the power heat influence from the upper active device; Step S4, establishing the coupling relationship between the electric-thermal-mechanical multi-physical fields of the defect-free model and the defect-containing model and performing multi-physical field coupling solving to obtain the comprehensive response of the vertical interconnection structure under stable working state; Step S5, comparing the global key indicators of the defect-containing model and the defect-free model, evaluating the influence of the defect on the overall performance of the vertical interconnection structure; analyzing the distribution of physical quantities on the key interface between the metal filler and the substrate of the vertical interconnection structure, evaluating the local influence of the defect on the key reliability interface; analyzing the distribution of physical quantities on the longitudinal section line passing through the center of the defect, evaluating the extreme physical field distribution of the local defect.

[0006] Another aspect of the present application provides a computer device comprising a memory, a processor and a computer program stored on the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0007] Still another aspect of the present application provides a computer readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the steps of the above method.

[0008] Still another aspect of the present application provides a computer program product comprising a computer program, wherein the computer program is executed by a processor to implement the steps of the above method.

[0009] According to the vertical interconnection structure defect analysis method, computer device, computer readable storage medium and computer program product of the above aspects of the present application, by constructing a highly faithful defect model, combining innovative boundary condition setting and systematic "three-order analysis method", comprehensive, quantitative and multi-scale evaluation of the influence of micro-nano cavity defects in the vertical interconnection structure under the electric-thermal-mechanical coupling field is realized. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings: Figure 1 is the flow chart of the vertical interconnection structure defect analysis method of an embodiment of the present application; Figure 2This is a schematic diagram of a defective model of a vertical interconnect structure according to an embodiment of the present invention; Figure 3 This is a schematic diagram of a transverse section according to an embodiment of the present invention; Figure 4 This is a schematic diagram of a longitudinal section of an embodiment of the present invention; Figure 5 This is a schematic diagram of the defect spatial arrangement according to an embodiment of the present invention; Figure 6 This is a structural diagram of a computer device according to an embodiment of the present invention. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0012] One embodiment of the present invention provides a method for analyzing defects in vertical interconnect structures. The core idea is to construct a multiphysics coupled simulation platform that can accurately reflect the actual working state of vertical interconnect structures (TSV / TGV). On this platform, by systematically changing the defect parameters (location, quantity, size, and arrangement), and using a set of "third-order analysis methods" from macro to micro, the intrinsic influence of defects on the electrical, thermal, and mechanical properties of the interconnect structure is quantitatively revealed, thereby providing strong data support for process optimization and reliability design.

[0013] like Figure 1 As shown, the vertical interconnect structure defect analysis method of this invention includes steps S1 to S5.

[0014] Step S1: Establish a 3D model containing parametric defects.

[0015] In 3D modeling software (such as COMSOL Multiphysics, ANSYS), a complete 3D model is created, including the vertical interconnect structure (TSV / TGV) and its substrate (silicon or glass), as a defect-free model. Further, within this defect-free model, one or more micro / nano-scale voids are parametrically created inside the metal filling of the TSV / TGV, resulting in a defect-containing model. These defects can be set to spherical, ellipsoidal, or other irregular shapes, and can be parameterized. Their position, size, and number can all be controlled as variables to achieve systematic defect research. Taking TSV as an example, the established defect-containing model is as follows: Figure 2The diagram includes a silicon substrate, a TSV metal filler, a TSV annular insulating dielectric, voids and defects, an upper buffer dielectric, and a lower buffer dielectric.

[0016] Step S2: Define material properties and physical fields.

[0017] Assign precise physical properties to the various components (metallic copper, silicon / glass, etc.) in the 3D model, including: Electrical properties: conductivity (can be set to be temperature-dependent).

[0018] Thermal properties: thermal conductivity, density, specific heat capacity.

[0019] Mechanical properties: Young's modulus, Poisson's ratio, coefficient of thermal expansion.

[0020] Activate the three physical field interfaces of "current", "solid heat transfer" and "solid mechanics" in the software to construct an electro-thermal-mechanical multiphysics coupling environment.

[0021] Step S3: Set the boundary conditions for innovation.

[0022] To simulate the real operating environment of TSV / TGV in multilayer stacked devices, the following boundary conditions are set: Electrical boundary conditions: Apply a DC current (e.g., 630 μA) to the input port at the top of the TSV / TGV to simulate its operating current; ground the output port at the bottom.

[0023] Thermal boundary conditions: An isothermal boundary condition (e.g., 25°C / 293.15K) was applied to the bottom of the TSV / TGV substrate to simulate the effect of the connected heat dissipation layer.

[0024] A virtual buffer layer with high thermal conductivity (e.g., 500 W / (m·K)) is placed on the top surface of the substrate. This layer is not involved in mechanical calculations but only serves for heat conduction, and its thermal conductivity is much higher than that of the substrate material. A generalized heat source (e.g., 70 W / cm²) is applied to the surface of this buffer layer to efficiently and stably simulate the power thermal effects from other active devices on the upper layer. This method avoids the numerical non-convergence problem that may result from directly applying heat flux boundary conditions to the solid surface.

[0025] The three-dimensional model is set as an adiabatic boundary.

[0026] Mechanical boundary conditions: The four sides of the substrate are completely fixed (fixed constraint) to simulate its state of being bound in the package.

[0027] Step S4: Define the physical field coupling relationship and solve it.

[0028] Establishing coupling relationships between physical fields: Electro-thermal coupling: The current density distribution calculated by the "Current" module generates a volumetric heat source through the Joule heating effect (Q=J² / σ), which is automatically input into the "Solid Heat Transfer" module.

[0029] Thermo-mechanical coupling: The temperature field distribution calculated by the "Solid Heat Transfer" module is input as a thermal load into the "Solid Mechanics" module, causing thermal stress and deformation of the structure through the thermal expansion effect of the material.

[0030] A steady-state solver was selected for calculation to analyze the integrated response of the TSV / TGV under steady-state operating conditions.

[0031] Step S5: Propose and execute the "third-order analysis method" for post-processing.

[0032] After the simulation is completed, this embodiment of the invention proposes an innovative "third-order analysis method" to systematically and multi-scale interpret the results: First stage: Overall unit-level comparative analysis.

[0033] Objective: To assess the macroscopic impact of defects on the overall performance of vertical interconnect structures.

[0034] Operation: Calculate and compare the total resistance, maximum temperature, maximum deformation displacement, and maximum von Mises stress of the "defect-free model" and the "defect-containing model" respectively. By quantifying the differences, intuitively determine the overall degree of degradation of the electrical, thermal, and mechanical properties of the interconnect structure caused by defects.

[0035] Second stage: Key interface-level path analysis.

[0036] Objective: To reveal the local impact of defects on critical reliability interfaces.

[0037] Procedure: At the critical interface between the TSV / TGV metal filler and the substrate, define a transverse cross-section passing through the defect center and the metal-insulator-substrate. Taking a TSV structure as an example... Figure 3 As shown, the transverse cross-section passes through the center of the silicon substrate, the annular insulating dielectric (SiO2), the metal filler (copper), and the void defect. Figure 3 In the middle, d TSV The diameter of the TSV metal is represented by 'tox', and the thickness of the annular insulating dielectric is represented by 'tox'. In the case of TGV, the transverse cross-section passes through the center of the glass substrate, the metal filler, and the void defect.

[0038] The temperature, stress (especially interfacial shear stress), and deformation distribution curves of the "defect-free model" and the "defect-containing model" along this path were extracted and compared. This analysis can accurately locate the stress concentration areas caused by defects and assess their contribution to the risk of interfacial delamination.

[0039] Third-order: Defect local level cut-off analysis.

[0040] Objective: To investigate the extreme physical field distribution of the defect itself and its adjacent region.

[0041] Operation: such as Figure 4 As shown, a longitudinal section is drawn through the center of the void defect, and the current density, temperature, and stress distribution along this section are extracted. This analysis reveals the current congestion effect, local hot spots, and dramatic stress gradients at the defect edge, which is key to understanding how defects become the "source" of failure.

[0042] By changing the spatial arrangement of defects (such as a square arrangement of 4 holes, or an enlarged rectangle of 4 holes, the influence of different defect arrangements can be further studied. Figure 5 The diagram shows four void defects, with different spacing between the defects. x1 and x2 represent the lateral spacing, and y1 and y2 represent the longitudinal spacing, representing different defect density arrangements.

[0043] In summary, the vertical interconnect structure defect analysis method of this invention has the following innovative points: Parametric 3D defect modeling methods: These methods enable the flexible and controllable creation of single or multiple micro / nano void defects within the TSV / TGV model, forming the basis for systematic research.

[0044] An innovative method for applying thermal boundary conditions using a "virtual buffer layer" is proposed: By setting up a virtual buffer layer with high thermal conductivity to indirectly apply external heat sources, this method effectively solves the technical problem that directly applying thermal flow boundary conditions in complex multiphysics coupling simulations can easily lead to numerical non-convergence, thus improving the stability and accuracy of the simulation.

[0045] The electro-thermal-mechanical fully coupled steady-state solution strategy accurately uses the Joule heat generated by the current as the heat source and the temperature field as the mechanical load, thus constructing a complete physical chain of energy transfer and conversion and ensuring the authenticity of the simulation results.

[0046] "Three-level analysis method": This is the core innovation of this invention. This analysis method achieves a systematic, quantitative, and multi-scale assessment of the impact of defects through a progressive analysis at three levels: "overall unit level," "critical interface level," and "defect local level," which is the fundamental difference from existing technologies.

[0047] Compared with the prior art, the vertical interconnect structure defect analysis method of the present invention has the following significant advantages: Universality and Realism: This invention is not limited to TSV or TGV, but is a general-purpose defect analysis technique for vertical interconnect structures. By introducing a fully coupled electro-thermal-mechanical model and innovative boundary condition settings, it can highly realistically simulate the actual working state of interconnect structures in complex packaging environments. The simulation results are closer to physical reality and have stronger guiding significance.

[0048] Systematic and comprehensive: The proposed "third-order analysis method" constructs a systematic analytical framework that ranges from macroscopic overall performance to key interface behavior, and then to the microscopic mechanisms of defects. This method can comprehensively and multi-scale evaluate the impact of defects, avoiding the one-sidedness and superficiality of traditional simulation analysis.

[0049] High efficiency and low cost: Compared with expensive and time-consuming experimental characterization, the simulation-based method of this invention can quickly and cost-effectively evaluate a large number of different defect scenarios (such as combinations of defects of different sizes, locations and quantities) during the design phase, realizing virtual "failure experiments", which greatly shortens the R&D cycle and reduces R&D costs.

[0050] Profound Mechanism Revealing Capability: This method not only identifies "where the problem is," but also delves into "why the problem exists." Through third-order analysis, it clearly reveals the microscopic physical mechanisms underlying defects such as current congestion, localized overheating, and stress concentration, providing a direct theoretical basis for fundamentally optimizing processes (such as improving electroplating solution formulations and optimizing current waveforms).

[0051] Guiding Process Optimization and Reliability Design: The analysis results of this method can be directly used to guide the adjustment of process parameters to suppress the generation of harmful defects. Simultaneously, it can provide data support for reliability design, such as determining the critical size of defects and safety clearances, thereby establishing corresponding process specifications and design rules to improve product yield and long-term reliability.

[0052] Embodiments of the present invention also provide a computer device, which may be a server, and its internal structure diagram may be as follows: Figure 6 As shown. The computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores operating parameter data for various components. The network interface communicates with external terminals via a network connection. When executed by the processor, the computer program implements the steps of the method according to embodiments of the present invention.

[0053] Those skilled in the art will understand thatFigure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0054] Embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method of the embodiments of the present invention.

[0055] Embodiments of the present invention also provide a computer program product, including a computer program that, when executed by a processor, implements the steps of the method of the embodiments of the present invention.

[0056] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A method for analyzing defects in a vertical interconnect structure, characterized in that, include: Step S1: Establish a three-dimensional model containing the vertical interconnect structure and the substrate in which the vertical interconnect structure is located as a defect-free model. In this defect-free model, create one or more micro-nano scale voids and defects inside the metal filler of the vertical interconnect structure to obtain a defect-containing model. Step S2: Set the electrical, thermal, and mechanical properties of the 3D model to construct an electro-thermal-mechanical multiphysics coupling environment; Step S3: Set the electrical boundary conditions, thermal boundary conditions and mechanical boundary conditions of the three-dimensional model. Setting the thermal boundary conditions includes setting a virtual buffer layer with high thermal conductivity on the top surface of the substrate and using it only for heat conduction, and applying a generalized heat source on the buffer layer to simulate the power thermal effects from the upper active device. Step S4: Establish the coupling relationship between the electro-thermal-mechanical multiphysics fields of the defect-free model and the defective model, and perform multiphysics coupling solution to obtain the comprehensive response of the vertical interconnection structure under stable working conditions. Step S5: Compare the global key indicators of the defect-containing model and the defect-free model to evaluate the impact of defects on the overall performance of the vertical interconnect structure; analyze the distribution of physical quantities at the key interface between the metal filler and the substrate of the vertical interconnect structure to evaluate the local impact of defects on the key reliability interface; analyze the distribution of physical quantities on the longitudinal section passing through the defect center to evaluate the extreme physical field distribution in the defect locality.

2. The method as described in claim 1, characterized in that, In step S5, the global key indicators include total resistance, maximum temperature, maximum deformation displacement, and maximum von Mises stress; The key interface between the metal filler and the substrate in a vertical interconnect structure is the transverse section passing through the defect center and the metal filler and substrate. The distribution of physical quantities at the key interface includes the distribution curves of temperature, stress and deformation. The distribution of physical quantities along the longitudinal section passing through the center of the defect includes current density, temperature, and stress distribution.

3. The method as described in claim 1 or 2, characterized in that, In step S4, establishing the coupling relationship between multiple physics fields includes establishing electro-thermal coupling and thermo-mechanical coupling. Establishing an electro-thermal coupling involves calculating the current density distribution and generating a volumetric heat source through the Joule heating effect. Establishing a thermo-mechanical coupling involves calculating the temperature field distribution as a thermal load, and then using the thermal expansion effect of the material to induce thermal stress and deformation in the structure.

4. The method as described in claim 1 or 2, characterized in that, In step S3, setting the electrical boundary conditions includes: applying a DC current to the input port at the top of the vertical interconnect structure to simulate its operating current, and grounding the output port at the bottom of the vertical interconnect structure. Setting thermal boundary conditions also includes: applying isothermal boundary conditions at the bottom of the substrate to simulate the effect of connecting the heat dissipation layer, and setting the three-dimensional model as an adiabatic boundary around its perimeter. Setting mechanical boundary conditions includes: completely fixing the four sides of the substrate to simulate the state of being bound within the package.

5. The method as described in claim 1 or 2, characterized in that, In step S2, electrical properties include electrical conductivity, thermal properties include thermal conductivity, density and specific heat capacity, and mechanical properties include Young's modulus, Poisson's ratio and coefficient of thermal expansion.

6. The method as described in claim 1 or 2, characterized in that, The vertical interconnect structure is a glass via or a silicon via.

7. The method as described in claim 1 or 2, characterized in that, The void defect is a spherical or ellipsoidal air void.

8. A computer device, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1-7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-7.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-7.

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