Synaptic connection processing method and system for brain-like computing network

Abstract

The invention provides a synaptic connection processing method and system for a brain-like computing network, and the method comprises the steps: decoding a pulse signal through a pulse address decoding module, and obtaining a head address and data length information of a corresponding target synaptic index; reading a corresponding target synaptic index from a memory through a synaptic index DMA module according to the initial address and data length information of the target synaptic index; decoding the target synaptic index through a pulse address decoding module to obtain a first address and a number of corresponding target synaptic connections; reading all target synaptic connections from a memory through a synaptic index DMA module according to the initial addresses and the number of the target synaptic connections; and obtaining target neurons corresponding to the target synaptic connections and corresponding synaptic connection weights through a synaptic connection distribution module, and sending the synaptic connection weights to the corresponding target neurons in the neuron processing system. According to the method, the indexing and distribution of the synaptic connections can be efficiently and reliably realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of brain-inspired computing, and in particular to a synaptic connection processing method and system for a brain-inspired computing network. BACKGROUND Brain-inspired computing, also known as neuromorphic computing, is a general term for computing theories, architectures, chip designs, and application models and algorithms that draw on the information processing patterns and structures of biological neural systems. As a new computing paradigm, brain-inspired computing aims to achieve higher energy efficiency and higher-level intelligent computing tasks by simulating the structure and information processing mechanism of the brain.

[0002] In a brain-inspired computing network, at least one chip is included, each chip includes a neuron processing system, each neuron processing system is configured with at least one neuron, and each neuron can act as a source neuron or a destination neuron in the network. One source neuron can transmit information to one or more target neurons through one or more preset synaptic connections. The synaptic connections between each source neuron and the destination neurons in the corresponding chip are usually stored in the corresponding memory of the chip, usually in the DDR (Double Data Rate Synchronous Dynamic Random Access Memory) connected to the chip.

[0003] Among them, the source neuron activates the information transmission process by sending a pulse. This pulse acts as a trigger signal to trigger the reading of pre-defined synaptic connection data from the memory corresponding to the current chip. These synaptic connections, as static communication rules, precisely indicate the destination neurons of the signal transmission and contain connection weights to modulate the signal strength. Currently, how to efficiently and reliably implement the indexing and distribution of synaptic connections is still a problem to be solved in the field. SUMMARY

[0004] In order to efficiently and reliably implement the indexing and distribution of synaptic connections, the present application provides a synaptic connection processing method and system for a brain-inspired computing network.

[0005] In a first aspect, the present application provides a synaptic connection processing method for a brain-inspired computing network, wherein the brain-inspired computing network includes at least one chip, the chip includes a neuron processing system configured with at least one neuron, and the memory corresponding to each chip respectively stores a plurality of synaptic indexes and synaptic connections. The method is used for the current chip to perform the following steps after receiving a pulse signal containing the source neuron identifier sent by the source neuron: decoding the pulse signal through a pulse address decoding module to obtain the first address of the target synaptic index corresponding to the source neuron in the current chip and the data length information; reading, by a synaptic index DMA module, the target synaptic index corresponding to the source neuron from a memory corresponding to the current chip according to the first address and the data length information of the target synaptic index; decoding, by the pulse address decoding module, the target synaptic index to obtain the first address and the number of the target synaptic connection corresponding to the source neuron; reading, by the synaptic index DMA module, all the target synaptic connections from the memory corresponding to the current chip according to the first address and the number of the target synaptic connection; obtaining, by a synaptic connection distribution module, the destination neuron corresponding to each of the target synaptic connections and the synaptic connection weight corresponding to each of the destination neurons, and sending the synaptic connection weight to the corresponding destination neuron in the neuron processing system.

[0006] Further, when the single transmission bit width of the synaptic index DMA module is Wtrans , the maximum actual bit width of each of the synaptic connections is Ws,ideal , and the storage bit width allocated by the corresponding memory for each of the synaptic connections is Ws, hard calculated according to the following formula:

[0007] wherein MOD() represents a remainder function.

[0008] Further, the total number of the synaptic connections stored in the memory corresponding to each of the chips is not less than the total number of neurons configured on the corresponding chip.

[0009] Further, the synaptic index includes the first address and the number of the synaptic connection corresponding to the corresponding source neuron, and when the actual bit width of the synaptic index is Windex,ideal , the first address bit width of the synaptic connection is Wstaddr , the number bit width of the synaptic connection is Wfanout , and the total number of neurons configured on the chip is N, the number bit width of the synaptic connection Wfanout satisfies the following formula:

[0010] the first address bit width of the synaptic connection Wstaddr satisfies the following formula:

[0011] wherein MOD() represents a remainder function, and S represents the number of the corresponding synaptic connection. the actual bit width of the synaptic index Windex,ideal = Wfanout + Wstaddr ; The corresponding memory allocated to the synaptic index Windex,hardl Calculate using the following formula:

[0012] in, Wtrans This indicates the bit width of a single transmission of the synaptic index DMA module.

[0013] Furthermore, when the memory corresponding to the current chip allocates a storage bit width of 2 for each of the synaptic connections... H When the value is Byte, the pulse address decoding module obtains the starting address of the target synaptic connection by shifting the starting address in the target synaptic index to the left by H bits.

[0014] Furthermore, the source neuron identifier is the sequence number of the target synapse index corresponding to the source neuron in the memory corresponding to the current chip; When the memory corresponding to the current chip allocates a storage bit width of 2 for each of the synaptic indices... K When the value is Byte, the pulse address decoding module obtains the starting address of the target synapse index by shifting the neuron identifier to the left by K bits.

[0015] Furthermore, the synaptic index DMA module is connected to the pulse address decoding module through a read address channel of a preset bus protocol, and is connected to the memory corresponding to the current chip through a read data channel of the preset bus protocol.

[0016] Furthermore, the step of reading all the target synaptic connections from the memory corresponding to the current chip using the synaptic index DMA module according to the starting address and number of the target synaptic connections includes performing the following steps using the synaptic index DMA module: Based on the number of target synaptic connections and the number of burst transmissions required for each target synaptic connection, calculate the total number of burst transmissions required for all target synaptic connections; Determine whether the total number of transmissions exceeds the maximum length of a single burst transmission corresponding to the preset bus protocol; When the total number of transmissions does not exceed the maximum length of a single burst transmission, a burst transmission method is adopted to directly read all the target synaptic connections from the memory corresponding to the current chip; When the total number of transmissions exceeds the maximum length of a single burst transmission, the total number of transmissions is split, and based on the splitting result, all target synaptic connections are read from the memory corresponding to the current chip in batches using burst transmission.

[0017] Furthermore, the target synaptic connection includes at least one target neuron identifier, and the synaptic connection distribution module determines the corresponding target neuron based on the target neuron identifier; The target synaptic connection also includes a valid flag bit corresponding to each of the target neurons. When the valid flag bit indicates that the corresponding target neuron is invalid, the synaptic connection weight corresponding to the invalid target neuron is reset to zero.

[0018] In a second aspect, the present invention provides a synaptic connection processing system for a neuromorphic computing network, wherein the neuromorphic computing network includes at least one chip, the chip includes a neuron processing system configured with at least one neuron, and the memory corresponding to each chip stores a plurality of synaptic indices and synaptic connections respectively, the synaptic connection processing system is integrated in each chip, and includes a pulse address decoding module, a synaptic index DMA module and a synaptic connection distribution module; In this process, after the current chip receives a pulse signal containing the source neuron's identifier from the source neuron, it decodes the pulse signal using the pulse address decoding module to obtain the starting address and data length information of the target synapse index corresponding to the source neuron in the current chip. Then, the synapse index DMA module reads the target synapse index corresponding to the source neuron from the memory corresponding to the current chip based on the starting address and data length information of the target synapse index. Next, the pulse address decoding module decodes the target synapse index to obtain the starting address and number of target synaptic connections corresponding to the source neuron. Finally, the synapse connection distribution module obtains the target neuron corresponding to each target synapse connection and the synapse connection weight corresponding to each target neuron, and sends the synapse connection weight to the corresponding target neuron in the neuron processing system.

[0019] By adopting the above technical solution, the present invention has the following advantages over the prior art: This invention uses a pulse address decoding module to convert the pulse signal emitted by the source neuron into the starting address and data length information of the target synaptic index. Then, the synaptic index DMA module uses this information to efficiently read the corresponding synaptic connection data from the memory of the current chip. Finally, the data is parsed and distributed to the corresponding target neuron to realize information transmission and processing in the neural network. This enables efficient and reliable synaptic connection indexing and distribution, which helps to promote the development and application of neuromorphic computing technology. Attached Figure Description

[0020] Figure 1This is a structural block diagram of the synaptic connection processing system for neuromorphic computing networks according to the present invention; Figure 2 This is a flowchart illustrating the synaptic connection processing method for neuromorphic computing networks according to the present invention. Figure 3 This is a schematic diagram illustrating the storage of different synaptic connections under different data precision in this invention. Detailed Implementation

[0021] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0022] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components, the shape, quantity, positional relationship and proportion of each component can be arbitrarily changed under the premise of realizing the technical solution of this invention, and the layout of the components may also be more complex.

[0023] As mentioned earlier, a neuromorphic computing network includes at least one chip, each chip comprising a neuron processing system, and each neuron processing system being configured with at least one neuron. Each neuron can serve as either a source neuron or a target neuron. A source neuron can connect to one or more target neurons through one or more pre-defined synaptic connections. The synaptic connections between each source neuron and the target neuron in the corresponding chip are typically stored in the memory corresponding to the chip (such as an external DDR).

[0024] In this process, the source neuron activates the information transmission flow by sending a pulse signal. This pulse signal acts as a trigger signal, prompting the reading of predefined synaptic connection data from the memory corresponding to the current chip. These synaptic connections, as static communication rules, precisely identify the target neuron for signal transmission and include connection weights to modulate the signal strength.

[0025] To achieve efficient and reliable indexing and distribution of synaptic connections, this invention provides a method and system for synaptic connection processing in neuromorphic computing networks.

[0026] Example 1 This embodiment provides a synaptic connection processing method for neuromorphic computing networks. The neuromorphic computing network includes at least one chip, each chip including a neuron processing system (NPU) configured with at least one neuron, and each chip's corresponding memory stores a plurality of synaptic indices and a plurality of synaptic connections.

[0027] Specifically, each source neuron has a synaptic index in each chip. i,c (where i represents the i-th source neuron and c represents the c-th chip) Correspondingly, each synaptic index is stored sequentially in the memory of the corresponding chip according to the sequence number of the source neurons. Furthermore, the synaptic connections s between each source neuron and all target neurons in each chip are... i,j（ (i represents the i-th source neuron, and j represents the j-th target neuron) are also stored sequentially in the memory of the corresponding chip.

[0028] The method in this embodiment is based on Figure 1 The illustrated synaptic connection processing system is integrated into each chip and is used to execute [the signal] through the current chip after the source neuron sends a pulse signal containing the source neuron's identifier (ID). Figure 2 The following steps are shown: Step S1: Receive pulse signals through the pulse address decoding module via the multi-chip communication system.

[0029] Step S2: The pulse signal is decoded by the pulse address decoding module to obtain the starting address and data length information of the target synapse index corresponding to the source neuron in the current chip.

[0030] Step S3: The synaptic index DMA module reads the target synaptic index corresponding to the source neuron from the memory corresponding to the current chip according to the starting address and data length information of the target synaptic index.

[0031] Step S4: The target synapse index is decoded by the pulse address decoding module to obtain the starting address and number of target synapse connections corresponding to the source neuron.

[0032] Step S5: The synaptic index DMA module reads all target synaptic connections from the memory corresponding to the current chip according to the starting address and number of the target synaptic connections.

[0033] Step S6: Obtain the target neuron corresponding to each target synaptic connection and the synaptic connection weight corresponding to each target neuron through the synaptic connection distribution module, and send the synaptic connection weight to the corresponding target neuron in the neuron processing system.

[0034] The synaptic DMA module needs to go through the microprocessor system to read data from the memory.

[0035] This embodiment employs a source indexing mechanism. The pulse signal emitted by the source neuron is converted into the starting address and data length information of the target synaptic index through the pulse address decoding module. Then, the synaptic index DMA module efficiently reads the corresponding synaptic connection data from the memory of the current chip based on this information. Finally, the data is parsed and distributed to the corresponding target neuron to realize information transmission and processing in the neural network. This enables efficient and reliable synaptic connection indexing and distribution, which helps to promote the development and application of neuromorphic computing technology.

[0036] As mentioned earlier, each chip's corresponding memory stores a synaptic index. i,c and synaptic connections i,j The two parts require significant storage space and must be stored in off-chip DDR. The synaptic index storage needs to ensure unlimited neuron connection range and number, maximizing network connection reconfigurability. The synaptic connection storage, on the other hand, needs to consider storage formats within a reconfigurable synaptic model and with reconfigurable computational precision.

[0037] The following section will use a single-chip neuromorphic computing system containing 16 NPUs, each capable of computing 1024 reconfigurable neuron models, as an example.

[0038] In one feasible approach, multiple synapse types are predefined, and each synapse type can have multiple data precisions, such as... Figure 3 The storage table shown includes five synapse types, from type 1 to type V. Each synapse type has five data precisions: FP32, INT32, FP16, INT16, and INT8. This embodiment adopts a configurable synapse connection storage design, which requires consideration of the storage format of different synapse types under different data precisions.

[0039] In this embodiment, as Figure 3 As shown, the contents of the synaptic connection include the target neuron identifier j and the synaptic connection weights. w Weight type flag type and valid flag bit v In the storage table, (1 b) represents a point with 1 bit, (2 b) represents a point with 2 bits, and so on. Furthermore, the single-transfer bit width of the synaptic index DMA module needs to be considered to determine the storage space allocated to the synaptic connection in memory. When the single-transfer bit width of the synaptic index DMA module is... Wtrans The actual bit width of each synaptic connection s is Ws,ideal At that time, the corresponding memory allocates storage bit width for each synaptic connection s. Ws,hard Calculate using the following formula:

[0040] MOD() represents the modulo function.

[0041] For example, assuming the single transfer width of the synaptic index DMA module is 64 bits, the maximum actual width of each synaptic connection is 117 bits, and the corresponding memory allocates a storage width of 28 bits for each synaptic connection, the synaptic index DMA module needs to perform two burst transfers.

[0042] The above memory bit width design ensures that the memory space allocated to each synaptic connection is precisely aligned with the single transfer bit width of the synaptic index DMA module, avoiding waste of memory space and ensuring that the bus bandwidth is fully utilized for each transfer, thus eliminating the transfer efficiency loss caused by bit width mismatch.

[0043] Furthermore, by supporting arbitrary combinations of different synapse types and different data precisions, the same hardware can adapt to various operations ranging from complex floating-point operations to efficient fixed-point calculations, thereby improving system energy efficiency. By avoiding unnecessary storage space occupation and maximizing the effective payload of each data transfer, this design reduces the total number of memory accesses and related power consumption, thus significantly improving the energy efficiency ratio of the entire neuromorphic computing system.

[0044] In this embodiment, the synaptic index includes the starting address and number of synaptic connections corresponding to the respective source neuron. To ensure that the connection range and number of neurons are not limited, the total number of synaptic connections stored in the memory of each chip should not be less than the total number of neurons configured on the corresponding chip.

[0045] Assume the actual bit width of the synaptic index is Windex,ideal The starting address width of the synaptic connection is... Wstaddr The number of synaptic connections is bit-width. Wfanout If the total number of neurons in the chip is N, then the number of synaptic connections and their bit width are... Wfanout Satisfy the following formula:

[0046] The address decoding logic can convert the synapse number into an index address through shift operations.

[0047] Assuming the number of synaptic connections stored in the memory corresponding to the chip is S, then the starting address width of the synaptic connection is... Wstaddr Satisfy the following formula:

[0048] Therefore, the actual bit width of the synaptic index can be obtained. Windex,ideal = Wfanout + Wstaddr .

[0049] Furthermore, the corresponding memory allocates storage bits for the synaptic index. Windex,hardlThe following formula can be used for calculation:

[0050] in, Wtrans This indicates the bit width of a single transfer in the synaptic index DMA module.

[0051] For example, assuming the current chip has 16,384 neurons and stores 16,384,000 synaptic connections, then wfanout = 14 bits, wstaddr = 24 bits, windex,ideal = 38 bits, and windex,hard = 64 bits.

[0052] Therefore, the corresponding storage resources can be precisely allocated to the synaptic index, and by aligning the bit width of the synaptic index with the single transfer bit width of the synaptic index DMA module, it is possible to ensure that the storage and transfer of each synaptic index can achieve the highest efficiency, eliminating storage fragmentation and transfer bandwidth waste caused by bit width mismatch.

[0053] In this embodiment, the pulse address decoding module has the following two functions: The first function is that the pulse address decoding module receives the pulse signal sent by the source neuron through a multi-chip communication system and decodes the pulse signal to obtain the starting address and data length information of the target synapse index corresponding to the source neuron in the current chip. In one feasible embodiment, the source neuron is identified by the sequence number of the target synapse index corresponding to the source neuron in the memory of the current chip. When the memory of the current chip allocates a storage bit width of 2 for each synapse index... K When the value is 8 bytes, the pulse address decoding module obtains the starting address of the target synaptic index by shifting the neuron identifier left by K bits. For example, when the corresponding memory allocates 8 bytes of storage space for each synaptic index, and the single transfer width of the synaptic index DMA module is 64 bits, the pulse address decoding module obtains the starting address of the synaptic connection by shifting the starting address in the target synaptic index left by 3 bits. The synaptic index DMA module needs to perform one burst transfer.

[0054] This embodiment achieves an extremely efficient address decoding mechanism with very low hardware cost by directly converting the source neuron identifier (i.e., its sequence number) into the starting address of the target synapse index through a fixed left shift operation (such as left shift by 3 bits).

[0055] The second function is that after receiving the target synaptic index from the synaptic index DMA module, the pulse address decoding module decodes the target synaptic index to obtain the starting address and number of target synaptic connections corresponding to the source neuron. In one feasible implementation, when the memory allocated to each synaptic connection by the current chip has a storage bit width of 2... HWhen the target synapse connection is a byte, the pulse address decoding module obtains the starting address of the target synapse connection by shifting the starting address in the target synapse index left by H bits. For example, when the corresponding memory allocates 16 bytes of storage space for each synapse connection, and the DMA module's single transfer width is 64 bits, the pulse address decoding module obtains the starting address of the target synapse connection by shifting the starting address in the target synapse index left by 4 bits. The synapse index DMA module needs to perform two burst transfers. This embodiment achieves extremely efficient address resolution by using hardware shift operations (such as shifting left by 4 bits) to directly convert the starting address in the target synapse index into the starting address of the target synapse connection.

[0056] In this embodiment, the synaptic index DMA module processes the two read operations initiated by the pulse address decoding module. It is connected to the pulse address decoding module via a read address channel of a preset bus protocol (such as the AXI4 protocol) and to the memory corresponding to the current chip via a read data channel of the preset bus protocol. In one feasible implementation, the preset bus protocol is, for example, the AXI4 protocol, with a maximum single burst transfer length of 256 bits. Burst transfer is a mechanism for efficient data transfer in digital systems (especially between internal chip buses or between a chip and external memory). It only requires exchanging address information (starting address) once at the beginning to continuously transfer multiple data units.

[0057] In one feasible implementation, when the synaptic index DMA module reads the target synaptic index, it sends the starting address and burst transfer count of the target synaptic index obtained from the pulse address decoding module to the read address channel of the AXI4 bus to initiate the first read operation. After receiving the target synaptic index from the read data channel, it sends it to the pulse address decoding module.

[0058] In one feasible approach, when the synaptic index DMA module reads the target synaptic connection, the starting address and burst transfer count of the target synaptic connection received cannot be directly transmitted to the AXI4 bus as when reading the target synaptic index. This is because the AXI4 protocol specifies that the maximum length of a single burst transfer cannot exceed 256, but the number of transfers for the target synaptic connection may exceed 256. Therefore, the process of the synaptic index DMA module reading the target synaptic connection is as follows: First, based on the number of target synaptic connections and the number of burst transmissions required for each target synaptic connection, calculate the total number of burst transmissions required for all target synaptic connections.

[0059] Secondly, determine whether the total number of transmissions exceeds the maximum length of a single burst transmission corresponding to the preset bus protocol.

[0060] When the total number of transmissions does not exceed the maximum length of a single burst transmission, burst transmission mode is adopted to directly read all target synaptic connections from the memory corresponding to the current chip; When the total number of transmissions exceeds the maximum length of a single burst transmission, the total number of transmissions is split, and based on the splitting result, all target synaptic connections are read from the memory corresponding to the current chip in batches using burst transmission. For example, the obtained N-bit total burst transmission count is split into two parts: a high (N-8) bit and a low 8 bit, denoted as... bursthigh, (N-8) -bit burstlow, 8 -bit and bursthigh, (N-8) -bit Then according to bursthigh, (N-8) -bit + 1 The value breaks down the reading target synaptic connection process into bursthigh, (N-8) -bit Each read operation increments the starting address by 2048. fanouti,c si,j Decrement by 1, the formula for the burst transfer length of each read operation is as follows:

[0061] Received from the read data channel fanou Target synaptic connections i,c It is then sent to the synaptic connection distribution module.

[0062] Thus, by introducing an intelligent burst transmission splitting and batch reading mechanism, the contradiction between the single burst transmission length limit of the AXI4 bus protocol and the massive number of synaptic connections in large-scale neural networks is effectively resolved. This scheme first accurately calculates the total number of required burst transmissions, and when the protocol limit is exceeded, intelligently splits the transmission task into multiple burst transmissions conforming to the protocol specifications. This achieves efficient access to synaptic connection data of any scale while strictly adhering to the bus protocol. Automatic address incrementing after each transmission (e.g., adding 2048 bytes) and dynamic updating of the transmission counter ensure the continuity and integrity of large-scale data reading. This design not only completely avoids system errors caused by transmission exceeding limits but also maximizes the utilization of the theoretical transmission bandwidth of the AXI4 bus, minimizing the latency and overhead of large-scale data access, and providing a stable, reliable, and high-performance data path guarantee for neuromorphic computing systems to process ultra-large-scale neural networks.

[0063] The synaptic connection distribution module is responsible for receiving data from the synaptic index DMA module. si,j t Figure 1 Target synaptic connections ​The synaptic connections are sent to the corresponding target neuron (NPU) in the neuron processing system for computation. If the neuron processing system has only a single NPU, the synaptic connection distribution module does not need to process the connections before sending them. If the neuron processing system contains multiple NPUs, the target synaptic connection should contain at least one target neuron identifier, and the synaptic connection distribution module determines the corresponding target neuron based on the target neuron identifier. Therefore, by dynamically parsing the target neuron identifier and achieving precise routing, the efficient and error-free distribution of massive synaptic connections in the parallel computing architecture is ensured, providing crucial support for the large-scale parallel processing of multi-NPU systems.

[0064] Furthermore, the target synaptic connection also includes a valid flag bit corresponding to each target neuron. When a valid flag bit indicates that the corresponding target neuron is invalid, the weight of the synaptic connection corresponding to the invalid target neuron is reset to zero. Thus, by hardware-level masking of the weights of invalid connections based on valid flag bits at the data distribution source, interference from invalid data to neuron computation is fundamentally eliminated, ensuring the accuracy and energy efficiency of large-scale sparse neural network computation.

[0065] Example 2 This embodiment provides a synaptic connection processing system for neuromorphic computing networks. The synaptic connection processing system is integrated into each chip within the network, and as follows: ​ As shown, the system mainly includes a pulse address decoding module, a synaptic index DMA module, and a synaptic connection distribution module.

[0066] In this embodiment, after the current chip receives a pulse signal containing the source neuron's identifier sent by the source neuron, it decodes the pulse signal using a pulse address decoding module to obtain the starting address and data length information of the target synapse index corresponding to the source neuron in the current chip. Based on the starting address and data length information of the target synapse index, the synapse index DMA module reads the target synapse index corresponding to the source neuron from the memory corresponding to the current chip. The pulse address decoding module decodes the target synapse index to obtain the starting address and number of target synaptic connections corresponding to the source neuron. Based on the starting address and number of target synaptic connections, the synapse index DMA module reads all target synaptic connections from the memory corresponding to the current chip. The synapse connection distribution module obtains the target neuron corresponding to each target synapse connection and the synapse connection weights corresponding to each target neuron, and sends the synapse connection weights to the corresponding target neuron in the neuron processing system.

[0067] By adopting the above technical solution, this embodiment can efficiently and reliably realize the indexing and distribution of synaptic connections.

[0068] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of the present invention is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but all such changes and modifications fall within the scope of protection of the present invention.

Claims

1. A method for processing synaptic connections in neuromorphic computing networks, characterized in that, The neuromorphic computing network includes at least one chip, each chip comprising a neuron processing system configured with at least one neuron, and each chip's corresponding memory stores a plurality of synaptic indices and synaptic connections. The method is used for the current chip to perform the following steps after receiving a pulse signal containing the source neuron's identifier sent by the source neuron: The pulse signal is decoded by the pulse address decoding module to obtain the starting address and data length information of the target synapse index corresponding to the source neuron in the current chip; The synaptic index DMA module reads the target synaptic index corresponding to the source neuron from the memory corresponding to the current chip based on the starting address and data length information of the target synaptic index; The target synapse index is decoded by the pulse address decoding module to obtain the starting address and number of target synapse connections corresponding to the source neuron; The synaptic index DMA module reads all the target synaptic connections from the memory corresponding to the current chip according to the starting address and number of the target synaptic connections; The synaptic connection distribution module obtains the target neuron corresponding to each target synaptic connection and the synaptic connection weight corresponding to each target neuron, and sends the synaptic connection weight to the corresponding target neuron in the neuron processing system.

2. The synaptic connection processing method as described in claim 1, characterized in that, When the single-transmission bit width of the synaptic index DMA module is Wtrans The maximum actual bit width of each synaptic connection is Ws,ideal At that time, the corresponding memory allocates a storage bit width for each synaptic connection. Ws,hard Calculate using the following formula: MOD() represents the modulo function.

3. The synaptic connection processing method as described in claim 1, characterized in that, The total number of synaptic connections stored in the memory corresponding to each chip is not less than the total number of neurons configured on the corresponding chip.

4. The synaptic connection processing method as described in claim 1, characterized in that, The synaptic index includes the starting address and number of synaptic connections corresponding to the respective source neurons, where the actual bit width of the synaptic index is... Windex, ideal The starting address width of the synaptic connection is Wstaddr The number of synaptic connections is bit-width. Wfanout When the total number of neurons configured in the chip is N, the number of synaptic connections is [number] bits wide. Wfanout Satisfy the following formula: The starting address width of the synaptic connection Wstaddr Satisfy the following formula: Where MOD() represents the modulo function, and S represents the number of the corresponding synaptic connections; The actual bit width of the synaptic index Windex,ideal=Wfanout+wstaddr ; The corresponding memory allocated to the synaptic index Windex,hardl Calculate using the following formula: in, Wtrans This indicates the single-transmission bit width of the synaptic index DMA module.

5. The synaptic connection processing method as described in claim 1, characterized in that, When the memory allocated to each synaptic connection by the current chip has a memory bit width of 2... H When the value is Byte, the pulse address decoding module obtains the starting address of the target synaptic connection by shifting the starting address in the target synaptic index to the left by H bits.

6. The synaptic connection processing method as described in claim 1, characterized in that, The source neuron identifier is the sequence number of the target synapse index corresponding to the source neuron in the memory corresponding to the current chip; When the memory corresponding to the current chip allocates a storage bit width of 2 for each of the synaptic indices... K When the value is Byte, the pulse address decoding module obtains the starting address of the target synapse index by shifting the neuron identifier to the left by K bits.

7. The synaptic connection processing method as described in claim 1, characterized in that, The synaptic index DMA module is connected to the pulse address decoding module through a read address channel of a preset bus protocol, and is connected to the memory corresponding to the current chip through a read data channel of the preset bus protocol.

8. The synaptic connection processing method as described in claim 7, characterized in that, The step of reading all the target synaptic connections from the memory corresponding to the current chip using the synaptic index DMA module according to the starting address and number of the target synaptic connections includes performing the following steps using the synaptic index DMA module: Based on the number of target synaptic connections and the number of burst transmissions required for each target synaptic connection, calculate the total number of burst transmissions required for all target synaptic connections; Determine whether the total number of transmissions exceeds the maximum length of a single burst transmission corresponding to the preset bus protocol; When the total number of transmissions does not exceed the maximum length of a single burst transmission, a burst transmission method is used to directly read all the target synaptic connections from the memory corresponding to the current chip; When the total number of transmissions exceeds the maximum length of a single burst transmission, the total number of transmissions is split, and based on the splitting result, all target synaptic connections are read from the memory corresponding to the current chip in batches using burst transmission.

9. The synaptic connection processing method as described in claim 1, characterized in that, The target synaptic connection includes at least one target neuron identifier, and the synaptic connection distribution module determines the corresponding target neuron based on the target neuron identifier; The target synaptic connection also includes a valid flag bit corresponding to each of the target neurons. When the valid flag bit indicates that the corresponding target neuron is invalid, the synaptic connection weight corresponding to the invalid target neuron is reset to zero.

10. A synaptic connection processing system for neuromorphic computing networks, characterized in that, The neuromorphic computing network includes at least one chip, each chip including a neuron processing system configured with at least one neuron, and each chip has a memory that stores a plurality of synaptic indices and synaptic connections. The synaptic connection processing system is integrated into each chip and includes a pulse address decoding module, a synaptic index DMA module, and a synaptic connection distribution module. In this process, after the current chip receives a pulse signal containing the source neuron's identifier from the source neuron, it decodes the pulse signal using the pulse address decoding module to obtain the starting address and data length information of the target synapse index corresponding to the source neuron in the current chip. Then, the synapse index DMA module reads the target synapse index corresponding to the source neuron from the memory corresponding to the current chip based on the starting address and data length information of the target synapse index. Next, the pulse address decoding module decodes the target synapse index to obtain the starting address and number of target synaptic connections corresponding to the source neuron. Finally, the synapse connection distribution module obtains the target neuron corresponding to each target synapse connection and the synapse connection weight corresponding to each target neuron, and sends the synapse connection weight to the corresponding target neuron in the neuron processing system.

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