Storage and calculation integrated chip

Abstract

The invention provides a storage and calculation integrated chip which comprises a storage and calculation array which is divided into q groups according to columns, each group comprises M columns, the M columns of each group are respectively used for storing one column weight of an M-bit weight matrix according to bits, and the storage and calculation integrated chip is also used for realizing multiplication and addition calculation of an N-bit input vector and the M-bit weight matrix; the row driving module is used for converting an N-bit input vector into a voltage pulse form, and periodically inputting the N-bit input vector into word lines of each row of the storage and calculation array; the column driving module is used for inputting the bit line voltage to the bit line of each column of the storage and calculation array; q analog domain shift accumulation modules, each analog domain shift accumulation module being used for performing weighted accumulation operation on the output current of the M columns of source lines to obtain an input vector and an analog quantity of a column of multi-bit weight multiply-add calculation results; and the analog-to-digital conversion module is used for converting the analog quantity of the multiply-add calculation results obtained by the q analog domain shift accumulation modules into digital quantity. According to the invention, the energy consumption overhead of the storage and calculation integrated architecture can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory design, and particularly relates to a memory-computing integrated chip. BACKGROUND

[0002] Computing-In-Memory is one of the most potential solutions to break through the Von Neumann bottleneck in the future. In the existing Computing-In-Memory architecture, the Analog-to-Digital Converter (ADC) module occupies the main overhead of the Computing-In-Memory architecture area and energy consumption. For example, in the input / weight mapping scheme, the weight is quantized into multiple bits (for example, 7, converted into a 4-bit value “0111”), and mapped to different columns of the Computing-In-Memory array. The output of each column needs to be quantized to the digital domain by the ADC, and the results of other columns are added by the shift accumulator, and the weighted accumulation is performed according to the ratio of 1:2:4:8. The input is also quantized into multiple bits (for example, 10, converted into a 4-bit value “1010”), and sent to the input end of the Computing-In-Memory array in multiple periods. The output of each period needs to be quantized to the digital domain by the ADC, and the results of other periods are added by the shift accumulator, and the weighted accumulation is performed according to the ratio of 1:2:4:8. For the product calculation of a 4-bit input vector and a 4-bit weight matrix, 16 times of ADC quantization are required. Therefore, how to optimize the circuit design to reduce the number of ADC quantization and thus reduce the energy consumption overhead of the Computing-In-Memory architecture has become a technical problem that must be solved. SUMMARY

[0003] Therefore, the present application provides a memory-computing integrated chip, which can reduce the number of use of the Analog-to-Digital Converter module and reduce the energy consumption overhead of the Computing-In-Memory architecture.

[0004] The present application provides a memory-computing integrated chip, which is suitable for multiply-accumulate calculation of an N-bit input vector and an M-bit weight matrix. The N-bit input vector includes p N-bit input data, the M-bit weight matrix has a size of p rows and q columns, p≥1, q≥1, N≥1, and M≥1. The memory-computing integrated chip includes: a Computing-In-Memory array, which includes at least p rows and (q*M) columns, the (q*M) columns are divided into q groups, each group includes M columns, and the M columns of each group are respectively used to store a column of weights of the M-bit weight matrix by bit. The Computing-In-Memory array is also used to implement multiply-accumulate calculation of the N-bit input vector and the M-bit weight matrix, and the multiply-accumulate calculation result is represented by the output current of each column source line of the Computing-In-Memory array; a row driving module, which is connected with the word lines of each row of the Computing-In-Memory array, and is used to convert the N-bit input vector into a voltage pulse form and input to the word lines of each row of the Computing-In-Memory array in cycles, so as to implement multiply-accumulate calculation of the N-bit input vector and the M-bit weight matrix in the Computing-In-Memory array; a column driving module connected with bit lines of each column of the memory-computing array, configured to input bit line voltage to the bit lines of each column of the memory-computing array; q analog domain shift-accumulate modules, each connected with M source lines of each group of the memory-computing array, configured to perform weighted accumulation operation on output currents of the M source lines to obtain an analog quantity of a multiply-add calculation result of an input vector and a column of multi-bit weight; and an analog-digital conversion module configured to convert the analog quantity of the multiply-add calculation result obtained by the q analog domain shift-accumulate modules into a digital quantity.

[0005] Optionally, bit positions of M-bit weight of each group of M columns of the memory-computing array are arranged in a manner from left to right as follows: the most significant bit (MSB) of the M-bit weight to the least significant bit (LSB) of the M-bit weight.

[0006] Optionally, the analog domain shift-accumulate module comprises: M trans-impedance amplifiers corresponding to the M columns of each group of the memory-computing array, input ends of each trans-impedance amplifier are connected to source lines of a corresponding column, feedback resistance values of the M trans-impedance amplifiers are proportional to the bit position arrangement manner of the M-bit weight, and the proportional relationship is 2 M-1 :2 M-2 :…:2 0 ; M output control switches; M output capacitors corresponding to the M trans-impedance amplifiers, first ends of each output capacitor are connected to output ends of a corresponding trans-impedance amplifier through an output control switch; M-1 parallel control switches, first ends of any two output capacitors in the M output capacitors are connected through the parallel control switch, second ends of each output capacitor are grounded, and capacitance values of each output capacitor are equal; a sampling control switch; an ADC connection switch; a sampling capacitor, a first end of the sampling capacitor is connected to a first end of an output capacitor corresponding to a column where the most significant bit (MSB) of the M-bit weight through the sampling control switch, and is connected to the analog-digital conversion module through the ADC connection switch, a second end of the sampling capacitor is grounded, and a capacitance value of the sampling capacitor is 4 times that of the output capacitor.

[0007] Optionally, the analog domain shift-accumulate module comprises: M trans-impedance amplifiers corresponding to the M columns of each group of the memory-computing array, input ends of each trans-impedance amplifier are connected to source lines of a corresponding column, feedback resistance values of the M trans-impedance amplifiers are proportional to the bit position arrangement manner of the M-bit weight, and the proportional relationship is 2 a resistance network, comprising M output resistors, M-1 connection resistors and two ground resistors, the M output resistors corresponding to the M trans-impedance amplifiers, a first end of each of the output resistors being connected to an output end of a corresponding one of the trans-impedance amplifiers, second ends of any two of the output resistors being connected through the connection resistors, a second end of an output resistor corresponding to a column in which a most significant bit (MSB) of the M-bit weight is located being connected to a ground resistor, a second end of an output resistor corresponding to a column in which a least significant bit (LSB) of the M-bit weight is located being connected to a ground resistor, a resistance ratio of the output resistors, the connection resistors and the ground resistors being 2:1:2; an output control switch; an output capacitor, a first end of the output capacitor being connected to the second end of the output resistor corresponding to the column in which the MSB of the M-bit weight is located through the output control switch, a second end of the output capacitor being grounded; a sampling control switch; an ADC connection switch; a sampling capacitor, a first end of the sampling capacitor being connected to the first end of the output capacitor through the sampling control switch and being connected to the analog-to-digital conversion module through the ADC connection switch, a second end of the sampling capacitor being grounded, a capacitance of the sampling capacitor being equal to that of the output capacitor.

[0008] Optionally, the analog-domain shift-accumulate module comprises: M trans-impedance amplifiers, corresponding to M columns of each group of the memory-compute array, an input end of each of the trans-impedance amplifiers being connected to a source line of a corresponding column, feedback resistors of the M trans-impedance amplifiers having equal resistance values; M output capacitors, corresponding to the M trans-impedance amplifiers, a first end of each of the output capacitors being connected to an output end of a corresponding one of the trans-impedance amplifiers; M parallel control switches, a first end of any two of the M output capacitors being connected through the parallel control switches, a second end of each of the output capacitors being grounded, the output capacitors having equal capacitance values; a parallel capacitor, a first end of the parallel capacitor being connected to a first end of an output capacitor corresponding to a column in which a LSB of the M-bit weight is located through one of the parallel control switches, a second end of the parallel capacitor being grounded, the parallel capacitor having a capacitance value equal to that of the output capacitor; a sampling control switch; an ADC connection switch; A sampling capacitor, a first end of the sampling capacitor is connected with a first end of an output capacitor corresponding to a column of the highest bit MSB of the M-bit weight through the sampling control switch, and is connected with the analog-digital conversion module through the ADC connection switch, a second end of the sampling capacitor is grounded, and a capacitance of the sampling capacitor is equal to that of the output capacitor.

[0009] Optionally, the storage-computing integrated chip is any one of MRAM, RRAM, PCRAM, FeFET memory, Flash, and FeRAM.

[0010] The storage-computing integrated chip provided by the application utilizes an analog domain shift accumulation module to realize a weighted accumulation operation in a multiplication and addition calculation process of a multi-bit input vector and a multi-bit weight matrix, and only one ADC quantization operation is needed to convert an analog calculation result to a digital domain, so that the number of times of using an analog-digital conversion module can be reduced, and the energy consumption of the storage-computing integrated architecture can be reduced. On the other hand, the analog domain shift accumulation module reduces the requirement for the number of ADCs, improves the calculation parallelism of the storage-computing integrated architecture, and is beneficial to reducing the chip area. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 FIG. 1 is a schematic diagram of the overall structure of a storage-computing integrated chip according to an embodiment of the application; Figure 2 FIG. 2 is a schematic diagram of a storage-computing array of p rows (q*M) columns storing an M-bit weight matrix according to an embodiment of the application; Figure 3 FIG. 3 is a schematic diagram of the circuit structure of an analog domain shift accumulation module adopted by one column of a 4-bit weight matrix according to an embodiment of the application; Figure 4 FIG. 4 is a schematic diagram of the circuit structure of an analog domain shift accumulation module adopted by one column of a 4-bit weight matrix according to another embodiment of the application; Figure 5 FIG. 5 is a schematic diagram of the circuit structure of an analog domain shift accumulation module adopted by one column of a 4-bit weight matrix according to still another embodiment of the application. DETAILED DESCRIPTION

[0012] To make the objectives, technical solutions, and advantages of the embodiments of the application clearer, the technical solutions in the embodiments of the application will be described below in conjunction with the drawings of the embodiments of the application. Obviously, the described embodiments are only a part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the application.

[0013] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0014] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0015] This invention proposes a memory computing chip, such as... Figure 1 As shown, this in-memory computing chip is suitable for performing multiplication and addition calculations on an N-bit input vector and an M-bit weight matrix. The N-bit input vector includes p N-bit input data points, and the M-bit weight matrix has a size of p rows and q columns, where p ≥ 1, q ≥ 1, N ≥ 1, and M ≥ 1. The in-memory computing chip includes: The storage array 101 includes at least p rows (q*M) columns. The (q*M) columns are divided into q groups, each group including M columns. The M columns of each group are used to store the weights of one column of the M-bit weight matrix bit by bit. The storage array 101 is also used to implement the multiplication and addition calculation of the N-bit input vector and the M-bit weight matrix. The result of the multiplication and addition calculation is represented by the output current of each column source line. The row driver module 102 is connected to the word lines of each row of the memory array 101. It is used to convert the N-bit input vector into voltage pulse form and input it to the word lines of each row of the memory array 101 in a periodic manner so as to realize the multiplication and addition calculation of the N-bit input vector and the M-bit weight matrix in the memory array 101. The column driver module 103 is connected to the bit lines of each column of the memory array 101 and is used to input the bit line voltage to the bit lines of each column of the memory array 101. There are q analog domain shift-accumulator modules 1041, ..., 104q. Each analog domain shift-accumulator module is connected to M columns of source lines in each group of the storage array 101. It is used to perform weighted accumulation operation on the output current of the M columns of source lines to obtain the analog quantity of the input vector and a column of multi-bit weighted multiplication and addition calculation results. as well as, The analog-to-digital conversion module 105 is used to convert the analog quantity of the multiplication-accumulation calculation result into a digital quantity.

[0016] The storage-computation integrated chip provided by the embodiment of the application realizes the weighted accumulation operation in the multiplication and addition calculation process of the multi-bit input vector and the multi-bit weight matrix by using the analog domain shift accumulation module, and only one ADC quantization operation is needed to convert the analog calculation result to the digital domain, which can reduce the use frequency of the analog-digital conversion module and reduce the energy consumption of the storage-computation integrated architecture. On the other hand, the analog domain shift accumulation module reduces the requirement for the number of ADCs, improves the calculation parallelism of the storage-computation integrated architecture, and is beneficial to reducing the chip area.

[0017] Figure 2 A specific implementation of storing an M-bit weight matrix by a p-row (q*M-column) storage-computation array is shown. Figure 2 As shown in the figure, the M-column storage of each group of the storage-computation array 101 stores the bit arrangement of the M-bit weight in the following manner: the most significant bit (MSB) of the M-bit weight to the least significant bit (LSB) of the M-bit weight is arranged in sequence from left to right.

[0018] Suppose that each cell of the storage-computation array can store K (K>=1) bits of weight information, then an M (M>=1) bit weight is stored in column storage cells in the array (ceil(M / K), where ceil is the ceiling function). For simplicity of description, one storage cell stores one bit of weight information.

[0019] The row driving module 102 converts the input vector into a pulse form (pulse width, height, etc.), and suppose that P (P>=1) bits of information of an N (N>=1) bit input vector are input per cycle. Then one N-bit input vector needs to be divided into cycles (ceil(N / P), where ceil is the ceiling function). For simplicity of description, one cycle inputs one bit of information of an N-bit input vector.

[0020] In one calculation process of an N-bit input vector and an M-bit weight matrix, the analog domain shift accumulation module needs to complete * shift accumulation operations (M, N, P, and K are positive values, and ceil is the ceiling function).

[0021] The analog domain shift accumulation module 1041,..., 104q is described in detail below.

[0022] For ease of understanding, multiplication and addition calculation of a 4 (N=4) bit input vector and a 4 (M=4) bit weight matrix is taken as an example, and the input vector includes 4 input data, and the size of the weight matrix is 4 rows and 4 columns. In each input cycle, one bit of data of the 4-bit input vector is input to the storage-computation array, and each storage cell stores one bit of weight information. ​

[0023] Figure 3 An implementation of the storage of 4 4-bit weights is shown. It can be understood that the 4 4-bit weights are only the first column of a 4x4 weight matrix. Correspondingly, the specific circuit structure of the analog-domain shift-and-accumulate module 1041 shown matches the first column of a M-bit weight matrix. The structures of the analog-domain shift-and-accumulate modules of the remaining columns are the same, just extended.

[0024] As an implementation, as shown in Figure 3 The analog-domain shift-and-accumulate module 1041 includes: 4 trans-impedance amplifiers T10-T13, which correspond to 4 columns of the storage of 4-bit weights in the in-memory computing array, for example, T10 corresponds to the column of the least significant bit (LSB, i.e., the 0th bit) of the 4-bit weights, T11 corresponds to the column of the 1st bit of the 4-bit weights, T12 corresponds to the column of the 2nd bit of the 4-bit weights, and T13 corresponds to the column of the most significant bit (MSB, i.e., the 3rd bit) of the 4-bit weights. The input terminals of T10-T13 are respectively connected to the source lines of the corresponding columns of the in-memory computing array. The feedback resistances of T10-T13 are proportional to the bit arrangement of the 4-bit weights, that is, the feedback resistance of T10 is R, the feedback resistance of T11 is 2R, the feedback resistance of T12 is 4R, and the feedback resistance of T13 is 8R. 4 output control switches S10, S11, S12, and S13. 4 output capacitors C10-C13, which correspond to T10-T13. The first terminal of C10 is denoted as node A, the first terminal of C11 is denoted as node B, the first terminal of C12 is denoted as node C, and the first terminal of C13 is denoted as node D. Nodes A, B, C, and D are respectively connected to the output terminals of T10-T13 through switches S10-S13, that is, the output signals of T10, T11, T12, and T13 are controlled by S10, S11, S12, and S13, and are respectively connected to nodes A, B, C, and D. 3 parallel control switches S14, S15, and S16, which are respectively connected between nodes A and B, B and C, and C and D. The second terminals of C10-C13 are grounded, and the capacitances of C10-C13 are equal, that is, C10=C11=C12=C13=C. A sampling control switch S17. An ADC connection switch S18. A sampling capacitor Csamp1, a first end of Csamp1 is denoted as node E, node E is connected with node D through S17, node E is also connected with an analog-digital conversion module through S18, a second end of Csamp1 is grounded, the capacitance of the sampling capacitor is 4 times of the output capacitor, Csamp1 =4C.

[0025] The analog domain shift accumulation module adopts trans-impedance amplifiers (TIAs) with different feedback resistances, and combines with sampling capacitors to realize weighted accumulation of different weight column results.

[0026] Further referring to Figure 3 , the working process is as follows: in the input period of each bit of the input vector, the output current of each column of the array is converted into voltage through a TIA, and shift accumulation is completed through a capacitor network. Taking 4-bit weight as an example, the 4-bit weight is stored in 4 columns of 4 1-bit storage units, the TIA feedback resistance corresponding to the storage of the lowest bit is R, the TIA feedback resistance corresponding to the storage of the second bit is 2R, the TIA feedback resistance corresponding to the storage of the third bit is 4R, and the TIA feedback resistance corresponding to the storage of the highest bit is 8R. For a 4-bit input vector, it is input in four periods. The initial charge of the sampling capacitor Csamp1 is 0.

[0027] In the input period of the lowest bit of the input vector, S10-S13 are turned on, and the voltage converted through the TIA is stored in the output capacitor C10-C13 of each column. Then S10-S13 are turned off, S14-S17 are turned on, and C10-C13 share the charge with the sampling capacitor Csamp1. The voltage value of Csamp1 is also the calculation result of the input period of the lowest bit: = + + . S14-S17 are turned off.

[0028] The input periods of other bits are similar, and the calculation results of different input periods can be obtained.

[0029] The calculation result of the input period of the second bit is: = + + . The voltage value of Csamp1 changes from to + .

[0030] The calculation result of the input period of the third bit is: = + + . The voltage value of Csamp1 changes from + , becomes + + .

[0031] The calculation result of the input period of the highest bit: = + + . The voltage value of Csamp1 is changed to + + , becomes + + + .

[0032] When all the bits of the input vector are sent into the storage and calculation array, the voltage value on Csamp1 is the total multiplication and addition result of the input vector and the weight matrix: . Start S18 to connect Csamp1 to ADC, and finally complete the analog-to-digital conversion.

[0033] Figure 3 The analog domain shift accumulation module shown, the results between different input periods are weighted and accumulated in the proportion of 1:2:4:8, and the different columns of the storage and calculation array are weighted and accumulated in the proportion of 1:2:4:8. By adjusting the feedback resistance ratio of the transimpedance amplifier, and the capacitances C10, C11, C12, C13, and Csamp1, other proportional weighted accumulation can be realized.

[0034] Extending the above 4-bit weight analog domain shift accumulation module structure to M-bit weight, the M-bit weight analog domain shift accumulation module includes: M transimpedance amplifiers corresponding to each group of M columns of the storage and calculation array, the input end of each transimpedance amplifier is connected to the source line of the corresponding column, and the feedback resistance values of the M transimpedance amplifiers are proportional to the bit arrangement mode of the M-bit weight, and the proportional relationship is 2 M-1 :2 M-2 :…:2 0 ; M output control switches; M output capacitors corresponding to the M transimpedance amplifiers, the first end of each output capacitor is connected to the output end of the corresponding transimpedance amplifier through an output control switch; M-1 parallel control switches, any two of the M output capacitors are connected through the parallel control switches, the second end of each output capacitor is grounded, and the capacitance of each output capacitor is equal; a sampling control switch; an ADC connection switch; a sampling capacitor, a first end of the sampling capacitor is connected to a first end of an output capacitor corresponding to a column of the highest bit MSB of the M-bit weight through the sampling control switch, and connected to an analog-to-digital conversion module through the ADC connection switch, a second end of the sampling capacitor is grounded, and the capacitance of the sampling capacitor is 4 times that of the output capacitor.

[0035] Figure 4 An implementation of storing 4 4-bit weights by the in-memory computing array is shown. It can be understood that the 4 4-bit weights are only the first column of a 4x4 weight matrix. Correspondingly, the specific circuit structure of the analog domain shift and accumulation module 1041 shown matches the first column of the M-bit weight matrix. The structures of the analog domain shift and accumulation modules of the remaining columns are the same, which only need to be expanded.

[0036] As an implementation, as shown in Figure 4 the analog domain shift and accumulation module 1041 includes: 4 trans-impedance amplifiers T20-T23, T20-T23 correspond to 4 columns of the in-memory computing array for storing 4-bit weights, for example, T20 corresponds to the column of the lowest bit LSB (i.e. the 0th bit) of the 4-bit weight, T21 corresponds to the column of the 1st bit of the 4-bit weight, T22 corresponds to the column of the 2nd bit of the 4-bit weight, and T23 corresponds to the column of the highest bit MSB (i.e. the 3rd bit) of the 4-bit weight, the input ends of T20-T23 are respectively connected to the source lines of the corresponding columns of the in-memory computing array, and the feedback resistances of T20-T23 are equal, all being R1; a resistance network including 4 output resistors R20-R23, 3 connection resistors R24, R25, R26 and 2 ground resistors R27, R28, the 4 output resistors correspond to the 4 trans-impedance amplifiers T20-T23, the first ends of R20-R23 are respectively connected to the output ends of the corresponding T20-T23, the second end of R20 is denoted as node A, the second end of R21 is denoted as node B, the second end of R22 is denoted as node C, and the second end of R23 is denoted as node D, then nodes A and B, B and C, and C and D are respectively connected through connection resistors R24, R25, and R26, node D is grounded through resistor R27, and node A is grounded through resistor R28, the resistance ratio relationship of the output resistors R20-R23, the connection resistors R24, R25, R26, and the ground resistors R27, R28 is 2:1:2; an output control switch S21; An output capacitor C21, a first end of C21 is connected to node D through switch S21, and a second end of C21 is grounded; A sampling control switch S22, an ADC connection switch S23, and a sampling capacitor Csamp2. A first end of Csamp2 is denoted as node E, node E is connected to the first end of C21 through S22, and node E is also connected to the analog-digital conversion module through S23. A second end of Csamp2 is grounded. The capacitance of the sampling capacitor is equal to that of the output capacitor, Csamp1 = C21 = C.

[0037] The above-described analog-domain shift-accumulation module adopts a trans-impedance amplifier (TIA) with equal feedback resistors, and combines a resistor network to achieve weighted accumulation of results of different weight columns.

[0038] Further reference Figure 4 is made to the following: in each bit input period of the input vector, the output current of each column of the array is converted into voltage through the TIA, and shift-accumulation is completed through the resistor and capacitor network. Taking 4-bit weight as an example, the 4-bit weight is stored in 4 1-bit storage units in 4 columns, and the feedback resistors of the four columns of TIA are all R1. For a 4-bit input vector, the input is divided into four periods. The initial charge of Csamp2 is 0.

[0039] In the input period of the lowest bit of the input vector, S21 is opened, and S22 and S23 are closed. The lowest bit of the input vector is input into the storage- calculation array, and the output current of the 4 columns of weight passes through the four TIAs T20-T23. The output voltage is After passing through the resistor network, the voltage at node D is: Then S21 and S23 are closed, and S22 is opened. Capacitor C21 and Csamp2 complete charge sharing, and the voltage on the sampling capacitor Csamp2 is: = .

[0040] The input periods of other bits are similar, and the voltages on Csamp2 in different input periods can be obtained.

[0041] The voltage on Csamp2 in the input period of the second bit is: = + .

[0042] The voltage on Csamp2 in the input period of the third bit is: = + .

[0043] The voltage on Csamp2 in the input period of the highest bit is:

[0044] When all the bits of the input vector are sent into the array, the voltage value on Csamp2 is 1 / 6 of the total multiplication and addition result of the input vector and the weight matrix: S23 is turned on and S21 and S22 are turned off, Csamp2 is connected to the ADC, and the analog-to-digital conversion is finally completed.

[0045] Figure 4 The analog domain shift accumulation module shown, the results between different input periods are weighted and accumulated in a ratio of 1:2:4:8, and the storage and calculation arrays between different columns are weighted and accumulated in a ratio of 1:2:4:8. By adjusting the resistance values of the resistance network or the capacitances C21 and Csamp2, other ratios of weighted accumulation can be achieved.

[0046] Extending the analog domain shift accumulation module structure of the above 4-bit weight to M-bit weight, the analog domain shift accumulation module of M-bit weight includes: M transimpedance amplifiers corresponding to M columns of each group of the storage and calculation array, the input end of each transimpedance amplifier is connected to the source line of the corresponding column, and the feedback resistances of the M transimpedance amplifiers are equal in value; a resistance network including M output resistors, M-1 connection resistors, and two ground resistors, the M output resistors correspond to the M transimpedance amplifiers, the first end of each output resistor is connected to the output end of the corresponding transimpedance amplifier, the second ends of any two output resistors are connected through a connection resistor, the second end of the output resistor corresponding to the column of the most significant bit MSB of the M-bit weight is connected to a ground resistor, the second end of the output resistor corresponding to the column of the least significant bit LSB of the M-bit weight is connected to a ground resistor, and the resistance ratio relationship of the output resistor, the connection resistor, and the ground resistor is 2:1:2; an output control switch; an output capacitor, the first end of the output capacitor is connected to the second end of the output resistor corresponding to the column of the most significant bit MSB of the M-bit weight through the output control switch, and the second end of the output capacitor is grounded; a sampling control switch; an ADC connection switch; a sampling capacitor, the first end of the sampling capacitor is connected to the first end of the output capacitor through the sampling control switch and connected to the analog-to-digital conversion module through the ADC connection switch, and the second end of the sampling capacitor is grounded, and the capacitance of the sampling capacitor is equal to that of the output capacitor.

[0047] Figure 5 ​​An implementation of the in-memory computing array storing 4 4-bit weights is shown. It can be understood that the 4 4-bit weights are only the first column of a 4x4 weight matrix. Correspondingly, the specific circuit structure of the analog-domain shift-and-accumulate module 1041 matches the first column of a M-bit weight matrix. The structures of the analog-domain shift-and-accumulate modules for the rest columns are the same, just need to be extended.

[0048] As an implementation, as shown in FIG. 4, the analog-domain shift-and-accumulate module 1041 includes: Figure 5 4 trans-impedance amplifiers T30-T33, which correspond to 4 columns of the in-memory computing array for storing 4-bit weights, for example, T30 corresponds to the column of the least significant bit (LSB, i.e., the 0th bit) of the 4-bit weights, T31 corresponds to the column of the 1st bit of the 4-bit weights, T32 corresponds to the column of the 2nd bit of the 4-bit weights, and T33 corresponds to the column of the most significant bit (MSB, i.e., the 3rd bit) of the 4-bit weights. The input terminals of T30-T33 are respectively connected to the source lines of the corresponding columns of the in-memory computing array, and the feedback resistances of T30-T33 are equal, all being R. 4 output capacitors C31-C34, which correspond to T30-T33, and the first terminals of C31-C34 are respectively connected to the output terminals of T30-T33. 4 parallel control switches S30-S33, the first terminal of C31 is denoted as node A, the first terminal of C32 is denoted as node B, the first terminal of C33 is denoted as node C, and the first terminal of C34 is denoted as node D. Node A and B, B and C, and C and D are respectively connected through switches S31, S32, and S33. The second terminals of C31-C34 are grounded, and the capacitances of C31-C34 are equal. A parallel capacitor C30, the first terminal of C30 is connected to node A through switch S30, and the second terminal of C30 is grounded. The capacitance of C30 is the same as that of C31-C34. A sampling control switch S34. An ADC connection switch S35. A sampling capacitor Csamp3, the first terminal of Csamp3 is denoted as node E, node E is connected to node D through S34, and node E is also connected to an analog-to-digital conversion module through S35. The second terminal of Csamp3 is grounded, and the capacitance of the sampling capacitor is equal to that of the output capacitor. The capacitances of C30, C31, C32, C33, C34, and Csamp3 are equal.

[0049] The above analog-domain shift-and-accumulate module alternately opens the switches, uses a trans-impedance amplifier (TIA) with equal feedback resistances, and combines multiple equal sampling capacitors to achieve weighted accumulation of results of different weight columns.

[0050] Further reference​Figure 5 The working process is as follows: in the input period of each bit of the input vector, the output current of each column of the array is converted into voltage through the TIA, and the shift accumulation is completed through the switch and the capacitor network. Taking 4-bit weight as an example, the weight is stored in 4 one-bit storage units of 4 columns, and the feedback resistances of the four column TIAs are all R. For a 4-bit input vector, the input is divided into four periods. The initial charge of Csamp3 is 0.

[0051] In the input period of the lowest bit of the input vector, the lowest bit of the input vector is sent into the storage and calculation array, and the output current of the 4-column weight is output through the four TIAs T30-T33, and the output voltage is The switches S30-S34 are opened from right to left in turn, and the voltage on the sampling capacitor Csamp3 is: After that, all the capacitors except Csamp3 need to be discharged, and enter the next input period.

[0052] When all the bits of the input vector are sent into the storage and calculation array, the voltage value on Csamp3 is the total multiplication and addition result of the input vector and the weight matrix: S35 is opened to connect Csamp3 to the ADC, and the analog-to-digital conversion is finally completed.

[0053] Figure 5 The analog domain shift accumulation module shown is weighted and accumulated according to the ratio of 1:2:4:8 between different input periods, and the storage and calculation array is weighted and accumulated according to the ratio of 1:2:4:8 between different columns. By adjusting the capacitances C31, C32, C33, C34 and Csamp3, other ratios of weighted accumulation can be realized.

[0054] The structure of the above 4-bit weight analog domain shift accumulation module is extended to M-bit weight, and the M-bit weight analog domain shift accumulation module includes: M transimpedance amplifiers corresponding to M columns of each group of the storage and calculation array, the input end of each transimpedance amplifier is connected to the source line of the corresponding column, and the feedback resistances of the M transimpedance amplifiers are equal in value; M output capacitors corresponding to the M transimpedance amplifiers, the first end of each output capacitor is connected to the output end of the corresponding transimpedance amplifier; M parallel control switches, the first ends of any two output capacitors in the M output capacitors are connected through the parallel control switch, the second end of each output capacitor is grounded, and the capacitance values of the output capacitors are equal; The first end of the parallel capacitor is connected with the first end of the output capacitor corresponding to the column of the lowest bit LSB of the M-bit weight through a parallel control switch, the second end of the parallel capacitor is grounded, and the capacitance of the parallel capacitor is equal to that of the output capacitor; A sampling control switch; An ADC connection switch; A sampling capacitor, the first end of the sampling capacitor is connected with the first end of the output capacitor corresponding to the column of the highest bit MSB of the M-bit weight through the sampling control switch, and is connected with the analog-digital conversion module through the ADC connection switch, the second end of the sampling capacitor is grounded, and the capacitance of the sampling capacitor is equal to that of the output capacitor.

[0055] The above embodiments give several circuit structures of the analog domain shift accumulation module, but are not limited thereto.

[0056] In addition, it should be explained that the storage-computing integrated chip in the embodiments of the present application can be any one of MRAM, RRAM, PCRAM, FeFET memory, Flash and FeRAM.

[0057] Finally, it should be explained that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory computing chip, characterized in that, This is suitable for performing multiplication and addition calculations on an N-bit input vector and an M-bit weight matrix. The N-bit input vector includes p N-bit input data points, and the M-bit weight matrix has a size of p rows and q columns, where p ≥ 1, q ≥ 1, N ≥ 1, and M ≥ 1. The in-memory computing chip includes: The storage array includes at least p rows (q*M) columns, the (q*M) columns are divided into q groups, each group includes M columns, and the M columns of each group are used to store the weights of one column of the M-bit weight matrix bit by bit. The storage array is also used to implement the multiplication and addition calculation of the N-bit input vector and the M-bit weight matrix. The result of the multiplication and addition calculation is represented by the output current of each column source line of the storage array. The row driving module is connected to the word lines of each row of the memory array and is used to convert the N-bit input vector into voltage pulses and input them to the word lines of each row of the memory array periodically, so as to realize the multiplication and addition calculation of the N-bit input vector and the M-bit weight matrix in the memory array. The column driving module is connected to the bit lines of each column of the memory array and is used to input the bit line voltage to the bit lines of each column of the memory array. q analog domain shift-accumulator modules, each of which is connected to M columns of source lines in each group of the memory array, are used to perform weighted accumulation operation on the output current of the M columns of source lines to obtain an analog quantity of the input vector and a column of multi-bit weighted multiplication and addition calculation results; as well as, The analog-to-digital conversion module is used to convert the analog quantities of the multiplication and addition calculation results obtained by the q analog domain shift and accumulation modules into digital quantities.

2. The in-memory computing chip according to claim 1, characterized in that, The M columns of the storage array store the M-bit weights in the following arrangement: the most significant bit (MSB) to the least significant bit (LSB) of the M-bit weights are arranged from left to right.

3. The in-memory computing chip according to claim 1, characterized in that, The analog domain shift-accumulation module includes: M transimpedance amplifiers, corresponding to the M columns of each group of the memory array, with the input terminal of each transimpedance amplifier connected to the source line of the corresponding column. The feedback resistor values ​​of the M transimpedance amplifiers are proportional according to the bit arrangement of the M-bit weights, with a ratio of 2:

1. M-1 :2 M-2 :...:2 0 ; M output control switches; M output capacitors, corresponding to the M transimpedance amplifiers, with the first terminal of each output capacitor connected to the output terminal of the corresponding transimpedance amplifier via an output control switch; M-1 parallel control switches are used, and the first terminals of any two of the M output capacitors are connected through the parallel control switches. The second terminal of each output capacitor is grounded, and the capacitance value of each output capacitor is equal. Sampling control switch; ADC connection switch; The sampling capacitor has its first terminal connected to the first terminal of the output capacitor corresponding to the column where the most significant bit (MSB) of the M-bit weight is located via the sampling control switch, and is also connected to the analog-to-digital conversion module via the ADC connection switch. The second terminal of the sampling capacitor is grounded, and the capacitance value of the sampling capacitor is 4 times that of the output capacitor.

4. The in-memory computing chip according to claim 1, characterized in that, The analog domain shift-accumulation module includes: M transimpedance amplifiers, corresponding to M columns in each group of the memory array, with the input terminal of each transimpedance amplifier connected to the source line of the corresponding column, and the feedback resistor values ​​of the M transimpedance amplifiers being equal; The resistor network includes M output resistors, M-1 connection resistors, and two grounding resistors. The M output resistors correspond to the M transimpedance amplifiers. The first end of each output resistor is connected to the output end of the corresponding transimpedance amplifier. The second ends of any two output resistors are connected through the connection resistors. The second end of the output resistor corresponding to the column where the most significant bit (MSB) of the M-bit weight is located is grounded through a grounding resistor. The second end of the output resistor corresponding to the column where the least significant bit (LSB) of the M-bit weight is located is grounded through a grounding resistor. The ratio of the resistance values ​​of the output resistors, connection resistors, and grounding resistors is 2:1:

2. Output control switch; An output capacitor, the first terminal of which is connected to the second terminal of the output resistor corresponding to the column where the most significant bit (MSB) of the M-bit weight is located via the output control switch, and the second terminal of the output capacitor is grounded. Sampling control switch; ADC connection switch; A sampling capacitor is provided, the first end of which is connected to the first end of the output capacitor via the sampling control switch and to the analog-to-digital conversion module via the ADC connection switch. The second end of the sampling capacitor is grounded, and the capacitance value of the sampling capacitor is equal to that of the output capacitor.

5. The in-memory computing chip according to claim 1, characterized in that, The analog domain shift-accumulation module includes: M transimpedance amplifiers, corresponding to M columns in each group of the memory array, with the input terminal of each transimpedance amplifier connected to the source line of the corresponding column, and the feedback resistor values ​​of the M transimpedance amplifiers being equal; M output capacitors, corresponding to the M transimpedance amplifiers, with the first terminal of each output capacitor connected to the output terminal of the corresponding transimpedance amplifier; M parallel control switches are used, and the first terminals of any two of the M output capacitors are connected through the parallel control switches. The second terminal of each output capacitor is grounded, and the capacitance value of each output capacitor is equal. A parallel capacitor is provided, wherein the first terminal of the parallel capacitor is connected to the first terminal of the output capacitor corresponding to the column where the least significant bit (LSB) of the M-bit weight is located through a parallel control switch, the second terminal of the parallel capacitor is grounded, and the capacitance value of the parallel capacitor is equal to that of the output capacitor. Sampling control switch; ADC connection switch; The sampling capacitor has its first terminal connected to the first terminal of the output capacitor corresponding to the column where the most significant bit (MSB) of the M-bit weight is located via the sampling control switch, and connected to the analog-to-digital conversion module via the ADC connection switch. The second terminal of the sampling capacitor is grounded, and the capacitance value of the sampling capacitor is equal to that of the output capacitor.

6. The in-memory computing chip according to claim 1, characterized in that, The in-memory computing chip is any one of MRAM, RRAM, PCRAM, FeFET memory, Flash, and FeRAM.

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