Test board and test system for solid state disk

Abstract

The invention discloses a test board and a test system for a solid state disk. A first end of a first interface is used for connecting a test host, and a second end is connected with a first end of a switching chip; the second end of the switching chip is connected with the first end of the channel switching module; the first end of the control module is connected with the second end of the channel switching module; the third end of the channel switching module is connected with the first group of pins of the second interface, and the fourth end is connected with the second group of pins of the second interface; the first group of pins and the second group of pins of the second interface are respectively used for connecting an input channel and an output channel of the solid state disk; the control module is used for sending a first control signal to the channel switching module, so that the third end of the channel switching module is communicated with the fourth end, and sending a second control signal to the channel switching module, so that the channel switching module is communicated with the switching chip; and the switching chip is used for performing bidirectional protocol conversion between the first interface and the second interface when the channel switching module is connected with the switching chip. The test efficiency of the solid state disk can be improved.

Description

Technical Field

[0001] This application relates to the field of test control technology, specifically to a test board and test system for a solid-state drive. Background Technology

[0002] Before PCI Express (PCIe) storage devices like solid-state drives (SSDs) can be developed, validated, and mass-produced, they typically require PCIe physical layer testing, such as link speed and bandwidth, and error rate. In current technology, a common practice is to directly insert the SSD under test into a device slot (such as a PCIe / M.2 slot) on the motherboard of the test host (PC). The test host then runs the appropriate tools to perform the tests and saves the results on the test host for subsequent analysis.

[0003] However, some test host motherboards lack the hardware and firmware support required for PCIe hot-swapping. For test hosts that do not support hot-swapping, replacing the hard drive under test usually requires shutting down and disconnecting the power, removing the original hard drive, inserting the new hard drive, and finally powering on the test host. Frequent shutdowns / restarts can easily prolong test time and reduce test efficiency. Summary of the Invention

[0004] In view of this, this application provides a test board and test system for solid-state drives (SSDs) to solve the problem of low efficiency in traditional SSD testing solutions.

[0005] This application provides a solid-state drive (SSD) test board, which includes a first interface, a control module, an adapter chip, a channel switching module, and a second interface, wherein the first interface is a hot-swappable interface. The first end of the first interface is used to connect to the test host, and the second end is connected to the first end of the adapter chip; the second end of the adapter chip is connected to the first end of the channel switching module; the first end of the control module is connected to the second end of the channel switching module; the third end of the channel switching module is connected to the first set of pins of the second interface, and the fourth end is connected to the second set of pins of the second interface; the first set of pins and the second set of pins of the second interface are respectively used to connect to the input channel and output channel of the solid-state drive. The control module is used to send a first control signal to the channel switching module to connect the third terminal of the channel switching module to the fourth terminal; it is also used to send a second control signal to the channel switching module to connect the adapter chip. The adapter chip is used to perform bidirectional protocol conversion between the first interface and the second interface when the channel switching module is turned on.

[0006] Optionally, the solid-state drive test board further includes a hub; the first end of the hub is connected to the second end of the first interface, the second end is connected to the first end of the adapter chip, and the third end is connected to the second end of the control module; the hub is used to establish a first communication link between the test host and the adapter chip and a second communication link between the test host and the control module.

[0007] Optionally, the second interface is a hot-pluggable interface.

[0008] Optionally, the second interface includes multiple test channels between the first group of pins and the second group of pins, and each test channel is implemented using a multiplexer; the channel switching module includes multiplexers corresponding to each of the test channels.

[0009] This application also provides a solid-state drive (SSD) testing system, including a test host, an SSD, and a test board for any of the above-mentioned SSDs; The test host is used to send a first command and a second command to the control module; The control module responds to the first command from the test host by sending a first control signal to the channel switching module; the solid-state drive responds to the third terminal of the channel switching module being connected to the fourth terminal by sending test data to the test board through the output channel and receiving feedback data from the test board through the input channel, comparing the test data and the feedback data to obtain the test result; The control module responds to the second command from the test host by sending a second control signal to the channel switching module; the solid-state drive is also used to send the test results to the test host when the channel switching module connects the adapter chip.

[0010] Optionally, the hub is further configured to send new device access information to the test host after identifying the solid-state drive connected to the second interface via the first communication link; the test host receives the new device access information and sends the first command to the control module via the second communication link.

[0011] Optionally, the test host sends a first command to the control module, and after a preset time interval, sends a second command to the control module.

[0012] Optionally, the control module further includes a third terminal, the second interface further includes a first setting pin, and the solid-state drive further includes a second setting pin. The third terminal of the control module is connected to the first setting pin of the second interface. The control module is further configured to send test completion information to the test host after updating the level at the first setting pin of the second interface. In response to the test completion information, the test host sends a second command to the control module. The solid-state drive is configured to update the level signal of the second setting pin after completing the test, so as to update the level at the first setting pin connected to the second setting pin in the second interface.

[0013] Optionally, the adapter chip is used to convert the received test results into data matching the first interface after the channel switching module is turned on, and send the converted test results to the test host through the first communication link.

[0014] Optionally, after the solid-state drive sends the test results to the test host, the test host sends a third command to the adapter chip; in response to the third command, the adapter chip sends communication status data between the solid-state drive and the adapter chip to the test host; the test host is further configured to analyze the communication status data to determine the quality of the input channel and / or output channel of the solid-state drive.

[0015] In the solid-state drive (SSD) test board and test system described in this application, the control module sends a first control signal to the channel switching module, causing the third terminal of the channel switching module to connect to its fourth terminal, thus constructing a self-test loop in the SSD. The SSD performs testing through this self-test loop and obtains test results. The control module can also send a second control signal to the channel switching module, causing the channel switching module to connect to the adapter chip, establishing a connection path between the SSD and the test host, uploading the test results to the test host, and completing the test of the SSD currently inserted into the second interface. The entire test process is automatically executed according to the first and second control signals sent by the control module, which can improve the testing efficiency of the SSD. Furthermore, the first and / or second interfaces can also have hot-swappable features, allowing the SSD to be directly unplugged after completing the test of one SSD and plugged in for the next test, enabling rapid replacement of the SSD under test, which can further improve the testing efficiency. Therefore, the aforementioned SSD test board can improve the testing efficiency of SSDs in multiple ways. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the test system structure of a solid-state drive according to an embodiment of this application; Figure 2 This is a schematic diagram of the test board structure of a solid-state drive according to an embodiment of this application; Figure 3 This is a schematic diagram of the test board structure of a solid-state drive according to another embodiment of this application; Figure 4 This is a schematic diagram of the connection between an SSD and a multiplexer according to an embodiment of this application; Figure 5 This is a schematic diagram of the connection between an SSD and a multiplexer according to another embodiment of this application; Figure 6 This is a schematic diagram of the test system structure of a solid-state drive according to an embodiment of this application; Figure 7 This is a schematic diagram of a test system structure for a solid-state drive according to another embodiment of this application. Detailed Implementation

[0018] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0019] This application provides a test board for a solid-state drive (SSD), which can be installed in an SSD testing system. (Reference) Figure 1 As shown, the solid-state drive (SSD) testing system may include components such as a test host 210, an SSD test board 100, and an SSD under test (also referred to as a hard drive under test or SSD, etc.) 220. The test host 210 can send test commands to the SSD test board 100 to control the SSD test board 100 and the SSD 220 to perform test operations. The test host 210 may include a computer or other intelligent control terminal.

[0020] refer to Figure 2As shown, the solid-state drive test board 100 includes a first interface 110, a control module 120, an adapter chip 130, a channel switching module 140, and a second interface 150. The first interface 110 is a hot-swappable interface, including an interface that matches the test host 210, such as a USB (Universal Serial Bus) interface. The second interface 150 can be an interface that matches the solid-state drive 220, such as a PCIe (High-Speed ​​Peripheral Component Interconnect) interface for inserting the solid-state drive 220.

[0021] The first end of the first interface 110 is used to connect to the test host 210, and the second end of the first interface 110 is connected to the first end of the adapter chip 130. The second end of the adapter chip 130 is connected to the first end of the channel switching module 140. The first end of the control module 120 is connected to the second end of the channel switching module 140; the third end of the channel switching module 140 is connected to the first set of pins of the second interface 150, and the fourth end of the channel switching module 140 is connected to the second set of pins of the second interface 150. The first set of pins of the second interface 150 and the second set of pins of the second interface 150 are respectively used to connect to the input channel and output channel of the solid-state drive (SSD). When the SSD 220 under test is connected to the second interface 150, its first set of pins and second set of pins are connected through the channel switching module 140. The connected first set of pins and second set of pins enable the SSD 220 to form a self-test loop. The SSD 220 can send test data to the test board 100 through its output channel and receive feedback data from the test board 100 through its input channel. By comparing the test data and the feedback data, the test result is obtained, thereby testing the SSD 220.

[0022] The control module 120 sends a first control signal to the channel switching module 140, causing the third terminal of the channel switching module 140 to connect to its fourth terminal. At this time, the first set of pins of the second interface 150 connects to its second set of pins, forming a self-test loop in the currently connected solid-state drive 220. The control module 120 also sends a second control signal to the channel switching module 140, causing the third terminal of the channel switching module 140 to connect to its first terminal. The channel switching module 140 connects to the adapter chip 130, and the channel switching module 140 connects to the test host 210 through the adapter chip 130 and the first interface 110. That is, the solid-state drive 220 connected to the second interface 150 is connected to the test host 210, and the test host 210 can obtain test results from the solid-state drive 220.

[0023] Optionally, the control module 120 can be implemented using a chip such as an MCU. In practical applications, the control module 120 can also be connected to the test host 210 and, in response to the test command (such as the first command) of the test host 210, send a first control signal to the channel switching module 140 to connect the third terminal of the channel switching module 140 to its fourth terminal, thus constructing a self-test loop in the solid-state drive 220; the control module 120 can also, in response to the result upload command (such as the second command) of the test host 210, send a second control signal to the channel switching module 140 to connect the adapter chip 130, thus constructing a connection path between the solid-state drive 220 and the test host 210.

[0024] The adapter chip 130 is used to perform bidirectional protocol conversion between the first interface 110 and the second interface 150 when the third terminal of the channel switching module 140 is connected to the second terminal of the adapter chip 130, so that the test host 210 and the solid-state drive 22 can communicate stably and reliably. Specifically, the adapter chip 130 can convert data (such as USB data) sent by the test host 210 through the first interface 110 to data (such as PCIe data) that matches the second interface 150, for example, converting the relevant commands sent by the test host 210 into data that can be directly read by the solid-state drive 220, etc.; the adapter chip 130 can also convert the data corresponding to the solid-state drive 220 into data that matches the first interface 110, for example, converting the test results of the solid-state drive 220 into data that can be directly read by the test host 210, etc.

[0025] In the aforementioned solid-state drive (SSD) test board 100, the control module 120 sends a first control signal to the channel switching module 140, causing the third terminal of the channel switching module 140 to connect to its fourth terminal, thus constructing a self-test loop in the SSD 220. The SSD 220 performs tests through its self-test loop and obtains test results. The control module 120 can also send a second control signal to the channel switching module 140, causing the channel switching module 140 to connect to the adapter chip 130, thus constructing a connection path between the SSD 220 and the test host 210, uploading the test results to the test host 210, and completing the test of the SSD 220 currently inserted into the second interface 150. The entire test process is automatically executed according to the first and second control signals sent by the control module 120, which can improve the testing efficiency of the SSD 220. The first interface 110 can be a hot-swappable interface such as a USB interface. When connected to the test host 210, the control module 120 controls the channel switching module 140 to switch the signal path, enabling the solid-state drive 220 to perform physical layer self-testing in closed loop mode. It can also establish a connection path with the test host 210 through the adapter chip 130 to upload test results. This avoids the limitation that some test host 210's PCIe interface does not support hot-swapping. When replacing the solid-state drive 220, it is not necessary to shut down the test host 210 first and then unplug the solid-state drive 220, which can further improve the corresponding testing efficiency.

[0026] In some embodiments, reference Figure 3 As shown, the solid-state drive test board also includes a hub 160. The first end of the hub 160 is connected to the second end of the first interface 110, the second end of the hub 160 is connected to the first end of the adapter chip 130, and the third end of the hub 160 is connected to the second end of the control module 120.

[0027] Hub 160 is used to establish a first communication link between test host 210 and adapter chip 130, enabling high-speed data transmission between test host 210 and solid-state drive 220 via the first communication link, thereby efficiently obtaining test results. Hub 160 is also used to establish a second communication link between test host 210 and control module 120, enabling test host 210 to send test commands and / or result upload commands, etc., to control module 120 via the second communication link.

[0028] In some embodiments, the second interface 150 is a hot-swappable interface, so that the solid-state drive 220 can be quickly inserted into or removed from the second interface 150, avoiding the need to remove the test board 100 when replacing the solid-state drive 220, thereby improving the efficiency of replacing the solid-state drive 220 and thus improving the corresponding testing efficiency.

[0029] Optionally, the second interface 150 may include an SSD slot or other structure for connecting the solid-state drive 220.

[0030] In some embodiments, the second interface 150 includes multiple test channels between the first group of pins and the second group of pins. The channel switching module 140 can be implemented using a multiplexer. If a multiplexer includes multiple groups of ports, for example, a multiplexer includes a group of ports corresponding to each test channel, then the channel switching module 140 can be implemented using a single multiplexer.

[0031] If a multiplexer includes a set of ports corresponding to a test channel, then each test channel can be implemented using a separate multiplexer; the channel switching module 140 includes multiplexers corresponding to each test channel to improve the reliability of each test channel.

[0032] Optionally, Figure 4 and Figure 5 This diagram illustrates the connection between one test channel and its corresponding multiplexer. The connection relationships between other test channels and their corresponding multiplexers can be found by referring to this diagram. Figure 4 and Figure 5 As shown. In this test channel, the first group of pins in the second interface 150 is connected to the input channel of the SSD (i.e., solid-state drive 220). Figure 4 and Figure 5 The input channels of the SSD include the RXN and RXP pins, and the second set of pins in the second interface 150 connects to the output channels of the SSD. Figure 4 and Figure 5 The SSD's output channels include the TXN and TXP pins; RXN and RXP are connected to the multiplexer's A1- and A1+ pins respectively, and TXN and TXP are connected to the multiplexer's A0- and A0+ pins respectively. The multiplexer's A0-, A0+, A1-, and A1+ pins can be a portion of the channel ports of the third terminal in the channel switching module 140. A portion of the channel ports of the fourth terminal in the channel switching module 140 can include the multiplexer's C0-, C0+, C1-, and C1+ pins, such as... Figure 4 As shown, A0- connects to C0-, A0+ connects to C0+, A1- connects to C1-, and A1+ connects to C1+. That is, the third terminal of the channel switching module 140 connects to its fourth terminal, connecting the input and output channels of the SSD to form a self-test loop. Figure 4 As shown, a portion of the channel ports at the first end of the channel switching module 140 may include B0-, B0+, B1-, and B1+ of the multiplexer. If A0- is connected to B0-, A0+ is connected to B0+, A1- is connected to B1-, and A1+ is connected to B1+, then the third end of the channel switching module 140 is connected to its first end. At this time, the channel switching module 140 is connected to the adapter chip 130, and the channel switching module 140 is connected to the test host 210 through the adapter chip 130 and the first interface 110.

[0033] Figure 5 In this configuration, the SEL pin of the multiplexer can be the second terminal of the channel switching module 140, to receive a first control signal or a second control signal sent by the control module 120 via the SEL pin. Optionally, the first control signal can be represented by a high level, and the second control signal can be represented by a low level, so that the multiplexer controls the connection state of each group of ports according to the high or low level; for example, the control module 120 sends a high level to the SEL pin of the multiplexer, and the internal control module of the multiplexer ( Figure 5 The control module 120 can select to connect pin A to pin C (i.e., A0- connects to C0-, A0+ connects to C0+, A1- connects to C1-, and A1+ connects to C1+), thus forming a self-test loop. The input signal of the SSD can be fed back to the SSD to achieve self-test. For example, the control module 120 sends a low level to the SEL pin of the multiplexer. The internal control module of the multiplexer can select to connect pin A to pin B (i.e., A0- connects to B0-, A0+ connects to B0+, A1- connects to B1-, and A1+ connects to B1+). In this case, the input signal of the SSD can be directed to the adapter chip 130, thereby communicating with the test host 210 and uploading the test results of the SSD to the test host 210.

[0034] In the above solid-state drive test board, the control module 120 sends a first control signal to the channel switching module 140, causing the third terminal of the channel switching module 140 to connect to its fourth terminal, thus constructing a self-test loop in the solid-state drive 220. The solid-state drive 220 performs tests through its self-test loop and obtains test results. The control module 120 can also send a second control signal to the channel switching module 140, causing the channel switching module 140 to connect to the adapter chip 130, thus constructing a connection path between the solid-state drive 220 and the test host 210, uploading the test results to the test host 210, and completing the test of the solid-state drive 220 currently inserted into the second interface 150. The entire test process is automatically executed according to the first and second control signals sent by the control module 120, which can improve the testing efficiency of the solid-state drive 220. Furthermore, the first interface 110 and / or the second interface 150 may also have hot-swappable features, allowing the SSD 220 to be directly unplugged after testing and the next SSD 220 to be tested to be inserted, enabling rapid replacement of the SSD 220 under test and improving the testing efficiency of the SSD 220 from another perspective. It is evident that the aforementioned SSD test board 100 can improve the testing efficiency of the SSD 220 in multiple ways.

[0035] This application also provides a testing system for solid-state drives, for reference. Figure 6As shown, the test system includes a test host 210, a solid-state drive 220, and a test board 100 for the solid-state drive as described in any of the above embodiments.

[0036] The test host 210 is used to send a first command and a second command to the control module 120 of the test board 100. The first command represents a command to perform a test, and the second command represents a command to obtain the test results.

[0037] In response to a first command from the test host 210, the control module 120 sends a first control signal to the channel switching module 140, causing the third terminal of the channel switching module 140 to connect to its fourth terminal. In response to the connection of the third terminal to the fourth terminal of the channel switching module 140, the solid-state drive 200 sends test data to the test board 100 through its output channel and receives feedback data from the test board 100 through its input channel. It then compares the test data and the feedback data to obtain the test result.

[0038] Optionally, the solid-state drive 200 can compare and analyze test data and feedback data to evaluate PCIe physical layer indicators such as the number of channels, channel speed, signal integrity, and bit error rate, and obtain test results. Optionally, after the test is completed, the solid-state drive 200 can write the test results (such as log files, pass / fail status, performance data, etc.) to its own storage area in file form for the test host 210 to read.

[0039] In response to a second command from the test host 210, the control module 120 sends a second control signal to the channel switching module 140, causing the third terminal of the channel switching module 140 to connect to its first terminal, and the channel switching module 140 to connect to the adapter chip 130. The solid-state drive 220 is also used to send test results to the test host 210 when the channel switching module 140 connects to the adapter chip 130.

[0040] In some embodiments, the hub 160 is further configured to send new device access information to the test host 210 after identifying the connection of the solid-state drive 220 to the second interface 150 via the first communication link. Upon receiving the new device access information, the test host 210 sends a first command to the control module 120 via the second communication link, causing the control module 120 to respond to the first command and send a first control signal to the channel switching module 140.

[0041] In some embodiments, the test host 210 sends a first command to the control module. After a preset time interval, the solid-state drive 220 performs the corresponding test and obtains the test result. Then, the test host 210 sends a second command to the control module 120, so that the control module 120 responds to the second command and sends a second control signal to the channel switching module 140. The third terminal of the channel switching module 140 is connected to its first terminal. The channel switching module 140 connects to the adapter chip 130. When the channel switching module 140 connects to the adapter chip 130, the solid-state drive 220 sends the test result to the test host 210.

[0042] Optionally, the preset duration can be set according to the maximum time required for the solid-state drive 220 to perform the test, so that the solid-state drive 220 can perform a complete test within the preset duration and obtain reliable test results.

[0043] In this embodiment, the test host 210 sends a first command to the control module, and after a preset time interval, sends a second command to the control module 120, causing the control module 120 to respond to the second command. The channel switching module 140 connects to the adapter chip 130, thereby enabling the test host 210 to obtain the test results at the solid-state drive 220, which simplifies wiring and thus simplifies the corresponding test system structure.

[0044] In some embodiments, reference Figure 7 As shown, the control module 120 also includes a third terminal, the second interface 150 includes a first setting pin, and the solid-state drive 220 includes a second setting pin. The third terminal of the control module 120 is connected to the first setting pin of the second interface 150. The first setting pin of the second interface 150 can be connected to the second setting pin of the solid-state drive 220, so that the first setting pin of the second interface 150 can follow the level change at the second setting pin of the solid-state drive 220.

[0045] Solid-state drive 220 is used to update the level signal of the second setting pin after the test is completed, so as to update the level at the first setting pin connected to the second setting pin in the second interface 150.

[0046] The control module 120 is also used to send test completion information to the test host 210 after the level is updated at the first setting pin of the second interface 150.

[0047] In response to the test completion information, the test host 210 sends a second command to the control module 120.

[0048] In this embodiment, the control module 120 sends a first command so that after the solid-state drive 220 performs the corresponding test, it does not go into sleep mode and wait, but continuously monitors the level change of the first set pin of the second interface 150 to obtain the level update at the first set pin in the second interface 150 in real time, thereby efficiently sending the test completion information to the test host 210, which can avoid waiting time or interrupting the test process of the solid-state drive 220.

[0049] In some embodiments, the adapter chip 130 is used to convert the received test results into data matching the first interface 110 after the channel switching module 140 is turned on, and send the converted test results to the test host 210 through the first communication link so that the test host 210 can accurately identify the test results.

[0050] Optionally, after receiving the test results, the test host 210 can also determine that the communication connection between the test host 210 and the adapter chip 130 is stable, that is, the corresponding first communication link test is passed.

[0051] In some examples, after the solid-state drive 220 sends the test results to the test host 210, the test host 210 sends a third command to the adapter chip 130. The third command includes a command characterizing the test communication status.

[0052] In response to the third command, the adapter chip 130 sends communication status data between the solid-state drive 220 and the adapter chip 130 to the test host.

[0053] The test host 210 is also used to analyze communication status data to determine the quality of the input and / or output channels of the solid-state drive 220, thereby testing the communication status between the solid-state drive 220 and the adapter chip 130.

[0054] This embodiment can not only obtain the test results obtained by testing the solid-state drive 220 and test the physical layer of the PCIe link corresponding to the solid-state drive 220, but also analyze the communication status data between the solid-state drive 220 and the adapter chip 130 to verify whether the upper layers of the physical layer (such as the data link layer, transaction layer, etc.) can work normally.

[0055] The above-mentioned solid-state drive testing system, including the solid-state drive testing board described in any of the above embodiments, has all the beneficial effects of the solid-state drive testing board described in any of the above embodiments, and will not be repeated here.

[0056] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0057] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0058] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0059] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A test board for a solid-state drive, characterized in that, The solid-state drive test board includes a first interface, a control module, an adapter chip, a channel switching module, and a second interface, wherein the first interface is a hot-swappable interface; The first end of the first interface is used to connect to the test host, and the second end is connected to the first end of the adapter chip; the second end of the adapter chip is connected to the first end of the channel switching module; the first end of the control module is connected to the second end of the channel switching module; the third end of the channel switching module is connected to the first set of pins of the second interface, and the fourth end is connected to the second set of pins of the second interface; the first set of pins and the second set of pins of the second interface are respectively used to connect to the input channel and output channel of the solid-state drive. The control module is used to send a first control signal to the channel switching module to connect the third terminal of the channel switching module to the fourth terminal; it is also used to send a second control signal to the channel switching module to connect the adapter chip. The adapter chip is used to perform bidirectional protocol conversion between the first interface and the second interface when the channel switching module is turned on.

2. The solid-state drive test board according to claim 1, characterized in that, The solid-state drive test board also includes a hub; the first end of the hub is connected to the second end of the first interface, the second end is connected to the first end of the adapter chip, and the third end is connected to the second end of the control module. The hub is used to establish a first communication link between the test host and the adapter chip and a second communication link between the test host and the control module.

3. The solid-state drive test board according to claim 1, characterized in that, The second interface is a hot-swappable interface.

4. The test board for a solid-state drive according to claim 1, characterized in that, The second interface includes multiple test channels between the first group of pins and the second group of pins, and each test channel is implemented using a multiplexer; The channel switching module includes multiplexers corresponding to each of the test channels.

5. A testing system for solid-state drives, characterized in that, Includes a test host, a solid-state drive, and a test board for the solid-state drive as described in any one of claims 1 to 4; The test host is used to send a first command and a second command to the control module; The control module responds to the first command from the test host by sending a first control signal to the channel switching module; the solid-state drive responds to the third terminal of the channel switching module being connected to the fourth terminal by sending test data to the test board through the output channel and receiving feedback data from the test board through the input channel, comparing the test data and the feedback data to obtain the test result; The control module responds to the second command from the test host by sending a second control signal to the channel switching module; the solid-state drive is also used to send the test results to the test host when the channel switching module connects the adapter chip.

6. The solid-state drive testing system according to claim 5, characterized in that, The hub is also used to send new device access information to the test host after identifying the solid-state drive connected to the second interface through the first communication link; The test host receives the new device access information and sends the first command to the control module through the second communication link.

7. The solid-state drive testing system according to claim 5, characterized in that, The test host sends a first command to the control module, and after a preset time interval, sends a second command to the control module.

8. The solid-state drive testing system according to claim 5, characterized in that, The control module further includes a third terminal, the second interface further includes a first setting pin, the solid-state drive further includes a second setting pin, and the third terminal of the control module is connected to the first setting pin of the second interface; The control module is also used to send test completion information to the test host after updating the level at the first set pin of the second interface; In response to the test completion information, the test host sends a second command to the control module; The solid-state drive is used to update the level signal of the second setting pin after the test is completed, so as to update the level at the first setting pin in the second interface that is connected to the second setting pin.

9. The solid-state drive testing system according to claim 5, characterized in that, The adapter chip is used to convert the received test results into data matching the first interface after the channel switching module is turned on, and send the converted test results to the test host through the first communication link.

10. The solid-state drive testing system according to claim 5, characterized in that, After the solid-state drive sends the test results to the test host, the test host sends a third command to the adapter chip; In response to the third command, the adapter chip sends communication status data between the solid-state drive and the adapter chip to the test host. The test host is also used to analyze the communication status data to determine the quality of the input and / or output channels of the solid-state drive.

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