Time-dependent defect inspection device

Abstract

Disclosed is an improved charged particle beam inspection apparatus, and more particularly, a particle beam inspection apparatus for detecting defects of a thin device structure. The beam inspection apparatus includes: a charged particle beam source for guiding charged particles to a position under inspection of a wafer in a time series; and a controller configured to sample a plurality of images (510-538) of a region of the wafer at different times over a time series. The plurality of images are compared to detect voltage contrast differences or voltage contrast changes (560-564) to identify thin device structure defects (562).

Description

[0001] This application is a divisional application of the application filed on August 22, 2019, with application number 201980056389.2 and invention title "Time-related Defect Inspection Device". Technical Field

[0002] The embodiments provided herein disclose a particle beam inspection apparatus, and more specifically, a particle beam inspection apparatus including an improved detection unit. Background Technology

[0003] When manufacturing semiconductor integrated circuit (IC) chips, pattern defects or uninvited particles (residues) inevitably appear on the wafer or mask during the manufacturing process, reducing yield. For example, uninvited particles can be problematic for patterns with small critical feature sizes that have been adopted to meet the increasing performance requirements of IC chips.

[0004] Pattern inspection tools with charged particle beams have been used to detect defects or uninvited particles. These tools typically employ scanning electron microscopy (SEM). In SEM, a relatively high-energy primary electron beam is slowed down, landing on the sample with a relatively low landing energy and focused to form a probe spot. Due to this focused probe spot of primary electrons, secondary electrons are generated from the surface. Secondary electrons can include backscattered electrons, secondary electrons, or Auger electrons resulting from the interaction of primary electrons with the wafer. By scanning the probe spot above the sample surface and collecting the secondary electrons, the pattern inspection tool can obtain an image of the sample surface. Summary of the Invention

[0005] The embodiments provided herein disclose a charged particle beam system for inspecting wafers, and more specifically, a particle beam system including an improved detection unit.

[0006] In some embodiments, the charged particle beam system for inspecting a wafer includes a charged particle beam source comprising a circuit system for guiding charged particles to one or more regions of the wafer over one or more time series. The charged particle beam system also includes a controller comprising a circuit system that generates a first set of images of a first region within the one or more time series during a first time series. The controller further includes a circuit system for processing the first set of images to detect defects in thin device structures within the wafer.

[0007] In some embodiments, a wafer inspection method is provided. The method uses a charged particle beam system with a charged particle beam source to direct charged particles onto one or more regions of a wafer over one or more time series. The method includes: generating a first set of images of a first region within the one or more time series during a first time series. The method further includes: processing the first set of images to detect defects in thin device structures within the wafer.

[0008] In some embodiments, a non-transitory computer-readable medium is provided storing a set of instructions executable by a processor of a charged particle beam system. The instructions cause the charged particle beam system, having a charged particle beam source, to perform a method to direct charged particles onto one or more regions of a wafer over one or more time series. The method includes generating a first set of images of a first region within the one or more time series during a first time series. The method further includes processing the first set of images to detect defects in a thin device structure within the wafer.

[0009] Other advantages of the invention will become apparent from the following description taken in conjunction with the accompanying drawings, in which certain embodiments of the invention are illustrated by way of description and example. Attached Figure Description

[0010] The above and other aspects of this disclosure become more apparent from the description of exemplary embodiments taken in conjunction with the accompanying drawings.

[0011] Figure 1 This is a schematic diagram illustrating an exemplary charged particle beam inspection system according to an embodiment of the present disclosure.

[0012] Figure 2 This is a schematic diagram illustrating an exemplary electron beam tool according to an embodiment of the present disclosure.

[0013] Figure 3 This is an exemplary graph illustrating the yield of landing energies of secondary electrons relative to primary electrons.

[0014] Figure 4 This is a schematic diagram illustrating the voltage comparison response of a chip according to an embodiment of the present disclosure.

[0015] Figure 5A and Figure 5B This is a time-series illustration of exemplary voltage comparison images according to embodiments of the present disclosure.

[0016] Figure 6 This is an illustration of exemplary processing of a voltage comparison image according to an embodiment of the present disclosure.

[0017] Figure 7This is a flowchart illustrating an exemplary method for detecting time-related defects according to an embodiment of the present disclosure. Detailed Implementation

[0018] Now, reference will be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, wherein, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The implementations set forth in the following description of the exemplary embodiments do not represent all implementations consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with aspects of the invention as set forth in the appended claims.

[0019] While reducing the physical size of devices, the computing power of electronic devices can be enhanced by significantly increasing the packaging density of circuit components such as transistors, capacitors, and diodes on IC chips. For example, the IC chip in a smartphone (about the size of a thumbnail) can include more than 2 billion transistors, each less than 1 / 1000th the size of a human hair. Therefore, it is not surprising that the manufacture of semiconductor ICs is a complex and time-consuming process with hundreds of individual steps. Even an error in one step can drastically affect the functionality of the final product. Even a "fatal defect" can cause equipment failure. The goal of the manufacturing process is to improve the overall yield. For example, to achieve a 75% yield in a 50-step process, the yield of each step must be greater than 99.4%. If the yield of a single step is 95%, the overall yield of the process drops to 7%.

[0020] While high process yields are required in IC chip manufacturing facilities, maintaining high chip throughput (defined as the number of chips processed per hour) is also crucial. This is especially true in environments requiring operator intervention to inspect for defects, as the presence of defects can negatively impact both process yields and chip throughput. Therefore, high-throughput inspection using tools such as SEM and the identification of micron- and nanometer-level defects are essential for maintaining both high yields and low costs.

[0021] SEM uses a focused electron beam to scan the surface of a wafer. Electrons interact with the wafer and generate secondary electrons. By scanning the chip with the electron beam and capturing these secondary electrons with a detector, SEM generates an image of the chip that reveals the internal device structure within the area of ​​the chip being examined.

[0022] Traditional SEM inspection tools obtain a single image of a wafer region and compare it with a reference image representing a corresponding device structure without defects. Differences detected from the image comparison can indicate defects in the inspected wafer region.

[0023] However, because the electrical characteristics of defective thin structures change over time, traditional inspection techniques (such as capturing a single image at any given time point) may not be effective in identifying defects in thin device structures. For example, even if a defect is actually present in the wafer being inspected, due to the time-dependent behavior of thin structures, sometimes a single image captured at the correct time may show a difference from a reference image, while images acquired at other times may not show any difference at all. Therefore, traditional SEM inspection tools cannot reliably identify defects in thin device structures.

[0024] One aspect of this disclosure includes an improved inspection tool that can reliably detect thin-film device defects exhibiting the time-dependent behavior described above. For example, the improved inspection tool can acquire multiple images from the same region of the wafer over a time series. By comparing multiple images of the same location (where those images were sampled at different times), the improved inspection tool can detect any changes in electrical characteristics caused by thin-film device defects within the wafer region.

[0025] For clarity, the relative dimensions of the components in the accompanying drawings may be enlarged. In the following description of the drawings, the same or similar reference numerals refer to the same or similar components or entities, and only differences with respect to the various embodiments are described. As used herein, unless expressly stated otherwise, the term "or" covers all possible combinations, except those that are impractical. For example, if it is stated that a database may contain A or B, then unless expressly stated otherwise or impractical, the database may contain A or B or A and B. As a second example, if it is stated that a database may contain A, B, or C, then unless expressly stated otherwise or impractical, the database may contain A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0026] Now, for reference Figure 1 , Figure 1 This is a schematic diagram illustrating an exemplary charged particle beam inspection system 100 according to an embodiment of the present disclosure. Figure 1 As shown, the charged particle beam inspection system 100 includes a main chamber 10, a loading and locking chamber 20, an electron beam tool 40, and an equipment front-end module (EFEM) 30. The electron beam tool 40 is located within the main chamber 10. Although the description and figures refer to electron beams, it should be understood that the embodiments are not intended to limit this disclosure to specific charged particles.

[0027] EFEM 30 includes a first loading port 30a and a second loading port 30b. EFEM 30 may include other loading ports. The first loading port 30a and the second loading port 30b may, for example, receive a front-opening wafer transfer cassette (FOUP) containing wafers to be inspected (e.g., semiconductor wafers or wafers made of one or more other materials) or samples (wafers and samples are collectively referred to as “wafers” hereinafter). One or more robotic arms (not shown) in EFEM 30 transport the wafers to the loading locking chamber 20.

[0028] Load-locking chamber 20 may be connected to a load-locking vacuum pump system (not shown) that removes gas molecules from load-locking chamber 20 to achieve a first pressure below atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) transport the wafer from load-locking chamber 20 to main chamber 10. Main chamber 10 is connected to a main chamber vacuum pump system (not shown) that removes gas molecules from main chamber 10 to achieve a second pressure below the first pressure. After reaching the second pressure, the wafer is inspected by an electron beam tool 40. In some embodiments, electron beam tool 40 may include a single-beam electron inspection tool. In other embodiments, electron beam tool 40 may include a multi-beam electron inspection tool.

[0029] The controller 50 is electrically connected to the electron beam tool 40. The controller 50 can be a computer configured to perform various controls on the charged particle beam inspection system 100. Although the controller 50 is... Figure 1 The controller 50 is shown outside the structure comprising the main chamber 10, the loading and locking chamber 20, and the EFEM 30; however, it should be understood that the controller 50 may be part of this structure. While this disclosure provides an example of a main chamber 10 for housing an electron beam inspection tool, it should be noted that aspects of this disclosure are not, in their broadest sense, limited to chambers housing electron beam inspection tools. Rather, it should be understood that the foregoing principles can also be applied to other tools operating under a second pressure.

[0030] Now, for reference Figure 2 , Figure 2 This is a schematic diagram illustrating an exemplary imaging system 200 including an electron beam tool 40 and an image processing system 250 according to an embodiment of the present disclosure.

[0031] like Figure 2As shown, the electron beam tool 40 may include a motorized stage 201 and a wafer holder 202 supported by the motorized stage 201 to hold the wafer 203 to be inspected. The electron beam tool 40 may also include a compound mirror 204, an electron detector 206 (which includes an electron sensor surface), an objective aperture 208, a condenser lens 210, a beam confinement aperture 212, a gun aperture 214, an anode 216, and a cathode 218, wherein one or more of the electron beam tools 40 may be aligned with the optical axis 217 of the electron beam tool 40. In some embodiments, the detector 206 may be arranged off-axis 217.

[0032] In some embodiments, the composite mirror 204 may include a modified oscillating deceleration immersion objective (SORIL), which may include an electrode 204a, a control electrode 204b, a deflector or a set of deflectors 204c, and an excitation coil 204d. Additionally, the electron beam tool 40 may include an energy-dispersive X-ray spectroscopy (EDS) detector (not shown) for characterizing materials on a wafer.

[0033] A primary electron beam 220 can be emitted from the cathode 218 by applying a voltage between the anode 216 and the cathode 218. The primary electron beam 220 can pass through the gun aperture 214 and the beam confinement aperture 212, both of which determine the current of the electron beam entering the condenser lens 210, located below the beam confinement aperture 212. The condenser lens 210 can focus the primary electron beam 220 before it enters the objective aperture 208 to set the current of the electron beam before it enters the compound lens 204.

[0034] The composite mirror 204 can focus the primary electron beam 220 onto the wafer 203 for inspection and can form a probe spot 222 on the surface of the wafer 203. One or more deflectors 204c can deflect the primary electron beam 220 to scan the probe spot 222 on the wafer 203. For example, during scanning, one or more deflectors 204c can be controlled to sequentially deflect the primary electron beam 220 to different positions on the top surface of the wafer 203 at different time points to provide data for image reconstruction of different portions of the wafer 203. Moreover, in some embodiments, the deflectors 204c can also be controlled to deflect the primary electron beam 220 to different sides of the wafer 203 at a specific location at different time points to provide data for stereoscopic image reconstruction of the wafer structure at that location. Further, in some embodiments, the anode 216 and cathode 218 can be configured to generate a plurality of primary electron beams 220, and the electron beam tool 40 can include a plurality of deflectors 204c for simultaneously projecting the plurality of primary electron beams 220 onto different portions / sides of the wafer 203.

[0035] When current is applied to the excitation coil 204d, an axially symmetrical (i.e., symmetrical about the optical axis 217) magnetic field may be generated in the wafer surface region. A portion of the wafer 203 being scanned by the primary electron beam 220 is immersed in the magnetic field. In some embodiments, different voltages may be applied to the wafer 203, the electrode 204a, and the control electrode 204b to generate an axially symmetrical decelerating electric field near the wafer surface. The electric field can reduce the energy of the primary electron beam 220 striking the wafer surface before the electrons of the beam collide with the wafer 203. The control electrode 204b, electrically isolated from the electrode 204a, can control the axially symmetrical electric field on the wafer to prevent micro-arcs from forming on the wafer and to ensure that the appropriate beam is focused together at the wafer surface by means of the axially symmetrical magnetic field.

[0036] Following the reception of the primary electron beam 220, a secondary electron beam 230 can be emitted from a portion of the wafer 203. The secondary electron beam 230 may include backscattered electrons, secondary electrons, or Auger electrons generated due to the interaction of primary electrons with the wafer 203. The secondary electron beam 230 can be received via the sensor surface of the electron detector 206. In some embodiments, the electron detector 206 may generate a signal (e.g., voltage, current, etc.) representing the intensity of the secondary electron beams 230 and 230; and may provide the signal to an image processing system 250 communicating with the electron detector 206. The intensity of the secondary electron beam 230 can vary depending on the external or internal structure of the wafer 203, thus indicating whether the wafer 203 contains defects. Moreover, as discussed above, the primary electron beam 220 can be projected onto different locations on the top surface of the wafer 203 or onto different sides of the wafer 203 at a specific location to generate secondary electron beams 230 of varying intensities. Therefore, by mapping the region of wafer 203 and the intensity of the secondary electron beam 230, the image processing system 250 can reconstruct an image that reflects the characteristics of the internal or external structure of wafer 203.

[0037] In some embodiments, the imaging system 200 may further include an image processing system 250, which includes an image acquirer 260, a memory 270, and a controller 50. The image acquirer 260 may include one or more processors. For example, the image acquirer 260 may include a computer, server, mainframe, terminal, personal computer, any kind of mobile computing device, or a combination thereof. The image acquirer 260 may be communicatively coupled to the detector 206 of the electron beam tool 40 via a medium such as an electrical conductor, fiber optic cable, portable storage medium, IR, Bluetooth, the Internet, wireless network, wireless broadcasting, or a combination thereof. In some embodiments, the image acquirer 260 may receive signals from the detector 206 and may construct an image. Thus, the image acquirer 260 may acquire an image of the wafer 203. The image acquirer 260 may also perform various post-processing functions, such as generating contours, overlaying indicators on the acquired image, etc. The image acquirer 260 may be configured to perform adjustments to the brightness and contrast, etc., of the acquired image. In some embodiments, storage device 270 may be a storage medium, such as a hard disk, flash drive, cloud storage device, random access memory (RAM), or other types of computer-readable storage. Storage device 270 may be coupled to image acquirer 260 and may be used to save scanned raw image data as raw images and post-processed images. Image acquirer 260 and storage device 270 may be connected to controller 50. In some embodiments, image acquirer 260, storage device 270, and controller 50 may be integrated into a single control unit.

[0038] In some embodiments, image acquirer 260 may acquire one or more images of a sample based on imaging signals received from detector 206. The imaging signals may correspond to a scanning operation for imaging charged particles. The acquired image may be a single image comprising multiple imaging regions. The single image may be stored in storage device 270. The single image may be an original image that can be divided into multiple regions. Each region may include an imaging region containing features of wafer 203. The acquired images may include multiple images of a single imaging region of wafer 203 sampled multiple times over a time series. Multiple images may be stored in storage device 270. In some embodiments, image processing system 250 may be configured to perform image processing steps on multiple images of the same location on wafer 203.

[0039] In some embodiments, the image processing system 250 may include a measurement circuitry (e.g., an analog-to-digital converter) to obtain the distribution of the detected secondary electrons. Combined with corresponding scan path data of the primary electron beam 220 incident on the wafer surface, the electron distribution data collected during the detection time window can be used to reconstruct an image of the inspected wafer structure. The reconstructed image can be used to reveal various features of the internal or external structure of the wafer 203, thereby revealing any defects that may be present in the wafer.

[0040] Moreover, despite Figure 2 The electron beam tool 40 is shown using a single primary electron beam; however, it should be understood that the electron beam tool 40 can also be a multi-beam inspection tool using multiple primary electron beams. This disclosure does not limit the number of primary electron beams used in the electron beam tool 40.

[0041] Now, for reference Figure 3 This is an exemplary graph illustrating the productivity of secondary electrons relative to the landing energy of primary electrons. The graph illustrates a primary electron beam (such as...) Figure 2 The landing energy of the primary electron beam (220) and the secondary electron beam (such as...) Figure 2 The relationship between the productivity of the secondary electron beam (230) and the number of secondary electrons generated in response to the impact of primary electrons. For example, a productivity higher than 1.0 indicates that a larger number of secondary electrons can be generated compared to the number of primary electrons already landed on the wafer. Similarly, a productivity lower than 1.0 indicates that a smaller number of secondary electrons can be generated in response to the impact of primary electrons.

[0042] like Figure 3 As shown in the diagram, when the landing energy of primary electrons is in the range of E1 to E2, more electrons may leave the wafer surface than have landed on it, thus generating a positive potential at the wafer surface. In some embodiments, defect inspection can be performed within the aforementioned landing energy range, which is referred to as the "positive mode." (See also: Regarding...) Figure 4 Described in more detail, because detectors (such as...) Figure 2 The detector 206 can receive a small number of secondary electrons, so the device structure with a higher positive surface potential can generate a darker voltage contrast image.

[0043] When the landing energy is below E1 or above E2, a small number of electrons may leave the surface, generating a negative potential at the surface. In some embodiments, defect inspection can be performed within this range of landing energies, which is referred to as a "negative mode." Device structures with higher negative surface potentials can generate brighter voltage contrast images of the chip.

[0044] In some embodiments, the landing energy of the primary electron beam can be controlled by the total bias voltage between the electron gun and the wafer.

[0045] Now, for reference Figure 4 This is a schematic diagram of the voltage contrast response of a device structure of a chip according to embodiments of the present disclosure. In some embodiments, a voltage contrast method using a charged particle inspection system can be used to detect physical and electrical defects on a wafer. To detect defects using voltage contrast imaging, a process known as pre-charging is typically employed, in which charged particles are applied to the area to be inspected prior to inspection. Pre-charging can be used to enhance voltage contrast-type defect signals, for example, as discussed in U.S. Patent Nos. 8,748,815 and 8,759,762, the entire contents of which are incorporated herein by reference.

[0046] For example, electron beam tools can be used to inspect wafers (such as...) based on the voltage contrast response of the wafer to irradiation with a primary electron beam. Figure 2 Defects in the internal or external structure of the wafer (203). In some embodiments, the wafer may include a test apparatus 420 that develops on top of a substrate 410. In some embodiments, the test apparatus 420 may include a plurality of device structures 430 and 440 separated by an insulating material 450. For example, device structure 430 is attached to the substrate 410. In contrast, device structure 440 is spaced apart by an insulating material 450 that forms a thin insulating structure 470 (e.g., a thin oxide) between device structure 440 and substrate 410.

[0047] When electron beam tools (such as Figure 2 The electron beam tool 40) uses primary electrons (such as... Figure 2 When the primary electron beam 220 scans the surface of the test device 420, secondary electrons (such as...) can be generated from the surface. Figure 2 The secondary electron beam 230). As previously stated in Figure 2 As described, when the landing energy of primary electrons is in the range of E1 to E2 (making the productivity higher than 1.0), more electrons may leave the wafer surface than have landed on the surface, thus generating a positive potential at the chip surface.

[0048] Figure 4This illustrates how a positive potential can accumulate at the wafer surface. For example, after electron beam scanning test equipment 420 (e.g., during the pre-charge phase), because device structure 440 is not connected to an electrical ground in the substrate, device structure 440 can retain more positive charge, thereby generating a positive potential at the surface of device structure 440. In contrast, although primary electrons with the same landing energy (and therefore the same productivity) have been applied, device structure 430 can retain less positive charge because the accumulated positive charge can be neutralized by additional electrons supplied via the connection to substrate 410.

[0049] Image processing systems (such as) Figure 2 The image processing system 250 can generate voltage contrast images 435 and 445 corresponding to device structures 430 and 440, respectively. For example, device structure 430 is shorted to ground and cannot retain the positive charge accumulated during the pre-charge phase. Thus, when the primary electron beam lands on the surface of the wafer during the inspection phase, device structure 430 can repel more secondary electrons, thereby generating a brighter area in the voltage contrast image. In contrast, device structure 440 is not connected to the substrate or any other ground, and therefore can retain the positive charge accumulated during the pre-charge phase, which allows device structure 440 to repel fewer secondary electrons during the inspection phase, thereby generating a darker area in the voltage contrast image.

[0050] Traditional defect inspection tools use electrons to build up a potential on the wafer surface during the pre-charge phase. After pre-charging, the tool acquires images of multiple dies within the wafer. Because all dies can contain the same device structure, the defect can be detected by comparing the voltage contrast differences between these images from multiple dies. For example, if the voltage contrast level of one image is lower or higher than that of the others, it can be determined that the corresponding die has a defect in that die region. Traditional inspection techniques assume that the surface potential built up during the pre-charge phase may remain above the tool's detection level throughout the inspection process.

[0051] However, as semiconductor process technology nodes shrink (e.g., 10nm, 7nm and below), the accumulated surface potential level may change during the inspection phase due to electrical breakdown or tunneling, making defects in thin devices undetectable. When sufficiently high voltages are applied to thin insulating structures (e.g., thin oxides) such as insulating structure 470, leakage current can flow through the thin insulating structure, and the thin insulating structure may not function as a complete insulator. This can affect circuit functionality and lead to failure. Similar leakage current effects can also occur through high-resistivity metal layers (e.g., cobalt silicide layers such as CoSi, CoSi2, Co2Si, Co3Si, etc.) between tungsten (W) plugs and the source or drain regions of field-effect transistors (FETs).

[0052] Insulator structure 470 can represent a thin defect susceptible to such breakdown effects. For example, due to manufacturing errors, even if device structures 430 and 440 are designed to contact the substrate 410 and operate in the same manner, insulator structure 470 may have been defectively present in device structure 440. Defective etching processes may leave thin oxide layers, resulting in unwanted electrical blockages (e.g., open circuits) between the two structures that should be electrically connected (e.g., device structure 440 and substrate 410).

[0053] In this scenario, if the insulator structure 470 is sufficiently thick (e.g., greater than 10 nm), the positive charge accumulated in the device structure 440 will not leak through the insulator structure 470. Therefore, conventional defect inspection tools may be able to detect defects by taking a sample image during the inspection phase and comparing it with a reference image. As a result, a voltage contrast difference between 435 and 445 can be detected, indicating a defect in the device structure 440 (e.g., the insulator structure 470).

[0054] However, as the insulator structure 470 becomes thinner (e.g., less than 10 nm), the level of positive surface potential accumulated in device structure 440 is more likely to decrease over time due to the leakage current described above. As device structure 440 loses positive charge, the voltage contrast level may also change from darker (e.g., image 445) to brighter (e.g., image 446) over time, and because the voltage contrast level is below the detector's threshold (e.g., image 447), the final inspection tool may fail to detect anything. As a result, when the cutoff inspection phase begins and the inspection tool starts sampling the voltage contrast image, the positive potential accumulated in device structure 440 may have completely disappeared due to the leakage current through the thin insulator structure 470, resulting in no difference in surface potential between device structures 430 and 440. In this case, if a conventional inspection tool samples the image after all the positive charge has disappeared, the defect inspection tool may not be able to reliably detect defects in the thin device. For example, the inspection tool may not be able to detect any difference between voltage comparison image 435 (from device structure 430) and voltage comparison image 447 (from device structure 440).

[0055] Therefore, to detect defects in thin devices that are susceptible to time-dependent changes in the accumulated surface potential described above, the inspection tool can sample multiple images of the wafer across one or more time series while gradually increasing the surface potential, so that time-dependent changes can be captured through a sequence of multiple images. Additionally, in some embodiments, the inspection tool can use low-energy primary electrons to gradually charge the wafer without inducing this breakdown effect during the pre-charge phase. In other embodiments, the inspection tool can sample and generate voltage contrast images while pre-charging is in progress, so that transient voltage contrast changes can be captured even during the pre-charge phase.

[0056] The preceding description has described the existence of short-circuit conditions that cause the corresponding feature to appear bright, and the existence of open-circuit conditions that cause the corresponding feature to appear dark. However, those skilled in the art will understand that, depending on the actual processing of the test structure or the settings of the electron beam tool, the bright and dark appearances can be altered or even reversed.

[0057] Now, for reference Figure 5A This is an illustration of exemplary voltage comparison images in a time series according to embodiments of the present disclosure. In some embodiments, the defect inspection process may include a pre-charge phase 501 and an inspection phase 503. During the pre-charge phase 501, an imaging system (such as...) Figure 2The imaging system 200 in the example uses electrons to build a potential on the wafer surface. As explained above, to detect defects in thin devices, the imaging system can use low-energy electrons to gradually build a surface potential without inducing breakdown or tunneling during pre-charging. During inspection phase 503, in some embodiments, the imaging system can perform time-series inspections of the wafer (such as...) Figure 2 The system samples multiple images of the location region of the wafer (203). By comparing multiple voltage contrast images of the same location but from different times, the system can detect changes in surface potential over time, which indicate device breakdown or tunneling effects due to defects in the thin device.

[0058] For example, such as Figure 5A As shown, at the beginning of the pre-charge phase 501, the surface potential may be insufficient to display any detectable voltage contrast regions, as shown in voltage contrast images 510 and 512. At the end of the pre-charge phase, dark voltage contrast (DVC) regions 560a, 562a, and 564a may begin to appear (e.g., at time T). pre3 (Location).

[0059] In some embodiments, during the pre-charge phase 501, the electron beam tool (such as...) Figure 2 The electron beam tool 40 in the middle can use primary electrons with lower energy than conventional systems to avoid device breakdown during the pre-charge phase (e.g., before the sampling of the voltage contrast image begins), as explained above.

[0060] In other embodiments, the electron beam tool may skip the pre-charge phase 501 and begin the inspection process from the inspection phase 503 to detect structural defects in thin devices. In such an embodiment, the electron beam tool can begin sampling the image once the inspection process is initiated. Because there is no pre-charge potential at the surface of the wafer, the primary electron beam scan used for image generation can be used to gradually build up charge at the surface of the wafer while the image is continuously sampled.

[0061] After pre-charging is complete, the electron beam tool can begin sampling the image multiple times from a region of the wafer in a time sequence. For example, as Figure 5A As shown, during the inspection phase, multiple images 530, 532, 534, 536 and 538 were sampled at times T1, T2, T3, T4 and T5, respectively.

[0062] At time T1, image 530 shows the presence of three DVC regions 560a, 562a, and 564a. DVC regions 560b, 562b, and 564b can represent three device structures (such as...). Figure 4The surface potential accumulated in the device structure (440). At times T2 and T3, images 532 and 534 show that the DVC regions 560b, 562b and 564b were detected again, which indicates that the accumulated positive charge remains in the device structure and has remained unchanged since time T1.

[0063] At time T4, image 536 shows that DVC region 562b has disappeared, while DVC regions 560b and 564b still exist. This could indicate that the corresponding device structure for DVC region 562b may have lost accumulated positive charge due to leakage current, resulting in a drop in surface potential to an undetectable level (e.g., breakdown effect). When applied to thinner structures (e.g., Figure 4 When a high voltage is applied to the insulating structure 470, even if the structure is made of insulating material, leakage current may still flow through the thin structure. The leakage current ratio is higher when the device structure is thinner. For example, if the thickness of the device structure is less than 10 nm, device breakdown may occur more frequently. Therefore, the positive charge accumulated at the corresponding device structure location in the DVC region 562b may have been neutralized due to device breakdown caused by defects in the thin device structure.

[0064] In some embodiments, structural defects in thin devices can be identified by detecting such transient effects on surface potential. For example, an electron beam tool can compare multiple images at the same location, such as images 530, 532, 534, 536, and 538, and detect changes in the DVC region over time to identify structural defects in thin devices. In some embodiments, by comparing multiple voltage contrast images at the same location but from different times, the system can detect changes in surface potential over time, indicating device breakdown due to defects in the thin device. For example, as... Figure 5B As shown, voltage comparison image 534 (sampled at time T3) and voltage comparison image 536 (sampled at time T4) show that the DVC region 562b has disappeared between time T3 and T4, which can indicate that the corresponding device structure may include thin device structure defects.

[0065] although Figure 5A An example with five images is illustrated, but it should be understood that two or more images can be used to detect structural defects in thin devices. Furthermore, although... Figure 5A and Figure 5B The images shown illustrate a detection mechanism using dark voltage contrast, but it should be understood that bright voltage contrast can also be used when the electron beam tool is operating in negative mode.

[0066] In some embodiments, the time intervals between sampling times T1, T2, T3, T4, and T5 can be adjusted to capture different timings of transient effects on voltage contrast images. This timing may depend on the amount of current supplied during the pre-charge phase or on the characteristics of thin device structure defects, such as the thickness of the structure, the speed at which electrons move through the structure due to breakdown, etc.

[0067] In some embodiments, a positive surface potential can be accumulated because the electron beam tool operates in the positive mode (e.g., E1 < landing energy < E2). In other embodiments, a negative potential can be accumulated because the electron beam tool operates in the negative mode (e.g., landing energy < E1 or landing energy > E2).

[0068] Now, refer to Figure 6 , which is an illustration of an exemplary process of voltage contrast images according to embodiments of the present disclosure. In some embodiments, an inspection tool (such as the imaging system 200 in Figure 2 ) can compare a set of voltage contrast images with another set of voltage contrast images. For example, the inspection tool can generate a first set of voltage contrast images 610 and a second set of voltage contrast images 640, and then compare the corresponding images from each set one by one (e.g., 612 vs. 642, 614 vs. 644, 616 vs. 646, 618 vs. 648) to detect time-related defects caused by breakdown at the thin device structure. In some embodiments, the two sets of voltage contrast images 610 and 640 can be sampled from the same location on the wafer but at two different time sequences. In other embodiments, the first set of voltage contrast images 610 can be sampled from a first location on the wafer, while the second set of voltage contrast images 640 can be sampled from a second location on the wafer, where the first and second locations on the wafer can include the same device structure.

[0069] As Figure 6 shows, the first set of voltage contrast images 610 illustrates that the DVC region 621 can temporarily disappear (as in image 616) and reappear (as in image 618). Breakdown caused by leakage current through the thin device structure may cause the disappearance. After breakdown, because the primary particle beam is subsequently scanned for inspection, a positive surface potential may be accumulated again, resulting in the DVC region 621 may reappear, as shown in image 618. The inspection tool can detect the transient change of the DVC region 621 by comparing the voltage contrast image 616 and the voltage contrast image 646. Because the two sets of images (610 and 640) represent the same device structure (either from the same location or from different locations with the same device structure), the difference between image 616 and 646 can indicate a thin device defect at the wafer location.

[0070] Now, for reference Figure 7 This is a flowchart illustrating an exemplary method for detecting time-related defects according to embodiments of the present disclosure. The method can be performed by an imaging system (such as...) Figure 2 The imaging system 200) is executed.

[0071] In step 710, the electron beam tool (such as...) Figure 2 The electron beam tool 40 pre-charges the wafer under inspection to build up a potential on the wafer surface. When the electron beam tool uses primary electrons (such as...) Figure 2 When a primary electron beam 220 scans the surface of a wafer, secondary electrons (such as...) can be generated from that surface. Figure 2 The secondary electron beam 230). As previously mentioned Figure 2 As described, when the landing energy of primary electrons is in the range of E1 to E2 (making the productivity higher than 1.0), more electrons may leave the wafer surface than have already landed on the surface, thus generating a positive potential at the chip surface.

[0072] If the insulating structure (such as Figure 4 If the insulator structure 470 is thick enough (e.g., greater than 10 nm), then the device structure (such as...) Figure 4 The positive charge accumulated in the device structure 440 does not leak through the insulating structure, so traditional defect inspection tools may detect defects by taking a sample image during the inspection phase. As a result, the voltage contrast difference between the defective structure and the defect-free structure can be detected.

[0073] However, as device structures become thinner (e.g., less than 10 nm), the surface potential level accumulated during the inspection phase is highly susceptible to change due to electrical breakdown or tunneling effects. Consequently, by the time the inspection phase begins and the inspection tool starts sampling voltage contrast images, the positive potential accumulated in the device structure may have completely disappeared through the thin insulating structure due to breakdown or other thin-film-related mechanisms. This results in no difference in surface potential between defective and defect-free device structures, and no difference below the detection threshold. Consequently, conventional defect inspection tools may fail to detect defects in thin devices. Therefore, imaging systems can use low-energy primary electrons to gradually charge the wafer to avoid causing breakdown, which leads to the loss of surface potential during the pre-charging phase.

[0074] In step 720, after pre-charging the wafer, the electron beam tool is used at different times (e.g., Figure 5A Sampling times T1, T2, T3, T4, and T5) were used to obtain multiple voltage comparison images from the same location region of the wafer (e.g., Figure 5AImages 530, 532, 534, 536, and 538 are sampled. In order to detect changes in surface potential over time, in some embodiments, the inspection tool can sample images multiple times from the same location area of ​​the wafer over a certain time series while gradually increasing the surface potential.

[0075] In step 730, the image processing system (such as...) Figure 2 The image processing system 250 processes multiple voltage contrast images and detects dark voltage contrast (DVC) differences between the multiple images to identify defects in the thin device structure. In some embodiments, by comparing multiple voltage contrast images from the same location but from different times, the system can detect changes in surface potential over time that indicate device breakdown due to defects in the thin device. For example, as Figure 5B As shown, voltage contrast image 534 (sampled at time T3) and voltage contrast image 536 (sampled at time T4) show that the DVC region 562b has disappeared between times T3 and T4, which can indicate that the corresponding device structure may include thin device structure defects. In some embodiments, a bright voltage contrast difference can be detected.

[0076] The embodiments can also be described using the following terms: 1. A charged particle beam system for inspecting wafers, comprising: A charged particle beam source, including a circuit system that guides charged particles to one or more regions of a wafer in one or more time sequences; and The controller includes a circuit system for: During a first time series within one or more time series, generate a first set of images of a first region within one or more regions; and The first set of images is processed to detect defects in the thin device structure within the wafer. 2. The system according to Clause 1, wherein the controller includes a circuit system for: A first image and a second image are sampled from a first set of images, wherein the first image is sampled at a first time point in a first time series, and the second image is sampled at a second time point in the first time series; and Compare the first image with the second image to identify defects in the first region of one or more regions of the wafer. 3. The system according to Clause 1, wherein the controller includes a circuit system for: During a second time series in one or more time series, a second set of images of a first region in one or more regions is generated; Sample a first image from a first set of images, and sample a second image from a second set of images; and Compare the first image with the second image to identify defects in the first region of one or more regions of the wafer. 4. The system according to Clause 1, wherein the controller includes a circuit system for: During a second time series in one or more time series, a second set of images of a second region in one or more regions is generated, wherein the first region and the second region include the same device structure; Sample a first image from a first set of images, and sample a second image from a second set of images; and Compare the first image with the second image to identify defects in one or more regions of the wafer, either in the first region or the second region. 5. The system according to any one of Clauses 3 and 4, wherein the first image and the second image are sampled at corresponding times in the first time series and the second time series. 6. The system according to any one of Clauses 2 to 5, wherein the first image and the second image include voltage contrast levels. 7. The system according to Clause 6, wherein the controller includes a circuit system for detecting a difference between the voltage contrast level of a first image and the voltage contrast level of a second image to identify defects in the thin device structure. 8. The system according to any one of clauses 1 to 7, wherein the charged particle beam source includes a circuit system for: During the first part of one or more time series, one or more regions of the pre-scanned wafer are scanned; and During the second part of one or more time series, one or more regions of the wafer are examined. 9. The system according to Clause 8, wherein the charged particle beam source includes a circuit system for establishing one or more surface potentials at one or more regions of a wafer while performing a pre-scan during a first portion of one or more time series. 10. The system according to Clause 9, wherein the charged particle beam source performs a pre-scan until device breakdown occurs. 11. The system according to any one of clauses 1 to 10, wherein the controller includes a circuit system for adjusting the time interval between the generation of each image in the first set of images. 12. The system according to any one of clauses 2 to 10, wherein the controller includes a circuit system for adjusting the time interval between the generation of each image in the second set of images. 13. The system according to any one of clauses 1 to 12, wherein the defect includes an electrical defect associated with electrical leakage in the thin device structure at the region. 14. The system according to Clause 13, wherein the thin device structure includes thin oxide residues remaining after the etching process. 15. The system according to any one of clauses 1 to 14 further comprises: The detector, communicatively coupled to the controller, is configured to generate detection data based on the detection of secondary charged particles associated with charged particles affecting one or more regions of the wafer. 16. The system according to Clause 15, wherein the controller includes a circuit system that constructs a corresponding voltage comparison image based on detection data generated by the detector. 17. A method for inspecting a wafer using a charged particle beam system, the charged particle beam system having a charged particle beam source to direct charged particles onto one or more regions of the wafer in one or more time series, the method comprising: During a first time series within one or more time series, generate a first set of images of a first region within one or more regions; and The first set of images is processed to detect defects in the thin device structure within the wafer. 18. The method described pursuant to Clause 17 further comprises: A first image and a second image are sampled from a first set of images, wherein the first image is sampled at a first time point in the first time series, and the second image is sampled at a second time point in the first time series; and Compare the first image with the second image to identify defects in the first region of one or more regions of the wafer. 19. The method described pursuant to Clause 17 further comprises: During a second time series in one or more time series, a second set of images of a first region in one or more regions is generated; Sample a first image from a first set of images, and sample a second image from a second set of images; and Compare the first image with the second image to identify defects in one or more regions of the wafer in the first region. 20. The method described pursuant to Clause 17 further comprises: During a second time series in one or more time series, a second set of images of a second region in one or more regions is generated, wherein the first region and the second region include the same device structure; Sample a first image from a first set of images, and sample a second image from a second set of images; and Compare the first image with the second image to identify defects in one or more regions of the wafer, either in the first region or the second region. 21. The method according to any one of Clauses 19 and 20, wherein the first image and the second image are sampled at corresponding times in the first time series and the second time series. 22. The method according to any one of clauses 18 to 21, wherein the first image and the second image include voltage contrast levels. 23. The method according to Clause 22 further includes: detecting a difference between the voltage contrast level of the first image and the voltage contrast level of the second image to identify defects in the thin device structure. 24. The method according to any one of clauses 17 to 23 further includes: adjusting the time interval between the generation of each image in the first set of images. 25. The method according to any one of clauses 18 to 23 further includes: adjusting the time interval between the generation of each image in the second set of images. 26. A non-transitory computer-readable medium storing a set of instructions executable by a processor of a charged particle beam system to cause the charged particle beam system to perform a method having a charged particle beam source to direct a charged particle beam onto one or more regions of a wafer in one or more time sequences, the method comprising: During a first time series within one or more time series, generate a first set of images of a first region within one or more regions; and The first set of images is processed to detect defects in the thin device structure within the wafer. 27. The computer-readable medium according to Clause 26, wherein the set of instructions is executable by a processor of a charged particle beam system such that the charged particle beam system also performs: A first image and a second image are sampled from a first set of images, wherein the first image is sampled at a first time point in a first time series, and the second image is sampled at a second time point in the first time series; and Compare the first image with the second image to identify defects in one or more regions of the wafer in the first region. 28. The computer-readable medium according to Clause 26, wherein the set of instructions is executable by a processor of a charged particle beam system, such that the charged particle beam system also performs: During a second time series in one or more time series, a second set of images of a first region in one or more regions is generated; Sample a first image from a first set of images, and sample a second image from a second set of images; and Compare the first image with the second image to identify defects in one or more regions of the wafer in the first region. 29. The computer-readable medium according to Clause 26, wherein the set of instructions is executable by a processor of a charged particle beam system, such that the charged particle beam system also performs: During a second time series in one or more time series, a second set of images of a second region in one or more regions is generated, wherein the first region and the second region include the same device structure; Sample a first image from a first set of images, and sample a second image from a second set of images; and Compare the first image with the second image to identify defects in one or more regions of the wafer, either in the first region or the second region. 30. The computer-readable medium according to any one of clauses 28 and 29, wherein the set of instructions is executable by a processor of a charged particle beam system to cause the charged particle beam system to perform a method wherein the first image and the second image are sampled at corresponding times in the first time series and the second time series. 31. The computer-readable medium according to any one of Clauses 27 to 30, wherein the set of instructions is executable by a processor of a charged particle beam system to cause the charged particle beam system to perform a method, wherein the first image and the second image include voltage contrast levels. 32. The computer-readable medium according to Clause 31, wherein the set of instructions is executable by a processor of a charged particle beam system to cause the charged particle beam system to perform: The difference between the voltage contrast level of the first image and the voltage contrast level of the second image is detected to identify defects in the structure of thin devices. 33. The computer-readable medium according to any one of clauses 26 to 32, wherein the set of instructions is executable by a processor of a charged particle beam system to cause the charged particle beam system to perform: Adjust the time interval between the generation of each image in the first group of images. 34. The computer-readable medium according to any one of clauses 27 to 32, wherein the set of instructions is executable by a processor of a charged particle beam system to cause the charged particle beam system to perform: Adjust the time interval between the generation of each image in the second set of images.

[0077] It should be understood that image processing systems can use software to control the functionality described above. For example, an image processing system can control the functionality from a detector (such as...). Figure 2The detector 206 receives the signal and reconstructs the image of the wafer. Furthermore, the image processing system can execute image processing algorithms to adjust the brightness or contrast of the reconstructed image. The image processing system can also execute control functions to adjust the time interval between sampled images. The software can be stored on a non-transitory computer-readable medium. Common forms of non-transitory media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tape, or any other magnetic data storage medium, CD-ROMs, any other optical data storage medium, any physical medium with a perforated pattern, RAM, PROMs and EPROMs, cloud storage, FLASH-EPROMs, or any other flash memory, NVRAM, caches, registers, any other memory chips or cassette tapes, and their networked versions.

[0078] Although the disclosed embodiments have been explained with respect to their preferred embodiments, it should be understood that other modifications and variations may be made without departing from the spirit and scope of the subject matter claimed below.

Claims

1. A non-transitory computer-readable medium storing an instruction set executed by one or more processors of a charged particle beam system to cause the charged particle beam system to perform a method, the charged particle beam system having a charged particle beam source to direct charged particles onto a wafer, the method comprising: During the first time sequence, time intervals are controlled to generate each image in a first set of images of a first region of the wafer; as well as The first set of images is processed to detect defects in the wafer.

2. The computer-readable medium of claim 1, wherein the set of instructions executable by the one or more processors of the charged particle beam system causes the charged particle beam system to further perform: Sampling is performed on a first image and a second image from the first set of images, wherein the first image is sampled at a first time and the second image is sampled at a second time; and The first image is compared with the second image to identify the defect at the first region of the wafer.

3. The computer-readable medium of claim 2, wherein the first image and the second image include voltage contrast levels.

4. The computer-readable medium of claim 3, wherein the set of instructions executable by the one or more processors of the charged particle beam system causes the charged particle beam system to further perform: The difference between the voltage contrast level of the first image and the voltage contrast level of the second image is detected to identify defects in the wafer.

5. The computer-readable medium of claim 1, wherein the set of instructions executable by the one or more processors of the charged particle beam system causes the charged particle beam system to further perform: A second set of images of the first region is generated during the second time series. A first image from the first set of images is sampled, and a second image from the second set of images is sampled; and The first image is compared with the second image to identify the defect at the first region of the wafer.

6. The computer-readable medium of claim 5, wherein the first image and the second image are sampled at corresponding times in the first time series and the second time series.

7. The computer-readable medium of claim 1, wherein the set of instructions executable by the one or more processors of the charged particle beam system causes the charged particle beam system to further perform: During a second time series, a second set of images of a second region of the wafer is generated, wherein the first region and the second region contain the same device structure; A first image is sampled from the first set of images, and a second image is sampled from the second set of images; as well as The first image is compared with the second image to identify the defect in the first or second region of the wafer.

8. The computer-readable medium of claim 5, wherein the set of instructions executable by the one or more processors of the charged particle beam system causes the charged particle beam system to further perform: Control the time interval between each image in the second group of images.

9. A method for inspecting a wafer using a charged particle beam system, the charged particle beam system having a charged particle beam source to direct charged particles onto the wafer, the method comprising: During the first time sequence, time intervals are controlled to generate each image in a first set of images of a first region of the wafer; as well as The first set of images is processed to detect defects in the wafer.

10. The method of claim 9, further comprising: A first image and a second image from the first set of images are sampled, wherein the first image is sampled at a first time and the second image is sampled at a second time; as well as The first image is compared with the second image to identify the defect at the first region of the wafer.

11. The method of claim 10, wherein the first image and the second image include voltage contrast levels.

12. The method of claim 11, further comprising detecting a difference between the voltage contrast level of the first image and the voltage contrast level of the second image to identify defects in the wafer.

13. The method of claim 9, further comprising: A second set of images of the first region is generated during the second time series. A first image from the first set of images is sampled, and a second image from the second set of images is sampled. as well as The first image is compared with the second image to identify the defect at the first region of the wafer.

14. The method of claim 13, wherein the first image and the second image are sampled at corresponding times in the first time series and the second time series.

15. The method of claim 9, further comprising: During a second time series, a second set of images of a second region of the wafer is generated, wherein the first region and the second region contain the same device structure; A first image is sampled from the first set of images, and a second image is sampled from the second set of images; as well as The first image is compared with the second image to identify the defect in the first or second region of the wafer.

16. The method of claim 15, further comprising controlling the time interval between each image in the second set of images.

Images