Clock duty ratio calibration circuit based on digital-analog hybrid control delay line

Abstract

The invention discloses a clock duty ratio calibration circuit based on a digital-analog hybrid control delay line. The clock duty ratio calibration circuit comprises a delay line adjusting circuit, a single-ended to differential circuit, a charge pump, a low-pass filter and a transconductance operational amplifier, the delay line adjusting circuit is used for adjusting the time of the rising edge and the falling edge of the input clock signal; the single-ended to differential circuit is used for converting the adjusted clock signal into a differential clock signal and shaping the differential clock signal; the charge pump is used for converting the shaped differential clock signal into a differential signal; the low-pass filter is used for filtering the differential signal to obtain a filtered differential signal; and the operational transconductance amplifier is used for converting the common-mode error of the filtered differential signal into feedback voltage. According to the invention, the correction precision of the duty ratio is improved, the adjustable frequency range and the input duty ratio range of the clock are enlarged, and the output of the duty ratio of the clock can be adjusted by self-adapting to the power supply voltage disturbance and the temperature change.

Description

Technical Field

[0001] This invention belongs to the field of signal chain transmission technology, specifically relating to a clock duty cycle calibration circuit based on a mixed-signal control delay line. Background Technology

[0002] Signal chain transmission technology includes key modules such as multi-protocol serial links, memory interfaces, and high-frequency analog-to-digital converters (ADCs). These modules typically have dedicated clock systems, therefore, clock signal integrity directly affects high-performance signal transmission. Clock signal duty cycle is a critical parameter for signal integrity; variations in this parameter can lead to deterministic jitter in the serial link and degrade the signal-to-noise ratio of the ADC, and may even severely impact the functionality of clock duty cycle-sensitive circuits such as sample-and-hold and decision feedback equalizers. Therefore, ensuring the accuracy of the clock signal duty cycle is essential. Furthermore, to ensure the normal operation of high-speed signal systems over an ultra-wide operating frequency range, the selection of the Duty Cycle Correction (DCC) circuit architecture is particularly important. Summary of the Invention

[0003] To address the aforementioned problems in the prior art, this invention provides a clock duty cycle calibration circuit based on a mixed-signal control delay line.

[0004] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a clock duty cycle calibration circuit based on a mixed-signal control delay line, the circuit comprising: a delay line adjustment circuit, a single-ended to differential circuit, a charge pump, a low-pass filter, and a transconductance operational amplifier; The delay line adjustment circuit is used to adjust the rising and falling times of the input clock signal to obtain the adjusted clock signal and output it to the single-ended to differential circuit. The single-ended to differential circuit is used to convert the adjusted clock signal into a differential clock signal and shape the differential clock signal to obtain a shaped differential clock signal, which is then output to the charge pump. The charge pump is used to convert the shaped differential clock signal into a differential signal and output it to the low-pass filter; The low-pass filter is used to filter the differential signal to obtain a filtered differential signal, which is then output to the transconductance operational amplifier. The transconductance operational amplifier is used to convert the common-mode error of the filtered differential signal into a feedback voltage; wherein the feedback voltage controls the gate voltage of the NMOS transistor in the delay line adjustment circuit through negative feedback.

[0005] Optionally, the delay adjustment circuit includes: a delay line, a voltage-controlled delay line, and a digitally controlled delay line; The delay line is used to adjust the rising and falling times of the input clock signal according to the control level VP and the control level VN. The voltage control delay line is used to adjust the control level VN according to the feedback voltage; The digital control delay line is used to adjust the number of connected MOS transistors according to the connected digital control word, so as to adjust the control level VN and the control level VP.

[0006] Optionally, the voltage control delay line includes: a transistor M18; the gate of the transistor M18 is connected to a feedback voltage.

[0007] Optionally, the digital control delay line includes: transistors M0, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, and M13; the sources of transistors M0, M1, M2, M3, M4, and M11 are all grounded, and transistors M0, M1, M2, M3, M4, and M11 are all connected to the gate and drain of the drain transistor M10; the gate of transistor M0 is connected to the digital control word P. <0> The gate of transistor M1 is connected to the digital control word P. <1> The gate of transistor M2 is connected to the digital control word P. <2> The gate of transistor M3 is connected to the digital control word P. <3> The gate of transistor M4 is connected to the digital control word P. <4> The gate of transistor M11 and the source of transistor M10 are connected to the power supply. The sources of transistors M5, M6, M7, M8, M9, M12, and M18 are all connected to the power supply. The drains of transistors M5, M6, M7, M8, M9, M12, and M18 are all connected to the drain and gate of transistor M13. The source of transistor M13 is grounded. The gate of transistor M5 is connected to the digital control word N. <0> The gate of transistor M6 is connected to the digital control word N. <1> The gate of transistor M7 is connected to the digital control word N. <2> The gate of transistor M8 is connected to the digital control word N. <3> The gate of transistor M9 is connected to the digital control word N. <4> .

[0008] Optionally, the delay line includes transistors M14, M15, M16, and M17; the gate of transistor M14 is connected to the drain of transistor M10, the source of transistor M14 is connected to the power supply, the drain of transistor M14 is connected to the source of transistor M15, the gates of transistors M15 and M16 are both connected to the input clock signal, the drains of transistors M15 and M16 output the adjusted clock signal, the source of transistor M16 is connected to the drain of transistor M17, the gate of transistor M17 is connected to the gate of transistor M13, and the source of transistor M17 is grounded.

[0009] Optionally, the single-ended to differential circuit includes an inverter M19, a transmission gate M20, an inverter M21, an inverter M22, an inverter M23, an inverter M24, an inverter M25, an inverter M26, an inverter M27, and an inverter M28; the input terminal of inverter M19 and the first port of transmission gate M20 are both connected to the adjusted clock signal; the output terminal of inverter M19 is connected to the input terminals of inverters M21 and M23 respectively; the output terminal of inverter M21 is connected to the input terminal of inverter M25; and the input terminals of inverters M22 and M26 are... All are connected to the second port of transmission gate M20. The output of inverter M22 is connected to the input of inverter M24. The first gate of transmission gate M20 is connected to the power supply. The second gate of transmission gate M20 is grounded. The outputs of inverters M23 and M24 are both connected to the input of inverter M27. Inverter M27 outputs the first differential clock signal in the shaped differential clock signal. The outputs of inverters M25 and M26 are both connected to the input of inverter M28. Inverter M28 outputs the second differential clock signal in the shaped differential clock signal.

[0010] Optionally, the charge pump includes transistors M31, M32, M33, and M34, a charging current source M29, and a discharging current source M30; the input terminal of the charging current source M29 is connected to a power supply, the output terminal of the charging current source M29 is connected to the sources of transistors M31 and M32 respectively, the gates of transistors M31 and M33 are both connected to a first differential clock signal, the drain of transistor M31 is connected to the drain of transistor M33, the sources of transistors M33 and M34 are both connected to the input terminal of the discharging current source M30, the output terminal of the discharging current source M30 is grounded, the gates of transistors M32 and M34 are both connected to a second differential clock signal, and the drain of transistor M32 is connected to the drain of transistor M34.

[0011] Optionally, the low-pass filter includes: resistor M35, capacitor M36, resistor M37, capacitor M38, and capacitor M39; the first terminal of resistor M35 is connected to the drain of transistor M31 and the first terminal of capacitor M38, the second terminal of resistor M35 is connected to the first terminal of capacitor M36, the second terminal of capacitor M36 is connected to the first terminal of resistor M37, the second terminal of resistor M37 is connected to the drain of transistor M34 and the first terminal of capacitor M39, and the second terminals of capacitors M38 and M39 are both grounded.

[0012] Optionally, the transconductance operational amplifier includes: a 5-transistor active load differential pair M40; the first input terminal of the 5-transistor active load differential pair M40 is connected to the first terminal of capacitor M38, the second input terminal of the 5-transistor active load differential pair M40 is connected to the first terminal of capacitor M39, and the 5-transistor active load differential pair M40 outputs a feedback voltage.

[0013] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects: In the above technical solution, the clock duty cycle calibration circuit based on the mixed-signal control delay line designed in this invention introduces calibration of both digital control delay line and voltage control delay line loops. Combining the advantages of the wide adjustable clock frequency range of the digital control delay line and the high adjustment accuracy of the analog feedback voltage control delay line, it can transform the originally discrete and discontinuously adjustable delay line charging and discharging current into a continuously adjustable current. The voltage control delay line acts as a sliding rheostat, improving the correction accuracy of the duty cycle and increasing the adjustable frequency range and input duty cycle range of the clock. At the same time, the clock duty cycle calibration circuit based on the mixed-signal control delay line itself has a negative feedback adjustment loop, which can adaptively adjust the clock duty cycle output based on power supply voltage disturbances and temperature changes.

[0014] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a clock duty cycle calibration circuit based on a mixed-signal control delay line provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a delay adjustment circuit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a single-ended to differential circuit provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a charge pump, a low-pass filter, and a transconductance operational amplifier provided in an embodiment of the present invention. Detailed Implementation

[0016] To facilitate understanding of the present invention, a brief description of the prior art and the inventive concept of the present invention will be provided first.

[0017] Existing technologies primarily employ three architectures to calibrate clock duty cycle errors. The first is an analog detection and analog adjustment architecture. This architecture constructs a feedback loop consisting of a duty cycle adjustment (DCA) current-mode circuit, a clock buffer, a low-pass filter, and a duty cycle detector (DCD) integrator circuit. This enables high-frequency clock correction and high-precision calibration, but this structure requires a long time to stabilize the loop and may experience duty cycle fluctuations due to leakage current. The second is a digital detection and digital adjustment architecture. This architecture detects clock duty cycle errors through a digital state machine circuit and adjusts the delay of the half-cycle delay line or digitally controlled delay line based on coarse / fine delay control codes. The output delay difference signal is processed by the duty cycle adjustment module to output a calibrated duty cycle clock. The calibrated duty cycle clock is then input to the analog-to-digital converter's duty cycle detection circuit for the next cycle's duty cycle calibration decision, modifying the coarse / fine delay control codes output by the digital state machine. This duty cycle calibration method can quickly lock the clock, but its accuracy is relatively low. Furthermore, the large number of combinational logic gates in the digital circuit limits the frequency of the clock being detected. High-frequency clock detection requires advanced process technology for digital circuits, resulting in higher costs. Thirdly, there is the mixed-signal architecture, which mostly uses analog detection and digital adjustment. This involves constructing a duty cycle adjustment current control circuit, a single-ended to differential circuit, a charge pump and low-pass filter, and a feedback loop of a transconductance operational amplifier. This architecture can maintain good accuracy while achieving high-frequency clock duty cycle calibration, but the charging and discharging capability of the current control module depends on the range of voltage variation in the feedback loop, and it lacks a wide duty cycle adjustment range.

[0018] Therefore, this invention proposes a clock duty cycle calibration circuit based on a mixed-signal control delay line to solve this technical problem.

[0019] Figure 1 This is a schematic diagram of a clock duty cycle calibration circuit based on a mixed-signal control delay line provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the circuit includes: a delay line adjustment circuit 10, a single-ended to differential circuit 20, a charge pump 30, a low-pass filter 40, and a transconductance operational amplifier 50; The delay line adjustment circuit 10 is used to adjust the rising and falling times of the input clock signal to obtain the adjusted clock signal and output it to the single-ended to differential circuit.

[0020] It is understood that, in one embodiment of the present invention, taking a 5-bit control code as an example, the high and low levels of the digital codes N<0:4> and P<0:4> are assigned values, and the logic levels of N<0:4> and P<0:4> determine whether the parallel transistor connected to the delay line is in the on or off state.

[0021] Optionally, Figure 2 This is a schematic diagram of a delay adjustment circuit provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the delay adjustment circuit 10 includes: a delay line 103, a voltage-controlled delay line 101, and a digitally controlled delay line 102; Delay line 103 is used to adjust the rising and falling times of the input clock signal according to the control level VP and the control level VN; Voltage control delay line 101 is used to adjust the control level VN according to the feedback voltage; The digital control delay line 102 is used to adjust the number of connected MOS transistors according to the connected digital control word, so as to adjust the control level VN and the control level VP.

[0022] Optionally, the voltage-controlled delay line 101 includes: a transistor M18; the gate of the transistor M18 is connected to a feedback voltage.

[0023] It is understandable that in the voltage control delay line module 101, the fine-tuning of VN using a PMOS as the analog feedback voltage control transistor is illustrated, but it can also be achieved by using an NMOS as the analog feedback voltage control transistor to fine-tune VP. VCTRL is the feedback voltage of the duty cycle detection circuit. The magnitude of VCTRL affects the conduction current of transistor M18, which is equivalent to changing the resistance value of transistor M18 in the ratio logic. Therefore, the control level VN will change during the negative feedback adjustment process. In this example, there are several factors to consider in the design of the size of transistor M18. The size of transistor M18 should not be too small, otherwise the adjustable range of the resistance value will be small, and fine adjustment will not be able to continuously cover the difference between the 32 discrete digital control levels VN. The size of transistor M18 should not be too large. If the change in resistance value is too drastic with the change of VCTRL, it will lead to a decrease in the adjustment accuracy and may cause loop oscillation, making it impossible to lock. In this example of the invention, the size of transistor M18 is the same as that of transistor M7, which ensures a large adjustment range while also ensuring loop stability.

[0024] Optionally, the digital control delay line 102 includes transistors M0, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, and M13; the sources of transistors M0, M1, M2, M3, M4, and M11 are all grounded, and the drains of transistors M0, M1, M2, M3, M4, and M11 are all connected to the gate and drain of transistor M10; the gate of transistor M0 is connected to the digital control word P. <0> The gate of transistor M1 is connected to the digital control word P. <1> The gate of transistor M2 is connected to the digital control word P. <2> The gate of transistor M3 is connected to the digital control word P. <3> The gate of transistor M4 is connected to the digital control word P. <4> The gate of transistor M11 and the source of transistor M10 are connected to the power supply. The sources of transistors M5, M6, M7, M8, M9, M12, and M18 are all connected to the power supply. The drains of transistors M5, M6, M7, M8, M9, M12, and M18 are all connected to the drain and gate of transistor M13. The source of transistor M13 is grounded. The gate of transistor M5 is connected to the digital control word N. <0> The gate of transistor M6 is connected to the digital control word N. <1> The gate of transistor M7 is connected to the digital control word N. <2> The gate of transistor M8 is connected to the digital control word N. <3> The gate of transistor M9 is connected to the digital control word N. <4> .

[0025] Understandably, in the digital control delay line module 102, the gates of the PMOS gate voltage adjustment branches M0~M4 and NMOS gate voltage adjustment branches transistors M5~M9 are connected to digital control words P<0:4> and N<0:4>, respectively, to independently adjust the number of connected MOS transistors. The dimensions of transistors M0~M4 and M5~M9 are designed to increase in a binary manner, thus widening the adjustable range. Each set of control words corresponds to a set of connected MOS transistor gate widths. The PMOS gate voltage control branch transistors M0~M4 are connected in parallel with the normally-on transistor M11, and then in series with the diode-connected transistor M10 to form a ratio logic. Therefore, the five-bit control word P<0:4> provides 32 different control levels VP. Similarly, the NMOS gate voltage control branch transistors M5~M9 are connected in parallel with the normally-on transistor M12, and then in series with the diode-connected transistor M13 to form a ratio logic. Therefore, the five-bit control word N<0:4> provides 32 different control levels VN.

[0026] Optionally, the delay line 103 includes transistors M14, M15, M16, and M17; the gate of transistor M14 is connected to the drain of transistor M10, the source of transistor M14 is connected to the power supply, the drain of transistor M14 is connected to the source of transistor M15, the gates of transistors M15 and M16 are both connected to the input clock signal, the drains of transistors M15 and M16 output the adjusted clock signal, the source of transistor M16 is connected to the drain of transistor M17, the gate of transistor M17 is connected to the gate of transistor M13, and the source of transistor M17 is grounded.

[0027] Understandably, in the delay line module 103, the control level VP controls the charging capability of transistor M14, and the control level VN controls the discharging capability of transistor M17. The charging speed of the output adjusted clock signal CK_DCC is controlled by the charging capability of transistor M14, and the discharging speed is controlled by the discharging capability of transistor M17. Therefore, under the action of the delay line module, the rising and falling edges of the input clock signal CK_IN with the input duty cycle offset become slower or faster, resulting in the output clock signal CK_DCC with the adjusted duty cycle.

[0028] The single-ended to differential circuit 20 is used to convert the adjusted clock signal into a differential clock signal and shape the differential clock signal to obtain a shaped differential clock signal, which is then output to the charge pump.

[0029] Optionally, Figure 3 This is a schematic diagram of a single-ended to differential circuit provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the single-ended to differential circuit 20 includes an inverter M19, a transmission gate M20, an inverter M21, an inverter M22, an inverter M23, an inverter M24, an inverter M25, an inverter M26, an inverter M27, and an inverter M28. The input terminal of inverter M19 and the first port of transmission gate M20 are both connected to the adjusted clock signal. The output terminal of inverter M19 is connected to the input terminals of inverters M21 and M23, respectively. The output terminal of inverter M21 is connected to the input terminal of inverter M25. The input terminals of inverters M22 and M26 are... The output of inverter M22 is connected to the input of inverter M24, the first gate of inverter M20 is connected to the power supply, the second gate of inverter M20 is grounded, the outputs of inverters M23 and M24 are both connected to the input of inverter M27, and inverter M27 outputs the first differential clock signal in the shaped differential clock signal. The outputs of inverters M25 and M26 are both connected to the input of inverter M28, and inverter M28 outputs the second differential clock signal in the shaped differential clock signal.

[0030] Understandably, firstly, the adjusted clock signal CK_DCC output from the delay line adjustment circuit 10 is divided into two branches: one branch is inverted and output to node X0 after passing through an inverter, and the other branch is output in phase and output to node X1 after passing through a transmission gate. The charging and discharging capabilities of M19 and M20 should be designed to be as consistent as possible to reduce the clock phase difference between nodes X0 and X1. Then, the phase error between nodes X0 and X1 is effectively eliminated after being logically interlocked by the six inverters M21 to M26. M27 and M28 further shape the clock and provide driving capability, finally outputting the shaped differential clock signals CK+ and CK-.

[0031] Charge pump 30 is used to convert the shaped differential clock signal into a differential signal and output it to a low-pass filter.

[0032] Optionally, the charge pump 30 is used to sink and pull current at the output node of the low-pass filter 40. The timing of the pull and sink currents depends on the duty cycle error of the input differential clock. When the duty cycle of the input clock is highly symmetrical, the magnitudes of the pull and sink currents are consistent.

[0033] Optionally, Figure 4 This is a schematic diagram of the structure of a charge pump, a low-pass filter, and a transconductance operational amplifier provided in an embodiment of the present invention, as shown below. Figure 4 As shown, the charge pump includes transistors M31, M32, M33, and M34, a charging current source M29, and a discharging current source M30. The input terminal of the charging current source M29 is connected to the power supply, and the output terminal of the charging current source M29 is connected to the sources of transistors M31 and M32 respectively. The gates of transistors M31 and M33 are both connected to a first differential clock signal. The drain of transistor M31 is connected to the drain of transistor M33. The sources of transistors M33 and M34 are both connected to the input terminal of the discharging current source M30. The output terminal of the discharging current source M30 is grounded. The gates of transistors M32 and M34 are both connected to a second differential clock signal, and the drain of transistor M32 is connected to the drain of transistor M34.

[0034] Understandably, in the design of charge pump 30, transistors M31~M34 are used to integrate the duty cycle logic high and low level durations of the shaped differential clock signals CK+ and CK-, and output a pair of differential signals to enter the low-pass filter. When the duty cycles of CK+ and CK- are both adjusted to around 50%, the charging and discharging currents within one cycle are equal, and the common-mode levels at X2 and X3 do not change. The design of the charge pump must ensure that the charging current source M29 and the discharging current source M30 have comparable charging and discharging capabilities; mismatch in the charge pump will affect the accuracy of duty cycle detection.

[0035] The low-pass filter 40 is used to filter the differential signal to obtain the filtered differential signal, and then output it to the transconductance operational amplifier.

[0036] Optionally, such as Figure 4 As shown, the low-pass filter 40 includes: resistor M35, capacitor M36, resistor M37, capacitor M38, and capacitor M39; the first end of resistor M35 is connected to the drain of transistor M31 and the first end of capacitor M38 respectively; the second end of resistor M35 is connected to the first end of capacitor M36; the second end of capacitor M36 is connected to the first end of resistor M37; the second end of resistor M37 is connected to the drain of transistor M34 and the first end of capacitor M39 respectively; the second ends of capacitors M38 and M39 are both grounded.

[0037] Understandably, the low-pass filter structure 40 is related to loop stability. This invention uses a second-order Miller low-pass filter, composed of M35 to M39, which can achieve higher stability and reduce the time required for locking compared to a first-order Miller low-pass filter.

[0038] The transconductance operational amplifier 50 is used to convert the common-mode error of the filtered differential signal into a feedback voltage; wherein, the feedback voltage controls the gate voltage of the NMOS transistor in the delay line adjustment circuit through negative feedback.

[0039] Optionally, such as Figure 4 As shown, the transconductance operational amplifier 50 includes: a 5-transistor active load differential pair M40; the first input terminal of the 5-transistor active load differential pair M40 is connected to the first terminal of capacitor M38, the second input terminal of the 5-transistor active load differential pair M40 is connected to the first terminal of capacitor M39, and the 5-transistor active load differential pair M40 outputs a feedback voltage.

[0040] Understandably, the transconductance operational amplifier 50 is designed to convert the common-mode level offset of the filtered differential signal into a control voltage VCTRL, which acts on transistor M18 of the delay line adjustment circuit 10, forming a negative feedback for the system. To obtain a higher phase margin, this design uses a 5-transistor active load differential pair M40 as the transconductance operational amplifier circuit in the loop. Based on the design using a Miller second-order low-pass filter, and considering the gain of the transconductance operational amplifier itself and the overall stability of the loop, the designed DCD circuit outputs a feedback voltage VCTRL with low ripple and high calibration accuracy.

[0041] This invention not only calibrates the clock frequency required for interface circuits of various protocols, but also adapts to duty cycle offset caused by power supply voltage disturbances and temperature changes under the action of feedback voltage. It solves the problem in the prior art that advanced process technology is required to design a digital state machine to detect duty cycle offset in calibration circuits based on delay lines, thus saving application costs. Furthermore, it changes the duty cycle adjustment circuit based on digital control codewords to a hybrid digital-analog control form, improving calibration accuracy.

[0042] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0043] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0044] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0045] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A clock duty cycle calibration circuit based on a mixed-signal control delay line, characterized in that, The circuit includes: a delay line adjustment circuit, a single-ended to differential circuit, a charge pump, a low-pass filter, and a transconductance operational amplifier; The delay line adjustment circuit is used to adjust the rising and falling times of the input clock signal to obtain the adjusted clock signal and output it to the single-ended to differential circuit. The single-ended to differential circuit is used to convert the adjusted clock signal into a differential clock signal and shape the differential clock signal to obtain a shaped differential clock signal, which is then output to the charge pump. The charge pump is used to convert the shaped differential clock signal into a differential signal and output it to the low-pass filter; The low-pass filter is used to filter the differential signal to obtain a filtered differential signal, which is then output to the transconductance operational amplifier. The transconductance operational amplifier is used to convert the common-mode error of the filtered differential signal into a feedback voltage; wherein the feedback voltage controls the gate voltage of the NMOS transistor in the delay line adjustment circuit through negative feedback.

2. The clock duty cycle calibration circuit based on a mixed-signal control delay line according to claim 1, characterized in that, The delay adjustment circuit includes: a delay line, a voltage-controlled delay line, and a digitally controlled delay line; The delay line is used to adjust the rising and falling times of the input clock signal according to the control level VP and the control level VN. The voltage control delay line is used to adjust the control level VN according to the feedback voltage; The digital control delay line is used to adjust the number of connected MOS transistors according to the connected digital control word, so as to adjust the control level VN and the control level VP.

3. The clock duty cycle calibration circuit based on a mixed-signal control delay line according to claim 2, characterized in that, The voltage-controlled delay line includes a transistor M18; the gate of the transistor M18 is connected to a feedback voltage.

4. The clock duty cycle calibration circuit based on a mixed-signal control delay line according to claim 3, characterized in that, The digital control delay line includes transistors M0, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, and M13. The sources of transistors M0, M1, M2, M3, M4, and M11 are all grounded. The drains of transistors M0, M1, M2, M3, M4, and M11 are all connected to the gate and drain of transistor M10. The gate of transistor M0 is connected to the digital control word P. <0> The gate of transistor M1 is connected to the digital control word P. <1> The gate of transistor M2 is connected to the digital control word P. <2> The gate of transistor M3 is connected to the digital control word P. <3> The gate of transistor M4 is connected to the digital control word P. <4> The gate of transistor M11 and the source of transistor M10 are connected to the power supply. The sources of transistors M5, M6, M7, M8, M9, M12, and M18 are all connected to the power supply. The drains of transistors M5, M6, M7, M8, M9, M12, and M18 are all connected to the drain and gate of transistor M13. The source of transistor M13 is grounded. The gate of transistor M5 is connected to the digital control word N. <0> The gate of transistor M6 is connected to the digital control word N. <1> The gate of transistor M7 is connected to the digital control word N. <2> The gate of transistor M8 is connected to the digital control word N. <3> The gate of transistor M9 is connected to the digital control word N. <4> .

5. The clock duty cycle calibration circuit based on a mixed-signal control delay line according to claim 4, characterized in that, The delay line includes transistors M14, M15, M16, and M17. The gate of transistor M14 is connected to the drain of transistor M10, the source of transistor M14 is connected to the power supply, the drain of transistor M14 is connected to the source of transistor M15, the gates of transistors M15 and M16 are both connected to the input clock signal, the drains of transistors M15 and M16 output the adjusted clock signal, the source of transistor M16 is connected to the drain of transistor M17, the gate of transistor M17 is connected to the gate of transistor M13, and the source of transistor M17 is grounded.

6. The clock duty cycle calibration circuit based on a mixed-signal control delay line according to claim 1, characterized in that, The single-ended to differential circuit includes inverter M19, transmission gate M20, inverter M21, inverter M22, inverter M23, inverter M24, inverter M25, inverter M26, inverter M27, and inverter M28. The input terminal of inverter M19 and the first port of transmission gate M20 are both connected to the adjusted clock signal. The output terminal of inverter M19 is connected to the input terminals of inverters M21 and M23, respectively. The output terminal of inverter M21 is connected to the input terminal of inverter M25. The input terminals of inverters M22 and M26 are both connected to... The second port of transmission gate M20 is connected, the output of inverter M22 is connected to the input of inverter M24, the first gate of transmission gate M20 is connected to the power supply, the second gate of transmission gate M20 is grounded, the outputs of inverters M23 and M24 are both connected to the input of inverter M27, inverter M27 outputs the first differential clock signal in the shaped differential clock signal, the outputs of inverters M25 and M26 are both connected to the input of inverter M28, inverter M28 outputs the second differential clock signal in the shaped differential clock signal.

7. The clock duty cycle calibration circuit based on a mixed-signal control delay line according to claim 6, characterized in that, The charge pump includes transistors M31, M32, M33, and M34, a charging current source M29, and a discharging current source M30. The input terminal of the charging current source M29 is connected to a power supply, and the output terminal of the charging current source M29 is connected to the sources of transistors M31 and M32 respectively. The gates of transistors M31 and M33 are both connected to a first differential clock signal. The drain of transistor M31 is connected to the drain of transistor M33. The sources of transistors M33 and M34 are both connected to the input terminal of the discharging current source M30. The output terminal of the discharging current source M30 is grounded. The gates of transistors M32 and M34 are both connected to a second differential clock signal, and the drain of transistor M32 is connected to the drain of transistor M34.

8. The clock duty cycle calibration circuit based on a mixed-signal control delay line according to claim 7, characterized in that, The low-pass filter includes: resistor M35, capacitor M36, resistor M37, capacitor M38, and capacitor M39; the first terminal of resistor M35 is connected to the drain of transistor M31 and the first terminal of capacitor M38, the second terminal of resistor M35 is connected to the first terminal of capacitor M36, the second terminal of capacitor M36 is connected to the first terminal of resistor M37, the second terminal of resistor M37 is connected to the drain of transistor M34 and the first terminal of capacitor M39, and the second terminals of capacitors M38 and M39 are both grounded.

9. The clock duty cycle calibration circuit based on a mixed-signal control delay line according to claim 8, characterized in that, The transconductance operational amplifier includes: a 5-transistor active load differential pair M40; the first input terminal of the 5-transistor active load differential pair M40 is connected to the first terminal of capacitor M38, the second input terminal of the 5-transistor active load differential pair M40 is connected to the first terminal of capacitor M39, and the 5-transistor active load differential pair M40 outputs a feedback voltage.

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