A method for reducing clock and data jitter during CDR recovery and a digital-to-analog converter thereof

Abstract

The application relates to the technical field of clock signal recovery, and discloses a method for reducing CDR (Clock Data Recovery) recovered clock and data jitter, which comprises the following steps: generating a plurality of phase-locked clock signals through a phase-locked loop (PLL); selecting two pairs of differential clock signals which are orthogonal from the plurality of phase-locked clock signals through a phase interval selection module, and taking the two pairs of differential clock signals as interpolation intervals; interpolating the two pairs of orthogonal clock signals through a phase interpolation module to generate a new pair of orthogonal sampling clock signals, and the driving current of the phase interpolation module is provided by an IDAC (current digital-to-analog converter). The application adds a clamping tube in the current IDAC, so that the clamping tube provides stable and non-overshoot driving current for the interpolation module, and then the clock signal output by the interpolation module can be smoothly switched without overshoot when the phase is switched, so that the jitter of the recovered clock is greatly reduced; meanwhile, because the recovered clock is used to sample and deserial the received data, the jitter of the recovered data is also indirectly reduced.

Description

Technical Field

[0001] This invention relates to the field of clock signal recovery technology, and in particular to a method for reducing clock and data jitter during CDR recovery and a digital-to-analog converter thereof. Background Technology

[0002] High-speed serial communication systems mainly consist of three parts: the transmitter, the receiver, and the intermediate medium. The receiver is the most complex to design. It must not only be able to correctly receive the attenuated and superimposed crosstalk and noise signals from the channel, but also correctly sample and decode the high-speed serial signal and recover the clock signal with the same frequency as the signal. The module with this function is called the clock data recovery circuit, or CDR.

[0003] There are various ways to implement a Clock Reset (CDR), such as CDRs based on PLL / DLL / hybrid types with / without reference clocks, phase interpolation-based, injection-locked, and oversampling-based CDRs, etc. Each type of CDR has its own advantages and disadvantages, depending mainly on the application requirements. This invention is based on a phase interpolation-based CDR. This structure has fast locking speed, is easy to stabilize, and has a large frequency acquisition range. However, due to the influence of quantization errors, the recovered clock and data have relatively large jitter. The linearity of the interpolator and the delay overshoot during interpolation code switching can cause deterministic jitter in the recovered clock and data. Summary of the Invention

[0004] This invention provides a method for reducing CDR recovery clock and data jitter and a digital-to-analog converter to solve existing technical problems, and solves the deterministic jitter problem caused by charge injection due to voltage changes at the IDAC current device terminal in the interpolator.

[0005] To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, a method for reducing CDR recovery clock and data jitter, comprising the following steps:

[0006] S1. Generate a multi-phase clock signal through a phase-locked loop (PLL);

[0007] S2. Select two pairs of orthogonal differential clock signals from the multiphase clock signals through the phase interval selection module as the interpolation interval;

[0008] S3. The two pairs of quadrature clock signals are interpolated by the phase interpolation module to generate a new pair of quadrature sampling clock signals, and the drive current of the phase interpolation module is provided by the current-mode digital-to-analog converter IDAC.

[0009] S4. The sampling module uses an orthogonal sampling clock signal to sample the input serial data and outputs an edge sampling signal and a data sampling signal.

[0010] S5. The edge sampling signal and data sampling signal are processed by the digital processing module to generate interpolation control code for controlling the current-mode digital-to-analog converter (IDAC) to adjust the phase of the quadrature sampling clock signal.

[0011] S6. When the phase of the quadrature sampling clock signal is adjusted to lock by the digital processing module, the sampling clock signal is the CDR recovery clock, and the sampled and deserialized data is the CDR recovery data.

[0012] Furthermore, the multi-phase clock signal is a four-phase clock signal or an eight-phase clock signal; the interpolation control code is a thermometer code. Specifically, the advantages of thermometer code-controlled current-type IDAC are:

[0013] Thermometer code is a glitch-free encoding method. Changes in each bit only cause a change in current of one unit, avoiding current spikes caused by multiple bit jumps during binary code switching, thereby further reducing jitter.

[0014] Furthermore, step S7 specifically includes:

[0015] When the interpolation control code is at the first level, the switch is turned off, and the control circuit turns on the clamping transistor to clamp the voltage of the connected node to a preset voltage value.

[0016] When the interpolation control code switches to the second level, the switching transistor is turned on, and the control circuit turns off the clamping transistor.

[0017] Furthermore, the preset voltage value is between 240mV and 510mV. The clamping voltage VCL varies between 240mV and 510mV. The preset voltage design goal of this clamping voltage is to make it as close as possible to the switching transistor when it is turned on and off, thereby minimizing the voltage change ΔV. The specific value of VCL depends on factors such as process technology, power supply voltage, and transistor size, and needs to be determined through simulation optimization.

[0018] Furthermore, the control circuit includes a transmission gate and a control transistor;

[0019] The first control terminal of the transmission gate receives the interpolation control code, and the second control terminal of the transmission gate receives the inverted signal of the interpolation control code.

[0020] The gate of the control transistor receives the inverted signal of the interpolation control code, the source of the control transistor is connected to the power supply voltage, and the drain of the control transistor is connected to the gate of the clamping transistor.

[0021] The transmission gate is used to turn on when the switch is off, pull down the gate voltage of the clamping transistor to turn it on, and turn off when the switch is on.

[0022] Furthermore, the control circuit further includes an inverter for generating an inverted signal of the interpolation control code and providing it to the second control terminal of the transmission gate and the gate of the control transistor.

[0023] The transmission gate is composed of a PMOS transistor and an NMOS transistor connected in parallel. Its first control terminal receives the interpolation control code, and its second control terminal receives the inverted signal.

[0024] The control transistor is a PMOS transistor, whose gate receives an inverted signal, whose source is connected to the power supply voltage, and whose drain is connected to the gate of the clamping transistor.

[0025] The clamping transistor is a PMOS transistor, with its source connected to the power supply voltage, its drain connected to the connection node, and its gate controlled by the control circuit.

[0026] Furthermore, the power supply voltage of the inverter is the same as the power supply voltage of the control transistor and the clamping transistor;

[0027] The on-resistance of the transmission gate is less than that of the control transistor to ensure that the gate voltage of the clamping transistor can be quickly pulled down when the switching transistor is turned off.

[0028] A current-mode digital-to-analog converter (IDAC) includes multiple parallel current branches, each of which includes:

[0029] A current mirror tube, whose gate is used to receive the bias voltage, whose source is grounded, and whose drain is connected to a node.

[0030] The switching transistor has its gate used to receive one bit of the interpolation control code, its source connected to the node, and its drain as the current output terminal.

[0031] A clamping transistor, whose source is connected to the power supply voltage and whose drain is connected to the node;

[0032] The control circuit, connected to the gate of the clamping transistor, is used to control the conduction and cutoff of the clamping transistor according to the level change of the interpolation control code.

[0033] Furthermore, the control circuit includes:

[0034] The control transistor has its gate used to receive the inverted signal of the interpolation control code, its source connected to the power supply voltage, and its drain connected to the gate of the clamping transistor.

[0035] The transmission gate has its first end connected to the gate of the clamping transistor and its second end connected to the node. The first control terminal is used to receive the inverted signal of the interpolation control code, and the second control terminal is used to receive the interpolation control code.

[0036] Specifically, when the state of the switching transistor changes due to the switching of the interpolation control code, the clamping transistor is controlled by the control circuit to clamp the voltage of the connection node between the switching transistor and the current mirror transistor, so that the voltage of the connection node remains basically unchanged before and after the switching transistor state switch.

[0037] A clock data recovery (CDR) circuit includes:

[0038] A phase-locked loop (PLL) is used to generate multiphase clock signals;

[0039] The phase interval selection module is used to select two pairs of quadrature differential clock signals from multiphase clock signals;

[0040] The current-mode digital-to-analog converter (IDAC) as described in claim 8 or 9;

[0041] The phase interpolation module is connected to the current-mode digital-to-analog converter (IDAC) and is used to interpolate the two pairs of quadrature differential clock signals according to the drive current provided by the current-mode digital-to-analog converter (IDAC), and finally output a pair of quadrature recovery clock signals.

[0042] The sampling module is used to sample the input serial data signal using an orthogonal recovery clock signal;

[0043] The digital processing module is used to process the sampled signal and generate interpolation control codes to feed back to the current-mode digital-to-analog converter (IDAC).

[0044] This invention provides a method for reducing CDR recovery clock and data jitter, and a digital-to-analog converter thereof. Compared with the prior art, the advantages achieved by this method are:

[0045] 1. This invention adds a clamping transistor to a current-type IDAC, enabling the IDAC to provide a stable, overshoot-free drive current to the interpolation module. This allows the clock signal output by the interpolation module to smoothly transition without overshoot during phase switching, greatly reducing the jitter of the recovery clock. At the same time, because the received data is sampled and deserialized using the recovery clock, the jitter of the recovery data is also indirectly reduced.

[0046] 2. This invention optimizes the delay overshoot generated during the interpolation code transition in phase interpolation CDR, eliminates the charge injection problem caused by voltage changes at the IDAC current device in the interpolator, makes the IDAC current change in the interpolator smooth and without overshoot, effectively reduces the deterministic jitter of the data and clock recovered by the receiving system, increases the sampling window of the recovered clock for data, and improves the jitter tolerance of the receiver in the high-speed serial communication interface.

[0047] 3. This invention provides the required stable and non-overcharged drive current to the PI module in the CDR by using a current-type IDAC; and uses a clamping transistor to clamp the switching node to eliminate the charge injection problem caused by switching state switching; by adding a circuit to control the clamping transistor, it is turned off when the switching transistor is turned on, so as not to affect the normal drive current. Attached Figure Description

[0048] Figure 1 This is a structural diagram of the CDR system in this invention;

[0049] Figure 2 This is a schematic diagram of a current-mode IDAC in the prior art;

[0050] Figure 3 This is a schematic diagram of the current-mode IDAC in this invention;

[0051] Figure 4 For the present invention Figure 3 Enlarged view of region A in the middle;

[0052] Figure 5 This is a schematic diagram of the phase interpolation module in this invention;

[0053] Figure 6 To use a partial phase change diagram of a conventional IDAC;

[0054] Figure 7 This is a phase change diagram of the IDAC portion in implementation state 1 of this invention;

[0055] Figure 8 This is a phase change diagram of the IDAC portion in implementation state 2 of this invention;

[0056] Figure 9 This is a phase change diagram of the IDAC portion in implementation state 3 of this invention;

[0057] Figure 10 This is a phase change diagram of the IDAC portion in embodiment 4 of the present invention;

[0058] Figure 11 This is a phase change diagram of the IDAC portion in implementation state 5 of this invention;

[0059] Figure 12 Clock eye diagram recovered using a traditional IDAC;

[0060] Figure 13 This is the clock eye diagram for IDAC recovery in this invention. Detailed Implementation

[0061] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Example 1

[0062] like Figure 1 As shown, a method for reducing CDR recovery clock and data jitter involves generating multi-phase clock signals using a phase-locked loop (PLL); selecting two pairs of quadrature clock signals from the multi-phase clock signals using a phase interval selection module; and interpolating the two pairs of quadrature clock signals using a phase interpolation module to generate a new pair of quadrature sampling clock signals. The drive current of this phase interpolation module is provided by a current-mode digital-to-analog converter (IDAC). An example of the specific phases used to generate the new pair of quadrature sampling clock signals is as follows:

[0063] Two pairs of differential clocks were selected: (0°, 180°) and (45°, 225°), and (90°, 270°) and (135°, 315°). (Differential means one clock is positive and the other is negative, with a phase difference of 180°; orthogonal means the phase difference is 90°.) Simply put, interpolation is performed in the 0°~45° range, and the same interpolation operation is performed in the 90°~135° range. The new clocks after interpolation are (11.25°, 191.25°) and (101.25°, 281.25°). The system loop determines whether the new phase is suitable. If it is not suitable, the phase is adjusted until a suitable phase is found. The loop is then locked, and the clock at this point is the recovered high-speed clock. The recovered clock is still differential. Figure 1 The CKI and CKQ in the code are simplified clocks and do not represent differential. The detailed representation should be CKI and CKIB, CKQ and CKQB.

[0064] The sampling module samples the input serial data using an orthogonal recovery clock signal, outputting edge sampling signals and data sampling signals. The digital processing module processes the edge sampling signals and data sampling signals to generate interpolation control codes for controlling the current-type IDAC, thereby adjusting the phase of the orthogonal recovery clock signal. The current-type IDAC includes multiple parallel current branches, each of which includes a current mirror, a switching transistor, a clamping transistor, and a control circuit. When the state of the switching transistor changes due to the switching of the interpolation control code, the control circuit controls the clamping transistor to clamp the voltage at the connection node between the switching transistor and the current mirror, so that the voltage at the connection node remains basically unchanged before and after the switching transistor state switch.

[0065] The PLL module generates multi-phase clock signals (e.g., four-phase or eight-phase); the phase interval selection module (PS) selects two pairs of quadrature clocks from the multi-phase clocks; the phase interpolation module (PI) interpolates the selected clocks and outputs quadrature clocks CKI and CKQ; the sampling module (SAMP) uses CKI and CKQ to sample the input data DIN at the edges and center; the digital processing module (Digital) deserializes, determines phase deviation, and generates interpolation control codes; and the current-type IDAC module provides the PI module with a drive current corresponding to the code value based on the interpolation control code.

[0066] The corresponding drive current refers to the linear relationship between the output current value of the current-type IDAC and the value of the interpolation control code. The switching state of each branch is controlled by the thermometer code, and the total current equals the sum of the unit currents of the open branches. This mechanism ensures that the phase interpolation module can accurately adjust the clock phase according to the code value, thereby reducing jitter. The introduction of the clamping transistor further stabilizes the current output and avoids overshoot problems during switching.

[0067] like Figure 5 As shown, the phase interpolation module (PI) is typically composed of a current-mode logic (CML) buffer. Its inputs are two pairs of quadrature clocks: IP1 / IN1, IP3 / IN3, IP2 / IN2, and IP4 / IN4. Iin1–Iin4 represent the input drive currents. The outputs are a pair of interpolated quadrature clock signals (CK1, CKQ). The interpolation weights are controlled by the current (Iout1–Iout4) provided by the IDAC, and the current magnitude is determined by the interpolation control code, thus achieving fine-tuning of the phase.

[0068] In this design, an auxiliary circuit is added to the current-mode IDAC (the auxiliary circuit mainly consists of a clamping transistor, a control transistor, and a transmission gate. Its function is to clamp the current mirror node voltage to a potential close to that when the switching transistor is turned on when the switching transistor is off, thereby avoiding charge injection caused by drastic changes in node voltage during switching). This prevents phase overshoot during phase adjustment, increases the sampling window for data recovery clock, improves the jitter tolerance of the high-speed receiving system, and effectively reduces jitter in the system recovery clock and data. Figure 1 The specific structure and functions are described below:

[0069] The phase interpolation type CDR structure includes: a four-phase or eight-phase input clock (usually generated by a PLL), a phase range selection module (PS), a phase interpolation module (PI), a sampling module (SAMP), and a digital module (Digital).

[0070] 1. The PLL generates a four- or eight-phase clock with uniform phase difference through the local reference clock CKR, such as 0°, 90°, 180°, 270°, or 0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°, for the PS module in the CDR to select the phase interval;

[0071] 2. The PS module selects the input multiphase clocks, choosing two pairs of orthogonal clocks to form two orthogonal intervals, such as 0° and 45°, 90° and 135°, and sends them to the PI module;

[0072] 3. The PI module interpolates two pairs of quadrature clocks, that is, further subdivides the phase, and outputs a pair of quadrature clocks CKI and CKQ. Its accuracy depends on the number of bits in the interpolation control code. The more bits, the higher the accuracy and the smaller the jitter of the recovered clock, but at the same time, the system complexity is also higher. This invention will use a 4-bit interpolation control code as an example for the following description, but in practical applications, it is not limited to a 4-bit interpolation control code, and may also use 16 bits, 32 bits, or more.

[0073] 4. The IDAC module is the core innovation of this invention. It provides the PI module with complementary drive currents of different magnitudes (complementary because Iout1 and Iout2 are complementary, that is, Iout1 + Iout2 = a fixed value. If Iout1 increases by a certain amount, Iout2 decreases by the same amount. Similarly, Iout3 and Iout4 are complementary), thereby adjusting the phase of the PI output clocks CKI and CKQ.

[0074] 5. The SAMP module uses the quadrature clocks CKI and CKQ to perform edge sampling and center sampling on the equalized high-speed serial signal DIN, respectively. If it is half-speed sampling, it also performs parity separation to reduce the speed of the signal and outputs edge signal E[1:0] and data signal D[1:0].

[0075] 6. The Digital module further deserializes E[1:0] and D[1:0], and at the same time determines whether the sampling clock in the SAMP is ahead or behind DIN. It adjusts the phase of CKI and CKQ through control codes code1 and code2 so that CKI is finally aligned with the edge of DIN and CKQ is aligned with the center of DIN, so as to ensure the maximum sampling window and the minimum bit error rate. Its output signal DOUT is the recovered data, and CKOUT is the clock accompanying the recovered data.

[0076] The working principle of phase interpolation CDR is as follows:

[0077] Phase interpolation-type clock signals synthesize multiple clock signals with different phases through weighted summation and feedback adjustment, ultimately generating a clock signal whose phase is aligned with the input serial data center for correct sampling of the input data. Its core principle is to achieve fine-tuning of the output phase by controlling the weights (i.e., interpolation codes) of each phase clock.

[0078] The configuration of the scale in this embodiment is as follows:

[0079] like Figure 2 The diagram shows the existing IDAC. For a traditional current-type IDAC, NM1 and NM18 are used as examples. When CA[3] is logic 0, the switch NM18 is turned off, and the voltage of node A drops to 0V. When CA[3] is switched to logic 1, the switch NM18 is turned on. Since node A has a certain parasitic capacitance, and the voltage across the capacitor cannot produce a step transient, there will be a certain excess current charging node A. This will cause the output current Iout1 to be momentarily greater than the static stable value, which is current overshoot. In the PI module, this will be reflected in the phase overshoot of CKI and CKQ, and will eventually be reflected in the jitter of the CDR recovery clock data.

[0080] Therefore, based on the technical solution and proportional configuration of the above embodiments, data monitoring is performed. The basic configuration information is as follows: the phase is divided into 32 equal parts, the ideal phase step (LSB) is 360° ÷ 32 = 11.25°, and a 1.5625GHz clock frequency is used for simulation. Ideally, the LSB in the time domain is 20ps. Therefore:

[0081] Comparison State 1

[0082] like Figure 6 The figure shows the phase change of the CDR part using a traditional IDAC. It can be seen that there is a delay overshoot at the clock phase switching edge, which is equivalent to a phase overshoot in the frequency domain. In severe cases, the delay overshoot is 12ps, and the equivalent phase overshoot is about 6.25°, which exceeds 0.5LSB.

[0083] Implementation Status 1

[0084] like Figure 7 As shown, this is the phase change of the CDR section of the IDAC using the present invention, VDD=0.8V, clamping transistor size W / L=1.4u / 0.2u, clamping voltage VCL=377mV. It can be seen that the step change at the clock phase switching edge is clear and there is no overshoot.

[0085] Implementation Status 2

[0086] like Figure 8As shown, this is the phase change of the CDR section of the IDAC using the present invention, VDD=0.8V, clamping transistor size W / L=1.4u / 0.5u, clamping voltage VCL=325mV. It can be seen that the step change at the clock phase switching edge is clear and there is no overshoot.

[0087] Implementation Status 3

[0088] like Figure 9 As shown in Figure 3, the phase change of the CDR section of the IDAC using the present invention is shown. VDD=0.8V, clamping transistor size W / L=1.4u / 1u, clamping voltage VCL=268mV. It can be seen that the step change at the clock phase switching edge is clear and there is basically no overshoot.

[0089] Implementation Status 4

[0090] like Figure 10 As shown in Figure 4, the phase change of the CDR section of the IDAC using the present invention is shown. VDD=0.9V, clamping transistor size W / L=1.4u / 0.2u, clamping voltage VCL=475mV. It can be seen that the step change at the clock phase switching edge is clear and there is basically no overshoot.

[0091] Implementation Status 5

[0092] like Figure 11 As shown in Figure 5, the phase change of the CDR section of the IDAC using the present invention is as follows: VDD=0.7V, clamping transistor size W / L=1.4u / 0.2u, clamping voltage VCL=278mV. It can be seen that the step change at the clock phase switching edge is clear and there is basically no overshoot.

[0093] By comparing state 1 with implementation states 1-5 above, we can conclude that:

[0094] Depend on Figures 7-11 As can be seen, variations in the size (W / L) of clamping transistors PM1~PM16 affect the clamping voltage VCL, as do variations in the power supply voltage VDD. Other conditions, such as changes in process angle and small variations in the IDAC bias current Ibias, also influence the clamping voltage. Under all PVT combinations, the clamping voltage in the IDAC varies between approximately 240mV and 510mV. Within this range, the interpolator phase switching does not produce phase overshoot, demonstrating the good performance of the IDAC of this invention.

[0095] Furthermore, compared with the existing IDAC technology, the key difference is that the IDAC current mirror transistors NM1~NM16 of the present invention have current in all situations, which can eliminate the charge injection problem caused by node voltage changes as much as possible. In contrast, in the existing IDAC technology, the current in the current mirror transistors NM1~NM16 drops to 0 when the corresponding switch transistor is turned off during phase switching. As a result, at the moment the switch transistor is turned on, a current much larger than the ideal value will flow, causing delay overshoot, i.e. phase overshoot.

[0096] The relationship between delay overshoot and deterministic jitter is as follows: In a current-type IDAC, the charge injection effect caused by the sudden change in node voltage during switching will cause the output current to deviate from the ideal value instantaneously, which in turn causes a sudden change in the phase of the phase interpolator output clock (i.e., phase overshoot). This overshoot is deterministic and repeatable, and therefore belongs to deterministic jitter. Example 2

[0097] like Figure 3 , 4 As shown, a current-mode digital-to-analog converter (IDAC) is described in detail below, including its functions and implementation:

[0098] NM0~NM16 are current mirror transistors used to generate mirrored current. NM18~NM33 are switching transistors used to control the output of the corresponding branch current. NM17 is for matching with the switching transistors in other branches, and its gate is connected to the power supply. PM1~PM16 are clamping transistors. When the switching transistors NM18~NM33 are off, they clamp the A~P nodes. PM17~PM32 and transmission gates SW1~SW16 are used to control whether the clamping transistors are working. When the switching transistors in the branch are on, the clamping transistors are off, so as not to affect the normal output drive current.

[0099] The 16 branches in the IDAC have the same structure. The connection relationship and function implementation are described below using the first branch as an example: The gate of the current mirror transistor NM1 is connected to the current input terminal Ibias, the source and substrate are grounded, and the drain is connected to the source of NM18, i.e., point A; the gate of the switching transistor NM18 is connected to the interpolation control code CA[3], and the drain is connected to the current output terminal Iout1.

[0100] The source of clamping transistor PM1 is connected to the power supply (positive voltage of VDD power supply), the drain is connected to the second transmission terminal of transmission gate SW1, and is also connected to point A. The gate is connected to the drain of control transistor PM17 and the first transmission terminal of transmission gate SW1. The source of control transistor PM17 is connected to the power supply (positive voltage of VDD power supply), the gate is connected to the interpolation control code CB[3], and is also connected to the first control terminal of transmission gate SW1. The second control terminal of transmission gate SW1 is connected to the interpolation control code CA[3]. The interpolation control code CA[3] and CB[3] are logically opposite.

[0101] When CA[3] is logic 0 and CB[3] is logic 1, NM18 is off, SW1 is on, PM17 is off, and PM1 is working, clamping point A to a certain voltage value, for example, when the power supply is 0.8V, the voltage at point A is about 0.4V.

[0102] When CA[3] is switched to logic 1, CB[3] is logic 0, NM18 is turned on, SW1 is turned off, PM17 is turned on, and PM1 is turned off, the voltage at point A is still about 0.4V. This eliminates the charge sharing caused by the change in node voltage, so that the output current Iout1 will not overshoot during the interpolation control code switching process.

[0103] The working principle of the clamping transistor is as follows: When the switching transistor (such as NM18–NM33) is turned off, the clamping transistor (such as PM1–PM16) is activated by the control circuit (including transmission gates SW1–SW16 and control transistors PM17–PM32), clamping the voltage of the node (such as A–P) connected to its drain at a preset voltage value (such as 240mV–510mV). This voltage value should be as close as possible to the steady-state voltage of the node when the switching transistor is turned on, thereby minimizing the voltage change during switching, suppressing the charge injection effect caused by the charging and discharging of parasitic capacitance, and avoiding output current overshoot.

[0104] Explanation of charge sharing: Sharing means redistribution. In this invention, charge sharing specifically refers to charge injection. When the voltage at a node changes from a voltage value V1 to another voltage value V2, a certain amount of charge will be injected into this node. The relationship between the changing voltage, the parasitic capacitance of this node, and the amount of injected charge is ΔV=ΔQ / C. In addition, for MOSFETs, a certain amount of charge will also be injected during the process of the channel changing from no current to current. Both of these charges are unwanted and deviate from the ideal situation. Since charge is the integral of current and time, it is instantaneously reflected in the change of current, that is, there is an instantaneous current that exceeds the ideal current.

[0105] Explanation of deterministic jitter: Jitter is divided into two main categories: random jitter and deterministic jitter. Random jitter is caused by random noise sources, has no specific pattern or regularity, and has no boundary, such as thermal noise and 1 / f noise, and cannot be completely eliminated. Deterministic jitter, on the other hand, is caused by specific interference or design defects, has a fixed pattern and regularity, is bounded, and is repeatable, predictable, and eliminateable. The method in this invention eliminates this part of deterministic jitter caused by the original design defects by improving the original design defects. Example 3

[0106] like Figure 1As shown, a clock data recovery (CDR) circuit includes: a phase-locked loop (PLL) for generating multi-phase clock signals; a phase interval selection module for selecting two pairs of quadrature clock signals from the multi-phase clock signals; a current-mode digital-to-analog converter (IDAC) module connected to a phase interpolation module for providing the required drive current; and a phase interpolation module for interpolating the two pairs of quadrature clock signals with different weights according to the drive current provided by the IDAC, outputting a pair of quadrature recovered clock signals. Examples of outputting a pair of quadrature recovered clock signals include:

[0107] (0°, 180°) is considered a differential clock. (0°, 180°) and (90°, 270°) are considered a pair of orthogonal differential clocks. (0°, 180°) and (90°, 270°), (45°, 225°) and (135°, 315°) are considered two pairs of orthogonal differential clocks (differential means one is positive and the other is negative, with a phase difference of 180°, orthogonal means a phase difference of 90°). Simply put, interpolation is performed in the 0°~45° range, and the same interpolation operation is performed in the 90°~135° range. The new clocks after one step of interpolation are (11.25°, 191.25°) and (101.25°, 281.25°), which is a pair of orthogonal clocks.

[0108] The sampling module is used to sample the input data signal using the quadrature recovery clock signal; the digital processing module is used to process the sampled signal and generate interpolation control codes to be fed back to the IDAC.

[0109] Specifically, the phase interpolation module is as follows: Figure 5 As shown, its phase interpolator structure consists of a common CML-type buffer, where Iin and Iin2 are complementary, Iin3 and Iin4 are complementary, and Iin1, Iin2, Iin3, and Iin4 are respectively complementary to... Figure 3 The Iout1, Iout2, Iout3, and Iout4 are connected.

[0110] The technical solutions of the above embodiments and the configurations of the comparative examples are compared using clock eye diagrams:

[0111] like Figure 12 As shown, the clock eye diagram is recovered using a CDR with a traditional IDAC, and the peak-to-peak jitter is approximately 45 ps.

[0112] like Figure 13 As shown, the peak-to-peak jitter of the CDR recovery clock eye diagram using the IDAC of this invention is approximately 22 ps, which is only half that of the conventional type. Under different combinations of process, voltage, and temperature (PVT), the eye diagram performance of the recovery clock of this invention is similar, and the jitter performance is good when there is no phase overshoot.

[0113] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method of reducing clock and data jitter during CDR recovery, characterized by, Includes the following steps: S1. Generate a multi-phase clock signal through a phase-locked loop (PLL); S2. Select two pairs of orthogonal differential clock signals from the multiphase clock signals through the phase interval selection module as the interpolation interval; S3. The two pairs of quadrature clock signals are interpolated by the phase interpolation module to generate a new pair of quadrature sampling clock signals, and the drive current of the phase interpolation module is provided by the current-mode digital-to-analog converter IDAC. The current-mode digital-to-analog converter (IDAC) includes multiple parallel current branches, each of which is equipped with a control circuit for controlling the on and off of the clamping transistor during interpolation control code switching. S4. The sampling module uses an orthogonal sampling clock signal to sample the input serial data and outputs an edge sampling signal and a data sampling signal. S5. The edge sampling signal and data sampling signal are processed by the digital processing module to generate interpolation control code for controlling the current-mode digital-to-analog converter (IDAC) to adjust the phase of the quadrature sampling clock signal. S6. When the phase of the quadrature sampling clock signal is adjusted to lock by the digital processing module, the sampling clock signal is the CDR recovery clock, and the sampled and deserialized data is the CDR recovery data. The control circuit includes a transmission gate and a control transistor; The first control terminal of the transmission gate receives the interpolation control code, and the second control terminal of the transmission gate receives the inverted signal of the interpolation control code. The gate of the control transistor receives the inverted signal of the interpolation control code, the source of the control transistor is connected to the power supply voltage, and the drain of the control transistor is connected to the gate of the clamping transistor. The transmission gate is used to turn on when the switching transistor is off, pull down the gate voltage of the clamping transistor to turn it on, and turn off when the switching transistor is on. The control circuit further includes an inverter for generating an inverted signal of the interpolation control code and providing it to the second control terminal of the transmission gate and the gate of the control transistor. The transmission gate is composed of a PMOS transistor and an NMOS transistor connected in parallel. Its first control terminal receives the interpolation control code, and its second control terminal receives the inverted signal. The control transistor is a PMOS transistor, whose gate receives an inverted signal, whose source is connected to the power supply voltage, and whose drain is connected to the gate of the clamping transistor. The clamping transistor is a PMOS transistor, with its source connected to the power supply voltage, its drain connected to the connection node, and its gate controlled by the control circuit.

2. The method of claim 1, wherein: The multiphase clock signal is a four-phase clock signal or an eight-phase clock signal; the interpolation control code is a thermometer code.

3. The method of claim 1, wherein: Step S3 specifically includes: When the interpolation control code is at the first level, the switch is turned off, and the control circuit turns on the clamping transistor to clamp the voltage of the connected node to a preset voltage value. When the interpolation control code switches to the second level, the switching transistor is turned on, and the control circuit turns off the clamping transistor.

4. The method of claim 3, wherein: The preset voltage value is between 240mV and 510mV.

5. The method of claim 1, wherein: The power supply voltage of the inverter is the same as the power supply voltage of the control transistor and the clamping transistor. The on-resistance of the transmission gate is less than that of the control transistor to ensure that the gate voltage of the clamping transistor can be quickly pulled down when the switching transistor is turned off.

6. A current-mode digital-to-analog converter (IDAC) for implementing the method of reducing CDR recovery clock and data jitter as described in any one of claims 1-5, characterized in that, It includes multiple current branches connected in parallel, each of the current branches including: A current mirror tube, whose gate is used to receive the bias voltage, whose source is grounded, and whose drain is connected to a node. The switching transistor has its gate used to receive one bit of the interpolation control code, its source connected to the node, and its drain as the current output terminal. A clamping transistor, whose source is connected to the power supply voltage and whose drain is connected to the node; The control circuit, connected to the gate of the clamping transistor, is used to control the conduction and cutoff of the clamping transistor according to the level change of the interpolation control code.

7. The current-mode digital-to-analog converter (IDAC) of claim 6, wherein: The control circuit includes: The control transistor has its gate used to receive the inverted signal of the interpolation control code, its source connected to the power supply voltage, and its drain connected to the gate of the clamping transistor. The transmission gate has its first end connected to the gate of the clamping transistor and its second end connected to the node. The first control terminal is used to receive the inverted signal of the interpolation control code, and the second control terminal is used to receive the interpolation control code. Specifically, when the state of the switching transistor changes due to the switching of the interpolation control code, the clamping transistor is controlled by the control circuit to clamp the voltage of the connection node between the switching transistor and the current mirror transistor, so that the voltage of the connection node remains unchanged before and after the switching transistor state switch.

8. A clock data recovery (CDR) circuit, comprising: include: A phase-locked loop (PLL) is used to generate multiphase clock signals; The phase interval selection module is used to select two pairs of quadrature differential clock signals from multiphase clock signals; The current-mode digital-to-analog converter (IDAC) as described in claim 6 or 7; The phase interpolation module is connected to the current-mode digital-to-analog converter (IDAC) and is used to interpolate the two pairs of quadrature differential clock signals according to the drive current provided by the current-mode digital-to-analog converter (IDAC), and finally output a pair of quadrature recovery clock signals. The sampling module is used to sample the input serial data signal using an orthogonal recovery clock signal; The digital processing module is used to process the sampled signal and generate interpolation control codes to feed back to the current-mode digital-to-analog converter (IDAC).

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