Method for calibrating phase modulation converter and phase modulation converter

Abstract

The invention relates to a method for calibrating a phase modulation converter and a phase modulation converter, the phase modulation converter (1) comprising: an amplitude modulator (2) with carrier suppression; an adder (7); a limiter (11); and a demodulation device (16) which receives the signal (SigBA) output by the limiter (11) and in which demodulation can be carried out, in which a comparison of the signal (SigBA) output by the limiter with a reference signal (SigRF) can be achieved in the range of demodulation; a calibration switch (S) connected upstream of the adder (7), which calibration switch can be actuated between a control setting, in which the adder (7) is connected via the calibration switch (S) to the input of the phase modulation converter (1), and at least one calibration setting, in which the connection is interrupted.

Description

TECHNICAL FIELD

[0001] The present invention relates to a method for calibrating a phase modulation converter and to a phase modulation converter. BACKGROUND

[0002] Analog-digital converters are used to convert an analog input quantity into a digital signal. Conventional analog-digital converters are, for example, SAR converters (successive approximation converter) and sigma-delta converters. Both types of converters have the disadvantage that they are subject to a DC error of the analog input signal.

[0003] EP 3 624 334 A1 discloses an improved device for converting an analog input signal into a digital output signal. In particular, the device is an analog-digital converter (ADC converter) which is based on the difference between the phase of a signal modulated on the input voltage to be measured and a reference signal. The analog-digital converter known from EP 3 624 334 A1 can also be referred to as a phase modulation converter.

[0004] The phase modulation converter according to EP 3 624 334 A1 comprises an amplitude modulator with carrier suppression for providing a carrier-free amplitude modulation signal. The amplitude modulator has a signal input which can be fed with an analog input signal to be converted. In addition, there is an adder for receiving the carrier-free amplitude modulation signal output by the amplitude modulator and configured to add a carrier signal shifted in phase by 90° thereto, thereby providing a phase modulation signal. In addition, there is a limiter which receives the phase modulation signal output by the adder and is configured to suppress an interference-induced amplitude modulation in the phase modulation signal.

[0005] The output signal of the limiter has an amplitude which is either 0 or 1. It can also be referred to as a digital signal in terms of amplitude. The length of the pulses is continuous in value depending on the carrier frequency selected. The information is contained in the length of the square-wave pulses. The output signal of the limiter carries the modulation by the zero crossings in time from the 90° carrier signal. Reference is also made here to the figures of EP 3 624 334 A1, in particular to the Figure 5 This principle is explained in more detail with reference to Figure 8 and the associated description.

[0006] The signal output by the limiter, also referred to simply as the amplitude-limited signal in this case, can then be sampled, and the sampling speed should be fast enough to capture the zero crossings (sampling theorem).

[0007] It has proven to be effective for analog-digital converters, in particular before they are put into use, to be calibrated. For example, to compensate for differences in the delay of a printed circuit board. Here, the abbreviation PCB stands for Printed Circuit Board, i.e. printed circuit board.

[0008] In conventional analog-digital converters as described above, the offset calibration is usually carried out at the factory. At this time, for example, the input voltage is set to 0 V and the corresponding digital value is stored for subsequent calculation of the correction. The applicant is also aware that the calibration can also be carried out during operation. For this purpose, the wiring has to be temporarily changed on the user device or corresponding switching elements have to be provided in the analog circuit. This can be technically realized in a conventional manner, for example, by means of relays SSR or transistors controlled by the logic system already present on the potential-isolated side. However, such a calibration must always have no effect on the connected sensor, which is the source of the signal to be converted. A short circuit of the measuring electronics to the active sensor should be avoided. This would lead to a further increase in the complexity of the circuit.

[0009] The applicant is also aware that with conventional analog-digital converters a bidirectional analog input (+ / - 10 V, + / - 20 mA) can be realized. However, compared to a unidirectional input, significantly higher circuit complexity is required here, since the first-stage amplifiers for signal processing must be able to measure negative input voltages. Therefore, it is usually necessary to provide these amplifier stages with positive and negative supply voltages. This involves, for example, additional windings in the transformer, switching regulators, additional linear voltage regulators and additional passive elements for filtering. According to the applicant's knowledge, as an alternative to establishing a negative supply voltage, there is also a solution in which the input voltage is placed at half the reference voltage. Subsequently, this signal is input to a conventional ADC in the form of a fully or pseudo-differential signal. In this solution, additional high-precision resistors are required in the operational amplifier circuit. In addition, due to the mismatch of the resistors, a negative effect on the common-mode rejection capability of the operational amplifier occurs.

[0010] However, these problems are not relevant in the principle of a phase-modulation converter, since here the input voltage is converted into a corresponding modulation voltage. However, it has been found that, especially due to transmission delays on the printed circuit board, i.e. PCB, on which the phase-modulation converter or its components, including the analog filter stage, are implemented, it is sometimes not possible to define a zero point very precisely. SUMMARY

[0011] It is an object of the present application to provide a method by which a phase-modulation converter can be calibrated. Furthermore, it is another object of the present application to provide a phase-modulation converter with which the method can be implemented.

[0012] The above primary object is achieved by a method for calibrating a phase-modulation converter, wherein the phase-modulation converter comprises:

[0013] an amplitude modulator with carrier suppression, to which an input signal to be converted can be fed at the input of the amplitude modulator in order to obtain a carrier-free amplitude modulation signal,

[0014] An adder is used to add a phase-shifted, preferably sinusoidal, adder carrier signal to a carrier-free amplitude-modulated signal, and obtain a phase-modulated signal.

[0015] A limiter is used to feed a phase-modulated signal, and the limiter can suppress amplitude modulation caused by interference in the phase-modulated signal.

[0016] The demodulation device allows the signal output from the limiter to be fed into and demodulated within the demodulation device. Within the demodulation range, the signal output from the limiter can be compared with a reference signal, and an adder carrier signal can be generated within the demodulation device.

[0017] A calibration switch is connected upstream of the adder, particularly arranged between the amplitude modulator and the adder, and the calibration switch is actuated between a control setting and at least one calibration setting, in which the adder is connected to the input of the phase modulator-converter via the calibration switch, and in the calibration setting the connection between the adder and the input of the phase modulator-converter is disconnected and preferably another connection is established, particularly the connection between the adder and ground.

[0018] The method includes, in step S1, in the calibration settings of the calibration switch, especially when connected to a ground wire or ground, preferably dynamically changing the phase of the reference signal, and finding the phase of the reference signal that causes the output signal of the demodulation device to adopt a calibration value, which represents the maximum value that can be achieved at the phase shift or the calibration value differing from the maximum value that can be achieved at the phase shift by no more than a predetermined maximum deviation.

[0019] The second objective is achieved by a phase modulation converter, which includes:

[0020] An amplitude modulator with carrier rejection allows the input signal to be converted to be fed into the input of the amplitude modulator to obtain a carrier-free amplitude modulated signal.

[0021] An adder is used to add a phase-shifted, preferably sinusoidal, adder carrier signal to a carrier-free amplitude-modulated signal, and obtain a phase-modulated signal.

[0022] A limiter is used to feed a phase-modulated signal, and the limiter can suppress amplitude modulation caused by interference in the phase-modulated signal; and

[0023] A demodulation device is provided, wherein the signal output from the limiter can be fed into and demodulated within the demodulation device, wherein the signal output from the limiter can be compared with a reference signal within the demodulation range, and wherein an adder carrier signal can be generated within the demodulation device; and

[0024] A calibration switch is connected upstream of the adder, particularly arranged between the amplitude modulator and the adder, and the calibration switch is actuated between a control setting and at least one calibration setting, in which the adder is connected to the input of the phase modulator-converter via the calibration switch, and in the calibration setting the connection between the adder and the input of the phase modulator-converter is disconnected and preferably another connection is established, particularly the connection between the adder and ground.

[0025] The phase modulator-converter is designed and / or configured to preferably dynamically change the phase of the reference signal for calibration, and to find a phase of the reference signal that causes the output signal of the demodulation device to adopt a calibration value, which represents the maximum value that can be achieved at the phase shift or the calibration value differing from the maximum value that can be achieved at the phase shift by no more than a predetermined maximum deviation.

[0026] In other words, the present invention also relates to a phase modulation converter constructed and / or configured for performing the method of the present invention. The phase modulation converter according to the present invention is particularly constructed and / or configured for performing step S1 of the method.

[0027] In other words, this invention proposes a bias calibration method for phase modulators, particularly dynamic ones. It is noted that in a phase modulator, calibration can be achieved by selectively and actively adjusting the phase of the reference signal used for demodulation. Therefore, a signal generated for the operation of the phase modulator and readily available on its own can be utilized. Through the method of this invention, reliable calibration of an analog-to-digital converter (ADC) acting as a phase modulator can be achieved at a reasonable cost, thereby compensating for errors including manufacturing and component tolerances.

[0028] The phase modulation converter of the present invention can implement this method and is characterized by its relatively simple structure.

[0029] The phase of the reference signal is dynamically changed, particularly through multiple, repeated changes. This change is preferably continuous until a desired value is reached. Preferably, it is made to reach or approach its maximum value. For example, it is possible to first make a change in one direction and observe or determine whether the demodulator's output value increases. If so, the change can continue in that direction; otherwise, it is changed to another direction. This can be implemented, for example, through at least one logic system.

[0030] If the deviation between the calibrated value and the maximum value achievable under that phase shift is at most a predetermined maximum deviation, then preferably, the maximum deviation is 3% of the maximum value achievable under that phase shift, particularly 2%, and more preferably 1%.

[0031] The calibration switch, designed for this purpose, allows the voltage on the demodulator side, particularly the logic system side, to be shorted. This enables the input voltage to be zeroed in the adder for subsequent calibration.

[0032] To set the input voltage to 0V, it is particularly suitable to use SSRs (Solid State Relays) or simple MEMS switches, thereby still taking advantage of the purely passive circuitry that can be implemented on the processing side by the phase modulator-converter. The calibration switch can be specifically constructed as a changeover switch. The calibration switch can comprise at least one mechanical relay and / or at least one solid state relay and / or at least one reed relay and / or at least one MEMS switch, or the calibration switch can be composed of at least one mechanical relay and / or at least one solid state relay and / or at least one reed relay and / or at least one MEMS switch. MEMS is an abbreviation herein for "Micro-Electro-Mechanical Systems" in a known manner.

[0033] The calibration switch is connected before the adder. In the input direction of the phase modulator-converter, the calibration switch is located before the adder. In principle, the calibration switch can be placed anywhere in the phase modulator-converter signal path before the adder. In other words, it is located between the input of the phase modulator-converter and the adder. It can be the last component before the adder, but it is not required to be. One or more other components, such as at least one filter and / or at least one current isolation device, can also be placed between the adder and the calibration switch.

[0034] The calibration switch can be positioned before or after the amplitude modulator; in other words, it can be located between the input of the phase modulator-converter and the amplitude modulator, or between the amplitude modulator and the adder. This second variant has proven to have particularly significant advantages.

[0035] The calibration switch is configured to interrupt the signal path, which can be a differential signal path, and establish an alternative connection. In the control setup, the calibration switch connects the adder to the input of the phase modulator-converter, and this connection can be implemented or provided by other components if necessary.

[0036] Preferably, the calibration switch is disconnected in the calibration setting; in other words, the connection to at least one input of the adder is interrupted. This input is connected in the control setting to at least one output of the amplitude modulator—either directly or via one or more other components. In the calibration setting, the calibration switch specifically connects at least one input on the adder signal path to ground or ground. Of course, this connection can also be achieved via other components, such as connecting at least one input of the adder to ground / ground via the amplitude modulator and / or at least one filter and / or at least one electrical isolation device.

[0037] If the adder is used for differential signal transmission and has two inputs, then typically, during calibration settings, the calibration switch connects each input for differential signal transmission (rather than to the input of the phase modulator-converter or amplitude modulator) to ground. More preferably, in differential signal transmission, under the control of the calibration switch, the two signal inputs of the adder are each connected to one of the two differential outputs of the amplitude modulator, either directly or via one or more other components.

[0038] The calibration of the phase modulator-converter can be achieved completely without feedback for an external signal as a new zero phase. This feature can be advantageously utilized when the external analog signal only needs to monitor large changes or thresholds.

[0039] Furthermore, the characteristic of phase modulator-demodulators (PDAs) that map the input voltage to the output voltage using an arctan function can be more fully utilized. Near zero, a small change in phase difference results in a larger signal amplitude than the same change at the edges of the input voltage range. This means that the signal-to-noise ratio remains constant for all input voltages under a first-order approximation, which is not the case in traditional analog-to-digital converters (ADCs).

[0040] The calibration of the phase modulator / converter of the present invention can be performed by the user, for example, before initial use, at least once at the factory. Alternatively, or additionally, the calibration of the present invention can also be performed at least once after initial use, for example when the phase modulator / converter is installed in the field of an industrial installation or machine and used for the conversion of sensor signals.

[0041] It has proven particularly advantageous when the phase modulator-converter has at least one electrical isolation device, which is preferably connected before the calibration switch. Here, "before" means it is located before the calibration switch in the input direction of the phase modulator-converter. In particular, it is possible to place at least one electrical isolation device between the amplitude modulator and the adder. The electrical isolation device preferably includes at least one pair of coupling capacitors. Especially in the case of differential signal transmission, one coupling capacitor is provided for each differential signal path.

[0042] Due to its structure, it is particularly easy, especially without the need for potential isolation switching elements, to directly short-circuit the amplitude modulation voltage from the amplitude modulator, especially the switching modulator, on the logic system side via the coupling capacitor.

[0043] Preferably, differential signal transmission is performed, particularly from the amplitude modulator output and / or to the limiter output or demodulation input. The phase modulator-converter of the present invention is accordingly designed in further improvements. It can also be stated that differential signal transmission is established at least from the amplitude modulator output, particularly at least to the limiter output or to the demodulation device.

[0044] An adder can include, or be implemented by, at least one operational amplifier. In particular, it can be at least one fully differential operational amplifier.

[0045] Preferably, the demodulation device calculates the area overlap between the clipped signal and the reference signal, particularly over multiple cycles. The demodulation device can be designed and / or configured accordingly.

[0046] For the output signal of the demodulation device, especially when the calibration switch is in the calibration setting, observe its behavior under the phase change of the reference signal, especially referring to one or more digital values ​​output by the phase modulator-converter.

[0047] The phase modulator-demodulator and its demodulation device preferably include at least one FPGA (Field Programmable Gate Array) and / or at least one ASIC (Application-Specific Integrated Circuit). Therefore, it is particularly possible to dynamically adjust the phase of the reference signal within the FPGA or FPGA evaluation unit or the ASIC or ASIC evaluation unit.

[0048] The phase modulator-converter of the present invention can have at least one logic system designed and / or configured to, preferably dynamically change the phase of a reference signal, and find a phase in which the output signal of the demodulation device adopts a calibration value, which represents the maximum value achievable at the phase shift or the calibration value differing from the maximum value achievable at the phase shift by no more than a predetermined maximum deviation. This logic system, also referred to herein as a reference logic system, can be a component of the demodulation device, for example, preset or implemented on the FPGA of the device.

[0049] The operation of the calibration switch to the desired position can also be achieved through at least one logic system.

[0050] Furthermore, it has proven advantageous that the reference signal is generated from the output signal, particularly from the output signal of a voltage-controlled oscillator that is part of a phase-locked loop, and that the dynamic change of the reference signal is achieved by dynamically changing the phase of the reference signal, particularly in steps of less than 40°, preferably less than 20°, and most preferably less than 10°, i.e. by dynamically changing the phase of the feedback signal of the oscillator, which is taken at the output of the oscillator and preferably fed back to the oscillator at the input.

[0051] It can be assumed that the oscillator has at least one phase-variable tap and preferably at least one phase-locked tap, wherein the at least one phase-variable tap is capable of dividing the 360° phase of the oscillator into n steps, where n is a natural number greater than or equal to 30, especially greater than or equal to 40, preferably greater than or equal to 50, and particularly preferably greater than or equal to 100. It can further be assumed that a reference signal is obtained from the at least one phase-variable tap. The phase-variable tap can then output the reference signal, or the reference signal can be extracted from the tap. The phase of the reference signal can be adjusted by correspondingly driving or setting the phase-variable tap, especially dynamically, in steps of 360° / n, until the desired value is achieved.

[0052] It can also connect the phase energy variable tap to the feedback path of the oscillator, so that the signal from the phase energy variable tap is used as a feedback signal, especially at the input end, and the phase of the signal changes dynamically in steps of 360° / n.

[0053] It can also be stated that the phase-variable tap can be used in the feedback path of the oscillator or directly in the "forward branch" to achieve phase change of the reference signal.

[0054] The phase modulation converter according to the invention, and particularly its demodulation device, can have a reference signal generation module for generating a reference signal, which has proven to be a suitable structural implementation. The reference signal generation module can include, in particular, a voltage-controlled oscillator, which is part of a phase-locked loop, and the reference signal can be generated from the output signal of the oscillator of the reference signal generation module. The oscillator can have at least one phase-variable tap and at least one phase-locked tap, wherein the at least one phase-variable tap can divide the 360° phase of the oscillator into n steps. The at least one phase-variable tap can be configured accordingly.

[0055] The reference signal can be obtained directly from the phase energy change tap.

[0056] The phase-capable tap can also be connected to the feedback path of the oscillator, so that the signal from the phase-capable tap can be used as a feedback signal, especially fed back to the oscillator at the input. The phase modulation converter, for example, its reference logic system is particularly constructed and / or configured to preferably dynamically change the phase of the phase-capable tap signal from the oscillator of the reference signal generation module in steps of 360° / n.

[0057] In other words, phase change can be achieved by employing an oscillator with variable phase taps, which can subdivide the phase into tiny steps. In this context, FPGA devices from Xilinx or AMD are mentioned by way of example, which have implementations equipped with a mixed-mode clock management module (i.e., an MMCM module) that enables fine phase subdivision at the variable phase taps. This function is also referred to as "finePS," an abbreviation for "finephaseShift." This option can be used in this invention to achieve dynamic, incremental phase changes, particularly until a maximum value is found. Specifically, this is achieved by utilizing the variable phase taps as feedback signals to the oscillator. The applicant is aware of FPGA device models from, for example, Xilinx or AMD, that can subdivide the phase ("finePS") into 56 steps at the corresponding variable phase taps; in other words, subdivision in steps of 360° / n, n = 56, which has proven suitable within the scope of this invention. However, it should be emphasized that even finer or coarser subdivisions can, of course, be achieved and utilized. To give another example, Lattice Semiconductor's FPGA devices, especially the EPS, ECP5, and EPC5-5G series, can also achieve fine phase subdivision, up to 300 steps.

[0058] According to another particularly preferred embodiment of the invention, it is also proposed that: in order to achieve carrier suppression, a carrier signal generated by the demodulation device, i.e., a modulator carrier signal, is provided to the amplitude modulator, especially at another input terminal of the amplitude modulator, which may also be referred to as the carrier input terminal; and in step S2, when the calibration switch is set to calibration, especially when connected to ground or ground, the phase of the modulator carrier signal and / or the adder carrier signal is preferably dynamically changed, and in this process, the phase of the modulator carrier signal and / or the adder carrier signal that causes the output signal of the demodulation device to adopt a calibration value is found, which represents the maximum value that can be achieved at the phase shift (i.e., the phase shift of the modulator carrier signal and / or the adder carrier signal) or the calibration value differs from the maximum value that can be achieved at the phase shift by no more than a predetermined maximum deviation.

[0059] If the value calibrated to is no more than a predetermined maximum deviation from the maximum value achievable at that phase shift, then preferably the maximum deviation is 3% of the maximum value achievable at that phase shift, particularly 2%, and more preferably 1%.

[0060] In other words, in step S2, in addition to the pure calibration by moving the reference signal, an additional calibration can be performed to ensure the positional relationship between the adder carrier signal and the modulator carrier signal. Ideally, there is a 90° phase shift between the two carrier signals. For example, the adder carrier signal can be a sine wave, and the modulator carrier signal can be a cosine wave with a 90° phase shift. In step S2, the phase shift between the modulator carrier signal and the adder carrier signal is actively adjusted, preferably until a maximum value is obtained under such changes. The maximum value is obtained when the modulator carrier signal and the adder carrier signal are 90° out of phase. A deviation of 90° will result in different phase shifts in different directions, which may lead to inaccurate results or errors. Calibration by adjusting the phase of the modulator carrier signal and the adder carrier signal can also compensate for factors such as manufacturing and component tolerances.

[0061] Step S2 is preferably performed under the reference signal phase previously found in step S1.

[0062] It should be noted that in step S2, by shifting the phase of the modulator carrier signal and / or the adder carrier signal, it is usually possible to find a value higher than the maximum value in step S1, but this is not always the case. For example, if there is already an exact 90° phase shift between the modulator carrier signal and / or the adder carrier signal at the starting point of step S2 (accidentally), this value will not increase further.

[0063] Furthermore, it is understandable that in order to obtain the desired phase of the modulator carrier signal and the adder carrier signal, it is only necessary to change the phase of the modulator carrier signal or the phase of the adder carrier signal and observe the resulting output signal, especially in order to obtain the maximum value or a value that is close enough to the maximum value.

[0064] The phase modulation converter according to the invention is designed and / or configured in an advantageously improved manner for performing step S2.

[0065] In the phase modulator according to the invention, the amplitude modulator can be correspondingly connected to the demodulation device, and a carrier signal generated by the demodulation device can be provided to the amplitude modulator for carrier suppression, i.e., the modulator carrier signal, particularly at another input terminal (carrier input) of the amplitude modulator; and the phase modulator-converter has a logic system designed and / or configured to preferably dynamically change the phase of the modulator carrier signal and / or the adder carrier signal, and find a phase of the modulator carrier signal and / or the adder carrier signal such that the output signal of the demodulation device adopts a calibration value, which represents the maximum value achievable at the phase shift or the calibration value differing from the maximum value achievable at the phase shift by no more than a predetermined maximum deviation. The difference lies in the adder logic system. The adder logic system is preferably an integral part of the demodulation device.

[0066] The modulator carrier signal and / or adder carrier signal can also be generated by an output signal, particularly by the output signal of a voltage-controlled oscillator that is part of a phase-locked loop.

[0067] The dynamic change of the phase of the modulator carrier signal and / or the adder carrier signal can be achieved, for example, by dynamically changing the phase of the oscillator feedback signal, which is taken at the oscillator output and preferably fed back to the oscillator at the input, particularly by dynamically changing the phase in steps of less than 40°, more preferably in steps of less than 20°, and most preferably in steps of less than 10°.

[0068] Preferably, one oscillator is used to generate the reference signal; and at least another oscillator is used to generate the modulator carrier signal and / or the adder carrier signal. In principle, the at least two oscillators used for the reference signal and for the modulator carrier signal and / or the adder carrier signal can be identical in structure. It has been found that it is particularly suitable to use the same oscillator for generating both the modulator carrier signal and the adder carrier signal.

[0069] The oscillator for the modulator carrier signal and / or adder carrier signal can also have at least one phase-variable tap and optionally at least one phase-locked tap, wherein the at least one phase-variable tap can divide the 360° phase of the oscillator into n steps, where n is a natural number greater than or equal to 30, especially greater than or equal to 40, preferably greater than or equal to 50, and particularly preferably a natural number greater than or equal to 100.

[0070] Furthermore, it is also applicable that the modulator carrier signal and / or adder carrier signal are obtained from at least one phase-variable tap. The phase-variable tap can output the modulator carrier signal and / or adder carrier signal, or can be obtained from the modulator carrier signal and / or adder carrier signal. The phase of the reference signal can be changed by correspondingly driving or setting the phase-variable tap, especially dynamically in steps of 360° / n, until the desired value is achieved.

[0071] Similarly, when the modulator carrier signal and / or adder carrier signal are obtained, the phase-variable tap can be connected to the feedback path of the oscillator, so that the signal from the phase-variable tap is used as a feedback signal, especially fed back to the oscillator at the input, and the phase of the signal from the phase-variable tap changes dynamically in steps of 360° / n. The at least one phase-variable tap can be configured accordingly.

[0072] The phase modulation converter according to the invention, and especially its demodulation device, can further include a carrier signal generation module for generating a modulator carrier signal and / or an adder carrier signal. The carrier signal generation module can include, in particular, a voltage-controlled oscillator, which is part of a phase-locked loop, wherein the modulator carrier signal and / or adder carrier signal can be generated from the output signal of the oscillator.

[0073] Similarly, the oscillator has at least one phase-variable tap, and preferably at least one phase-locked tap, wherein the at least one phase-variable tap is capable of dividing the 360° phase of the oscillator into n steps, where n is a natural number greater than or equal to 30, especially greater than or equal to 40, preferably greater than or equal to 50, and particularly preferably a natural number greater than or equal to 100.

[0074] The modulator carrier signal and / or adder carrier signal can be obtained, for example, directly from the phase energy change tap. The carrier signal generation module is designed and / or configured accordingly.

[0075] Alternatively, the phase energy variable tap can be connected to the feedback path of the oscillator, so that the signal from the phase energy variable tap, especially at the input, can be fed back to the oscillator as a feedback signal.

[0076] Phase modulation converters, such as their adder logic, can be designed and / or configured in both of the above cases to dynamically change the phase of the phase-variable tap signal from the oscillator of the carrier signal generation module, preferably in steps of 360° / n. The at least one phase-variable tap can be configured accordingly.

[0077] In a particularly preferred improvement of the method of the present invention, in step S3, under the control setting of the calibration switch, the phase of the reference signal is again preferably changed dynamically, and in the change, a phase of the reference signal is found that causes the output signal of the demodulation device to adopt a calibration value, which is zero or differs from zero by no more than a predetermined maximum deviation or is equal to half of the maximum value that can be reached at the phase shift or differs from half of the maximum value that can be reached at the phase shift by no more than a predetermined maximum deviation.

[0078] The phase modulation converter according to the present invention is constructed and / or configured in a preferred improved manner for performing step S3.

[0079] Step S3 is preferably performed under the phase of the modulator carrier signal and / or adder carrier signal previously determined in step S2.

[0080] With lower circuit complexity, bidirectional industrial analog input channels can also be implemented. When potential isolation between the analog channel and the evaluation logic system is required, the phase modulation converter according to the present invention allows for simple calibration even during operation, making the solution easier to implement than ever before.

[0081] Particularly preferred is that, in step S3, when the calibration switch is in the control setting, an input voltage of 0V is applied to the phase modulation converter. In other words, step S3 is performed specifically when a 0V input voltage is applied to the phase modulation converter. This step enables calibration to 0V, depending on the measurement range.

[0082] Optionally, a "direction test" can also be performed in step S4.

[0083] Specifically, it can be proposed that in step S4, when the calibration switch is in the control setting, a non-zero input voltage is applied to the phase modulator-converter, and it is detected whether the output signal of the demodulator adopts the value of the output signal when the input voltage is greater than zero and when the input voltage is less than zero. If not, the phase shift of the reference signal by 180° is preferable. It is also preferable to dynamically change the phase of the reference signal only in one direction until the initial value of the demodulator output signal is obtained again. Preferably, the change of the reference signal phase is performed when the phase modulator-converter applies a 0V input voltage. This change until the output value is obtained again is particularly suitable for situations where a sufficiently precise 180° phase difference setting cannot be achieved.

[0084] In a phase modulator-demodulator, for a given input voltage, there may be two phase angles that result in the same digital value. The reference signal used for comparison can be positioned before or after the limiting signal supplied to the demodulator. Depending on the order of the reference signal and the limiting signal, the digital value will exhibit different behavior as the input voltage increases or decreases accordingly. The order of the reference signal and the limiting signal defines the sign of the digital value gradient. By calibration according to step S4, a gradient with the correct sign can be achieved.

[0085] The phase modulation converter according to the invention is advantageously modified and / or configured to perform step S4.

[0086] It has proven particularly advantageous that, in the method according to the invention, steps S1, S2, and S3, and optionally S4, are performed in this order, or the phase modulator / converter of the invention is designed and / or configured to perform steps S1, S2, and S3, and optionally S4, in this order. This enables particularly reliable and comprehensive calibration of the phase modulator / converter.

[0087] The reference signal generation module and / or carrier signal generation module can be used as a component of the clock generation device of the phase modulation converter, and are preferably a component of the clock generation device of the demodulation device of the phase modulation converter.

[0088] In particular, when using at least one logic system, automated calibration can be performed, during which steps S1, S2 (optional), S3, and S4 are also optional. Multiple logic systems can also be configured, or a shared logic system can encompass the steps of multiple modules. As described above, for example, a reference logic system and an adder logic system can be used to achieve phase changes.

[0089] Amplitude modulators with carrier suppression can be, for example, (digital) switching modulators, such as bipolar modulators, or (digital) ring modulators. Switching modulators preferably comprise at least one, particularly a digital switch, and / or at least one mechanical relay and / or at least one reed relay and / or at least one MEMS switch, or are composed of the aforementioned elements.

[0090] The phase modulation converter according to the invention can be used as a component of, in particular, a programmable logic controller, especially as an input or input module of the controller. The phase modulation converter of the invention can also be used as a component of a measuring device, such as an oscilloscope or, in particular, a digital multimeter, preferably as an input or input module thereof. Attached Figure Description

[0091] Other advantages and features of the invention will become more apparent from the following description taken in conjunction with the accompanying drawings. Wherein it is shown that:

[0092] Figure 1 A purely schematic diagram illustrating an embodiment of a phase modulation converter according to the present invention is shown;

[0093] Figure 2 An enlarged, purely schematic diagram of the clock generation device, XOR module, integrator, and other components in an alternative demodulation apparatus employing four sampled clock signals is shown.

[0094] Figure 3 Show Figure 1 The demodulation device of the phase modulator-demodulator shown is an enlarged pure schematic diagram of the clock generation device, XOR module, integrator and other components.

[0095] Figure 4 Show Figure 1 An enlarged schematic diagram of the three clock generation modules in the clock generation device of the phase modulation converter shown.

[0096] Figure 5 Show SigRF and Sig BA Sequence diagrams for unidirectional or bidirectional measurements.

[0097] Figure 6 Three pointer diagrams are shown, involving the modulator carrier signal Sig. MT The corresponding shifted adder carrier signal Sig AT Reference signal Sig RF Amplitude modulation signal Sig AM and the phase modulation signal Sig PM ,

[0098] Figure 7 Six more pointer diagrams are shown, involving Sig MT The corresponding shifted adder carrier signal Sig AT Reference signal Sig RF Amplitude modulation signal Sig AM and the phase modulation signal Sig PM .

[0099] In the figures, identical or similar elements and components are represented by the same reference numerals. Detailed Implementation

[0100] Figure 1 An embodiment of the phase modulation converter 1 according to the present invention is shown in purely schematic block diagram form, for converting the analog input signal Sig... A Converted to digital output signal Sig O .

[0101] Phase modulation converter 1 includes an amplitude modulator 2 with carrier rejection, and the analog signal to be converted is Sig. A It can be or has been fed to its input 3. Amplitude modulator 2 is designed to receive the analog input signal Sig. A Obtain the carrier-free amplitude modulation signal Sig AM The signal is transmitted to subsequent stages via two differential lines. It should be noted that the two lines used for differential transmission and the input terminals are not shown separately in the figure; only one is shown for ease of explanation. The amplitude modulator 2 can be, for example, a switching modulator or a ring modulator. The switching modulator can include at least one, particularly a digital switch, and / or at least one mechanical relay and / or at least one reed relay and / or at least one MEMS switch, or be composed of the aforementioned elements.

[0102] At another input terminal 4, which can also be called carrier input terminal 4 to distinguish it from input terminal 3, a rectangular or sinusoidal modulator carrier signal Sig is provided to the amplitude modulator 2. MTThe method of its generation will be further explained below. The output terminal 5 of amplitude modulator 2 outputs an amplitude modulated signal Sig as a differential signal. AM .

[0103] Amplitude Modulation Signal Sig AM The signal then passes through the analog filter 6 following the amplitude modulator 2, and is fed into the adder 7 following the phase modulator-converter 1 via its input 8. At another input 9, which can be called the carrier input, another rectangular or sinusoidal adder carrier signal Sig is provided to the adder 7. AT This signal is related to the sinusoidal modulator carrier signal Sig. MT There must be a phase difference, especially a 90° phase difference. It can also be said that the adder carrier signal Sig... AT It is a cosine waveform. This is achieved by modulating the carrier-free amplitude-modulated signal Sig. AM With the sinusoidal waveform adder carrier signal Sig AT Adding them together yields a phase-modulated signal Sig with amplitude modulation caused by interference. PM .

[0104] A calibration switch S is connected before the adder 7, and its structure and purpose will be described in detail below. In this embodiment, the calibration switch S is located between the amplitude modulator 2 and the adder 7, specifically between the amplitude modulator 2 and the filter 6. It should be noted that the calibration switch S can also be located before the amplitude modulator 2 in principle, so it does not necessarily have to be located between the amplitude modulator 2 and the adder 7.

[0105] A current isolation device G, comprising a pair of coupling capacitors, is provided before the calibration switch S. This type of current isolation device can be implemented very easily in the phase modulator-converter 1 and can be placed at almost any location from the signal path P to the digital circuit section 15, which constitutes a significant advantage of the phase modulator-converter 1.

[0106] Signal Sig PM The output is at terminal 10 of adder 7 and fed into limiter 11 via its input terminal 12. Limiter 11 is designed to suppress the signal Sig. PM Amplitude modulation caused by interference. The obtained signal Sig BA This is also referred to as the limiting signal, and it is output from the output terminal 13 of the limiter 11.

[0107] Signal Sig BA Now, with the adder carrier signal Sig... AT Or suppressed carrier signal Sig MT Modulation is carried at different time zero-crossing points compared to the previous one. This is in Figure 1The limiter 11 in the upper right corner is shown purely schematically. It can be seen that in each time-related graph, the signal Sig is displayed. BA (Above) and signal Sig MT (Below), and the time offset Δt. Signal Sig BA The amplitude fluctuates between 0 and 1, thus obtaining a signal with a digital amplitude.

[0108] The signal Sig after limiting BA The signal is fed into input terminal 14 of digital circuit section 15, which is used to process the signal Sig. BA Demodulation is performed, and it can be used for other purposes. It should be noted that, although in Figure 1 No other components are shown between the limiter 11 and the digital circuit section 15, but the possibility of such components being present cannot be ruled out. In other words, the limiting signal Sig BA It can be directly input to the digital circuit section 15, or input through other components that may further process the signal.

[0109] The digital circuit section 15 may include at least one FPGA and / or ASIC, or be composed of at least one FPGA and / or ASIC. In this embodiment, the digital circuit section is composed of FPGA 15.

[0110] The demodulation device 16 of device 1 is implemented on FPGA15. This demodulation device can be used to process the limiting signal Sig. BA Digital demodulation is performed. The demodulation device 16 can also be called a digital demodulator.

[0111] Furthermore, within the demodulation framework, at least one sampling clock signal CLK0-CLK3 is used to sample the signal Sig. BA The sampling, and the reference signal Sig, which is also sampled by at least one sampling clock signal. RF The comparison, and the integration of the comparison results. Regarding the reference signal Sig... RF The generation and comparison of these will be explained in further detail below.

[0112] Figure 2 This is a purely schematic block diagram of digital demodulation, employing demodulation device 16, and is applicable to the case where sampling is performed using sampling clock signal CLK0. Figure 3 Another embodiment utilizing multiple sampling clock signals is shown, a method that has proven particularly advantageous. Figure 3 The diagram illustrates, for example, a structure utilizing four sampling clock signals CLK0-CLK3.

[0113] Demodulation device 16 includes clock generation device 17 and at least one for limiting signal Sig.BA The buffer 18, preferably a FIFO buffer, is referred to as signal buffer 18 in this example. Additionally, at least one reference signal Sig is provided. RF Buffer 19, which is also preferably a FIFO buffer, and is distinguished from the buffer used for signal Sig BA The buffer 18 is referred to as the reference buffer 19. It should be noted that, despite the different names mentioned above, at least one signal buffer 18 and at least one reference buffer 19 can have the same structure, and in this example they are indeed the same structure.

[0114] The number of signal buffers 18 is typically the same as the number of reference buffers 19, and is respectively equal to the number of sampling clock signals CLK0-CLK3 used. Therefore, as... Figure 2 As shown, the demodulation device 16 includes a signal buffer 18 and a reference buffer 19.

[0115] Figure 3 As shown exemplarily, the four sampling clock signals CLK0-CLK3 can be used to limit the signal Sig. BA and reference signal Sig RF Perform sampling. Figure 3 The demodulation device 16 thus includes four signal buffers 18, preferably identical in structure, and four reference buffers 19, preferably identical in structure. Figure 1 In the diagram, for ease of explanation, buffers 18 and 19 are shown in series, with the first buffers 18 and 19 drawn with solid lines and the subsequent buffers 18 and 19 drawn with dashed lines to indicate that these buffers can exist as optional additional buffers.

[0116] Following buffers 18 and 19 and connected to their outputs is an XOR module 20, which can include or be implemented with an XOR gate. Specifically, the output of at least one signal buffer 18 is connected to one input of the XOR module 20, and the output of at least one reference buffer 19 is connected to the other input of the XOR module 20, thereby enabling the output values ​​to be passed to the module for comparison. Figure 3 In the embodiment shown, the outputs of all four signal buffers 18 are connected to one input of the XOR module 20, and the outputs of all four reference buffers 19 are connected to the other input of the XOR module 20.

[0117] In addition, an integrator 21 is provided after the XOR module 20 to integrate the value output by the XOR module 20.

[0118] exist Figure 2 and Figure 3In the illustrated embodiment, the clock generation device 17 of the demodulation device 16 includes three clock modules 22, 23, and 24. These three clock modules 22, 23, and 24 generate a total of seven signals CLK0-CLK7, including a sampling clock signal CLK0 used for sampling. Figure 2 ) or CLK0-CLK3 ( Figure 3 ).

[0119] Each clock module 22-24 includes a phase-locked loop (PLL) with a voltage-controlled oscillator (VCO). The internal structure of the three clock modules 22-24—also highly simplified and purely illustrative—is shown in... Figure 4 As shown in the diagram. Here, the phase-locked loops (PLLs) of each clock module 22-24 and their voltage-controlled internal oscillators (VCOs) are simplified and represented as a modular element.

[0120] The internal oscillator VCO of each clock module 22-24 is adjusted to a higher internal frequency f than the external reference signal generated by the external clock source 25 (e.g., provided by a quartz resonator) by a correspondingly set factor. VCO The three clock modules 22-24 can be powered by the same external clock source 25, but this is not mandatory.

[0121] Clock modules 22-24 can, for example, be composed of, or contain a Mixed Mode Clock Manager (MMCM) module or block. For example, manufacturers such as Xilinx or AMD offer FPGA devices equipped with such modules or blocks.

[0122] Each clock module 22 to 24 has multiple clock outputs. Figure 4 The clock is represented by block elements with a reference number of 26. Each clock output can use a different divider—thus obtaining different frequencies—and different fixed-defined phases. All clocks are represented by f. VCO Output. Next to block element 26, which represents the clock output, are shown the clock signals CLK0-CLK7 generated and output by their respective clock blocks 22-24 in the illustrated embodiment. The corresponding numbers CLK0 to CLK7 also appear... Figure 2 and Figure 3 The diagrams are accompanied by arrows indicating their specific uses, which will be explained later. Each clock block 22-24 and its voltage-controlled oscillator (VCO) have a phase-locked tap 27 and at least one phase-variable tap 28. The phase-variable tap 28 can subdivide the phase into smaller steps. In this embodiment, it can be subdivided into 56 steps, that is, in steps of 360° / n, where n = 56. The number of 56 steps is for illustrative purposes only.

[0123] Clock module 22 is used for limiting signal SigBA and reference signal Sig RF The sampling provides a fast sampling clock signal, i.e., a sampling clock signal. In Figure 2 In the example shown, the sampling clock signal CLK0 is used. Figure 3 In the example shown, the sampling clock signals are CLK0-CLK3. This module is called the sampling clock signal generation module 22.

[0124] By way of example only, for the frequencies of the fast sampling clock signals CLK0-CLK3 used for sampling, which are determined by f VCO Export, up to 256MHz. VCO For example, it can be 1024MHz. Of course, other frequencies can also be used. Preferably, the frequencies of the (each) sampling clock signals CLK0-CLK3 are at least one order of magnitude higher than the modulator frequency of amplitude modulator 2, more preferably two orders of magnitude higher.

[0125] The second clock module 23 is used to generate slow internal signals. In the illustrated embodiment, this module generates clock signals CLK4, CLK5, and CLK6. CLK4 is a slower internal clock, 32MHz in this example, used for buffers 18 and 19, as well as the XOR module 20 and integrator 21. Figure 2 The corresponding arrows indicate the signal type. CLK5 is a square wave or sine wave signal. CLK6 is a signal with a phase difference from the square wave or sine wave signal, especially a cosine signal. The square wave or sine wave signal is output through the output terminal 29 of FPGA device 15, pointing to adder 7 to obtain Sig. AT The cosine signal is input to input terminal 9 of adder 7. The output terminal 30 of FPGA device 15 then converts the cosine signal into a Sig signal. MT The output is sent to input 4 of amplitude modulator 2. It should be noted that an analog filter 6 is also provided between output 29 of FPGA device 15 and input 9 of adder 7. This type of filter is not drawn between output 30 of FPGA device 15 and input 4 of amplitude modulator 2, but the possibility that such a filter is also present here cannot be ruled out. The second module is used to generate the modulator carrier signal Sig. MT and adder carrier signal Sig AT Therefore, it is called carrier signal generation module 23.

[0126] The third clock module 24 is used to generate CLK7, which corresponds to the reference signal Sig. RF This signal is either used for its generation or is purely internal and will not leave FPGA15. This module is called the reference signal generation module 24.

[0127] These three modules (22-24) are structurally identical. Differences may exist, which will be explained further below.

[0128] During the operation of the device, Figure 2 In this case, signal buffer 18 is used to fast sample the clock signal CLK0 to limit the signal Sig. BA Sampling was performed; while Figure 3 In this case, four signal buffers 18 are used to sample the limiting signal Sig with four fast-sampling clock signals CLK0-CLK3 with a fixed phase difference from each other. BA Sampling is performed and synchronized to the slower internal clock domain. The limiting signal Sig... BA The signals are fed into their respective signal buffers 18 at the input for sampling. Each signal buffer 18 receives both the fast sampling clock signals CLK0-CLK3 from the sampling clock signal generation module 22 for sampling and the slower internal clock signal CLK4 from the carrier signal generation module 23, and is synchronized through its respective signal buffer 18. It should be noted that... Figure 3 In order to use multiple sampling clock signals CLK0-CLK3 and their associated buffers 18 and 19, for clarity, no additional arrow pointing to the slower internal clock CLK4 is drawn.

[0129] Each signal buffer 18 has a 1-bit wide input and an 8-bit wide output. The ratio of the bit width of the input to the bit width of each signal buffer 18 is selected according to the ratio of the clock CLKi / CLK4, where i = 0, 1, 2, 3, or vice versa. In this example, CLKi / CLK4 = 256MHz / 32MHz = 8, where i = 0, 1, 2, 3.

[0130] Whenever eight sampled values ​​have accumulated in a signal buffer 18, these sampled values ​​are output from the signal buffer 18 and passed to the XOR module 20. The output uses a slower CLK4 clock, which is 32MHz in this example. In other words, each signal buffer 18 outputs the sampled digital limiting signal Sig in the correct timing sequence. BA .

[0131] The foregoing is entirely similar for each of the respective reference buffers 19, except that its input is not the limiting signal Sig. BA Instead, the reference signal Sig RF The signal is sampled by its respective high-speed sampling clock signals CLK0-CLK3 and synchronized by CLK4, such as... Figure 2 and Figure 3 The corresponding arrows are used to indicate this.

[0132] Therefore, a “sampled” digital reference signal can be obtained from the (each) reference buffer 19, which is timed by the same clock signal CLK0 or the same clock signals CLK0-CLK3. Thus, its timing sequence is consistent with the “sampled” limiting Sig obtained from the signal buffer 18. BA The signals are consistent.

[0133] exist Figure 3 In the variant shown, which uses four sampling clock signals CLK0-CLK3, each signal buffer 18 outputs a different portion of the signal. Each CLK sampling domain provides a data block. Within the same domain, the reference signal Sig is correspondingly... RF Sampling is performed. In the XOR module 20, block-by-block comparisons can be implemented.

[0134] To achieve higher resolution, the sampling process can be advantageously configured to handle the amplitude-limited signal Sig. BA and reference signal Sig RF A sampling clock signal CLK0 is used for sampling. Figure 2 ) or multiple sampling clock signals CLK0-CLK3 ( Figure 3 The phase of the sampling clock signal generation module 22 changes dynamically. For this purpose, the feedback path 31 of the sampling clock signal generation module 22 is connected to the phase energy-varying tap 28 of the voltage-controlled oscillator.

[0135] The signal fed back to the voltage-controlled oscillator (VCO) via feedback path 31 has its phase changed continuously or repeatedly. This process is preferably performed periodically, for example, every few microseconds, approximately every 42 microseconds. The phase shift occurs in 360° / 56 steps each time and in the same direction. A resolution enhancement logic system 32 is provided (see...). Figure 1 The demodulation device 16 is preferably implemented on an FPGA 15, which also includes or constitutes the demodulation device 16 and implements corresponding control over the dynamic phase change of the sampling clock signal. The resolution enhancement logic system 32 can be used as a component of the demodulation device 16.

[0136] Because in Figure 3 In the embodiment shown, multiple sampling clock signals CLK0-CLK3 are all generated by the output signal of an oscillator VCO of the sampling clock signal generation module 22. Therefore, the repeated change of the feedback signal phase will cause the phase of all sampling clock signals CLK0-CLK3 used for sampling to be synchronized and repeatedly changed with equal steps.

[0137] By adjusting the step size of the feedback signal through feedback path 31, the phase of all CLK outputs of the sampling clock signal generation module 22 will change synchronously with each phase step of the oscillator VCO. The individual sampling clock signals CLK0-CLK3 can also be fixedly 90° out of phase with each other.

[0138] In this case, the phase step size is

[0139] t STEP =1 / (768MHz*56)=1 / 43,008GHz=23,25ps.

[0140] Since the 256MHz sampling clocks CLK0-CLK3 are 90° out of phase, only one phase difference needs to be covered.

[0141] t diff =1 / (256MHz*4) = 976.56ps

[0142] This allows for the coverage of all possible discrete sampling points using a fine phase step. In FPGA15, 42 (976.56ps / 23.25ps) cycles of the modulator frequency are accumulated.

[0143] Its theoretical resolution is

[0144] log2(90° / 360°*43008MHz / 1MHz)=13,39Bit

[0145] No need to change the frequency of amplitude modulator 2.

[0146] The data rate was reduced from 1MHz to 1MHz / 42 = 23.8kHz.

[0147] If there is no dynamic phase shift, the calculated resolution is:

[0148] log2(90° / 360°*4*256MHz / 1MHz)=8bit.

[0149] By using the XOR module 20 connected after buffers 18 and 19, the limiting signal Sig can be determined after fast sampling and synchronization. BA With reference signal Sig RF When does the difference exist? It is then integrated using integrator 21 to obtain the converted value, which is used as Sig. O Output from FPGA15 (see) Figure 1 ).

[0150] Typically, integration will continue until the phase of the aforementioned sampling clock signals CLK0-CLK3 dynamically changes within an angular range of 360° / m, where m is the value used to limit the amplitude of the signal Sig. BA The number of sampling clock signals used for sampling. According to the device 1 of the present invention, especially its demodulation device 16 or the FPGA 15 of the device, this can be configured accordingly.

[0151] In phase modulator-converter 1, for example, there may be differences in printed circuit board (PCB) transmission delay, which may cause the output results to be distorted or inaccurate. Therefore, phase modulator-converter 1 needs to be calibrated at least once as described below, especially before the user first enables it (such as at the factory) and / or at least once more after enabling it.

[0152] Calibration can also be performed, especially when it is desired to measure bidirectional input voltage using phase modulator-converter 1.

[0153] Depending on whether the signal being measured is unipolar or bipolar, the phase zero position should be set to different values ​​(180° and 90°). This is important. Figure 5 The above is for illustrative purposes only. The upper part represents the reference signal Sig. RF The following two are the amplitude limiting signals Sig. BA They are located in the middle of the optimal output position for unidirectional measurement and below the optimal output position for bidirectional measurement, respectively.

[0154] Furthermore, ideally, especially when there may be transmission delay differences on the printed circuit board, the modulator carrier signal Sig MT With the corresponding shifted adder carrier signal Sig AT The phase shift should be maintained as precisely as possible at 90°. A deviation from 90° will result in different magnitudes of phase shift in different directions. This can be most intuitively understood through pointer diagrams, such as... Figure 6 As shown.

[0155] The pointer diagram at the top illustrates the ideal situation, where the phase shift equals the adder carrier signal Sig used for phase modulation. AT With carrier suppression amplitude modulation Sig AM Or signal Sig MT The angle between them is exactly 90°. The result is that the phase modulation Sig... PM Relative to the reference signal Sig RF It has a uniform phase shift.

[0156] The pointer diagram in the middle illustrates a situation where, for example, due to delay errors on the printed circuit board, the adder carrier Sig... AT With carrier suppression amplitude modulation Sig AM Or signal Sig MT The angle between them is not exactly 90°. This results in a phase modulation Sig PM Relative to the reference signal Sig RF The phase shift is no longer uniform.

[0157] The pointer graph below shows even the reference signal Sig RFEven after adjustment, a 90° deviation still exists. Even with the reference signal Sig... RF Already connected to adder carrier Sig AT Matching, due to carrier suppression amplitude modulation Sig AM Or signal Sig MT The phase shift caused by the offset is not necessarily at its maximum value. Therefore, the resolution of the phase modulator / converter may be reduced. This can be avoided by the following calibration. To perform calibration, the calibration switch S should first be set to the calibration setting, unless it is already in that position. Figure 7 In this context, the first step (if necessary) is marked S0. During calibration setup, the input 6 of adder 7, or the two inputs 6 in the case of differential signal transmission, is no longer connected to the output 5 (or multiple outputs) of amplitude modulator 2, but is instead connected to ground. It can also be said that the amplitude modulation Sig... AM =Zero, phase modulation Sig PM Become Sig AM This is a cosine signal, which, regardless of the position of the calibration switch S, further reaches the input terminal 9 of the adder 7.

[0158] To set the input voltage to 0V, a solid-state relay (SSR) or a simple MEMS switch is particularly recommended, as this allows for continued utilization of the purely passive circuitry that can be implemented on the process side for the phase modulator-converter 1. The calibration switch S can comprise, or be constructed from, at least one solid-state relay and / or at least one MEMS switch. This switch can particularly be a changeover switch.

[0159] Subsequently, in step S1, when the calibration switch S is in the calibration setting, the reference signal Sig is dynamically changed. RF The phase, and find the reference signal Sig RF The output signal of the demodulation device 16 is specifically the digital value Sig. O The phase of the reference signal Sig is used, and this calibration value is represented by the phase of the reference signal Sig. RF The maximum achievable value at the phase shift, or the calibrated value, differs from the maximum achievable value at that phase shift by no more than a predetermined maximum deviation. Alternatively, it can be stated that, firstly, for the reference signal Sig... RF Perform a shift to make the digital value Sig O To maximize or increase as much as possible.

[0160] To achieve the reference signal Sig RF The dynamic phase shift, such as Figure 4 As shown below, the feedback path 31 of the oscillator VCO can be connected to the phase energy change tap 28 of the reference generation module 24. Alternatively, the phase energy change tap 28 can also be used directly to generate the reference signal Sig. RFIn other words, the signal is provided by or obtained from this tap. Alternatively, in this case, the phase-variable tap 28 is not used for the feedback path, but rather for the "forward branch." The feedback path 31 is preferably connected to the phase-locked tap 27 of the reference generation module 24. Figure 4 The implementation method for module 24 is not shown in the text, but module 23 has been shown, which will be further explained later.

[0161] In addition, a reference logic system 33 is provided for implementing an offset to find the (most possible) maximum value. The reference logic system 33 is implemented on the FPGA 15 of the demodulation device 16, which is again for illustrative purposes only. This offset can be implemented multiple times or repeatedly in steps of 360° / 56, as described above in the description related to module 22.

[0162] In the next step S2, the reference signal is no longer shifted, but remains at the reference signal Sig determined in step S1. RF Based on the phase, actively Sig MT Move to Sig AT In this example, SIN is shifted to COS. This process continues until the modulator carrier signal Sig is found. M and / or adder carrier signal Sig AT The output signal Sig of the demodulation device O The phase of the phase is calibrated, which is the maximum value that can be achieved at the phase shift or the calibrated value differs from the maximum value that can be achieved at the phase shift by no more than a predetermined maximum deviation.

[0163] In the example shown, what is being changed or adjusted is the adder carrier signal Sig. AT The phase of (i.e., COS). Understandably, as an alternative, the phase of the modulator carrier signal SigMT can also be changed.

[0164] In changing Sig MT With Sig AT When the phase relationship between them is Sig O The maximum value occurs when the two signals differ by 90°. To achieve the adder carrier signal Sig... AT The dynamic phase shift also necessitates the use of a phase-variable output terminal 28 for this signal, specifically the output terminal of the oscillator VCO of the carrier generation module 23. This can also be referred to as the adder carrier signal Sig. AT The signal can be output through or obtained from the phase-variable output terminal 28. The phase-variable tap 28 is used for the "forward branch". For completeness, it should be noted that, in principle, the phase-variable tap 28 can also be connected to the feedback path 31. If the modulator carrier signal Sig... M and adder carrier signal SigAT If separate modules are set up (not shown in the figure), this can be achieved.

[0165] In addition, in order to add the carrier signal Sig AT A shift is performed using adder logic system 34, which utilizes phase-variable taps 28 to achieve the shift to obtain the (maximum possible) value. Adder logic system 34 is implemented on the FPGA 15 of demodulation device 16, which is again for illustrative purposes only. Here, the phase shift or change can also be performed in principle as described above for modules 22 and 24.

[0166] Then, the control setting of calibration switch S is switched to apply a 0V input voltage to phase modulation converter 1, and in step S3, the reference signal Sig is preferably changed again in a dynamic manner. RF The phase, and find the reference signal Sig RF The output signal Sig of demodulation device 16 is made O The phase of the calibration value is used, which is zero or differs from zero by no more than a predetermined maximum deviation, or is equal to half of the maximum value achievable at that phase shift, or differs from half of the maximum value achievable at that phase shift by no more than a predetermined maximum deviation. This depends on whether unidirectional (zero) or bidirectional (maximum / 2) measurement is to be achieved, especially for input voltage measurement. For this purpose, a reference logic system 33 can also be used.

[0167] Optionally, a "direction test" can also be performed in step S4, and adjustments can be made if necessary. Therefore, it can be specified that in step S4, when the calibration switch S is in the control setting, a non-zero input voltage is applied to the phase modulation converter 1, and it is checked whether the output signal of the demodulation device 16 adopts a value greater than 0V when the input voltage is greater than zero, and whether the output signal adopts a value less than 0V when the input voltage is less than zero. If this is not the case, the reference signal Sig should be... RF The phase shift is 180°. It can also preferably change dynamically in one direction until the output signal of the demodulation device 16 reaches its initial value again. The reference signal Sig... RF The phase change is preferably performed when a 0V input voltage is applied to the input terminal of the phase modulator-converter 1.

[0168] As mentioned above, Figure 7 The above steps and their results are visualized using a pointer diagram. Step S3 achieves a phase shift symmetrical to the input voltage. In the pointer diagram at the upper left, above the pointer diagram for step S0, Figure 7 The ideal scenario is shown again, and to its right, above the pointer diagram for step S1, is Sig. MT With Sig ATThe cases where the offset is not 90° are shown. Here, wl1, wl2, wr1, and wr2 represent the left and right rotation pointers at two different time points t1 and t2, respectively. In addition, pointers derived from parallelograms wr and wl are also drawn.

[0169] Through dynamic calibration of the bias and Sig MT With Sig AT The required fixed 90° phase shift distortion between (SIN and COS in this example) is corrected, compensating for manufacturing and component tolerances even during operation. Furthermore, this enables the implementation of bidirectional industrial analog input channels with lower circuit complexity. When potential isolation between the analog channel and evaluation logic is required, the solution using the in-operation calibrable phase modulator-converter 1 of this invention can be achieved more easily than ever before.

[0170] Furthermore, the characteristics of phase modulation converter 1, namely the input voltage Sig A Mapped to the output voltage Sig using the arctan function O This allows for more efficient utilization. Near zero, a small change in phase difference results in a larger signal amplitude compared to the same change at the edge of the input voltage range. This means that the signal-to-noise ratio is highest near zero.

[0171] Although the present invention has been described and illustrated in detail through preferred embodiments, the present invention is not limited to the disclosed embodiments, and those skilled in the art can derive other variations without departing from the scope of protection of the present invention.

[0172] Regardless of the grammatical gender of a particular term, it covers individuals with masculine, feminine, or other parts of speech.

Claims

1. A method for calibrating a phase modulation converter (P), wherein, The phase modulation converter (1) has: An amplitude modulator with carrier suppression (2), the input signal to be converted (Sig A The signal can be fed to the amplitude modulator at the input side to obtain a carrier-free amplitude modulated signal (Sig). AM ), Adder (7), used to convert a phase-shifted, preferably sinusoidal, adder carrier signal (Sig) AT ) and the carrierless amplitude modulation signal (Sig AM Add them together to obtain the phase modulation signal (Sig). PM ), limiter (11), the phase modulation signal (Sig PM The signal can be fed to the limiter, and the limiter can suppress the phase modulation signal (Sig). PM Amplitude modulation caused by interference in ) and The demodulation device (16) outputs the signal (Sig) from the limiter (11). BA The signal can be fed to the demodulation device and demodulated within the demodulation device, wherein the signal output by the limiter (Sig) can be demodulated within the demodulation range. BA ) and reference signal (Sig RF The comparison is performed, and wherein the adder carrier signal (Sig) can be generated in the demodulation device (16). AT ); A calibration switch (S) is connected upstream of the adder (7), particularly arranged between the amplitude modulator (2) and the adder (7), and the calibration switch is actuated between a control setting and at least one calibration setting, in which the adder (7) is connected to the input of the phase modulator (1) via the calibration switch (S), and in the calibration setting, the connection between the adder (7) and the input of the phase modulator (1) is disconnected and preferably another connection is established, particularly the connection between the adder (7) and ground or ground plane; The method includes: in step S1, in the calibration settings of the calibration switch (S), especially when connected to ground or ground, preferably dynamically changing the phase of the reference signal, and finding the phase of the reference signal that causes the output signal of the demodulation device to adopt a calibration value, the calibration value representing the maximum value that can be achieved at the phase shift or the calibration value differing from the maximum value that can be achieved at the phase shift by no more than a predetermined maximum deviation.

2. The method according to claim 1, characterized in that, The reference signal (Sig) is generated from the output signal of a voltage-controlled oscillator (VCO), in particular. RF The oscillator is a component of a phase-locked loop (PLL), and the phase of the reference signal is dynamically changed by dynamically altering the phase of the feedback signal of the oscillator (VCO) in steps of less than 40°, preferably less than 20°, and particularly preferably less than 10°. The feedback signal is taken from the output side of the oscillator (VCO) and, particularly, fed back to the oscillator (VCO) on the input side. Preferably, The oscillator (VCO) has at least one phase-variable tap (28) and at least one phase-locked tap (27), wherein the at least one phase-variable tap (28) is capable of dividing the 360° phase of the oscillator (VCO) into n steps, wherein n is a natural number greater than or equal to 30, particularly greater than or equal to 40, preferably greater than or equal to 50, especially preferably greater than or equal to 100, and wherein the reference signal (Sig RF The signal can be obtained from the phase energy change tap (28), or the phase energy change tap (28) can be connected to the feedback path of the oscillator (VCO), such that the signal originating from the phase energy change tap (28) can be fed back to the oscillator (VCO) as a feedback signal, especially on the input side, and the phase of the signal originating from the phase energy change tap (28) changes dynamically in steps of 360° / n.

3. The method according to claim 1 or 2, characterized in that, For carrier suppression, the carrier signal generated by the demodulation device (16) is fed to the amplitude modulator (2), and in particular, the modulator carrier signal (Sig) is fed at the second input terminal (9) of the amplitude modulator (2). MT And in step S2, in the calibration settings of the calibration switch (S), Especially when a connection to ground or the ground is provided, it is preferable to dynamically change the modulator carrier signal (Sig). MT ) and / or the adder carrier signal (Sig AT The phase of the modulator carrier signal (Sig) is determined, and the change is used to find the phase of the modulator carrier signal (Sig). MT ) and / or the adder carrier signal (Sig AT The output signal of the demodulation device (16) adopts a phase of a calibration value, which represents the maximum value that can be achieved at the phase shift or the calibration value differs from the maximum value that can be achieved at the phase shift by no more than a predetermined maximum deviation.

4. The method according to claim 3, characterized in that, The modulator carrier signal (Sig) is generated from the output signal of a voltage-controlled oscillator (VCO), in particular. MT ) and / or the adder carrier signal (Sig AT The oscillator is a component of a phase-locked loop (PLL), and the dynamic change of the phase of the modulator carrier signal and / or the adder carrier signal is achieved by dynamically changing the phase of the feedback signal of the oscillator (VCO) in steps of less than 40°, preferably less than 20°, and particularly preferably less than 10°. The feedback signal is taken from the output side of the oscillator (VCO) and, particularly, fed back to the oscillator (VCO) at the input side. Preferably, The oscillator (VCO) has at least one phase-variable tap (28) and at least one phase-locked tap (27), wherein the at least one phase-variable tap (28) is capable of dividing the 360° phase of the oscillator (VCO) into n steps, wherein n is a natural number greater than or equal to 30, particularly greater than or equal to 40, preferably greater than or equal to 50, especially preferably greater than or equal to 100, and wherein the modulator carrier signal (Sig MT or adder carrier signal (Sig AT The signal can be obtained from the phase energy change tap (28), or the phase energy change tap (28) can be connected to the feedback path of the oscillator (VCO), such that the signal originating from the phase energy change tap (28) can be fed back to the oscillator (VCO) as a feedback signal, especially on the input side, and the phase of the signal originating from the phase energy change tap (28) changes dynamically in steps of 360° / n.

5. The method according to any one of the preceding claims, especially according to claim 3 or 4, characterized in that, In step S3, in the control settings of the calibration switch (S), the reference signal (Sig) RF The phase of the signal is preferably changed dynamically again, and the reference signal (Sig) is found in the change. RF The output signal of the demodulation device (16) adopts the phase of the calibration value, wherein the calibration value is zero or the calibration value differs from zero by no more than a predetermined maximum deviation, or the calibration value represents half of the maximum value that can be reached at the phase shift or the calibration value differs from half of the maximum value that can be reached at the phase shift by no more than a predetermined maximum deviation.

6. The method according to claim 5, characterized in that, In step S4, if the calibration switch (S) is in the control setting, a non-zero input voltage is applied to the phase modulation converter (P), and it is checked whether the output signal of the demodulation device (16) adopts a value greater than the value of the output signal when the input voltage is 0V, and whether the output signal of the demodulation device adopts a value smaller than the value of the output signal when the input voltage is less than zero. In particular, if not adopted, especially when a 0V input voltage is applied to the phase modulation converter (1), it is preferable to dynamically change the reference signal (Sig) in one direction. RF The phase of the demodulation device (16) remains unchanged until a 180° phase change is achieved and / or the value of the output signal of the demodulation device (16) returns to its initial value.

7. The method according to any one of the preceding claims, characterized in that, The phase modulation converter (1) includes at least one current isolation device (G), wherein the at least one current isolation device (G) is connected upstream of the calibration switch (S) and / or the at least one current isolation device includes at least one pair of coupling capacitors.

8. A phase modulation converter (1), comprising: An amplitude modulator with carrier suppression (2), the input signal to be converted (Sig A The signal can be fed to the amplitude modulator at the input side to obtain a carrier-free amplitude modulated signal (Sig). AM ), Adder (7), used to convert a phase-shifted, preferably sinusoidal, adder carrier signal (Sig) AT ) and carrierless amplitude modulation signal (Sig AM Add them together to obtain the phase modulation signal (Sig). PM ), Limiter (11), the phase modulation signal (Sig PM The signal can be fed to the limiter, and the limiter can suppress the phase modulation signal (Sig). PM Amplitude modulation caused by interference in ) and The demodulation device (16) outputs the signal (Sig) from the limiter (11). BA The signal can be fed to the demodulation device and demodulated within the demodulation device, wherein the signal output by the limiter (Sig) can be demodulated within the demodulation range. BA ) and reference signal (Sig RF The comparison is performed, and wherein the adder carrier signal (Sig) can be generated in the demodulation device (16). AT );and A calibration switch (S) is connected upstream of the adder (7), particularly arranged between the amplitude modulator (2) and the adder (7), and the calibration switch is actuated between a control setting and at least one calibration setting, in which the adder (7) is connected to the input of the phase modulator (1) via the calibration switch (S), and in the calibration setting, the connection between the adder (7) and the input of the phase modulator (1) is disconnected and preferably another connection is established, particularly the connection between the adder (7) and ground or ground plane; The phase modulation converter (1) is constructed and / or configured to preferably dynamically change the reference signal (Sig) for calibration. RF The phase of ) and find the reference signal (Sig) RF The output signal of the demodulation device (16) adopts the phase of the calibration value, which represents the maximum value that can be achieved at the phase shift or the calibration value differs from the maximum value that can be achieved at the phase shift by no more than a predetermined maximum deviation.

9. The phase modulation converter (1) according to claim 8, characterized in that, The phase modulation converter (1) has a logic system that is constructed and / or configured to, preferably dynamically, change the reference signal (Sig). RF The phase of ) and the reference signal (Sig) are found in the change. RF The phase modulation converter (33) makes the output signal of the demodulation device (16) adopt the phase of the calibration value, which represents the maximum value that can be achieved at the phase shift or the calibration value differs from the maximum value that can be achieved at the phase shift by no more than a predetermined maximum deviation.

10. The phase modulation converter (1) according to claim 8 or 9, characterized in that, The phase modulation converter (1), and especially the demodulation device (16), has a function for generating the reference signal (Sig). RF The reference signal generation module (24) includes, in particular, a voltage-controlled oscillator (VCO), which is a component of a phase-locked loop (PLL), wherein the reference signal can be generated from the output signal of the oscillator (VCO). Preferably, the oscillator (VCO) has at least one phase-variable tap (28) and, more particularly, at least one phase-locked tap (27), wherein the at least one phase-variable tap (28) is capable of dividing the 360° phase of the oscillator (VCO) into n steps, wherein n is a natural number greater than or equal to 30, more particularly greater than or equal to 40, preferably greater than or equal to 50, and especially preferably greater than or equal to 100, and wherein the reference signal (Sig RF The signal can be obtained from the phase energy change tap (28) or the phase energy change tap (28) can be connected to the feedback path of the oscillator (VCO), so that the signal originating from the phase energy change tap (28) can be fed back to the oscillator (VCO) as a feedback signal, especially on the input side, and the phase modulation converter (P) is constructed and / or configured to dynamically change the phase of the signal originating from the phase energy change tap (28) of the oscillator (VCO) of the reference signal generation module (24) in steps of 360° / n.

11. The phase modulation converter (1) according to any one of claims 8 to 10, characterized in that, The amplitude modulator (2) is connected to the demodulation device (16), and in order to suppress carrier signals, a carrier signal generated by the demodulation device (16) is fed to the amplitude modulator (2), especially at the second input of the amplitude modulator (2), where a modulator carrier signal (Sig) is fed. MT The phase modulation converter (2) has a logic system that is constructed and / or configured to, preferably dynamically, change the modulator carrier signal (Sig). MT The phase of the adder carrier signal and / or the phase of the adder carrier signal (Sig) AT The phase of the modulator carrier signal (Sig) is determined, and the modulator carrier signal (Sig) is found. MT ) and / or the adder carrier signal (Sig AT The phase modulation converter (16) causes the output signal of the demodulation device (16) to adopt the phase of a calibration value, which represents the maximum value achievable at the phase shift or the calibration value differing from the maximum value achievable at the phase shift by no more than a predetermined maximum deviation. The phase modulation converter has an adder logic system. Preferably, The phase modulation converter (1), and especially the demodulation device (16), has a function for generating the modulator carrier signal (Sig). MT ) and / or the adder carrier signal (Sig AT The carrier signal generation module (23) includes, in particular, a voltage-controlled oscillator (VCO), which is a component of a phase-locked loop (PLL), wherein the modulator carrier signal and / or the adder carrier signal can be generated from the output signal of the oscillator (VCO). Preferably, the oscillator (VCO) has at least one phase-variable tap (28) and at least one phase-locked tap (27), wherein the at least one phase-variable tap (28) is capable of dividing the 360° phase of the oscillator (VCO) into n steps, wherein n is a natural number greater than or equal to 30, particularly greater than or equal to 40, preferably greater than or equal to 50, and especially preferably greater than or equal to 100. And therein, the modulator carrier signal (Sig MT ) or the adder carrier signal (Sig AT The signal can be obtained from the phase-variable tap (28), or the phase-variable tap (28) can be connected to the feedback path of the oscillator (VCO), so that the signal originating from the phase-variable tap (28) can be fed back to the oscillator (VCO) as a feedback signal, especially on the input side, and the phase modulator-converter (P) is constructed and / or configured to, preferably dynamically, change the phase of the signal originating from the phase-variable tap (28) of the oscillator (VCO) of the carrier signal generation module (23) in steps of 360° / n.

12. The phase modulation converter (1) according to any one of claims 8 to 11, characterized in that, The calibration switch (S) is configured as a changeover switch, and / or the calibration switch (S) includes or is equipped with at least one mechanical relay and / or at least one solid-state relay and / or at least one reed relay and / or at least one microelectromechanical system switch.

13. The phase modulation converter (1) according to any one of claims 8 to 12, characterized in that, The phase modulation converter (1) includes at least one current isolation device (G), wherein the at least one current isolation device (G) is connected upstream of the calibration switch (S), and / or the at least one current isolation device includes at least one pair of coupling capacitors.

14. The phase modulation converter (1) according to any one of claims 8 to 13, characterized in that, The phase modulation converter (1) is constructed and / or configured to perform the method according to claim 5, particularly wherein the phase modulation converter (1) is constructed and / or configured to perform steps S1, S2 and S3, preferably wherein the phase modulation converter (1) is constructed and / or configured to perform the method according to claim 6, particularly wherein the phase modulation converter (1) is constructed and / or configured to perform steps S1, S2, S3 and S4.

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