A bootstrap sampling switch circuit with pre-charge and an analog-to-digital converter

Abstract

This invention relates to the field of analog and mixed-signal integrated circuit technology, and discloses a bootstrap sampling switch circuit with pre-charge and an analog-to-digital converter (ADC). The circuit includes a sampling switch module and a timing control module. Under the control of a multi-phase clock signal generated by the timing control module, the sampling switch module operates sequentially in a hold phase, a pre-charge phase, and a tracking phase. By adding a pre-charge phase before the tracking phase, the gate voltage of the sampling switch is pre-raised, and the pre-charge time is dynamically controlled using an adjustable clock circuit, thereby effectively suppressing the charge-sharing effect caused by gate parasitic capacitance. The ADC includes the aforementioned sampling switch circuit. This invention significantly improves the linearity and conduction characteristics of the sampling switch and possesses excellent timing configurability, making it suitable for high-speed, high-precision analog-to-digital conversion systems.

Description

Technical Field

[0001] This invention relates to the field of analog and mixed-signal integrated circuit technology, and discloses a bootstrap sampling switch circuit with pre-charge and an analog-to-digital converter. Background Technology

[0002] As communication, medical, and measurement systems increasingly demand higher accuracy and speed in data conversion, the performance of analog-to-digital converters (ADCs) is crucial, and the linearity of the sampling switch is one of the core factors determining its performance. Traditional high-performance ADCs often employ a bootstrap switch structure, which improves linearity by bootstrapping the switch gate voltage to the input signal during the sampling (tracking) phase to maintain a constant on-resistance.

[0003] However, with the continuous shrinking of process dimensions and the increasing sampling speed, the gate parasitic capacitance effect of the sampling switch becomes increasingly significant. During the switching process from hold to track in traditional bootstrap switches, the bootstrap capacitor needs to share charge with the gate parasitic capacitance, resulting in a decrease in the effective bootstrap voltage applied to the gate. This increases the switch's on-resistance and severely degrades the sampling linearity and dynamic performance of the ADC. Although many studies have attempted to alleviate this problem by optimizing the bootstrap capacitor size or introducing compensation techniques, none have fundamentally eliminated the voltage loss caused by charge sharing, and it remains difficult to achieve a good balance between high speed, high accuracy, and design flexibility.

[0004] Therefore, there is an urgent need for an innovative sampling switch technology that can effectively suppress charge sharing effects, improve switching linearity, and have timing-adjustable capabilities to adapt to a wide range of applications with different process, speed, and accuracy requirements. Summary of the Invention

[0005] In view of this, this application provides a bootstrap sampling switch circuit and analog-to-digital converter with pre-charge, which fundamentally suppresses the charge sharing effect caused by gate parasitic capacitance, improves the linearity and dynamic performance of the sampling switch, and achieves flexible adaptation and performance optimization of the circuit under different processes and application scenarios through adjustable pre-charge time.

[0006] A bootstrap sampling switch circuit with pre-charge, comprising:

[0007] Sampling switch module and timing control module;

[0008] The sampling switch module is configured to operate sequentially in the hold phase, precharge phase, and tracking phase under the control of multiple clock signals generated by the timing control module;

[0009] The sampling switch module includes: a sampling switch NMOS transistor M13, a first switch K1, a second switch K2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a sampling capacitor Cs, an inverter INV1, a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh PMOS transistor M7, an eighth NMOS transistor M8, a ninth NMOS transistor M9, a tenth NMOS transistor M10, an eleventh NMOS transistor M12, and a twelfth PMOS transistor M14;

[0010] The gate of the sampling switch NMOS transistor M13 is connected to the second terminal of the first switch K1 and the second terminal of the second switch K2; the drain of the sampling switch NMOS transistor M13 receives the input signal Vin; the source of the sampling switch NMOS transistor M13 is connected to the upper plate of the sampling capacitor Cs; the lower plate of the sampling capacitor Cs is grounded.

[0011] The first terminal of the first switch K1 is connected to the source of the third NMOS transistor M3, the source of the twelfth PMOS transistor M14, and the upper plate of the third capacitor C3.

[0012] The first terminal of the second switch K2 is connected to the gate of the eighth NMOS transistor M8, the drain of the seventh PMOS transistor M7, the gate of the eleventh NMOS transistor M12, and the drain of the ninth NMOS transistor M9.

[0013] The gate of the third NMOS transistor M3 is connected to the gate of the second NMOS transistor M2 and the gate of the fourth NMOS transistor M4; the drain of the third NMOS transistor M3 and the drain of the fourth NMOS transistor M4 are connected to the power supply voltage Vdd; the source of the fourth NMOS transistor M4 is connected to the upper plate of the fourth capacitor C4; the lower plate of the fourth capacitor C4 is connected to the drain of the twelfth PMOS transistor M14 and the drain of the sixth NMOS transistor M6;

[0014] The gates of the fifth NMOS transistor M5 and the sixth NMOS transistor M6 both receive the second clock signal clk2; the sources of the fifth NMOS transistor M5 and the sixth NMOS transistor M6 are both grounded; the drain of the fifth NMOS transistor M5 is connected to the lower plate of the third capacitor C3 and the source of the eleventh NMOS transistor M12.

[0015] The gate of the first NMOS transistor M1 is connected to the source of the second NMOS transistor M2 and the upper plate of the second capacitor C2; the drain of the first NMOS transistor M1 is connected to the power supply voltage Vdd; the source of the first NMOS transistor M1 is connected to the gate of the second NMOS transistor M2 and the upper plate of the first capacitor C1; the drain of the second NMOS transistor M2 is connected to the power supply voltage Vdd; the lower plate of the first capacitor C1 receives the second clock signal clk2; the lower plate of the second capacitor C2 receives the first clock signal clk1.

[0016] The source of the seventh PMOS transistor M7 is connected to the source of the fourth NMOS transistor M4, the drain of the seventh PMOS transistor M7 is connected to the drain of the ninth NMOS transistor M9, the gate of the seventh PMOS transistor M7 is connected to the gate of the twelfth PMOS transistor M14 and the output of the inverter INV1, and the input of the inverter INV1 receives the first clock signal clk1.

[0017] The source of the eighth NMOS transistor M8 is connected to the output terminal of the inverter INV1, and its drain is connected to the source of the eleventh NMOS transistor M12.

[0018] The gate of the ninth NMOS transistor M9 is connected to the power supply voltage Vdd, and its source is connected to the drain of the tenth NMOS transistor M10; the gate of the tenth NMOS transistor M10 receives the second clock signal clk2, and its source is grounded.

[0019] The drain of the eleventh NMOS transistor M12 is connected to the drain of the sampling switch NMOS transistor M13 and receives the input signal Vin;

[0020] The timing control module is configured to generate the plurality of clock signals, including a first clock signal clk1, a second clock signal clk2, a first control signal SK1 for controlling the first switch K1 to be turned on or off, and a second control signal SK2 for controlling the second switch K2 to be turned on or off.

[0021] Optionally, in the pre-charge phase:

[0022] When the first control signal SK1 is high, it controls the first switch K1 to be turned on in order to establish a pre-charging path;

[0023] When the second control signal SK2 is low, the second switch K2 is turned off, which isolates the gate of the sampling switch NMOS transistor M13 from the gate nodes of the eighth NMOS transistor M8 and the eleventh NMOS transistor M12, thus turning off the sampling switch NMOS transistor M13, the eighth NMOS transistor M8 and the eleventh NMOS transistor M12.

[0024] The first clock signal clk1 is low level. After being inverted by the inverter INV1, it outputs a high level, which turns off the seventh PMOS transistor M7 and the twelfth PMOS transistor M14.

[0025] When the second clock signal clk2 is high, the third NMOS transistor M3, the fourth NMOS transistor M4, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the ninth NMOS transistor M9, and the tenth NMOS transistor M10 are turned on.

[0026] Optionally, in the tracking phase:

[0027] When the first control signal SK1 is low, the first switch K1 is turned off.

[0028] When the second control signal SK2 is high, it controls the second switch K2 to be turned on;

[0029] When the second clock signal clk2 is low, the third NMOS transistor M3, the fourth NMOS transistor M4, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the ninth NMOS transistor M9, and the tenth NMOS transistor M10 are turned off.

[0030] The first clock signal clk1 is high level. After being inverted by the inverter INV1, it outputs a low level, which turns on the twelfth PMOS transistor M14 and the seventh PMOS transistor M7.

[0031] The seventh PMOS transistor M7, which is turned on, connects the source of the fourth NMOS transistor M4 to the gate of the eighth NMOS transistor M8, thereby turning on the eighth NMOS transistor M8, the eleventh NMOS transistor M12, and the sampling switch NMOS transistor M13.

[0032] Optionally, in the holding phase:

[0033] When the first control signal SK1 is low, the first switch K1 is turned off.

[0034] When the second control signal SK2 is high, it controls the second switch K2 to be turned on;

[0035] The first clock signal clk1 is low level. After being inverted by the inverter INV1, it outputs a high level, which turns off the seventh PMOS transistor M7 and the twelfth PMOS transistor M14.

[0036] When the second clock signal clk2 is high, the third NMOS transistor M3, the fourth NMOS transistor M4, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the ninth NMOS transistor M9, and the tenth NMOS transistor M10 are turned on.

[0037] Specifically, the conducting ninth NMOS transistor M9 and tenth NMOS transistor M10 pull down the gate nodes of the eighth NMOS transistor M8, the eleventh NMOS transistor M12, and the sampling switch NMOS transistor M13 to a low level, thereby turning off the sampling switch NMOS transistor M13, the eighth NMOS transistor M8, and the eleventh NMOS transistor M12.

[0038] Optionally, in the tracking phase, the gate voltage of the sampling switch NMOS transistor M13 The following relationship must be satisfied:

[0039]

[0040] in, The power supply voltage is... The input signal, This refers to the gate parasitic capacitance of the sampling switch NMOS transistor M13.

[0041] Optionally, the timing control module includes:

[0042] The logic control unit, including multiple NOR gates, NAND gates and inverters, is used to receive input clock signals and enable signals, and generate intermediate control signals.

[0043] First charge / discharge module and second charge / discharge module;

[0044] The logic control unit generates the first clock signal clk1 and the second clock signal clk2; the input terminal of the first charging and discharging module receives the second clock signal clk2, and the input terminal of the second charging and discharging module receives the first clock signal clk1; the first charging and discharging module and the second charging and discharging module adjust the width of their output pulses by adjusting their internal charging and discharging speeds.

[0045] Optionally, the timing control module includes a first charging / discharging module, a second charging / discharging module, a first NOR gate NOR1, a second NOR gate NOR2, a third NOR gate NOR3, a fourth NOR gate NOR4, a fifth NOR gate NOR5, a sixth NOR gate NOR6, a seventh NOR gate NOR7, a NAND gate NAND, a first inverter INV1, and a second inverter INV2;

[0046] The input terminal of the first charging and discharging module receives the second clock signal clk2, and the output terminal outputs the first intermediate signal VA, which is connected to the first input terminal of the fourth NOR gate NOR4.

[0047] The output of the fourth NOR gate NOR4 is connected to the second input of the fifth NOR gate NOR5;

[0048] The first input of the fifth NOR gate NOR5 receives the intermediate clock signal CLKIN, the third input receives the enable signal ENN, and the output is connected to the first input of the first NOR gate NOR1.

[0049] The second input of the first NOR gate NOR1 is connected to the output of the third NOR gate NOR3. The third input receives the enable signal ENN, and the output is connected to the first input of the third NOR gate NOR3.

[0050] The second input terminal of the third NOR gate NOR3 is connected to the output terminal of the second charging module and the input terminal of the second inverter INV2;

[0051] The second inverter INV2 outputs a second control signal SK2;

[0052] The second charging and discharging module receives the clock signal clk1 at its input terminal and outputs the first control signal SK1 at its output terminal;

[0053] The first input terminal of the second NOR gate NOR2 is connected to the output terminal of the sixth NOR gate NOR6, the second input terminal is connected to the second input terminal of the first NOR gate NOR1, the third input terminal receives the enable signal ENN, and the output terminal is connected to the first input terminal of the seventh NOR gate NOR7.

[0054] The first input terminal of the sixth NOR gate NOR6 receives the intermediate clock signal CLKIN, the second input terminal is connected to the second input terminal of the fifth NOR gate NOR5, the third input terminal receives the enable signal ENN, and the output terminal is connected to the first input terminal of the first NOR gate NOR1.

[0055] The second input of the seventh NOR gate NOR7 receives the enable signal ENN, and its output is connected to the first input of the NAND gate NAND.

[0056] The second input terminal of the NAND gate receives the enable signal ENP, and the output terminal outputs the first clock signal clk1, which is connected to the input terminal of the first inverter INV1 and the input terminal of the second charge / discharge module.

[0057] The output terminal of the first inverter INV1 outputs a second clock signal clk2 and is connected to the input terminal of the first charge / discharge module.

[0058] Optionally, both the first charging / discharging module and the second charging / discharging module include:

[0059] The adjustable resistor unit includes n PMOS transistors MPP1-MPPn, whose sources are connected to the power supply voltage Vdd, whose gates receive n independent resistor configuration signals P1-Pn respectively, and whose drains are connected to the sources of the n PMOS transistors MP1-MPn respectively.

[0060] The charging switch unit includes a PMOS transistor MP0 and n PMOS transistors MP1-MPn; the source of the PMOS transistor MP0 is connected to the power supply voltage Vdd, and its gate, together with the gates of the n PMOS transistors MP1-MPn, receives a clock signal clk; the drain of the PMOS transistor MP0 is connected to one end of a resistor R0; the drains of the n PMOS transistors MP1-MPn are respectively connected to one end of n resistors R1-Rn;

[0061] A resistor network includes the resistor R0, the n resistors R1-Rn, and a common resistor R; the other end of the resistor R0 and the other end of the n resistors R1-Rn are connected to one end of the common resistor R, and the other end of the common resistor R is connected to an internal charging node VC;

[0062] The output buffer unit includes a third inverter INV3 and a fourth inverter INV4 connected in series. The input terminal of the third inverter INV3 is connected to the internal charging node VC, and its output terminal outputs an intermediate signal VB. The output terminal of the fourth inverter INV4 outputs a second intermediate signal VA.

[0063] The adjustable capacitor unit includes an NMOS transistor MN0 and n parallel capacitor branches; each of the n capacitor branches is connected in series with n capacitors C1-Cn and n NMOS switches MN1-MNn; one end of each of the n capacitors C1-Cn is connected to the internal charging node VC, and the other end is connected to the drain of the corresponding NMOS switch MN1-MNn; the sources of the n NMOS switches MN1-MNn are grounded, and their gates receive n independent capacitor configuration signals N1-Nn respectively; the gate of the NMOS transistor MN0 receives the clock signal clk, its drain is connected to the internal charging node VC, and its source is grounded;

[0064] Specifically, by setting the logic levels of the resistor configuration signals P1-Pn and the capacitor configuration signals N1-Nn, the charging speed of the internal charging node VC can be adjusted, thereby adjusting the width of the pulse signal output by the output buffer unit.

[0065] Optionally, the resistor configuration signals P1-Pn and the capacitor configuration signals N1-Nn are programmable digital control signals;

[0066] By changing the logic level combination of the resistor configuration signals P1-Pn and the logic level combination of the capacitor configuration signals N1-Nn, the equivalent resistance of the adjustable resistor unit and the equivalent load capacitance of the adjustable capacitor unit are adjusted respectively, thereby realizing the programmable control of the duration of the pre-charge phase.

[0067] An analog-to-digital converter includes a bootstrap sampling switch circuit with pre-charge, as described above.

[0068] In summary, due to the adoption of the above technical solutions, the beneficial effects of the present invention include at least the following:

[0069] By innovatively adding an independent pre-charge phase throughout the entire sampling cycle and introducing a first switch K1 and a second switch K2, the gate voltage of the sampling switch is directly and without charge loss pre-charged to the power supply voltage Vdd after the hold phase and before the tracking phase. This significantly offsets the voltage loss caused by charge sharing between the bootstrap capacitor and the gate parasitic capacitance during the subsequent bootstrap process, ultimately raising the effective gate drive voltage of the switch to a level higher than that of traditional structures. This effectively reduces the on-resistance of the sampling switch in the tracking phase and significantly improves sampling linearity and dynamic accuracy. Simultaneously, by designing a dedicated charging and discharging module containing adjustable resistors and capacitor networks to form the timing control core, precise and flexible programming of the pre-charge phase clock signal pulse width is achieved. This allows the sampling switch circuit to be easily adapted to different process nodes, sampling rates, and accuracy requirements through external configuration, greatly enhancing the applicability and design flexibility of the overall circuit. Attached Figure Description

[0070] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0071] Figure 1 The schematic diagram of the sampling switch module provided by this invention;

[0072] Figure 2 Timing diagram of the sampling switch module provided by the present invention;

[0073] Figure 3 The schematic diagram of the sampling switch module holding phase provided by the present invention;

[0074] Figure 4The sampling switch module provided by this invention maintains an equivalent principle diagram;

[0075] Figure 5 The schematic diagram of the pre-charge phase of the sampling switch module provided by the present invention;

[0076] Figure 6 The pre-charge phase equivalent schematic diagram of the sampling switch module provided by the present invention;

[0077] Figure 7 The sampling switch module tracking phase schematic diagram provided by the present invention;

[0078] Figure 8 The sampling switch module tracking equivalent principle diagram provided by the present invention;

[0079] Figure 9 The schematic diagram of the timing control module provided by this invention;

[0080] Figure 10 Timing diagram of the timing control module provided by the present invention;

[0081] Figure 11 The schematic diagram of the charging and discharging module provided by this invention;

[0082] Figure 12 The timing diagram of the charging and discharging module provided by the present invention. Detailed Implementation

[0083] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0084] In this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element. Example

[0085] As the background technology described above indicates, with the continuous evolution of integrated circuit process nodes and the continuous improvement of sampling rates, the charge-sharing effect between the gate parasitic capacitance and the bootstrap capacitance of the sampling switch has become a core bottleneck restricting further optimization of analog-to-digital converter performance. Traditional bootstrap switch structures cannot fundamentally eliminate the problems caused by this effect, such as effective gate voltage drop, increased on-resistance, and deteriorated linearity. Moreover, in pursuing high speed and high precision, they often sacrifice the design flexibility and configurability of the circuit in different application scenarios. Therefore, there is an urgent need for an innovative sampling switch technology that can suppress charge sharing, improve performance, and achieve flexible control of key timing parameters.

[0086] Therefore, this application provides a bootstrap sampling switch circuit with pre-charge, such as... Figures 1 to 8 As shown, it includes:

[0087] Sampling switch module and timing control module.

[0088] The sampling switch module is used to receive the input analog signal Vin and, under the control of the clock signal generated by the timing control module, to perform precise sampling and holding of the analog signal Vin. The timing control module is used to generate and output a multi-phase clock signal required to control the operation of the sampling switch module based on the input clock CLKIN, including a first clock signal clk1, a second clock signal clk2, a first control signal SK1, and a second control signal SK2, and can control the pulse width of the first control signal SK1 by adjusting internal parameters.

[0089] The specific circuit connection relationship of the sampling switch module is as follows: Figure 1 As shown. This module includes: sampling switch NMOS transistor M13, first switch K1, second switch K2, first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4, sampling capacitor Cs, inverter INV1, first NMOS transistor M1, second NMOS transistor M2, third NMOS transistor M3, fourth NMOS transistor M4, fifth NMOS transistor M5, sixth NMOS transistor M6, seventh PMOS transistor M7, eighth NMOS transistor M8, ninth NMOS transistor M9, tenth NMOS transistor M10, eleventh NMOS transistor M12, and twelfth PMOS transistor M14.

[0090] The gate of the sampling switch NMOS transistor M13 is connected to the second terminal of the first switch K1 and the second terminal of the second switch K2; the drain of the sampling switch NMOS transistor M13 receives the input signal Vin; the source of the sampling switch NMOS transistor M13 is connected to the upper plate of the sampling capacitor Cs; and the lower plate of the sampling capacitor Cs is grounded.

[0091] The first terminal of the first switch K1 is connected to the source of the third NMOS transistor M3, the source of the twelfth PMOS transistor M14, and the upper plate of the third capacitor C3. The first terminal of the second switch K2 is connected to the gate of the eighth NMOS transistor M8, the gate of the eleventh NMOS transistor M12, and the drain of the ninth NMOS transistor M9.

[0092] The gate of the third NMOS transistor M3 is connected to the gate of the second NMOS transistor M2 and the gate of the fourth NMOS transistor M4; the drain of the third NMOS transistor M3 and the drain of the fourth NMOS transistor M4 are connected to the power supply voltage Vdd; the source of the fourth NMOS transistor M4 is connected to the upper plate of the fourth capacitor C4; the lower plate of the fourth capacitor C4 is connected to the drain of the twelfth PMOS transistor M14 and the drain of the sixth NMOS transistor M6.

[0093] The gates of the fifth NMOS transistor M5 and the sixth NMOS transistor M6 both receive the second clock signal clk2; the sources of the fifth NMOS transistor M5 and the sixth NMOS transistor M6 are both grounded; the drain of the fifth NMOS transistor M5 is connected to the lower plate of the third capacitor C3 and the source of the eleventh NMOS transistor M12.

[0094] The gate of the first NMOS transistor M1 is connected to the source of the second NMOS transistor M2 and the upper plate of the second capacitor C2; the drain of the first NMOS transistor M1 is connected to the power supply voltage Vdd; the source of the first NMOS transistor M1 is connected to the gate of the second NMOS transistor M2 and the upper plate of the first capacitor C1; the drain of the second NMOS transistor M2 is connected to the power supply voltage Vdd; the lower plate of the first capacitor C1 receives the second clock signal clk2; the lower plate of the second capacitor C2 receives the first clock signal clk1.

[0095] The source of the seventh PMOS transistor M7 is connected to the source of the fourth NMOS transistor M4, the drain of the seventh PMOS transistor M7 is connected to the drain of the ninth NMOS transistor M9, the gate of the seventh PMOS transistor M7 is connected to the gate of the twelfth PMOS transistor M14 and the output of the inverter INV1, and the input of the inverter INV1 receives the first clock signal clk1.

[0096] The source of the eighth NMOS transistor M8 is connected to the output of the inverter INV1, and its drain is connected to the source of the eleventh NMOS transistor M12. The gate of the ninth NMOS transistor M9 is connected to the power supply voltage Vdd, and its source is connected to the drain of the tenth NMOS transistor M10; the gate of the tenth NMOS transistor M10 receives the second clock signal clk2, and its source is grounded. The drain of the eleventh NMOS transistor M12 is connected to the drain of the sampling switch NMOS transistor M13 and receives the input signal Vin.

[0097] The complete operating cycle of this sampling switch module is strictly defined by the four clock signals generated by the timing control module, and their timing relationship is as follows: Figure 2 As shown. By Figure 2 It can be seen that clk1 and clk2 are complementary clocks. Within one complete cycle, the circuit sequentially goes through the hold phase, precharge phase, and tracking phase. The hold phase is defined by the period when clk1 is low and clk2 is high, during which SK2 is high and SK1 is low. The precharge phase occurs in the latter half of the period when clk1 is low and clk2 is high, characterized by SK1 transitioning to high while SK2 transitions to low. The tracking phase is defined by the period when clk1 transitions to high and clk2 transitions to low, during which SK1 returns to low and SK2 returns to high. The high-level pulses of SK1 and SK2 do not overlap in time, ensuring clear switching of circuit states.

[0098] When the circuit is in the hold phase: the first control signal SK1 is low, the second control signal SK2 is high, the first clock signal clk1 is low, and the second clock signal clk2 is high. The first switch K1 is open, and the second switch K2 is on. The third NMOS transistor M3, the fourth NMOS transistor M4, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the ninth NMOS transistor M9, and the tenth NMOS transistor M10 are on; the seventh PMOS transistor M7, the eighth NMOS transistor M8, the eleventh NMOS transistor M12, the twelfth PMOS transistor M14, and the sampling switch M13 are off. At this time, the third capacitor C3 and the fourth capacitor C4 are connected in parallel, with their lower plates grounded and their upper plates connected to Vdd, and are charged to the power supply voltage. Meanwhile, the conducting ninth NMOS transistor M9 and tenth NMOS transistor M10 pull down the gate node voltages of the eighth NMOS transistor M8, eleventh NMOS transistor M12 and sampling switch M13 to a low level through the conducting second switch K2, ensuring that they are turned off, and the sampling capacitor Cs maintains the sampling voltage on it.

[0099] When the circuit enters the pre-charge phase: the first control signal SK1 jumps to a high level, the second control signal SK2 jumps to a low level, the first clock signal clk1 remains low, and the second clock signal clk2 remains high. The first switch K1 is turned on, and the second switch K2 is turned off. Except for the switching state, the conduction states of transistors M3-M6, M9, and M10 are the same as in the hold phase; M7, M8, M12, M13, and M14 remain off. Because the first switch K1 is turned on, the power supply Vdd forms a path through the turned-on third NMOS transistor M3 and the first switch K1, directly charging the gate parasitic capacitance of the sampling switch M13, rapidly boosting its voltage to the power supply voltage Vdd. This process is a direct charging without charge loss, isolated from the bootstrap capacitor network.

[0100] When the circuit enters the tracking phase (sampling phase): The first control signal SK1 returns to low level, the second control signal SK2 returns to high level, the first clock signal clk1 becomes high level, and the second clock signal clk2 becomes low level. The first switch K1 is open, and the second switch K2 is on. At this time, the third NMOS transistor M3, the fourth NMOS transistor M4, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the ninth NMOS transistor M9, and the tenth NMOS transistor M10 are turned off; the seventh PMOS transistor M7, the eighth NMOS transistor M8, the eleventh NMOS transistor M12, the twelfth PMOS transistor M14, and the sampling switch M13 are turned on. The third capacitor C3 and the fourth capacitor C4 change from parallel to series, forming a bootstrap capacitor network. The conduction of the twelfth PMOS transistor M14 connects this series network to the circuit, and the conduction of the seventh PMOS transistor M7 connects one end of the bootstrap capacitor network to the gate nodes of the eighth NMOS transistor M8, the eleventh NMOS transistor M12, and the sampling switch M13. Since the gate voltage of M13 has been pre-charged to Vdd during the pre-charge phase, and its gate parasitic capacitance is denoted as Cp, the bootstrap capacitor network (C3 and C4 in series) shares charge with this pre-charged gate parasitic capacitance. According to the law of charge conservation, the final voltage applied to the gate of sampling switch M13... for:

[0101]

[0102] in, The power supply voltage is... The input signal, Let M13 be the gate parasitic capacitance of the sampling switch NMOS transistor. Comparing this to the traditional bootstrap switch formula, it can be seen that the numerator contains an additional capacitance. and This is precisely the contribution of the pre-charge phase in raising the gate voltage in advance. Therefore, It is significantly superior to the traditional structure, thus effectively reducing the on-resistance of the sampling tube M13 in the tracking phase and greatly improving the sampling linearity and dynamic accuracy.

[0103] Through the above technical solution, the sampling switch circuit provided in this embodiment innovatively inserts an independent pre-charge phase between the traditional hold phase and tracking phase, and utilizes the newly added first switch K1 and second switch K2 for timing management, successfully raising the gate voltage of the sampling switch to the power supply voltage before bootstrapping. This mechanism fundamentally suppresses the gate voltage drop problem caused by charge sharing between the bootstrap capacitor and the gate parasitic capacitance, allowing the gate to obtain a higher effective drive voltage during the tracking phase, thereby reducing the on-resistance and significantly improving sampling linearity and accuracy. Simultaneously, the adjustable design of the pre-charge phase duration (i.e., the pulse width of the SK1 signal) through the timing control module provides crucial flexibility for the circuit to adapt to different speeds, processes, and application scenarios.

[0104] Example 2

[0105] This embodiment aims to provide a detailed description of the timing control module, specifically disclosing its internal circuit structure and working principle for generating adjustable clock signals, such as... Figures 9 to 12 As shown.

[0106] The timing control module includes a logic control unit and two charge / discharge modules (i.e., the first charge / discharge module and the second charge / discharge module).

[0107] The specific structure and connection relationship of the logic control unit are as follows: Figure 9 As shown, the circuit includes a first NOR gate (NOR1), a second NOR gate (NOR2), a third NOR gate (NOR3), a fourth NOR gate (NOR4), a fifth NOR gate (NOR5), a sixth NOR gate (NOR6), a seventh NOR gate (NOR7), a NAND gate (NAND), a first inverter (INV1), and a second inverter (INV2). The connections and signal paths of each part are as follows:

[0108] The input terminal of the first charging / discharging module receives the second clock signal clk2, and its output terminal outputs the first intermediate signal VA. This VA signal is input to the first input terminal of the fourth NOR gate NOR4.

[0109] The output of the fourth NOR gate NOR4 is connected to the second input of the fifth NOR gate NOR5.

[0110] The first input terminal of the fifth NOR gate NOR5 receives the input clock signal CLKIN, its third input terminal receives the enable signal ENN, and its output terminal is connected to the first input terminal of the first NOR gate NOR1.

[0111] The second input of the first NOR gate NOR1 is connected to the output of the third NOR gate NOR3, the third input of which receives the enable signal ENN, and the output of which is connected to the first input of the third NOR gate NOR3.

[0112] The input terminal of the second charging and discharging module receives the first clock signal clk1, and its output terminal outputs the first control signal SK1.

[0113] The second input terminal of the third NOR gate NOR3 is connected to the output terminal of the second charge / discharge module (i.e., the node that outputs SK1), and is also connected to the input terminal of the second inverter INV2.

[0114] The output terminal of the second inverter INV2 outputs the second control signal SK2.

[0115] The first input of the second NOR gate NOR2 is connected to the output of the sixth NOR gate NOR6, its second input is connected to the second input of the first NOR gate NOR1, its third input receives the enable signal ENN, and its output is connected to the first input of the seventh NOR gate NOR7.

[0116] The first input terminal of the sixth NOR gate NOR6 receives the input clock signal CLKIN, its second input terminal is connected to the second input terminal of the fifth NOR gate NOR5, its third input terminal receives the enable signal ENN, and its output terminal is connected to the first input terminal of the first NOR gate NOR1.

[0117] The second input of the seventh NOR gate NOR7 receives the enable signal ENN, and its output is connected to the first input of the NAND gate NAND.

[0118] The second input of the NAND gate receives an enable signal ENP, and its output outputs the first clock signal clk1. This clk1 signal is connected in two ways: one to the input of the first inverter INV1, and the other to the input of the second charge / discharge module.

[0119] The output of the first inverter INV1 outputs the second clock signal clk2, which is connected to the input of the first charge / discharge module.

[0120] The aforementioned logic control unit works in conjunction with the two charging and discharging modules, and their detailed timing relationship is as follows: Figure 10 As shown. Combined with Figure 10 The working principle of the timing control module is explained as follows:

[0121] Enable and Reset: When the first enable signal ENP is high and the second enable signal ENN is low, the module exits the reset state and begins operation. The input clock signal CLKIN serves as the system master clock.

[0122] Complex clock generation: CLKIN is processed by the logic control unit (specifically, the NAND gate network, NOR gate network, and the first inverter INV1), and does not generate a simple in-phase or out-of-phase clock. For example... Figure 10 As shown, within one CLKIN cycle, the waveform of the first clock signal clk1 is as follows: while CLKIN is high, clk1 is low; after CLKIN transitions to low, clk1 maintains a low level for a period, then generates a positive pulse (high level), and then returns to low until the next rising edge of CLKIN arrives. The waveform of the second clock signal clk2 is largely complementary to clk1, with its high-level pulse appearing during the low-level phase of clk1.

[0123] The triggering of the charge / discharge module and the formation of the SK1 pulse width:

[0124] clk2 serves as the clock input for the first charging and discharging module, controlling it to generate the first intermediate signal VA, which participates in the internal logic feedback.

[0125] clk1 serves as the clock input for the second charge / discharge module, controlling it to generate the first control signal SK1.

[0126] Combination Figure 10 The detailed formation process of the second charging / discharging module and the SK1 signal is as follows:

[0127] Initial and tracking phase: When clk1 is high (i.e., tracking phase), the second charge and discharge module discharges internally, and its output SK1 is a stable low level.

[0128] The start of the pre-charge phase and pulse width control: The charging process of the second charge / discharge module begins after the high-level pulse of clk1 ends and transitions to a low level. After an adjustable delay Td determined by the module's internal RC parameters, its output SK1 transitions from a low level to a high level. This period of high-level SK1 corresponds to the pre-charge phase of the sampling switch module.

[0129] End of precharge phase: The end of the SK1 high-level pulse (falling edge) is triggered by the next rising edge of clk1 (or the internal state of the logic cell).

[0130] Therefore, the width of the SK1 high-level pulse (i.e., the duration of the pre-charge phase) is directly equal to the adjustable delay Td. By configuring the resistor configuration signal (P1-Pn) and capacitor configuration signal (N1-Nn) inside the second charge / discharge module, its RC time constant can be changed, thereby directly adjusting the delay Td and achieving precise programmable control over the duration of the pre-charge phase.

[0131] Coordination of control signals:

[0132] The SK1 signal is directly output to the sampling switch module to control switch K1.

[0133] The SK2 signal is obtained by processing the signal from the logic control unit using the second inverter INV2. It exhibits a strictly complementary (non-overlapping) relationship with the SK1 signal. Figure 10 The complete timing cycle shows that the high-level pulse of SK2 occurs in two phases: the first phase occurs when clk1 is low, clk2 is high, and SK1 is low, corresponding to the hold phase of the sampling switch module; the second phase occurs when clk1 is high, clk2 is low, and SK1 is low, corresponding to the tracking phase (sampling phase) of the sampling switch module. When SK2 is low, it corresponds to the pre-charge phase when SK1 is high. This design strictly ensures that switches K1 and K2 will not be turned on simultaneously, guaranteeing safe switching of circuit states.

[0134] The VA signal output by the first charge / discharge module is fed back to the logic control unit (NOR4) to participate in maintaining the internal logic state and ensure the stability of the timing cycle.

[0135] Complete timing output: Finally, the timing control module synchronously outputs clk1, clk2, SK1, and SK2, which strictly meet the following requirements. Figure 10 The timing control signals drive the sampling switch module to operate correctly and reliably in the hold phase, precharge phase, and tracking phase in sequence.

[0136] The first and second charge / discharge modules are the core units for realizing the adjustable pulse width function, and their internal structures are as follows: Figure 11 As shown. Each charge / discharge module includes:

[0137] Adjustable resistor unit: consists of n PMOS transistors MPP1-MPPn. Their sources are connected to the power supply voltage Vdd, their gates receive independent resistor configuration signals P1-Pn, and their drains are connected to the sources of the n PMOS transistors MP1-MPPn respectively.

[0138] The charging switch unit includes one PMOS transistor MP0 and n PMOS transistors MP1-MPPn. The source of MP0 is connected to Vdd, and the gates of MP0 and MP1-MPPn share the clock signal clk (the first module is connected to clk2, and the second module is connected to clk1). The drain of MP0 is connected to one end of resistor R0; the drains of MP1-MPPn are respectively connected to one end of resistors R1 to Rn.

[0139] Resistor network: includes resistors R0, R1 to Rn and a common resistor R. The other end of R0 and the other ends of R1 to Rn are connected to one end of the common resistor R, and the other end of the common resistor R is connected to the internal charging node VC.

[0140] Output buffer unit: includes a third inverter INV3 and a fourth inverter INV4 connected in series. The input of the third inverter INV3 is connected to the internal charging node VC, and its output outputs the intermediate signal VB. The output of the fourth inverter INV4 outputs the second intermediate signal VA (i.e., the final output pulse signal of this module).

[0141] Adjustable capacitor unit: Includes one NMOS transistor MN0 and n parallel capacitor branches. Each of the n capacitor branches is connected in series with capacitors C1-Cn and NMOS switches MN1-MNn. One end of capacitors C1-Cn is connected to the internal charging node VC, and the other end is connected to the drain of the corresponding NMOS switches MN1-MNn. The sources of NMOS switches MN1-MNn are grounded, and their gates receive independent capacitor configuration signals N1-Nn. The gate of NMOS transistor MN0 receives the clock signal clk, its drain is connected to the internal charging node VC, and its source is grounded.

[0142] The working principle of the charging and discharging module combined with Figure 12 The timing diagram is explained as follows: When clk is high, MN0 is turned on, the VC node is discharged to low, and the output is low. When clk goes low, MN0 is turned off, MP0-MPn are turned on, and the power supply charges the load capacitor connected in the adjustable capacitor unit through the adjustable resistor unit and resistor network, causing the VC voltage to rise. When the VC voltage reaches the toggling threshold of INV3, the output pulse jumps to high. By changing the equivalent RC constant through the configuration signals P1-Pn and N1-Nn, the charging speed of VC can be adjusted, thereby controlling the width of the output pulse (e.g., ...). Figure 12 (W1 and W2 in the diagram). Since the output of the second charge / discharge module is SK1, this mechanism enables programmable control of the pre-charge phase time.

[0143] Example 3:

[0144] This embodiment aims to illustrate the application of the aforementioned bootstrap sampling switch circuit with pre-charge in a practical electronic system, specifically disclosing that it serves as a core component to form a high-performance analog-to-digital converter (ADC).

[0145] like Figure 1 As shown, the sampling switch circuit constitutes the key analog front-end of the analog-to-digital converter—the sample-and-hold circuit. In a typical successive approximation SAR ADC or pipelined ADC architecture, this sampling switch circuit is applied as follows:

[0146] The analog-to-digital converter includes core components such as the sampling switch module, the timing control module, the comparator, the digital logic control circuit, and the digital-to-analog converter (DAC) (not all are shown in the figure).

[0147] Integration of the sampling switch module: The input terminal of the sampling switch module receives the analog input signal Vin to be digitized. The upper plate of its sampling capacitor Cs serves as the output node of the sample-and-hold circuit, connected to subsequent circuits, such as the input terminal of a comparator or a shared sampling node.

[0148] Integration of the timing control module: The timing control module is part of the ADC clock generation system, and its input clock CLKIN can be provided by the ADC's global clock. Its enable signals ENP and ENN can be configured by the ADC's digital control logic according to the conversion cycle.

[0149] Workflow:

[0150] Sampling Phase: At the start of a conversion cycle, the ADC control logic enables the timing control module. The timing control module then generates the three-phase control timing sequence (clk1,clk2,SK1,SK2) as described in Example 1, driving the sampling switch module to operate.

[0151] Tracking and Sampling: In the tracking phase, the sampling switch M13 tracks Vin with high linearity and stores the signal charge on the sampling capacitor Cs.

[0152] Hold and Conversion: After entering the hold phase, the voltage on Cs is held and transmitted to the subsequent quantization circuit (such as a comparator array) of the ADC for digitization processing. Simultaneously, the timing control module and the sampling switch module prepare for the next sampling.

[0153] Application advantages:

[0154] By employing a bootstrap sampling switch circuit with pre-charge as described in Embodiments 1 and 2, the analog-to-digital converter constructed in this embodiment achieves significant performance improvements and design flexibility:

[0155] High precision and high linearity: Thanks to the pre-charge phase effectively suppressing the charge-sharing effect, the sampling switch exhibits lower on-resistance and higher linearity in the tracking phase. This directly translates to lower distortion, higher signal-to-noise ratio (SNR), and spurious-free dynamic range (SFDR) for the ADC, which is particularly beneficial for high-speed and high-precision conversion.

[0156] Programmable sampling timing: The resistor configuration signals (P1-Pn) and capacitor configuration signals (N1-Nn) in the timing control module can be programmed via an external configuration interface (such as SPI, I2C, or a dedicated configuration register), allowing dynamic adjustment of the pre-charge phase duration. This enables the same ADC chip to be optimized for different input signal frequencies, process angle variations, or specific system power consumption and speed requirements, greatly enhancing the system's adaptability and robustness.

[0157] Easy to integrate: The circuit has a clear structure and its timing control is self-contained, making it easy to integrate as a standard IP module into various ADC architectures.

[0158] In summary, this embodiment successfully applies the innovative sampling switch circuit to analog-to-digital converter products, which not only solves the key problem of limited sampling linearity in traditional ADCs, but also endows the ADC with programmable sampling timing characteristics, thereby realizing a higher performance and more flexible high-precision data conversion system.

[0159] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0160] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

[0161] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A bootstrap sampling switch circuit with pre-charge, characterized in that, Includes a sampling switch module and a timing control module; The sampling switch module is configured to operate sequentially in the hold phase, precharge phase, and tracking phase under the control of multiple clock signals generated by the timing control module; The sampling switch module includes: a sampling switch NMOS transistor M13, a first switch K1, a second switch K2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a sampling capacitor Cs, an inverter INV1, a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh PMOS transistor M7, an eighth NMOS transistor M8, a ninth NMOS transistor M9, a tenth NMOS transistor M10, an eleventh NMOS transistor M12, and a twelfth PMOS transistor M14; The gate of the sampling switch NMOS transistor M13 is connected to the second terminal of the first switch K1 and the second terminal of the second switch K2; the drain of the sampling switch NMOS transistor M13 receives the input signal Vin; the source of the sampling switch NMOS transistor M13 is connected to the upper plate of the sampling capacitor Cs; the lower plate of the sampling capacitor Cs is grounded. The first terminal of the first switch K1 is connected to the source of the third NMOS transistor M3, the source of the twelfth PMOS transistor M14, and the upper plate of the third capacitor C3. The first terminal of the second switch K2 is connected to the gate of the eighth NMOS transistor M8, the drain of the seventh PMOS transistor M7, the gate of the eleventh NMOS transistor M12, and the drain of the ninth NMOS transistor M9. The gate of the third NMOS transistor M3 is connected to the gate of the second NMOS transistor M2 and the gate of the fourth NMOS transistor M4; the drain of the third NMOS transistor M3 and the drain of the fourth NMOS transistor M4 are connected to the power supply voltage Vdd; the source of the fourth NMOS transistor M4 is connected to the upper plate of the fourth capacitor C4; the lower plate of the fourth capacitor C4 is connected to the drain of the twelfth PMOS transistor M14 and the drain of the sixth NMOS transistor M6; The gates of the fifth NMOS transistor M5 and the sixth NMOS transistor M6 both receive the second clock signal clk2; the sources of the fifth NMOS transistor M5 and the sixth NMOS transistor M6 are both grounded; the drain of the fifth NMOS transistor M5 is connected to the lower plate of the third capacitor C3 and the source of the eleventh NMOS transistor M12. The gate of the first NMOS transistor M1 is connected to the source of the second NMOS transistor M2 and the upper plate of the second capacitor C2; the drain of the first NMOS transistor M1 is connected to the power supply voltage Vdd; the source of the first NMOS transistor M1 is connected to the gate of the second NMOS transistor M2 and the upper plate of the first capacitor C1; the drain of the second NMOS transistor M2 is connected to the power supply voltage Vdd; the lower plate of the first capacitor C1 receives the second clock signal clk2; the lower plate of the second capacitor C2 receives the first clock signal clk1. The source of the seventh PMOS transistor M7 is connected to the source of the fourth NMOS transistor M4, the drain of the seventh PMOS transistor M7 is connected to the drain of the ninth NMOS transistor M9, the gate of the seventh PMOS transistor M7 is connected to the gate of the twelfth PMOS transistor M14 and the output of the inverter INV1, and the input of the inverter INV1 receives the first clock signal clk1. The source of the eighth NMOS transistor M8 is connected to the output terminal of the inverter INV1, and its drain is connected to the source of the eleventh NMOS transistor M12. The gate of the ninth NMOS transistor M9 is connected to the power supply voltage Vdd, and its source is connected to the drain of the tenth NMOS transistor M10; the gate of the tenth NMOS transistor M10 receives the second clock signal clk2, and its source is grounded. The drain of the eleventh NMOS transistor M12 is connected to the drain of the sampling switch NMOS transistor M13 and receives the input signal Vin; The timing control module is configured to generate the plurality of clock signals, including a first clock signal clk1, a second clock signal clk2, a first control signal SK1 for controlling the first switch K1 to be turned on or off, and a second control signal SK2 for controlling the second switch K2 to be turned on or off.

2. The bootstrap sampling switch circuit with pre-charge according to claim 1, characterized in that, In the pre-charge phase: When the first control signal SK1 is high, it controls the first switch K1 to be turned on in order to establish a pre-charging path; When the second control signal SK2 is low, the second switch K2 is turned off, which isolates the gate of the sampling switch NMOS transistor M13 from the gate nodes of the eighth NMOS transistor M8 and the eleventh NMOS transistor M12, thus turning off the sampling switch NMOS transistor M13, the eighth NMOS transistor M8 and the eleventh NMOS transistor M12. The first clock signal clk1 is low level. After being inverted by the inverter INV1, it outputs a high level, which turns off the seventh PMOS transistor M7 and the twelfth PMOS transistor M14. When the second clock signal clk2 is high, the third NMOS transistor M3, the fourth NMOS transistor M4, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the ninth NMOS transistor M9, and the tenth NMOS transistor M10 are turned on.

3. The bootstrap sampling switch circuit with pre-charge according to claim 1, characterized in that, In the tracking phase: When the first control signal SK1 is low, the first switch K1 is turned off. When the second control signal SK2 is high, it controls the second switch K2 to be turned on; When the second clock signal clk2 is low, the third NMOS transistor M3, the fourth NMOS transistor M4, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the ninth NMOS transistor M9, and the tenth NMOS transistor M10 are turned off. The first clock signal clk1 is high level. After being inverted by the inverter INV1, it outputs a low level, which turns on the twelfth PMOS transistor M14 and the seventh PMOS transistor M7. The seventh PMOS transistor M7, which is turned on, connects the source of the fourth NMOS transistor M4 to the gate of the eighth NMOS transistor M8, thereby turning on the eighth NMOS transistor M8, the eleventh NMOS transistor M12, and the sampling switch NMOS transistor M13.

4. The bootstrap sampling switch circuit with pre-charge according to claim 1, characterized in that, In the holding phase: When the first control signal SK1 is low, the first switch K1 is turned off. When the second control signal SK2 is high, it controls the second switch K2 to be turned on; The first clock signal clk1 is low level. After being inverted by the inverter INV1, it outputs a high level, which turns off the seventh PMOS transistor M7 and the twelfth PMOS transistor M14. When the second clock signal clk2 is high, the third NMOS transistor M3, the fourth NMOS transistor M4, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the ninth NMOS transistor M9, and the tenth NMOS transistor M10 are turned on. Specifically, the conducting ninth NMOS transistor M9 and tenth NMOS transistor M10 pull down the gate nodes of the eighth NMOS transistor M8, the eleventh NMOS transistor M12, and the sampling switch NMOS transistor M13 to a low level, thereby turning off the sampling switch NMOS transistor M13, the eighth NMOS transistor M8, and the eleventh NMOS transistor M12.

5. The bootstrap sampling switch circuit with pre-charge according to claim 3, characterized in that, In the tracking phase, the gate voltage of the sampling switch NMOS transistor M13 The following relationship must be satisfied: in, This is the power supply voltage. For input signal, This refers to the gate parasitic capacitance of the sampling switch NMOS transistor M13.

6. The bootstrap sampling switch circuit with pre-charge according to claim 1, characterized in that, The timing control module includes: The logic control unit, including multiple NOR gates, NAND gates and inverters, is used to receive input clock signals and enable signals, and generate intermediate control signals. First charge / discharge module and second charge / discharge module; The logic control unit generates the first clock signal clk1 and the second clock signal clk2; the input terminal of the first charging and discharging module receives the second clock signal clk2, and the input terminal of the second charging and discharging module receives the first clock signal clk1; the first charging and discharging module and the second charging and discharging module adjust the width of their output pulses by adjusting their internal charging and discharging speeds.

7. The bootstrap sampling switch circuit with pre-charge according to claim 6, characterized in that, The timing control module includes a first charging / discharging module, a second charging / discharging module, a first NOR gate (NOR1), a second NOR gate (NOR2), a third NOR gate (NOR3), a fourth NOR gate (NOR4), a fifth NOR gate (NOR5), a sixth NOR gate (NOR6), a seventh NOR gate (NOR7), a NAND gate (NAND), a first inverter (INV1), and a second inverter (INV2). The input terminal of the first charging and discharging module receives the second clock signal clk2, and the output terminal outputs the first intermediate signal VA, which is connected to the first input terminal of the fourth NOR gate NOR4. The output of the fourth NOR gate NOR4 is connected to the second input of the fifth NOR gate NOR5; The first input of the fifth NOR gate NOR5 receives the intermediate clock signal CLKIN, the third input receives the enable signal ENN, and the output is connected to the first input of the first NOR gate NOR1. The second input of the first NOR gate NOR1 is connected to the output of the third NOR gate NOR3. The third input receives the enable signal ENN, and the output is connected to the first input of the third NOR gate NOR3. The second input terminal of the third NOR gate NOR3 is connected to the output terminal of the second charging module and the input terminal of the second inverter INV2; The second inverter INV2 outputs a second control signal SK2; The second charging and discharging module receives the clock signal clk1 at its input terminal and outputs the first control signal SK1 at its output terminal; The first input terminal of the second NOR gate NOR2 is connected to the output terminal of the sixth NOR gate NOR6, the second input terminal is connected to the second input terminal of the first NOR gate NOR1, the third input terminal receives the enable signal ENN, and the output terminal is connected to the first input terminal of the seventh NOR gate NOR7. The first input terminal of the sixth NOR gate NOR6 receives the intermediate clock signal CLKIN, the second input terminal is connected to the second input terminal of the fifth NOR gate NOR5, the third input terminal receives the enable signal ENN, and the output terminal is connected to the first input terminal of the first NOR gate NOR1. The second input of the seventh NOR gate NOR7 receives the enable signal ENN, and its output is connected to the first input of the NAND gate NAND. The second input terminal of the NAND gate receives the enable signal ENP, and the output terminal outputs the first clock signal clk1, which is connected to the input terminal of the first inverter INV1 and the input terminal of the second charging and discharging module. The output terminal of the first inverter INV1 outputs a second clock signal clk2 and is connected to the input terminal of the first charge / discharge module.

8. The bootstrap sampling switch circuit with pre-charge according to claim 7, characterized in that, Both the first charging / discharging module and the second charging / discharging module include: The adjustable resistor unit includes n PMOS transistors MPP1-MPPn, whose sources are connected to the power supply voltage Vdd, whose gates receive n independent resistor configuration signals P1-Pn respectively, and whose drains are connected to the sources of the n PMOS transistors MP1-MPn respectively. The charging switch unit includes a PMOS transistor MP0 and n PMOS transistors MP1-MPn; the source of the PMOS transistor MP0 is connected to the power supply voltage Vdd, and its gate, together with the gates of the n PMOS transistors MP1-MPn, receives a clock signal clk; the drain of the PMOS transistor MP0 is connected to one end of a resistor R0; the drains of the n PMOS transistors MP1-MPn are respectively connected to one end of n resistors R1-Rn; A resistor network includes the resistor R0, the n resistors R1-Rn, and a common resistor R; the other end of the resistor R0 and the other end of the n resistors R1-Rn are connected to one end of the common resistor R, and the other end of the common resistor R is connected to an internal charging node VC; The output buffer unit includes a third inverter INV3 and a fourth inverter INV4 connected in series. The input terminal of the third inverter INV3 is connected to the internal charging node VC, and its output terminal outputs an intermediate signal VB. The output terminal of the fourth inverter INV4 outputs a second intermediate signal VA. The adjustable capacitor unit includes an NMOS transistor MN0 and n parallel capacitor branches; each of the n capacitor branches is connected in series with n capacitors C1-Cn and n NMOS switches MN1-MNn; one end of each of the n capacitors C1-Cn is connected to the internal charging node VC, and the other end is connected to the drain of the corresponding NMOS switch MN1-MNn; the sources of the n NMOS switches MN1-MNn are grounded, and their gates receive n independent capacitor configuration signals N1-Nn respectively; the gate of the NMOS transistor MN0 receives the clock signal clk, its drain is connected to the internal charging node VC, and its source is grounded; Specifically, by setting the logic levels of the resistor configuration signals P1-Pn and the capacitor configuration signals N1-Nn, the charging speed of the internal charging node VC can be adjusted, thereby adjusting the width of the pulse signal output by the output buffer unit.

9. The bootstrap sampling switch circuit with pre-charge according to claim 8, characterized in that, The resistor configuration signals P1-Pn and the capacitor configuration signals N1-Nn are programmable digital control signals; By changing the logic level combination of the resistor configuration signals P1-Pn and the logic level combination of the capacitor configuration signals N1-Nn, the equivalent resistance of the adjustable resistor unit and the equivalent load capacitance of the adjustable capacitor unit are adjusted respectively, thereby realizing the programmable control of the duration of the pre-charge phase.

10. An analog-to-digital converter, characterized in that, Includes a bootstrap sampling switch circuit with pre-charge as described in any one of claims 1 to 9.

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