Parameterization Reed-Solomon code unified decoding method and device and medium
By employing a recombination-inverseless algorithm and parameterized design in the Reed-Solomon decoder, the Galois field inversion operation is simplified, solving the problem of high resource consumption in existing decoders, achieving high efficiency and flexibility of the decoder, and reducing hardware costs.
Patent Information
- Application Number
- CN202511569347.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-30
- Publication Date
- 2026-02-03
AI Technical Summary
Existing configurable Reed-Solomon decoders, due to the need for complex Galois domain inversion operations in high-speed communication chip design, result in large circuit size and high resource consumption, becoming a bottleneck for performance and cost.
A recombined inverseless algorithm is adopted, and the solution steps of key equations are simplified through parameterized design to avoid Galois inversion operations. Furthermore, a parameterizable Reed-Solomon code unified decoding device is generated using hardware description language code, which supports decoding of multiple code types.
It significantly simplifies the hardware implementation logic, reduces circuit size and resource consumption, improves the reusability and flexibility of the decoder, and reduces the workload of development and verification.
Smart Images
Figure CN121462003A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of digital communication and data storage technology, and more specifically, to a parameterizable Reed-Solomon code unified decoding method, apparatus, and medium. Background Technology
[0002] Reed-Solomon codes, as an important forward error correction code, are widely used in digital communication and data storage to ensure the integrity of data transmission. For example, Reed-Solomon forward error correction technology plays a key role in Ethernet standards of 400Gb / s and higher speeds.
[0003] To improve the reusability and flexibility of hardware design to adapt to different communication standards or application scenarios, configurable Reed-Solomon decoders have emerged in the prior art. These decoders can handle various Reed-Solomon codes with different code lengths, information lengths, or check lengths by setting parameters, and can support the decoding of truncated codes by setting offset parameters.
[0004] However, existing configurable decoders still have shortcomings in implementation. Their core processing units, especially the modules used to solve key equations, typically employ traditional algorithms such as the Berlekamp-Massey algorithm. These algorithms require complex Galois inversion operations in certain iterative steps. In the design of high-speed communication chips, which are extremely sensitive to performance and resources, implementing Galois inversion operations requires complex hardware logic circuits. This results in a large circuit size and high resource consumption for the entire decoder, becoming a bottleneck restricting the decoder's performance and cost-effectiveness. Summary of the Invention
[0005] To address the shortcomings of existing technologies, the purpose of this invention is to provide a parameterizable Reed-Solomon code unified decoding method, apparatus, and medium.
[0006] According to the present invention, a parameterizable unified decoding method for Reed-Solomon codes is provided. The method is used to decode any selected Reed-Solomon code from a plurality of Reed-Solomon codes based on the same Galois field. The method includes: At least one processing step in the decoding method is configured according to a first code pattern parameter that characterizes the number of check symbols of the selected Reed-Solomon code; When the selected Reed-Solomon code is a truncated code, at least one processing step in the decoding method is configured according to the second code pattern parameter used to characterize the codeword truncation offset characteristics of the truncated code. The processing steps in the decoding method include: Perform the adjoint calculation to obtain the adjoint components; The inverseless algorithm of recombination is used to process the adjoint components in order to solve for the error position polynomial and the error value polynomial. Perform error location analysis to obtain the error location; Perform error value calculation to obtain the error value; Error correction is performed based on the error location and the error value.
[0007] Preferably, configuring at least one processing step in the decoding method according to the first code pattern parameter includes: The syndic calculation steps are configured according to the first code pattern parameters to calculate the syndic component corresponding to the number of check symbols.
[0008] Preferably, the first code pattern parameter is the number of check symbols in the selected Reed-Solomon code.
[0009] Preferably, configuring at least one processing step in the decoding method according to the second code pattern parameters includes: The error location locating step and the error value calculation step are configured according to the second code pattern parameters.
[0010] Preferably, the second code pattern parameter is the codeword truncation offset of the truncated code.
[0011] According to the present invention, a parameterizable Reed-Solomon code unified decoding apparatus is provided, the apparatus being used to decode any selected Reed-Solomon code from a plurality of Reed-Solomon codes based on the same Galois field, the apparatus comprising: The unit includes a computational unit, a key equation solving unit, an error location unit, an error value calculation unit, and an error correction unit. The key equation solving unit is used to process the output of the adjoint calculation unit using a recombined inverse-free algorithm to solve for the error position polynomial and the error value polynomial. The device is also configured to: At least one unit in the apparatus is configured according to a first code pattern parameter that characterizes the number of check symbols of the selected Reed-Solomon code; When the selected Reed-Solomon code is a truncated code, at least one unit in the device is configured according to a second code pattern parameter used to characterize the codeword truncation offset characteristics of the truncated code.
[0012] Preferably, the device is configured as follows: Configure the syntactic calculation unit according to the first code pattern parameters; and The error location unit and the error value calculation unit are configured according to the second code pattern parameters.
[0013] Preferably, at least one of the adjoint calculation unit, the key equation solving unit, the error location unit, or the error value calculation unit includes a lookup table for performing Galois field multiplication or inversion operations.
[0014] Preferably, the apparatus is defined by hardware description language code, which includes a generate loop structure for instantiating the at least one unit based on the first code pattern parameter and / or the second code pattern parameter.
[0015] According to the present invention, a computer-readable storage medium is provided thereon storing hardware description language code, which, when synthesized and implemented, is used to generate the parameterizable Reed-Solomon code unified decoding method.
[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention avoids complex Galois inversion operations by employing a recombined inverseless algorithm in the key equation solving step. Compared with traditional algorithms such as Berlekamp-Massey, this invention significantly simplifies the hardware implementation logic and reduces circuit size and resource consumption.
[0017] 2. Based on the characteristic that multiple Reed-Solomon codes share the same Galois field, this invention achieves high reusability of the decoder through parameterized design. A single hardware description language code can support multiple code types, greatly reducing the workload of code development and verification, and making the code easier to maintain and extend.
[0018] 3. The solution of this invention has strong versatility and can be extended to the unified decoding implementation of other Reed-Solomon full codes or truncated codes. Attached Figure Description
[0019] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A schematic diagram of the system architecture of the parameterizable Reed-Solomon code unified decoding device provided in an embodiment of the present invention; Figure 2 A flowchart of a parameterizable Reed-Solomon code unified decoding method provided in an embodiment of the present invention; Figure 3 This is a pseudocode diagram of the Recombination Inverseless Algorithm (RiBM) used for solving key equations in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the implementation of parameterized hardware generation using the generate statement of a hardware description language in an embodiment of the present invention. Figure 5 This is a schematic diagram illustrating the implementation of truncation code processing using a hardware description language in an embodiment of the present invention; Figure 6 This is a schematic diagram illustrating the calculation of the foney w(x) function in an embodiment of the present invention; Figure 7 This is a schematic diagram of the inversion of odd and the output of foney in an embodiment of the present invention; Figure 8 This is a schematic diagram illustrating the parallel coding principle in an embodiment of the present invention; Figure 9 This is a schematic diagram of the functional model of the Reed-Solomon encoder in an embodiment of the present invention; Figure 10 This is a schematic diagram of the A8 matrix in an embodiment of the present invention; Figure 11 This is a diagram showing the parallelism coding calculation in an embodiment of the present invention.
[0020] Explanation of reference numerals in the attached figures: Detailed Implementation
[0021] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.
[0022] Example 1 This embodiment provides a parameterizable Reed-Solomon code unified decoding method and apparatus. Specifically, this embodiment aims to perform efficient and low-complexity decoding of the RS(544, 514) code commonly used in high-speed Ethernet standards. It can be understood that this code type is defined over the Galois domain GF(2^10), and its primitive polynomial is... As a truncated code, the RS(544, 514) code is derived from a truncated master code of length 1023, containing 514 information symbols and 30 check symbols, with a total code length of 544. The following section will detail how to utilize a unified decoding architecture and configure specific code type parameters to complete the full decoding process for this code type.
[0023] Please see Figure 1This illustrates the system architecture of the parameterizable Reed-Solomon code unified decoding device provided in an embodiment of the present invention. In physical implementation, the device can be a dedicated integrated circuit or a logic circuit implemented on a field-programmable gate array (FPGA). The device as a whole constitutes a pipelined processing system, including a parameter configuration interface 10 for receiving external configuration information, and an adjoint computation unit 20, a key equation solving unit 30, an error location unit 40, an error value calculation unit 50, and an error correction unit 60 connected sequentially along the data processing path.
[0024] The parameter configuration interface 10 is the key entry point for realizing the parameterizable characteristics of the present invention. It is used to receive and latch at least two code pattern parameters: a first code pattern parameter characterizing the number of selected Reed-Solomon code parity symbols, and a second code pattern parameter characterizing the truncation offset characteristics of the truncated codeword. In this embodiment, for the RS(544, 514) code, the first code pattern parameter set through the parameter configuration interface 10 is 30, which directly corresponds to its 30 parity symbols; the second code pattern parameter is set to 479, which represents the truncation offset of the codeword, calculated as the length of the parent code minus the length of the truncated codeword, i.e., 1023 - 544 = 479. These parameters will be transmitted to the corresponding processing units inside the device to control its computational scale and logical behavior.
[0025] The following will combine Figure 1 Device architecture and Figure 2 The flowchart shown describes the complete decoding process of an RS(544, 514) codeword.
[0026] The process begins at step S101, where the decoding device receives a codeword to be decoded containing 544 symbols (typically represented as the receive polynomial R(x)). Simultaneously, the device receives and determines the current code pattern parameters to be processed via the parameter configuration interface 10, namely, the first code pattern parameter (number of parity symbols) is 30, and the second code pattern parameter (codeword truncation offset) is 479.
[0027] Accordingly, in step S102, the device configures the internal decoding processing unit using the acquired code pattern parameters. Specifically, the first code pattern parameter (value 30) will be mainly used to configure the syntactic calculation unit 20, while the second code pattern parameter (value 479) will be used to configure the error location unit 40 and the error value calculation unit 50.
[0028] Subsequently, in step S103, the syndrome calculation is performed. The syndrome calculation unit 20 receives the codeword data stream, and its core task is to calculate the syndrome components, which is the basis for determining whether the received codeword contains errors and for subsequently solving for the error location and error value. The coefficients of the syndrome polynomial S(x) By receiving specific elements of the polynomial R(x) in the Galois field The value is obtained by seeking it, that is ,in It is a primitive element of the Galois field. For an RS code that can correct t errors, 2t syndrome components need to be computed. , ..., In this embodiment, the number of check symbols in the RS(544, 514) code is 30, therefore the maximum value of t is 15. The syntactic calculation unit 20 determines the calculation required based on the first code pattern parameter (value 30) obtained from the parameter configuration interface 10. to There are a total of 30 adjoint components. This unit typically contains multiple parallel computations efficiently performed using Horner's rule. The computational circuitry, through parameterized configuration, can accurately calculate the number of syntactic components that match the current code pattern verification capability, thereby avoiding unnecessary computational overhead.
[0029] In one specific implementation, a specific parametric calculation method for RS(544, 514) and RS(528, 514) is disclosed: Let the adjoint polynomial be:
[0030] x= , ,..., Substituting these values yields 30 adjoint components. For example, substituting i=0~29 gives:
[0031] Based on the derivation of 8 times parallelism,
[0032] The code implementation controls whether to perform RS(544, 514) or RS(528, 514) syndromes via the PARITY_NUM parameter. For example, to calculate the RS(544, 514) syndrome, PARITY_NUM is set to 544-514=30. ,..., Substituting 30 roots into the equation yields 30 adjoint components. These are obtained by looking up a table. Please see Figure 4 .
[0033] After completing the adjoint calculation, the process proceeds to step S104, where the key equation is solved. The key equation solving unit 30 receives 30 adjoint components from the adjoint calculation unit 20. to As input. A core technical feature of this embodiment is that the unit uses a recombined inverse-free algorithm to solve the key equations. Its solution is the polynomial at the wrong position. and error value polynomial It should be noted that the traditional BM algorithm requires Galois field inversion during the iteration process, which is very complex and resource-intensive in hardware implementation. The recombined inverse-free algorithm, however, introduces additional auxiliary polynomials and variables to transform the inversion operation into a series of multiplication and addition operations, thus avoiding the inversion operation. Figure 3 The pseudocode diagram of the recombined inverseless algorithm is shown. The algorithm iterates through 2t (30 in this embodiment) steps, gradually correcting the polynomial coefficients, and finally outputs the polynomial at the erroneous position. and error value polynomial The coefficients. The use of a recombinant inverseless algorithm significantly reduces the hardware implementation complexity of the critical equation solving unit 30, reduces the number of logic gates and critical path delay, which is the key to the beneficial effects of the present invention.
[0034] In one specific implementation, a specific algorithm for solving the key equation is disclosed.
[0035] This invention embodiment selects the Reformulation of the iBM Algorithm (RiBM), a recombinant inverse-free algorithm, according to... Figure 3 A pseudocode implementation is sufficient. Considering different length validation fields such as RS(544, 514) and RS(528, 514), it is still implemented using the parameterized approach.
[0036] Obtaining the polynomial at the incorrect position Then, the process proceeds to step S105, where error location is located. The function of the error location location unit 40 is to find... The roots of the codeword, and the reciprocals of these roots, correspond to the indexes of the positions in the codeword where errors occurred. This process is typically implemented using the Chan's search method. The principle of Chan's search is to find the inverse of the Galois field element corresponding to all possible position indices j in the codeword. Substitute one by one ,like If the sign at position j is incorrect, it indicates that an error has occurred. For standard, uncrunted RS codes, the search range is j from 0 to n-1. However, this embodiment deals with RS(544, 514) truncated codes, where the second code pattern parameter (codeword truncation offset) plays a crucial role. The error location unit 40 adjusts its search range based on this parameter (value 479). Specifically, since the effective sign position index of the truncated code is from 479 to 1022, the range of the inverse of the root that needs to be substituted into the Chan search is... In hardware implementation, this can be achieved by setting a counter with an initial value of 479, incrementing it every clock cycle, and using its value to generate the corresponding Galois field element. The evaluation is performed. In this way, the error location unit 40 can accurately find all error locations within the correct codeword index range, avoiding futile searches within the invalid index range.
[0037] In one specific implementation, a method for locating execution error locations is disclosed.
[0038] The error position polynomial is expressed by the following equation:
[0039] The root The reverse It's an error location, indicating the receiving polynomial. Has an error occurred? For example, determine the first received data. Whether an error has occurred is the judgment. Is it an incorrect position, i.e., its reverse? Is it? The root. (Substitute) Its value is 0). Substitute Verification is then possible. Proceed in sequence... Substitution Verify that there are no errors in the corresponding positions.
[0040] Please see Figure 5 The Verilog implementation is given below because RS(544, 514) and RS(528, 514) do not start from 1023, but from 544 and 528, respectively; these are truncated codes. The implementation needs to be as follows: Calculation. To ensure compatibility with normal codes, the implementation specifies a truncated code offset of RS_OFFSET=479. First, calculate the offset, then... Begin traversal. This embodiment of the invention still uses parameterization, with DW=10 for RF(2^10) and PIPE_NUM=8 for 8-degree parallelism. This is obtained through control parameters. Traversal.
[0041] After all error locations are found, the process proceeds to step S106, where error value calculation is performed. For each located error location j, the error value calculation unit 50 needs to calculate the corresponding error value e_j, which typically uses the Furniture algorithm. The formula for the Furniture algorithm is: ,in yes The formal derivative. In this embodiment, the error value calculation unit 50 is also affected by the second code pattern parameter, because the range of the error position j required to calculate the error value e_j has been determined by the second code pattern parameter as [479, 1022]. Therefore, in the error value polynomial The derivative of the polynomial at the wrong position When evaluating, the variable substituted This is also within the valid index range of the truncated code. Understandably, while the inverse-free reassembly algorithm avoids inversion during iteration, the Furniture algorithm itself still requires one inversion operation to calculate each error value. Even so, this single, centralized inversion operation is still significantly simpler in hardware implementation compared to the inversion that may be required in each iteration of the BM algorithm.
[0042] In one specific implementation, a specific method for calculating error values is disclosed.
[0043] The error value is obtained using the Foney algorithm, and its formula is as follows:
[0044] Obtain the error location via step S105. inverse and Simply perform the Galois multiplication method.
[0045]
[0046] Because RS(544, 514) and RS(528, 514) are truncated codes, they need to be derived from... Substitution Calculation. In the implementation, the truncated code offset RS_OFFSET=479 is given. First, calculate the offset using Galois multiplication (see [link to relevant documentation]). Figure 6 Line 2 RS_OFFSET*(i+PARITY_NUM)), then from Begin traversal.
[0047] Please see Figure 7 For calculation The inverse can be achieved by looking up a table; the idea is... Reverse = Here, n=1023, and this table can be implemented using a script. Then, multiply the inverse value by Galois.
[0048] Finally, error correction is performed in step S107. The error correction unit 60 receives the original received code character R_j, the error position j output by the error position location unit 40, and the corresponding error value e_j output by the error value calculation unit 50. The error correction process is straightforward: the received symbol is added to the error value in the Galois domain. Since this is in the GF(2^m) domain, addition is equivalent to an XOR operation. Therefore, for each error position j, the corrected symbol... The calculation is as follows: For positions where no error occurred, the error value is 0, and the XOR operation does not change the original symbol. After performing this operation on all detected error positions, the error correction unit 60 outputs a complete, corrected codeword, thus completing the entire decoding process.
[0049] Through the above process, the apparatus and method shown in this embodiment can efficiently and accurately decode RS(544, 514) codes. Furthermore, due to the use of a recombination-free algorithm and parameterized design, its hardware implementation is simpler and consumes fewer resources compared to traditional solutions.
[0050] In one specific implementation, a specific error correction method is disclosed.
[0051] The error location is obtained through step S105 and the error value is obtained through the foney calculation in step S106. The received data is then read sequentially. or This involves correcting erroneous location values. .
[0052] Example 2 To further demonstrate the flexibility and versatility of the present invention, this embodiment will describe how, using the same unified decoding apparatus and method as in Embodiment 1, a seamless switch to decoding another RS code—RS(528, 514)—can be achieved simply by changing the code pattern parameter configuration. The RS(528, 514) code is also used in high-speed Ethernet standards. It shares the same Galois domain GF(2^10) as the RS(544, 514) code, but its check symbol count is 14, and its total code length is 528.
[0053] In this embodiment, the hardware architecture upon which the decoding process relies remains the same. Figure 1 The system shown, its decoding process still follows the same methodology. Figure 2 The steps shown are the same. The key difference lies in the initial parameter configuration.
[0054] In step S101, when the system needs to process the RS(528, 514) code stream, the external controller or system configuration module loads a new set of code pattern parameters into the decoding device through the parameter configuration interface 10. Specifically: the first code pattern parameter (number of check symbols) is set to 14 to match the 14 check symbols of the RS(528, 514) code. The second code pattern parameter (codeword truncation offset) is set to 495, which is calculated based on the code length of RS(528, 514), i.e., 1023 - 528 = 495.
[0055] In step S102, the decoding device dynamically configures the internal processing unit according to the new parameters (14 and 495), so that the same set of hardware logic can adapt to different working modes.
[0056] Accordingly, each step of the decoding process will automatically adjust its behavior based on the new parameters: In step S103 (syndrome calculation), the syndrome calculation unit 20 receives a new first code pattern parameter with a value of 14. Therefore, it will only activate or enable its internal function for calculating the first 14 syndrome components. to The circuit is described. Compared to calculating 30 components in Example 1, the computational load here is significantly reduced, demonstrating the energy efficiency advantages brought by parameterized configuration.
[0057] In step S104 (solving the key equation), the key equation solving unit 30 receives these 14 adjoint components. Its internal recombinant inverseless algorithm (such as...) Figure 3 The number of iterations (as shown) is determined by 2t, where 2t equals 14. Therefore, the main loop of the algorithm only needs to execute 14 iterations to solve for the polynomial at the error location. and error value polynomial The reduction in the number of iterations directly translates to shorter processing latency and lower power consumption.
[0058] In step S105 (error location), the error location unit 40 receives a new second code pattern parameter with a value of 495. During the Chan search, this unit sets the starting value of its internal counter used to generate the search index to 495, thereby precisely limiting the search range to the valid symbol index interval [495, 1022] of the RS(528, 514) code. This ensures the correctness of the error location and avoids processing invalid intervals.
[0059] In step S106 (error value calculation), the error value calculation unit 50 is also affected by two parameters when applying the Furni algorithm. First, the relevant polynomial in the Furni algorithm formula ( and The result is derived from 14 adjoint components, and its order is relatively low. Secondly, the evaluation point substituted when calculating the error value e_j... The range of index j is determined by the second code type parameter [495, 1022].
[0060] The final step S107 (error correction) is exactly the same in principle as in Embodiment 1. The error correction unit 60 performs an XOR operation on the symbol at the corresponding position in the received codeword according to the located error position and the calculated error value to complete the error correction.
[0061] As can be seen from this embodiment, the solution provided by the present invention has high flexibility and code reusability. Designers do not need to develop two separate decoder hardware sets for RS(544, 514) and RS(528, 514) code types, but only need to design a unified, parameterizable decoder. In practical applications, the system can dynamically load different parameter configurations onto the decoder according to the type of data stream being transmitted, thereby achieving correct decoding of different RS codes. This design method greatly simplifies the design, verification, and maintenance of multimode communication systems, and effectively reduces chip area and development costs.
[0062] Example 3 This embodiment describes an automated design and implementation method for a high-performance parallel encoder that complements the aforementioned parameterizable decoder. In high-speed communication systems, encoders also require high throughput, which is typically achieved through parallel processing. This embodiment demonstrates how, starting from the serial Reed-Solomon coding theory model, a hardware encoder circuit with arbitrary parallelism can be generated through mathematical derivation and automated scripting, thus forming a complete, high-performance forward error correction solution.
[0063] The Reed-Solomon coding process can be viewed as dividing the information polynomial by the generator polynomial g(x) and taking the remainder. Its hardware implementation is typically a linear feedback shift register circuit. For a serial encoder, a new information symbol m is input in each clock cycle, and the state of the register bank is updated once. This single-step state transition process can be precisely represented in matrix form.
[0064] Please see Figure 8 This is a schematic diagram illustrating the parallel encoding principle in an embodiment of the present invention. First, we matrix-encode the single-step state transition process of the serial encoder. Assuming the linear feedback shift register has 2t registers, its state can be represented as a 2t-dimensional column vector X. After receiving an input symbol m_0, the relationship between the new state vector X' and the old state vector X can be expressed as: Where A is a 2t×2t state transition matrix (e.g., ... Figure 8The A-state transition matrix (as shown in the diagram) describes the shift and feedback logic of the data inside the register; b is a 2t×1 input coefficient vector that describes how the input sign affects the register state; X(0) (as shown in the diagram) Figure 8 X(0) (shown as the initial state) represents the initial state before encoding begins, which is usually an all-zero vector.
[0065] To achieve P-way parallel encoding, i.e., to process P input symbols m0, m1, ..., m(P-1) simultaneously within one clock cycle (e.g., ... Figure 8 As shown in the parallel input m0…m(P-1)), we need to derive the equivalent state transition formula after P serial iterations. Iterating the above single-step state transition equation P times yields the final state X(P) after processing P symbols (as shown in the parallel input). Figure 8 The expression for X(P) (as shown in the final state): The core of this formula is calculating the parallel computation matrix A. P (like Figure 8 The AP-parallel computing matrix (shown in the diagram) is the P-th power of the state transition matrix A, along with a series of coefficient matrices. All elements in these matrices are constants within the Galois field GF(2^10).
[0066] The method provided in this embodiment uses scripts (e.g., written in high-level languages such as Python or Matlab) to automate this process. The specific process is as follows: 1. Define the Galois field: First, define the operation rules of GF(2^10) in the script, including addition (XOR) and multiplication (usually implemented based on logarithm and antilogarithm tables).
[0067] 2. Construct the basic matrix: Based on the generator polynomial g(x) of the selected RS code, manually or automatically generate the basic state transition matrix A and the input coefficient vector b.
[0068] 3. Compute the parallel matrix: The script receives an integer P representing the desired degree of parallelism (e.g., P=8). The script then performs matrix operations within the Galois field to compute A^P and all the coefficient matrices. .
[0069] 4. Generate Hardware Description Language Code: The script expands the final parallel computation formula and converts each Galois field multiplication (multiplication of a state / input symbol with a constant matrix element) and addition (XOR) into a logical expression in a specific hardware description language (such as Verilog or VHDL). For example, for 8-way parallelism, the final generated Verilog code will describe a large combinational logic circuit with eight 10-bit symbol input ports and one 2t×10-bit state input port, whose output is an updated 2t×10-bit state.
[0070] This automated approach allows designers to easily generate RS encoders with arbitrary parallelism. For example, when a 4-channel parallel encoder is needed, simply run the script and input P=4; when system requirements change to a 16-channel parallel encoder, simply modify the input parameter to P=16 and rerun the script. This significantly improves design efficiency and reduces the possibility of errors introduced by manually deriving and writing complex parallel logic. This parallel encoder, combined with the aforementioned parameterizable decoder, forms a complete, flexible, and high-performance high-speed Ethernet forward error correction solution.
[0071] In one specific implementation, the Ethernet 802.3 case91 Reed-sollomon forwarderror correction (RS-FEC) sublayer for 100G BASE-R PHYs provides generator polynomials for two encodings: RS(544, 514) and RS(528, 514).
[0072]
[0073] Define K message polynomials:
[0074] The following calculation yields 2t check polynomials:
[0075] The protocol describes a serial encoding method, suitable for high-speed data rates from 100Gbps to 400Gbps, requiring consideration of parallel implementation. Taking RS(544, 514) code as an example, this encoding yields 30 symbol checksums. Here, we assume the initial values of p0, p1, ..., p29 are:
[0076] After one round of calculation, it becomes:
[0077] according to Figure 9 get:
[0078] Converted to matrix form:
[0079] The parallelism of the 8 ground-based push operations is as follows:
[0080] Write a script to get Please see Figure 10 As shown. For 8-degree parallelism calculation, please refer to [link / reference]. Figure 11 As shown. This allows for the implementation of RS(544,514) and RS(528,514) encodings with any degree of parallelism.
[0081] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units of this invention function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.
[0082] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features of the present invention can be arbitrarily combined with each other.
Claims
1. A parameterizable Reed-Solomon code unified decoding method, characterized in that, The method is used to decode any selected Reed-Solomon code from multiple Reed-Solomon codes based on the same Galois field. The method includes: At least one processing step in the decoding method is configured according to a first code pattern parameter that characterizes the number of check symbols of the selected Reed-Solomon code; When the selected Reed-Solomon code is a truncated code, at least one processing step in the decoding method is configured according to the second code pattern parameter used to characterize the codeword truncation offset characteristics of the truncated code. The processing steps in the decoding method include: Perform the adjoint calculation to obtain the adjoint components; The inverseless algorithm of recombination is used to process the adjoint components in order to solve for the error position polynomial and the error value polynomial. Perform error location analysis to obtain the error location; Perform error value calculation to obtain the error value; Error correction is performed based on the error location and the error value.
2. The parameterizable Reed-Solomon code unified decoding method according to claim 1, characterized in that, The step of configuring at least one processing step in the decoding method according to the first code pattern parameters includes: The syndic calculation steps are configured according to the first code pattern parameters to calculate the syndic component corresponding to the number of check symbols.
3. The parameterizable Reed-Solomon code unified decoding method according to claim 2, characterized in that, The first code type parameter is the number of check symbols of the selected Reed-Solomon code.
4. The parameterizable Reed-Solomon code unified decoding method according to claim 1, characterized in that, The step of configuring at least one processing step in the decoding method according to the second code pattern parameters includes: The error location locating step and the error value calculation step are configured according to the second code pattern parameters.
5. The parameterizable Reed-Solomon code unified decoding method according to claim 4, characterized in that, The second code pattern parameter is the codeword truncation offset of the truncated code.
6. A parameterizable Reed-Solomon code unified decoding device, characterized in that, The apparatus is used to decode any selected Reed-Solomon code from a plurality of Reed-Solomon codes based on the same Galois field. The apparatus includes: The unit includes a computational unit, a key equation solving unit, an error location unit, an error value calculation unit, and an error correction unit. The key equation solving unit is used to process the output of the adjoint calculation unit using a recombined inverse-free algorithm to solve for the error position polynomial and the error value polynomial. The device is also configured to: At least one unit in the apparatus is configured according to a first code pattern parameter that characterizes the number of check symbols of the selected Reed-Solomon code; When the selected Reed-Solomon code is a truncated code, at least one unit in the device is configured according to a second code pattern parameter used to characterize the codeword truncation offset characteristics of the truncated code.
7. The parameterizable Reed-Solomon code unified decoding device according to claim 6, characterized in that, The device is configured to: Configure the syntactic calculation unit according to the first code pattern parameters; and The error location unit and the error value calculation unit are configured according to the second code pattern parameters.
8. The parameterizable Reed-Solomon code unified decoding device according to claim 6, characterized in that, At least one of the accompanying computation unit, the key equation solving unit, the error location unit, or the error value calculation unit includes a lookup table for performing Galois field multiplication or inversion operations.
9. The parameterizable Reed-Solomon code unified decoding device according to claim 6, characterized in that, The device is defined by hardware description language code, which includes a generate loop structure for instantiating the at least one unit based on the first code pattern parameter and / or the second code pattern parameter.
10. A computer-readable storage medium, characterized in that, It stores hardware description language code, which, when synthesized and implemented, is used to generate the parameterizable Reed-Solomon code unified decoding method as described in claim 1.