Fault positioning system and method based on broadband pulse generation circuit

Abstract

The invention belongs to the technical field of broadband pulse generation, and particularly relates to a fault positioning system and method based on a broadband pulse generation circuit, and the system comprises a broadband pulse generation circuit module, a high-frequency transmission line module, and an upper computer module. The broadband pulse generation circuit module is connected with the high-frequency transmission line module, and the high-frequency transmission line module is connected with the upper computer module through an Ethernet interface. The broadband pulse generation circuit module comprises an FPGA module, a signal input and level conversion module, a broadband signal conditioning module, a signal output module and a power conversion module, the signal input and level conversion module is connected with the FPGA module, and the broadband signal conditioning module is connected with the signal input and level conversion module. Square waves are generated through the FPGA module, the signal frequency is convenient to adjust, a high-speed laser driver is used as a main component to generate broadband pulses, pulses of dozens of picoseconds or even several picoseconds can be generated, and a method of a high-frequency cable and a transmission line to be detected is adopted, so that fault positioning can be accurately carried out.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of wideband pulse generation, and particularly relates to a fault positioning system and method based on a wideband pulse generation circuit. BACKGROUND

[0002] In high-frequency signal transmission, a transmission line is a core component for ensuring signal integrity. However, due to impedance mismatch, reflection loss, skin effect and thermal loss under high-frequency signals, and the like, the transmission line may have open-circuit, short-circuit and other faults, which will cause serious attenuation and distortion of the high-frequency signal. In order to avoid serious signal degradation, fault judgment of the transmission line is particularly necessary. Time domain reflection technology (TDR) is used to analyze voltage information of a reflected signal in a cable to determine fault types and positioning. TDR can be used to detect the transmission line, and the input voltage is low, which will not damage the cable itself.

[0003] The current fault positioning methods for the transmission line include visual inspection, bridge method, high-voltage pulse method and secondary pulse method. The visual inspection method cannot detect the fault hidden in the middle section. The bridge method can only measure low-resistance faults, and the accurate parameters of the transmission line are required when using the method, which greatly affects the measurement accuracy. Some shortcomings of the method make it very limited in fault ranging. The high-voltage pulse method needs to send a high-voltage or current pulse to break through the fault position, and then calculate the time difference to determine the fault position. The principle is simple and the speed is fast, but the safety of the high-voltage pulse is poor. The secondary pulse method can measure high-resistance faults, but it still needs to send a high-voltage signal to break through the fault position when the low-resistance is flashed. The signal at the flashover position is recorded, and the pulse is continued to be sent after the arc is extinguished. The fault distance is calculated by comparing the signal sampled before with the signal sampled after. However, the measurement needs high-voltage pulses, and the two measurement steps are relatively complicated. The sampling accuracy is affected by many environmental factors, and the error cannot be guaranteed. The TDR time domain reflection method based on the wideband pulse has low input voltage, which will not damage the cable itself. The operation is simple and the accuracy is high. SUMMARY

[0004] In view of the technical problems of the above-mentioned fault positioning methods for the transmission line, the application provides a fault positioning system and method based on a wideband pulse generation circuit.

[0005] To solve the above technical problems, the technical scheme adopted by the application is as follows: A fault positioning system based on a wideband pulse generation circuit, comprising a wideband pulse generation module, a high-frequency transmission line module and an upper computer module. The output end of the wideband pulse generation circuit module is connected to the input end of the high-frequency transmission line module. The output end of the high-frequency transmission line module is connected to the input end of the upper computer module through an Ethernet interface. The output end of the upper computer module exports data analysis.

[0006] The wideband pulse generation module comprises an FPGA module, a signal input and level conversion module, a wideband signal conditioning module, a signal output module and a power conversion module, the input end of the signal input and level conversion module is connected with the output end of the FPGA module, the input end of the wideband signal conditioning module is connected with the output end of the signal input and level conversion module, the output end of the wideband signal conditioning module is connected with the input end of the signal output module, and the power conversion module provides +3.3V and +1.2V voltages for the FPGA module, the signal input and level conversion module and the wideband signal conditioning module.

[0007] The FPGA module adopts PGL25G, is powered by 3.3V and 1.2V, downloads programs by a JTAG interface, outputs signals by the IO port of the pin T13, stores chips to latch, the latch chip adopts GD25Q64CSIG, the system clock used is 50MHz, the clock is 8-divided by a counter, and the frequency of a 3.125MHz square wave can be obtained.

[0008] The signal input and level conversion module comprises an SMA signal input end, a level conversion chip and a resistance impedance matching network, the SMA signal input end is connected to the D input pin of the level conversion chip through a circuit, the level conversion chip adopts MC100EPT20MNR4G, the 5 pin of the level conversion chip is connected with GND, the 8 pin of the level conversion chip is connected with 3.3V, and the output 2 pin Q and the output 3 pin Q# of the level conversion chip are connected with the resistance impedance matching network; the resistance impedance matching network is a circuit composed of resistors, processes the signals output by the level conversion chip, realizes further transmission and conditioning of the signals and provides appropriate signals for subsequent modules.

[0009] The wideband signal conditioning module comprises a signal input end and a high-speed laser drive chip, the signal input end is connected to the 13 pin TIN- and the 14 pin TIN+ of the high-speed laser drive chip through a first capacitor and a second capacitor, provides input signals for the internal signal processing unit of the chip and isolates the direct current component at the same time, the high-speed laser drive chip adopts MAX3798ETJ+T, the 26 pin VEER of the chip is directly grounded, provides a stable reference ground for the signal processing circuit inside the chip, the power supply pins VCCT, VCCD and VCCR of the chip are connected with +3.3V voltage, and the differential signal output 19 pin TOUT and the differential signal output 20 pin TOUT+ of the chip are connected to the signal output end through a fourth capacitor.

[0010] The signal output module comprises a third capacitor and a matching resistor and an SMA interface, the third capacitor and the matching resistor perform impedance matching on the differential signals output by the wideband signal conditioning module, reduce reflection and transmit the signals to the output end, the SMA interface radio frequency coaxial connector stably outputs the signals processed by the capacitor and the resistor, and the shell of the SMA interface is grounded.

[0011] The power conversion module comprises an interface, a power input end, a power conversion chip, a filter capacitor group, the interface 6th pin is connected with external DC power supply +5V, the 1st pin and the 2nd pin are grounded, the power input end is connected with +5V, the power conversion chip adopts TPS7A8001DRBR to generate 3.3V, the power conversion chip 7th pin and the 8th pin IN are connected with the power input end +5V, the 1st output pin and the 2nd output pin OUT output the converted +3.3V power supply, AMS1117 is adopted to generate +1.2V, the power conversion chip 3rd pin VIN is connected with the power input end +5V, the output 2nd pin VOUT outputs the converted +1.2V, and the filter capacitor group is connected at the position of the power conversion chip output end, and plays a role of filtering and stabilizing the power supply voltage.

[0012] The high-frequency transmission line module comprises a high-frequency connecting cable and a measured transmission line, the high-frequency connecting cable transmits the signal generated by the wideband pulse generating circuit module to the measured transmission line, and ensures the quality of the high-frequency signal in the transmission process, and the measured transmission line is the object of fault positioning, and the fault position of the test signal in the transmission.

[0013] A fault positioning method based on a wideband pulse generating circuit, comprising the following steps: S1, a square wave is output by controlling the FPGA module, the square wave frequency is 3.125MHz, and the square wave is input into the wideband pulse generating circuit as an input signal for shaping processing; S2, the rise time and amplitude of the wideband pulse generating circuit output signal are determined, the rise time of the wideband pulse generating circuit output signal is 40ps, and the amplitude is 0~200mV; S3, a high-frequency cable is connected at the output end of the wideband pulse generating circuit module, the cable terminal is kept in an open circuit state, the incident voltage, the open circuit reflection voltage, the half step voltage and the time point corresponding to the half step voltage of the waveform are saved in the upper computer, then the measured transmission line is connected to the other end of the high-frequency cable, the other end of the measured transmission line is kept in an open circuit state, testing is carried out, the incident voltage, the open circuit reflection voltage, the half step voltage and the time point corresponding to the half step voltage of the waveform are saved in the upper computer, and the difference between the two time points is obtained, and then the fault position is obtained from the time difference.

[0014] Compared with the prior art, the present application has the beneficial effects that: The application directly adjusts the signal frequency through the FPGA module square wave, uses the high-speed laser driver as the main component to generate a wideband pulse, has strong high-frequency response capability, can generate a pulse of tens of picoseconds or even a few picoseconds, improves the measurement accuracy of the system, and the fault positioning method adopts the method of high-frequency cable + measured transmission line, so that the time difference between the incidence and reflection can be accurately obtained, the time difference from the transmission of the first pulse wave to the echo reflection to the receiving end does not need to be calculated, the measurement steps are simplified, and the test efficiency is improved. The circuit system of the application has high integration, strong signal interference capability and low cost. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only exemplary, and those skilled in the art can also obtain other implementation drawings according to the provided drawings without creating any creative labor.

[0016] The structures, proportions, sizes, etc. shown in the specification are only used to cooperate with the content disclosed in the specification, to be understood and read by those skilled in the art, and do not define the limiting conditions for the implementation of the application, so they do not have technical substantive significance. Any modification of structure, change of proportion relationship or adjustment of size, without affecting the effect and purpose that the application can produce, should still fall within the scope of the technical content disclosed by the application.

[0017] Figure 1 is a block diagram of the overall structure of the application; Figure 2 is a circuit schematic diagram of the wideband pulse generation circuit module of the application; Figure 3 is a circuit schematic diagram of the FPGA module to which the wideband pulse generation circuit module belongs; Figure 4 is a step schematic diagram of the fault positioning method of the application.

[0018] Among them: U1 is a wideband pulse generation circuit module, U2 is a high-frequency transmission line module, U3 is an upper computer module, 1 is an FPGA module, 2 is a signal input and level conversion module, 3 is a wideband signal conditioning module, 4 is a signal output module, 5 is a power conversion module, C10 is a first capacitor, C11 is a second capacitor, C13 is a third capacitor, C14 is a fourth capacitor, R16 is a matching resistor. DETAILED DESCRIPTION

[0019] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. These descriptions are only used to further explain the features and advantages of the present application, rather than limit the claims of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0020] The specific embodiments of the present application will be further described in detail below with reference to the accompanying drawings and embodiments. The following embodiments are used to illustrate the present application, but are not used to limit the scope of the present application.

[0021] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0022] The embodiment provides a fault positioning method based on a wideband pulse generation circuit, as shown in Figure 1 The output end of the wideband pulse generation circuit module U1 is connected with the input end of the high-frequency transmission line module U2, the signal reflected back through the high-frequency transmission line module U2, that is, the output end of U2 is connected to the input end of the host computer module U3 through an Ethernet interface, and the output end of the host computer is connected to the output end of the host computer.

[0023] Further, as shown in Figure 2 、 3 The wideband pulse generation circuit module U1 includes an FPGA module 1, a signal input and level conversion module 2, a wideband signal conditioning module 3, a signal output module 4 and a power conversion module 5. The input end of the signal input and level conversion module 2 is connected with the output end of the FPGA module 1, the input end of the wideband signal conditioning module 3 is connected with the output end of the signal input and level conversion module 2, the output end of the wideband signal conditioning module 3 is connected with the input end of the signal output module 4, and the power conversion module 5 provides +3.3V and +1.2V voltage for the FPGA module 1, the signal input and level conversion module 2 and the wideband signal conditioning module 3.

[0024] Further, preferably, the FPGA module 1 adopts PGL25G, adopts 3.3V and 1.2V power supply, downloads program by JTAG interface, outputs signals by IO port of pin T13, and the signals are latched through a storage chip, and the latching chip adopts GD25Q64CSIG, and a system clock used is 50MHz, and the clock is divided by 8 through a counter, and a frequency of 3.125MHz square wave can be obtained.

[0025] Further, preferably, the signal input and level conversion module 2 comprises an SMA signal input end, a level conversion chip, and a resistance impedance matching network R3-R6, the SMA signal input end is connected to a D input pin of the level conversion chip through a circuit, the level conversion chip adopts MC100EPT20MNR4G, a 5 pin of the level conversion chip is connected to GND, an 8 pin of the level conversion chip is connected to 3.3V, and output pins 2 and 3 (Q, Q#) of the level conversion chip are connected to the resistance impedance matching network R3-R6; the resistance impedance matching network R3-R6 is a circuit composed of resistors, processes signals output by the level conversion chip, realizes further transmission and conditioning of the signals, and provides appropriate signals for subsequent modules.

[0026] Further, preferably, the wideband signal conditioning module 3 comprises a signal input end and a high-speed laser drive chip, the signal input end is connected to 13 and 14 (TIN-, TIN+) pins of the high-speed laser drive chip through a first capacitor C10 and a second capacitor C11, so as to provide input signals for an internal signal processing unit of the chip and isolate direct current components; the high-speed laser drive chip adopts MAX3798ETJ+T, a 26 pin VEER of the chip is directly connected to ground, so as to provide a stable reference ground for a signal processing circuit inside the chip, power supply pins VCCT, VCCD, and VCCR of the chip are connected to +3.3V voltage, and differential signal output 19 and 20 pins (TOUT-, TOUT+) of the chip are connected to a signal output end through a fourth capacitor C14.

[0027] Further, preferably, the signal output module 4 comprises a third capacitor C13, a matching resistor R16, and an SMA interface, the third capacitor C13 and the matching resistor R16 perform impedance matching on differential signals output by the wideband signal conditioning module, reduce reflection, and transmit the signals to an output end, and the SMA interface radio frequency coaxial connector stably outputs signals processed by the capacitor and the resistor, and an outer shell of the SMA interface is connected to ground.

[0028] Further, preferably, the power conversion module 5 includes an interface, a power input end, a power conversion chip, and a filter capacitor group C1-C6. The interface is connected to an external DC power supply +5V through the 6th pin, and the 1st and 2nd pins are grounded. The power input end is connected to +5V. The power conversion chip generates 3.3V by using TPS7A8001DRBR. The 7th and 8th pins (IN) of the chip are connected to the power input end +5V. The output pins 1 and 2 (OUT) output the converted +3.3V power supply. AMS1117 is used to generate +1.2V. The 3rd pin (VIN) of the chip is connected to the power input end +5V. The output pin 2 (VOUT) outputs the converted +1.2V. The capacitor group is connected to the output end of the power conversion chip, which plays a role in filtering and stabilizing the power supply voltage.

[0029] Further, the high-frequency transmission line module U2 includes a high-frequency connection cable and a measured transmission line. The high-frequency connection cable transmits the signal generated by the wideband pulse generation circuit module U1 to the measured transmission line, ensuring the quality of the high-frequency signal in the transmission process. The measured transmission line is the object of fault positioning, and the fault position of the test signal in the transmission.

[0030] Further, the host computer module U3 is the data processing center of the entire measurement system, which is used to collect and display the received fault signals for data analysis and processing.

[0031] A fault positioning method based on a wideband pulse generation circuit, as shown in Figure 4 , includes the following steps: Step one: output a square wave through the FPGA module, with a frequency of 3.125MHz. Input this square wave into the wideband pulse generation circuit as an input signal for shaping processing.

[0032] Step two: determine the rise time, amplitude, and other parameters of the output signal of the wideband pulse generation circuit. The rise time of the output signal of the wideband pulse generation circuit is 40ps, and the amplitude is 0-200mV.

[0033] Step three: connect a high-frequency cable to the output signal of the wideband pulse generation circuit, keep the terminal of the cable open, save the incident voltage, open-circuit reflection voltage, and half-step voltage and the corresponding time points of the half-step voltage in the host computer, then connect the measured transmission line to the other end of the high-frequency cable, keep the other end of the measured transmission line open, test, save the incident voltage, open-circuit reflection voltage, and half-step voltage and the corresponding time points of the half-step voltage in the host computer, and then subtract the two time points. According to formula 1, the fault point position is obtained. L represents the relative distance between the transmitted pulse and the fault position; V is the propagation speed of electromagnetic waves in the measured transmission line; c is the propagation speed of electromagnetic waves in vacuum, usually taking the value of 3×10 8 m / s; ɛ rVe is the rate factor of the transmission line; and T is the time difference between the incident pulse and the reflected pulse.

[0034] (1) The above detailed only the preferred embodiments of the present application, but the present application is not limited to the above-described embodiments, within the scope of knowledge possessed by those of ordinary skill in the art, can also be made under the premise of not departing from the purpose of the present application, various changes, all changes should be included within the scope of the present application.

Claims

1. A fault location system based on a broadband pulse generation circuit, characterized in that: It includes a broadband pulse generation module (U1), a high-frequency transmission line module (U2), and a host computer module (U3). The output terminal of the broadband pulse generation module (U1) is connected to the input terminal of the high-frequency transmission line module (U2). The output terminal of the high-frequency transmission line module (U2) is connected to the input terminal of the host computer module (U3) through an Ethernet interface. The output terminal of the host computer module (U3) exports data for analysis.

2. The fault location system based on a broadband pulse generation circuit according to claim 1, characterized in that: The broadband pulse generation module (U1) includes an FPGA module (1), a signal input and level conversion module (2), a broadband signal conditioning module (3), a signal output module (4), and a power conversion module (5). The input terminal of the signal input and level conversion module (2) is connected to the output terminal of the FPGA module (1). The input terminal of the broadband signal conditioning module (3) is connected to the output terminal of the signal input and level conversion module (2). The output terminal of the broadband signal conditioning module (3) is connected to the input terminal of the signal output module (4). The power conversion module (5) provides +3.3V and +1.2V voltages to the FPGA module (1), the signal input and level conversion module (2), and the broadband signal conditioning module (3).

3. The fault location system based on a broadband pulse generation circuit according to claim 2, characterized in that: The FPGA module (1) uses PGL25G, is powered by 3.3V and 1.2V, downloads programs via JTAG interface, outputs signals via the IO port of pin T13, and latches them through a memory chip. The latch chip uses GD25Q64CSIG, and the system clock used is 50MHz. The clock is divided by 8 by a counter to obtain a 3.125MHz square wave frequency.

4. The fault location system based on a broadband pulse generation circuit according to claim 1, characterized in that: The signal input and level conversion module (2) includes an SMA signal input terminal, a level conversion chip, and a resistor impedance matching network. The SMA signal input terminal is connected to the D input pin of the level conversion chip via a circuit. The level conversion chip is an MC100EPT20MNR4G. Pin 5 of the level conversion chip is connected to GND, and pin 8 of the level conversion chip is connected to 3.3V. Pins 2 (Q) and 3 (Q#) of the level conversion chip are connected to the resistor impedance matching network. The resistor impedance matching network is a circuit composed of resistors that processes the signal output by the level conversion chip to achieve further signal transmission and conditioning, and provides a suitable signal for subsequent modules.

5. A fault location system based on a broadband pulse generation circuit according to claim 2, characterized in that: The broadband signal conditioning module (3) includes a signal input terminal and a high-speed laser driver chip. The signal input terminal is connected to pins 13 (TIN-) and 14 (TIN+) of the high-speed laser driver chip through a first capacitor (C10) and a second capacitor (C11) to provide input signals to the internal signal processing unit of the chip and isolate DC components. The high-speed laser driver chip is a MAX3798ETJ+T. Pin 26 (VEER) of the chip is directly grounded to provide a stable reference ground for the internal signal processing circuit of the chip. The power supply pins VCCT, VCCD, and VCCR of the chip are connected to a +3.3V voltage. The differential signal output pins 19 (TOUT) and 20 (TOUT+) of the chip are connected to the signal output terminal through a fourth capacitor (C14).

6. A fault location system based on a broadband pulse generation circuit according to claim 2, characterized in that: The signal output module (4) includes a third capacitor (C13) and a matching resistor (R16), and an SMA interface. The third capacitor (C13) and the matching resistor (R16) perform impedance matching on the differential signal output by the broadband signal conditioning module to reduce reflection and transmit it to the output end. The SMA interface RF coaxial connector stably outputs the signal after capacitor and resistor processing. The SMA interface shell is grounded.

7. A fault location system based on a broadband pulse generation circuit according to claim 2, characterized in that: The power conversion module (5) includes an interface, a power input terminal, a power conversion chip, and a filter capacitor bank. Pin 6 of the interface is connected to an external DC power supply +5V, pins 1 and 2 are grounded, the power input terminal is connected to +5V, the power conversion chip uses TPS7A8001DRBR to generate 3.3V, pins 7 and 8 IN of the power conversion chip are connected to the power input terminal +5V, and pins 1 and 2 OUT output the converted +3.3V power supply. AMS1117 is used to generate +1.2V, pin 3 VIN of the power conversion chip is connected to the power input terminal +5V, and pin 2 VOUT outputs the converted +1.2V. The filter capacitor bank is connected at the output terminal of the power conversion chip to filter and stabilize the power supply voltage.

8. A fault location system based on a broadband pulse generation circuit according to claim 1, characterized in that: The high-frequency transmission line module (U2) includes a high-frequency connecting cable and a transmission line under test. The high-frequency connecting cable transmits the signal generated by the broadband pulse generation circuit module (U1) to the transmission line under test, ensuring the quality of the high-frequency signal during transmission. The transmission line under test is the object for fault location, testing the fault location of the signal during transmission.

9. A fault location method based on a broadband pulse generation circuit, wherein the method is used in a fault location system based on a broadband pulse generation circuit as described in any one of claims 1-8, characterized in that: Includes the following steps: S1. A square wave with a frequency of 3.125MHz is output through the FPGA module. This square wave is then input into the broadband pulse generation circuit as an input signal for shaping. S2. Determine the rise time and amplitude parameters of the output signal of the broadband pulse generation circuit. The rise time of the output signal of the broadband pulse generation circuit is 40ps and the amplitude is 0~200mV. S3. Connect a high-frequency cable to the output of the broadband pulse generation circuit module, keeping the cable end open. Save the incident voltage, open-circuit reflected voltage, half-step voltage, and the corresponding time point of the half-step voltage in the host computer. Then connect the transmission line under test to the other end of the high-frequency cable, keeping the other end of the transmission line under test open, and perform the test. Save the incident voltage, open-circuit reflected voltage, half-step voltage, and the corresponding time point of the half-step voltage in the host computer. Calculate the difference between the two time points and use this time difference to determine the fault location.

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