Semiconductor device, manufacturing method and access method thereof, and electronic equipment

Abstract

The invention relates to a semiconductor device, a manufacturing method and an access method thereof, and electronic equipment, and the manufacturing method comprises the steps: providing a substrate, and alternately forming a first sacrificial layer and a semiconductor layer to form a laminated structure; forming a first doped region and a second doped region on the semiconductor layer at two ends of the storage region; defining a first sub-region, removing the first sacrificial layer between the first sub-region and the first doped region, and exposing the semiconductor layer between the first sub-region and the first doped region; forming a floating gate dielectric layer to cover the semiconductor layer between the first sub-region and the first doped region; etching the first sub-region to expose the semiconductor layer of the first sub-region; forming a semi-floating gate to cover the floating gate dielectric layer and the semiconductor layer of the first sub-region; removing the first sacrificial layer between the first sub-region and the second doped region to expose the semiconductor layer between the first sub-region and the second doped region; and a control gate dielectric layer and a control gate are formed to cover the semiconductor layer and the semi-floating gate between the first sub-region and the second doped region, so that the integration density is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor device and its fabrication method, access method, and electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, making it possible for even the slightest differences in the manufacturing process to affect device performance.

[0003] To minimize product costs, the goal is to fabricate as many device cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor device design and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, this disclosure provides a method for fabricating a semiconductor device, comprising:

[0006] A substrate is provided on which a first sacrificial layer and a semiconductor layer are alternately formed to form a stacked structure, wherein at least one storage region is defined in the stacked structure;

[0007] Etching removes part of the stacked structure, exposing the semiconductor layers at both ends of the memory region, and doping the semiconductor layers at both ends of the memory region to form a first doped region and a second doped region at both ends of the memory region;

[0008] A first sub-region is defined between the first doped region and the second doped region, and the first sacrificial layer between the first sub-region and the first doped region is removed to expose the semiconductor layer between the first sub-region and the first doped region.

[0009] A floating gate dielectric layer is formed, which covers the semiconductor layer between the first sub-region and the first doped region;

[0010] The first sub-region is etched to expose the semiconductor layer of the first sub-region;

[0011] A semi-floating gate is formed, the semi-floating gate covering the floating gate dielectric layer and the semiconductor layer of the first sub-region;

[0012] Remove the first sacrificial layer between the first sub-region and the second doped region to expose the semiconductor layer between the first sub-region and the second doped region;

[0013] A control gate dielectric layer and a control gate are formed sequentially. The control gate dielectric layer covers the semiconductor layer between the first sub-region and the second doped region and the semi-floating gate. The control gate covers the control gate dielectric layer.

[0014] Optionally, the memory region extends along a first horizontal direction, and the plurality of memory regions are spaced apart along a second horizontal direction; before etching away a portion of the stacked structure to expose the semiconductor layers at both ends of the memory region, the method further includes:

[0015] A bit line region is defined on one side of the storage area along the first horizontal direction, and the bit line region is etched to form a first trench that penetrates the stacked structure. The first trench extends along the second horizontal direction.

[0016] The semiconductor layer exposed by the first trench is etched to form a bit line groove on the sidewall of the first trench, the bit line groove extending along the second horizontal direction;

[0017] A bit line extending along the second horizontal direction is formed in the bit line groove, and the bit line is used to connect with the second doped region.

[0018] Optionally, after forming a bit line extending along the second horizontal direction in the bit line groove, the method further includes:

[0019] The first sacrificial layer exposed by the first trench is etched, and a first transverse trench is formed on the sidewall of the first trench. Along the first horizontal direction, the width of the first transverse trench is greater than the width of the bit line trench, and the first transverse trench extends to the storage area.

[0020] A first isolation layer is filled into the first trench and the first transverse groove.

[0021] Optionally, after forming the control gate, the system further includes:

[0022] The stacked structure is etched to expose the first doped region;

[0023] A first electrode line is formed, which is vertically disposed on the substrate and connected to the first doped region.

[0024] Optionally, the semiconductor layers at both ends of the memory region are doped to form a first doped region and a second doped region at both ends of the memory region, including:

[0025] Etching removes a portion of the stacked structure between adjacent memory regions, forming a first isolation trench and a second isolation trench between adjacent memory regions;

[0026] Based on the first isolation trench and the second isolation trench, the memory region is etched to expose the semiconductor layers at both ends of the memory region;

[0027] The semiconductor layer exposed at both ends of the storage region is doped to form the first doped region and the second doped region.

[0028] Optionally, before removing the first sacrificial layer between the first sub-region and the first doped region, the first sacrificial layer of the first sub-region is etched away to expose the semiconductor layer of the first sub-region, and a second sacrificial layer is formed to cover the semiconductor layer of the first sub-region.

[0029] After the floating gate dielectric layer is formed, the second sacrificial layer is removed to expose the semiconductor layer of the first sub-region.

[0030] Optionally, the manufacturing method further includes:

[0031] The semiconductor layer between the first sub-region and the first doped region is doped to form a third doped region connected to the first doped region, and the third doped region is spaced apart from the first sub-region.

[0032] Optionally, the manufacturing method further includes:

[0033] The semiconductor layer of the first sub-region is doped to form a fourth doped region on the surface of the semiconductor layer of the first sub-region. The fourth doped region is spaced apart from the second doped region and from the third doped region.

[0034] Optionally, the semiconductor layer deposited on the substrate has a first conductivity type;

[0035] The first doped region and the second doped region have the same conductivity type as the semiconductor layer;

[0036] The third doped region and the fourth doped region have the opposite conductivity type to the semiconductor layer, and the fourth doped region forms a PN junction with the semiconductor layer inside it.

[0037] Optionally, the manufacturing method includes:

[0038] Etching removes part of the stacked structure, exposing the semiconductor layers at both ends of the memory region, and forming a first ion implantation layer covering the semiconductor layers at both ends of the memory region;

[0039] Etching removes a portion of the stacked structure, exposing a portion of the semiconductor layer near one end of the storage region, and forming a second ion implantation layer to cover the exposed semiconductor layer;

[0040] Etching removes part of the stacked structure, exposing the semiconductor layer of the first sub-region, and forming a third ion implantation layer to cover the semiconductor layer of the first sub-region;

[0041] The structure formed after heat treatment to form the third ion implantation layer also forms the first doped region, the second doped region, the third doped region, and the fourth doped region.

[0042] In a second aspect, this disclosure provides a semiconductor device, including a substrate and a plurality of memory cells spaced apart on the substrate along a direction perpendicular to the substrate, each memory cell comprising:

[0043] A semiconductor layer, the semiconductor layer including a first doped region and a second doped region disposed at both ends thereon, and a first sub-region disposed between the first doped region and the second doped region;

[0044] A floating gate dielectric layer, the floating gate dielectric layer covering the semiconductor layer between the first sub-region and the first doped region;

[0045] A semi-floating gate, the semi-floating gate covering the floating gate dielectric layer and the semiconductor layer of the first sub-region;

[0046] A control gate dielectric layer covers the semiconductor layer and the semi-floating gate between the first sub-region and the second doped region;

[0047] A control gate, covering the control gate dielectric layer.

[0048] Optionally, the semiconductor layer has a first conductivity type, and the first doped region, the second doped region, and the semiconductor layer have the same conductivity type.

[0049] Optionally, the semiconductor layer further includes:

[0050] A third doped region is disposed between the first sub-region and the first doped region. The third doped region is connected to the first doped region and spaced apart from the first sub-region. The conductivity type of the third doped region is opposite to that of the semiconductor layer.

[0051] Optionally, the semiconductor layer further includes:

[0052] A fourth doped region is disposed on the surface of the semiconductor layer in the first sub-region. The fourth doped region is spaced apart from the second doped region and from the third doped region. The fourth doped region has an opposite conductivity type to the semiconductor layer. The fourth doped region forms a PN junction with the semiconductor layer inside it.

[0053] Optionally, the memory cells extend along a first horizontal direction, and a plurality of the memory cells are spaced apart along a second horizontal direction; the semiconductor device further includes:

[0054] Bit lines are disposed on one side of the memory cell along the first horizontal direction, the bit lines extend along the second horizontal direction, and the bit lines connect the second doped regions of the plurality of memory cells arranged along the second horizontal direction;

[0055] A first electrode line is disposed on the side of the memory cell away from the bit line. The first electrode line is perpendicularly disposed on the substrate. The first electrode line connects to the first doped regions of a plurality of memory cells disposed in a direction perpendicular to the substrate.

[0056] Optionally, the control gate connections of the memory cells arranged perpendicular to the substrate form word lines.

[0057] Thirdly, this disclosure provides a method for accessing a semiconductor device, including performing write control operations and read operations on the semiconductor device;

[0058] The write control operation includes:

[0059] A preset reference voltage is applied to the first doped region, a first write control voltage is applied to the second doped region, and a first reference voltage is applied to the control gate. The first write control voltage is greater than the first reference voltage. Holes tunnel through the first sub-region from the second doped region and inject into the semi-floating gate, writing logic "1".

[0060] A preset reference voltage is applied to the first doped region, a second write control voltage is applied to the second doped region, and a second reference voltage is applied to the control gate. The second write control voltage is less than the second reference voltage. Electrons are injected from the second doped region through the first sub-region into the semi-floating gate to write logic "0".

[0061] The read operation includes:

[0062] A preset reference voltage is applied to the first doped region, and a third reference voltage is applied to the control gate, the third reference voltage being between the first reference voltage and the second reference voltage. A read control voltage is applied to the second doped region, the read control voltage being a positive voltage less than the first write control voltage. The second doped region responds to whether the first sub-region is turned on to read the data written to the semiconductor device.

[0063] Fourthly, this disclosure provides an electronic device, including a semiconductor device manufactured according to the method for manufacturing a semiconductor device according to the first aspect, or a semiconductor device as described in the second aspect.

[0064] The semiconductor device, fabrication method, access method, and electronic device disclosed herein improve the integration density of memory cells by optimizing the fabrication process and utilizing a third dimension perpendicular to the substrate, thus breaking through the physical limits of two-dimensional planar integration. A semi-floating gate is formed for storing and releasing charges, and a control gate is formed to charge and discharge the semi-floating gate through the quantum tunneling effect to realize data access operations, thereby improving the integration density of the semiconductor device, reducing production costs, and reducing operating power consumption. Attached Figure Description

[0065] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0066] Figure 1 This is a process flow diagram of a method for fabricating a semiconductor device provided in one embodiment.

[0067] Figure 2 This is a top view of the stacked structure provided in one embodiment.

[0068] Figure 3 In one embodiment, after forming the stacked structure along Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0069] Figure 4 In one embodiment, after forming the first trench, along Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0070] Figure 5 In one embodiment, after forming the bit line groove, along Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0071] Figure 6 In one embodiment, after depositing conductive material to fill the bit groove and the first trench, along... Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0072] Figure 7 In one embodiment, after forming the bit line, along Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0073] Figure 8 In one embodiment, after forming the first transverse groove along... Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0074] Figure 9 In one embodiment, after the first insulating layer is filled into the first transverse groove, along... Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0075] Figure 10 In one embodiment, after forming the first isolation groove and the second isolation groove, along Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0076] Figure 11 In one embodiment, after forming the first and second grooves, along Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0077] Figure 12 In one embodiment, after forming the first ion implantation layer along... Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0078] Figure 13 In one embodiment, after forming the third isolation groove along Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0079] Figure 14 In one embodiment, after the third groove is formed, along Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0080] Figure 15 In one embodiment, after forming the second sacrificial layer along... Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0081] Figure 16 In one embodiment, after forming the fourth isolation groove along Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0082] Figure 17 In one embodiment, after the fourth groove is formed, along Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0083] Figure 18 In one embodiment, after forming the floating gate dielectric layer, along Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0084] Figure 19 In one embodiment, after removing the second sacrificial layer along... Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0085] Figure 20 In one embodiment, after forming the floating grid material layer along... Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0086] Figure 21 In one embodiment, after the third sacrificial layer is formed along... Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0087] Figure 22 In one embodiment, the fifth isolation groove is formed along the edge Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0088] Figure 23 In one embodiment, the edge after the fifth groove is formed Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0089] Figure 24 In one embodiment, after removing the floating gate material layer connected to the first sacrificial layer, along... Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0090] Figure 25 In one embodiment, the edge after removing the third sacrificial layer Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0091] Figure 26 In one embodiment, after the control gate dielectric layer is formed, along... Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0092] Figure 27 In one embodiment, after the control gate material layer is formed, along... Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0093] Figure 28 In one embodiment, the edge after forming the control gate Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0094] Figure 29 In one embodiment, after the formation of the second isolation layer, along Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0095] Figure 30 In one embodiment, after removing the first ion implantation layer in the first isolation trench, along... Figure 2Cross-sectional view of lines aa, bb, cc, and dd.

[0096] Figure 31a In one embodiment, after removing the first ion implantation layer in the first trench, along... Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0097] Figure 31b In one embodiment, after removing the first ion implantation layer in the first trench, along... Figure 2 A cross-sectional view of aa.

[0098] Figure 31c In one embodiment, after removing the floating gate material layer connected to the first ion implantation layer, along... Figure 2 A cross-sectional view of aa.

[0099] Figure 32 In one embodiment, the conductive material is deposited along the edge after filling the first isolation trench and the first trench portion. Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0100] Figure 33 In one embodiment, the line after the first electrode line is formed... Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0101] Figure 34 In one embodiment, after removing the first ion implantation layer from the second isolation trench and the second trench portion, along... Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0102] Figure 35 In one embodiment, after the formation of the third isolation layer, along Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0103] Figure 36 This is a schematic diagram of a storage unit provided in one embodiment.

[0104] Figure 37 A top view of a semiconductor device provided in one embodiment.

[0105] Figure 38 This is a process flow diagram of a method for fabricating a semiconductor device provided in another embodiment.

[0106] Figure 39 In another embodiment, the sixth isolation groove is formed along the edge Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0107] Figure 40In another embodiment, the edge after the formation of the sixth groove Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0108] Figure 41 In another embodiment, after the formation of the second ion implantation layer, along Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0109] Figure 42 In another embodiment, the third isolation groove is formed along the edge Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0110] Figure 43 In another embodiment, the edge after the third groove is formed Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0111] Figure 44 In another embodiment, along the path after forming the third ion implantation layer Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0112] Figure 45 In another embodiment, after removing the third ion implantation layer, along Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0113] Figure 46 In another embodiment, after the formation of the second sacrificial layer, along Figure 2 Cross-sectional view of lines aa, bb, cc, and dd.

[0114] Figure 47 A schematic diagram of a storage unit provided for another embodiment.

[0115] Explanation of reference numerals in the attached figures:

[0116] 100, Substrate; 110, Semiconductor layer; 111, First doped region; 112, Second doped region; 113, Third doped region; 114, Fourth doped region; 121, First sacrificial layer; 130, Floating gate dielectric layer; 140, Semi-floating gate; 140a, Floating gate material layer; 150, Control gate dielectric layer; 160, Control gate; 160a, Control gate material layer; 221, Second sacrificial layer; 321, Third sacrificial layer;

[0117] 200. Stacked structure; 171. First isolation layer; 271. Second isolation layer; 371. Third isolation layer; 310. First trench; 320. Bit line groove; 330. First transverse groove; 341. First isolation groove; 342. Second isolation groove; 343. Third isolation groove; 344. Fourth isolation groove; 345. Fifth isolation groove; 346. Sixth isolation groove; 351. First groove section; 352. Second groove section; 353. Third groove section; 354. Fourth groove section; 355. Fifth groove section; 356. Sixth groove section; 411. First ion implantation layer; 412. Second ion implantation layer; 413. Third ion implantation layer;

[0118] A1, storage region; A11, first sub-region; A2, bit line region; BL, bit line; SL, first electrode line; S, source; D, drain; D1, first horizontal direction; D2, second horizontal direction. Detailed Implementation

[0119] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0120] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0121] This disclosure provides a method for fabricating a semiconductor device in exemplary embodiments, referring to... Figure 1 As shown, Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to an exemplary embodiment of the present disclosure is shown. This embodiment does not limit the semiconductor device; the following description will use Dynamic Random Access Memory (DRAM) as an example.

[0122] Reference Figure 1 As shown in some embodiments of this disclosure, a method for fabricating a semiconductor device includes the following steps:

[0123] Step S110: Provide a substrate, and alternately form a first sacrificial layer and a semiconductor layer on the substrate to form a stacked structure, defining at least one memory region in the stacked structure.

[0124] Step S120: Etch away part of the stacked structure to expose the semiconductor layers at both ends of the memory region, and dop the semiconductor layers at both ends of the memory region to form a first doped region and a second doped region at both ends of the memory region.

[0125] Step S130: Define a first sub-region between the first doped region and the second doped region, remove the first sacrificial layer between the first sub-region and the first doped region, and expose the semiconductor layer between the first sub-region and the first doped region.

[0126] Step S140: Form a floating gate dielectric layer, which covers the semiconductor layer between the first sub-region and the first doped region.

[0127] Step S150: Etch the first sub-region to expose the semiconductor layer of the first sub-region.

[0128] Step S160: Form a semi-floating gate, which covers the floating gate dielectric layer and the semiconductor layer of the first sub-region.

[0129] Step S170: Remove the first sacrificial layer between the first sub-region and the second doped region to expose the semiconductor layer between the first sub-region and the second doped region.

[0130] Step S180: A control gate dielectric layer and a control gate are formed sequentially. The control gate dielectric layer covers the semiconductor layer between the first sub-region and the second doped region and the semi-floating gate. The control gate covers the control gate dielectric layer.

[0131] Figures 2-37 This example illustrates schematic diagrams of various stages of a method for fabricating a semiconductor device according to some embodiments of this example. The following is in conjunction with... Figures 2-37 A method for fabricating a semiconductor device according to this exemplary embodiment will be described.

[0132] In step S110, as Figure 2 , Figure 3 As shown, substrate 100 can be a semiconductor substrate, and the material of the semiconductor substrate can include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or other III / V or II / VI semiconductor materials. Alternatively, for example, the semiconductor substrate can be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator.

[0133] The substrate 100 is doped with conductive ions, and the substrate 100 can have a P-type conductivity type or an N-type conductivity type.

[0134] A stacked structure 200 is formed by alternately epitaxially depositing a first sacrificial layer 121 and a semiconductor layer 110 on a substrate 100, or by alternately depositing a first sacrificial layer 121 and a semiconductor layer 110. The number of stacked layers in the stacked structure 200 can be set according to the number of stacked semiconductor devices. The bottom layer and the top layer of the stacked structure 200 are both the first sacrificial layer 121.

[0135] The first sacrificial layer 121 and the semiconductor layer 110 both include semiconductor materials, and the first sacrificial layer 121 has a high etch ratio relative to the semiconductor layer 110. For example, the material of the first sacrificial layer 121 includes germanium silicon, and the material of the semiconductor layer 110 includes single crystal silicon.

[0136] The semiconductor layer 110 is doped with conductive ions and has a first conductivity type, which is either N-type or P-type. In this embodiment, the example of the semiconductor layer 110 having an N-type conductivity type is used for illustration.

[0137] Reference Figure 2 As shown, at least one storage area A1 is defined in the stacked structure 200; in this embodiment, multiple storage areas A1 are defined in the stacked structure 200, each storage area A1 extends along a first horizontal direction D1, and the multiple storage areas A1 are arranged at intervals along a second horizontal direction D2.

[0138] In some embodiments, the following steps are performed before performing step S120:

[0139] Step S101: Define a bit line region on one side of the storage area along the first horizontal direction, etch the bit line region to form a first trench that penetrates the stacked structure, and the first trench extends along the second horizontal direction.

[0140] Reference Figure 2 , Figure 3 As shown, a bit line region A2 is defined on one side of the storage region A1 along the first horizontal direction D1. The bit line region A2 is defined between two storage regions A1 that are spaced apart along the first horizontal direction D1. The bit line region A2 extends along the second horizontal direction D2.

[0141] like Figure 4 As shown, refer to Figure 3 The stacked structure 200 of bit line region A2 is etched away, and a first trench 310 extending along the second horizontal direction D2 is formed in bit line region A2. The first trench 310 vertically penetrates the stacked structure 200 and exposes part of the top surface of substrate 100. Along the first horizontal direction D1, the first trench 310 is spaced apart from the storage regions A1 on both sides.

[0142] Step S102: Etch the semiconductor layer exposed by the first trench to form bit line grooves on the sidewalls of the first trench, the bit line grooves extending along the second horizontal direction.

[0143] like Figure 5 As shown, refer to Figure 4 The semiconductor layer 110 exposed by etching the trench wall of the first trench 310 is removed, and the semiconductor layer 110 of the bit line region A2 is removed, forming a bit line trench 320 extending along the second horizontal direction D2 on the sidewall of the first trench 310.

[0144] For example, the semiconductor layer 110 can be etched using a dry process or a wet process to form bit line grooves 320.

[0145] Step S103: Form a bit line extending along the second horizontal direction in the bit line groove. The bit line is used to connect with the second doped region.

[0146] like Figure 6 As shown, refer to Figure 5 The conductive material can be filled into the bit groove 320 using any of the following deposition processes: Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or sputtering. Then, as... Figure 7 As shown, refer to Figure 6 The conductive material in the first trench 310 is removed by etching, while the conductive material in the bit line trench 320 is retained to form the bit line BL.

[0147] For example, the material of the bit line BL may include at least one of tungsten or tungsten nitride, tantalum or tantalum nitride, or titanium or titanium nitride.

[0148] In this embodiment, after forming the bit line BL, the following steps are also performed:

[0149] Step S104: Etch the first sacrificial layer exposed by the first trench, form a first transverse trench on the sidewall of the first trench, the width of the first transverse trench is greater than the width of the bit line trench along the first horizontal direction, and the first transverse trench extends to the storage area.

[0150] like Figure 8 As shown, refer to Figure 7 Based on the first trench 310, the first sacrificial layer 121 is etched laterally to remove a portion of the first sacrificial layer 121 on both sides of the first trench 310, and a first transverse trench 330 is formed on both sides of the first trench 310. During the etching process to form the first transverse trench 330, the width of the first transverse trench 330 is controlled to be greater than the width of the bit line trench 320, and the portion of the first transverse trench 330 that is wider than the bit line trench 320 extends to the memory area A1.

[0151] In this embodiment, the portion of the first transverse groove 330 that is wider than the bit line groove 320 is located at one end of the storage area A1, and is used to define the positions of the first doped region 111 or the second doped region 112 of the storage area A1 on both sides of the bit line area A2.

[0152] Step S105: Fill the first isolation layer into the first trench and the first transverse groove.

[0153] like Figure 9 As shown, refer to Figure 8 The first isolation layer 171 is an insulating material used for isolation between bit lines and devices in the memory area A1; the material of the first isolation layer 171 has a high etching selectivity relative to the material of the first sacrificial layer 121.

[0154] For example, the first isolation layer 171 can be formed by a deposition process (ALD or CVD), and the material of the first isolation layer 171 includes silicon oxide; or, the first isolation layer 171 can be formed by a spin coating process, and the material of the first isolation layer 171 includes spin-on dielectric (SOD).

[0155] In step S120, a portion of the stacked structure is etched away to expose the semiconductor layers at both ends of the memory region. The semiconductor layers at both ends of the memory region are then doped to form a first doped region and a second doped region at both ends of the memory region. This includes the following steps:

[0156] Step S121: Etch away part of the stacked structure between adjacent memory areas to form a first isolation trench and a second isolation trench between adjacent memory areas.

[0157] like Figure 10 As shown, refer to Figure 2 , Figure 9 A mask layer can be formed above the bit line region A2. The mask layer protects the first isolation layer 171 of the bit line region A2. The mask layer defines a pattern for forming a first isolation trench 341 and a second isolation trench 342. The pattern of the mask layer exposes part of the first isolation layer 171 and the stacked structure 200. The first isolation layer 171 and the stacked structure 200 exposed by the mask layer are removed by etching. A first isolation trench 341 and a second isolation trench 342 are formed between two adjacent memory regions A1. The first isolation trench 341 exposes the semiconductor layer 110 and the first sacrificial layer 121 at one end of the memory region A1, and the second isolation trench 342 exposes the semiconductor layer 110 and the first sacrificial layer 121 at the other end of the memory region A1.

[0158] Step S122: Etch the memory region based on the first isolation trench and the second isolation trench to expose the semiconductor layers at both ends of the memory region.

[0159] like Figure 11 As shown, refer to Figure 2 , Figure 10 The etching process removes the first isolation layer 171 and part of the first sacrificial layer 121 in the memory region A1 by etching the first isolation trench 341 and the second isolation trench 342. The etching process has a high etching selectivity relative to the semiconductor layer 110. At the locations where part of the first sacrificial layer 121 and the first isolation layer 171 are removed at both ends of the memory region A1, a first trench 351 and a second trench 352 are formed respectively. The first trench 351 is connected to the first isolation trench 341 and exposes the semiconductor layer 110 at one end of the memory region A1. The second trench 352 is connected to the second isolation trench 342 and exposes the semiconductor layer 110 at the other end of the memory region A1.

[0160] For example, a dry etching process can be used to etch the first sacrificial layer 121 and the first isolation layer 171 to form the first trench 351 and the second trench 352.

[0161] Step S123: Doping the semiconductor layers exposed at both ends of the storage region to form a first doped region and a second doped region.

[0162] like Figure 12 As shown, refer to Figure 2 , Figure 11 The first ion implantation layer 411 can be deposited using a chemical vapor deposition process. The first ion implantation layer 411 covers the exposed semiconductor layer 110 of the storage region A1 and fills the first trench 351, the second trench 352, the first isolation trench 341 and the second isolation trench 342.

[0163] For example, the material of the first ion implantation layer 411 may include phosphosilicate glass.

[0164] The first ion implantation layer 411 is heat-treated to allow conductive ions in the first ion implantation layer 411 to diffuse into the semiconductor layers 110 at both ends of the storage region A1, as shown in the figure. Figure 2 , Figure 36 , Figure 37 As shown, the concentration of doped ions of the first conductivity type in the semiconductor layer 110 at both ends of the storage region A1 increases, forming a first doped region 111 and a second doped region 112 at both ends of the storage region A1.

[0165] For example, the structure after forming the first ion implantation layer 411 can be placed in an annealing furnace to perform thermal annealing to form the first doped region 111, the second doped region 112 and activate the doped ions.

[0166] In step S130, a first sub-region A11 is defined between the first doped region 111 and the second doped region 112 (refer to...). Figure 2 Or refer to Figure 14The first sub-region A11 and the first doped region 111 are spaced apart, and the second doped region 112 is spaced apart.

[0167] In this embodiment, as Figure 13 As shown, refer to Figure 12 , Figure 36 Before removing the first sacrificial layer 121 between the first sub-region A11 and the first doped region 111, the first sacrificial layer 121 of the first sub-region A11 is etched away to expose the semiconductor layer 110 of the first sub-region A11, and a second sacrificial layer 221 is formed to cover the semiconductor layer 110 of the first sub-region A11.

[0168] The stacked structure 200 between adjacent memory regions A1 is etched to form a third isolation trench 343 between adjacent memory regions A1. For example... Figure 11 , Figure 13 As shown, after the third isolation trench 343 is formed, a first isolation trench 341, a second isolation trench 342 and a third isolation trench 343 are provided between two storage areas A1 that are spaced apart along the second horizontal direction D2. The first isolation trench 341 corresponds to the position of the first doped region 111, the second isolation trench 342 corresponds to the position of the second doped region 112, and the third isolation trench 343 corresponds to the position of the first sub-region A11. The third isolation trench 343 is spaced apart from the first isolation trench 341 and the second isolation trench 342 along the first horizontal direction D1.

[0169] like Figure 14 As shown, refer to Figure 13 Based on the third isolation trench 343, the memory region A1 is etched to remove the first sacrificial layer 121 of the first sub-region A11, exposing the semiconductor layer 110 of the first sub-region A11.

[0170] Then, as Figure 15 As shown, refer to Figure 14 A second sacrificial layer 221 is deposited to form a second sacrificial layer 221, which covers the semiconductor layer 110 of the first sub-region A11 and fills the unfilled areas between the semiconductor layers 110 of the first sub-region A11 and the third isolation trench 343.

[0171] For example, a second sacrificial layer 221 can be formed by chemical vapor deposition.

[0172] For example, the material of the second sacrificial layer 221 may include at least one of silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0173] Then, as Figure 16 As shown, refer to Figure 15The stacked structure 200 between the first isolation trench 341 and the third isolation trench 343 is etched away to form a fourth isolation trench 344, which exposes the storage region A1 between the first sub-region A11 and the first doped region 111.

[0174] like Figure 17 As shown, refer to Figure 16 Based on the fourth isolation trench 344, the storage region A1 is etched, and the first sacrificial layer 121 between the first sub-region A11 and the first doped region 111 is removed by lateral etching to form the fourth trench 354, exposing the semiconductor layer 110 between the first sub-region A11 and the first doped region 111.

[0175] For example, a dry etching process can be used to etch the first sacrificial layer 121 to form the fourth groove 354.

[0176] In step S140, as Figure 18 As shown, refer to Figure 2 , Figure 17 , Figure 36 , Figure 37 A floating gate dielectric layer 130 is formed on the surface of the semiconductor layer 110 between the first sub-region A11 and the first doped region 111.

[0177] For example, an in-situ water vapor oxidation process can be used to form a floating gate dielectric layer 130 on the surface of the semiconductor layer 110 between the first sub-region A11 and the first doped region 111.

[0178] For example, the material of the floating gate dielectric layer 130 may include silicon oxide.

[0179] In step S150, after the floating gate dielectric layer 130 is formed, the second sacrificial layer 221 is removed, exposing the semiconductor layer 110 of the first sub-region A11.

[0180] like Figure 19 As shown, refer to Figure 18 The second sacrificial layer 221 can be removed by wet etching. For example, a phosphoric acid solution can be used as the etching solution.

[0181] In step S160, a semi-floating gate is formed, which covers the floating gate dielectric layer and the semiconductor layer of the first sub-region, including the following steps:

[0182] Step S161: Deposit to form a floating gate material layer, which covers the floating gate dielectric layer, the semiconductor layer of the first sub-region, the first sacrificial layer, and the first ion implantation layer.

[0183] like Figure 20 As shown, refer to Figure 19The material of the floating gate material layer 140a may include a doped semiconductor material. The floating gate material layer 140a has a second conductivity type, which is opposite to the conductivity type of the semiconductor layer 110.

[0184] In this embodiment, the semiconductor layer 110 has an N-type conductivity type, and the floating gate material layer 140a has a P-type conductivity type.

[0185] For example, the floating gate material layer 140a can be a polycrystalline silicon layer doped with P-type conductive ions.

[0186] For example, a floating gate material layer 140a can be formed by chemical vapor deposition.

[0187] Step S162: Etch the floating gate material layer covering the first sacrificial layer and the first ion implantation layer, and the remaining floating gate material layer forms a semi-floating gate.

[0188] To save on process steps, the floating gate material layer 140a covering the first sacrificial layer 121 and the floating gate material layer 140a covering the first ion implantation layer 411 can be etched and removed in different steps. The detailed removal process will be explained in detail in subsequent steps.

[0189] In step S170: First, as Figure 21 As shown, refer to Figure 20 A third sacrificial layer 321 is formed, which covers the floating grid material layer 140a and fills the third isolation groove 343 and the third groove portion 353, and fills the fourth isolation groove 344 and the fourth groove portion 354.

[0190] For example, a third sacrificial layer 321 can be formed using a chemical vapor deposition process.

[0191] For example, the material of the third sacrificial layer 321 may include at least one of silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0192] Then, as Figure 22 As shown, refer to Figure 2 , Figure 21 The stacked structure 200 between the third isolation trench 343 and the second isolation trench 342 is etched away to form the fifth isolation trench 345.

[0193] Next, as Figure 23 As shown, refer to Figure 2 , Figure 22 Based on the fifth isolation trench 345, the storage region A1 is etched laterally to remove the first sacrificial layer 121 between the first sub-region A11 and the second doped region 112, forming the fifth trench 355 and exposing the floating gate material layer 140a connected to the first sacrificial layer 121.

[0194] For example, the first sacrificial layer 121 between the first sub-region A11 and the second doped region 112 can be etched away using a dry or wet process to form the fifth trench 355.

[0195] Next, as Figure 24 As shown, refer to Figure 23 The floating gate material layer 140a connected to the first sacrificial layer 121 is removed by etching.

[0196] For example, a wet etching process can be used to remove the floating gate material layer 140a connected to the first sacrificial layer 121.

[0197] In step S180, firstly, as Figure 25 As shown, refer to Figure 2 , Figure 24 , Figure 36 As shown, the third sacrificial layer 321 is etched away, exposing the semi-floating gate 140 and the semiconductor layer 110 between the first sub-region A11 and the second doped region 112.

[0198] For example, a wet process can be used to remove the third sacrificial layer 321.

[0199] Then, as Figure 26 As shown, refer to Figure 2 , Figure 25 , Figure 36 As shown, a control gate dielectric layer 150 is formed, which covers the semiconductor layer 110 and the semi-floating gate 140 between the first sub-region A11 and the second doped region 112.

[0200] For example, the control gate dielectric layer 150 can be formed using an in-situ water vapor oxidation process.

[0201] For example, the material of the control gate dielectric layer 150 may include silicon oxide.

[0202] Then, as Figure 27 As shown, refer to Figure 2 , Figure 26 , Figure 36 A control gate material layer 160a is formed, which covers the control gate dielectric layer 150 and fills the unfilled areas between semiconductor layers 110 and the unfilled areas between adjacent memory regions A1 (unfilled areas in the third isolation trench 343, the fourth isolation trench 344, the fifth isolation trench 345, the third trench portion 353, the fourth trench portion 354, and the fifth trench portion 355).

[0203] For example, atomic layer deposition (ALD) can be used to deposit the control gate material layer 160a.

[0204] Then, as Figure 28 As shown, refer to Figure 27 The control gate material layer 160a in the third isolation trench 343, the fourth isolation trench 344, and the fifth isolation trench 345 is etched away, and the control gate material layer 160a in the storage area A1 is retained to form the control gate 160.

[0205] For example, the material of the control gate 160 may include at least one of tungsten or tungsten nitride, tantalum or tantalum nitride, or titanium or titanium nitride.

[0206] In this embodiment, the material of the control gate 160 includes titanium nitride.

[0207] Reference Figure 36 As shown, the first doped region 111 serves as the source (S) or drain (D) of the semiconductor device, and the second doped region 112 serves as the drain (D) or source (S) of the semiconductor device.

[0208] The semiconductor device fabrication method of this embodiment improves the integration density of memory cells by optimizing the fabrication process and utilizing the third dimension perpendicular to the substrate, thus breaking through the physical limit of two-dimensional planar integration. A semi-floating gate is formed for storing and releasing charges, and a control gate is formed to charge and discharge the semi-floating gate through the quantum tunneling effect, thereby improving the integration density of the semiconductor device, reducing production costs, and reducing operating power consumption.

[0209] In some embodiments, after forming the control gate, the following steps are also performed: such as Figure 29 As shown, refer to Figure 28 A second isolation layer 271 is deposited, which fills the unfilled areas in the third isolation trench 343, the fourth isolation trench 344, and the fifth isolation trench 345. The second isolation layer 271 is used for electrical insulation of the storage cell SU in the adjacent storage area A1.

[0210] For example, a second isolation layer 271 can be formed by chemical vapor deposition or atomic layer deposition.

[0211] For example, the material of the second isolation layer 271 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0212] In some embodiments, after the control gate is formed, the following steps are also performed:

[0213] Step S191: Etch the stacked structure to expose the first doped region.

[0214] like Figure 30 As shown, refer to Figure 29 The first ion implantation layer 411 in the first isolation trench 341 and the first trench portion 351 is removed by etching, exposing the first doped region 111.

[0215] For example, a dry etching process can be used to etch the first ion implantation layer 411.

[0216] like Figure 31a , Figure 31b As shown, refer to Figure 30 After removing the first ion implantation layer 411 from the first isolation trench 341 and the first trench portion 351, the floating gate material layer 140a connected to the first ion implantation layer 411 is exposed; as Figure 31c As shown, refer to Figure 31b The floating gate material layer 140a connected to the first ion implantation layer 411 is etched away to break the floating gate material layer 140a, forming a plurality of semi-floating gates 140 spaced apart in a direction perpendicular to the substrate 100. (Refer to...) Figure 37 As shown, each semi-floating gate 140 corresponds to the first sub-region A11 of the memory region A1 and the semiconductor layer 110 between the first sub-region A11 and the first doped region 111.

[0217] Step S192: Form a first electrode line, which extends in a direction perpendicular to the substrate and is connected to the first doped region.

[0218] like Figure 32 As shown, refer to Figure 31a A conductive material is deposited to cover the first doped region 111 and fill the first isolation trench 341 and the first trench portion 351.

[0219] For example, conductive materials can be produced using chemical vapor deposition or atomic layer deposition processes.

[0220] Then, as Figure 33 As shown, refer to Figure 32 The conductive material in the first isolation trench 341 is removed by etching, while the conductive material in the first trench 351 is etched and retained to form a first electrode line SL that is spaced along the second horizontal direction D2 and extends perpendicular to the substrate.

[0221] For example, the material of the first electrode line SL may include at least one of tungsten or tungsten nitride, tantalum or tantalum nitride, or titanium or titanium nitride.

[0222] In this embodiment, the material of the first electrode line SL includes tungsten.

[0223] like Figure 34 As shown, refer to Figure 33 The first ion implantation layer 411 in the second isolation trench 342 and the second trench portion 352 is removed by etching, exposing the second isolation trench 342 and the second trench portion 352.

[0224] For example, the first ion implantation layer 411 can be removed by wet etching.

[0225] like Figure 35 As shown, refer to Figure 34 The third isolation layer 371 is formed to fill the first isolation groove 341, the second isolation groove 342 and the second groove portion 352.

[0226] Thus, referring to Figure 35 As shown, in this embodiment, the memory cell SU of the semiconductor device is electrically isolated by the first isolation layer 171, the second isolation layer 271 and the third isolation layer 371, which avoids leakage current or conduction of adjacent devices in the semiconductor junction and helps to improve the electrical performance of the semiconductor device.

[0227] In some other embodiments, the first ion implantation layer 411 in the second isolation trench 342 and the second trench portion 352 may not be removed and may remain in the semiconductor device.

[0228] According to an exemplary embodiment, this embodiment provides a method for fabricating a semiconductor device, referring to... Figure 38 As shown, Figure 38 A flowchart illustrating a method for fabricating a semiconductor device according to an exemplary embodiment of this disclosure is shown. This embodiment does not limit the semiconductor device; the following description will use a dynamic random access memory as an example.

[0229] Reference Figure 38 As shown in some embodiments of this disclosure, a method for fabricating a semiconductor device includes the following steps:

[0230] Step S210: Provide a substrate, and alternately form a first sacrificial layer and a semiconductor layer on the substrate to form a stacked structure, defining at least one memory region in the stacked structure.

[0231] Step S220: Doping the semiconductor layers at both ends of the memory region to form a first doped region and a second doped region at both ends of the memory region.

[0232] Step S230: Define a first sub-region between the first doped region and the second doped region, and dop the semiconductor layer between the first sub-region and the first doped region to form a third doped region connected to the first doped region. The third doped region and the first sub-region are spaced apart.

[0233] Step S240: Doping the semiconductor layer of the first sub-region to form a fourth doped region on the surface of the semiconductor layer of the first sub-region. The fourth doped region is spaced apart from the second doped region and from the third doped region.

[0234] Step S250: Form a second sacrificial layer to protect the fourth doped region.

[0235] Step S260: Form a floating gate dielectric layer, which covers the third doped region and the semiconductor layer between the third doped region and the fourth doped region.

[0236] Step S270: Etch the first sub-region to expose the fourth doped region.

[0237] Step S280: Form a semi-floating gate, which covers the floating gate dielectric layer and the fourth doped region.

[0238] Step S290: Remove the first sacrificial layer between the first sub-region and the second doped region to expose the semiconductor layer between the first sub-region and the second doped region.

[0239] Step S300: A control gate dielectric layer and a control gate are formed sequentially. The control gate dielectric layer covers the semiconductor layer between the first sub-region and the second doped region and the semi-floating gate. The control gate covers the control gate dielectric layer.

[0240] In this embodiment, refer to Figure 47 As shown, the first doped region 111, the second doped region 112, the third doped region 113, and the fourth doped region 114 can be formed using the following embodiments:

[0241] Reference Figure 2 , Figure 12 , Figure 37 The stacked structure 200 is partially etched away, exposing the semiconductor layers 110 at both ends of the memory region A1, and forming a first ion implantation layer 411 covering the semiconductor layers 110 at both ends of the memory region A1.

[0242] Reference Figure 2 , Figures 39-41 The stacked structure 200 is etched away to expose a portion of the semiconductor layer 110 near the end of the memory region A1, and a second ion implantation layer 412 is formed to cover the exposed semiconductor layer 110.

[0243] Reference Figure 2 , Figures 42-44 The stacked structure 200 is etched away to expose the semiconductor layer 110 of the first sub-region A11, and a third ion implantation layer 413 is formed to cover the semiconductor layer 110 of the first sub-region A11.

[0244] Reference Figure 37 , Figure 47 The structure formed by heat treatment to form the third ion implantation layer 413 also forms the first doped region 111, the second doped region 112, the third doped region 113 and the fourth doped region 114.

[0245] In this way, the first doped region 111, the second doped region 112, the third doped region 113 and the fourth doped region 114 can be formed simultaneously through a single heat treatment step. This not only saves process steps and improves process efficiency, but also reduces the damage to semiconductor devices during the heat treatment process, which is beneficial to improving the product yield and electrical performance of semiconductor devices.

[0246] Figures 2-12 , Figures 39-47 , Figures 16-35 This example illustrates schematic diagrams of various stages of a method for fabricating a semiconductor device according to some embodiments of this example. The following is in conjunction with... Figures 2-12 , Figures 39-47 , Figures 16-35 and refer to Figure 37 A method for fabricating a semiconductor device according to this exemplary embodiment will be described.

[0247] In this embodiment, refer to Figures 2-12 Step S210 is implemented in the same way as step S110 in the above embodiments, and will not be described again here.

[0248] The difference between step S220 and step S120 in the above embodiment is only that, referring to Figure 12 As shown, after the first ion implantation layer 411 is formed, the heat treatment step is not performed. The rest of the implementation method is the same as step S120, and will not be described again here.

[0249] In step S230, as Figure 39 As shown, refer to Figure 2 , Figure 12 As shown, etching removes part of the stacked structure 200 between storage areas A1, forming a sixth isolation trench 346 on one side of the first isolation trench 341. Figure 40 As shown, refer to Figure 39 Based on the sixth isolation trench 346, the stacked structure 200 of the memory region A1 is etched, and the first sacrificial layer 121 exposed by the sixth isolation trench 346 is removed by lateral etching to form the sixth trench portion 356. The sixth trench portion 356 exposes a portion of the semiconductor layer 110 connected to the first doped region 111.

[0250] like Figure 41 As shown, refer to Figure 40 A second ion implantation layer 412 is deposited to form a second ion implantation layer 412, which covers the exposed semiconductor layer 110 and fills the sixth trench 356 and the sixth isolation trench 346.

[0251] For example, a chemical vapor deposition process can be used to deposit and form the second ion implantation layer 412. The second ion implantation layer 412 includes doped ions of a second conductivity type, and for example, the material of the second ion implantation layer 412 may include borosilicate glass.

[0252] In step S240, firstly, as Figure 42 As shown, refer to Figure 2 , Figure 37 , Figure 41The stacked structure 200 between adjacent storage areas A1 is etched to form a third isolation trench 343 between adjacent storage areas A1. The third isolation trench 343 corresponds to the position of the first sub-area A11 and is arranged at intervals with the sixth isolation trench 346 and the second isolation trench 342 along the first horizontal direction D1.

[0253] Then, as Figure 43 As shown, refer to Figure 42 Based on the third isolation trench 343, the memory region A1 is etched to remove the first sacrificial layer 121 of the first sub-region A11, exposing the semiconductor layer 110 of the first sub-region A11.

[0254] Next, as Figure 44 As shown, refer to Figure 43 A third ion implantation layer 413 is deposited to form a semiconductor layer 110 covering the first sub-region A11.

[0255] For example, a third ion implantation layer 413 can be formed using a chemical vapor deposition process. The third ion implantation layer 413 includes dopant ions of a second conductivity type; for example, the material of the third ion implantation layer 413 may include borosilicate glass.

[0256] Reference Figure 37 , Figure 44 , Figure 47 After the third ion implantation layer 413 is formed, the structure after the formation of the third ion implantation layer 413 is placed in a furnace tube for annealing treatment, so that the conductive ions in the first ion implantation layer 411, the second ion implantation layer 412, and the third ion implantation layer 413 diffuse into the semiconductor layer 110 they are in contact with. A first doped region 111 and a second doped region 112 are formed at both ends of the semiconductor layer 110 of the storage region A1, respectively. At the same time, a third doped region 113 connected to the first doped region 111 is formed, and a fourth doped region 114 is formed between the third doped region 113 and the second doped region 112. The fourth doped region 114 is spaced apart from the third doped region 113 and the second doped region 112.

[0257] The semiconductor layer 110 deposited on the substrate 100 has a first conductivity type; the first doped region 111 and the second doped region 112 have the same conductivity type as the semiconductor layer 110; the third doped region 113 and the fourth doped region 114 have the opposite conductivity type to the semiconductor layer 110, and the fourth doped region 114 forms a PN junction with the semiconductor layer 110 inside it.

[0258] In this embodiment, the semiconductor layer 110 has an N-type conductivity type, the first doped region 111 and the second doped region 112 have an N-type conductivity type, and the third doped region 113 and the fourth doped region 114 have a P-type conductivity type.

[0259] In step S250, as Figure 45 As shown, refer to Figure 44 The third ion implantation layer 413 is etched away, exposing the fourth doped region 114. Then, as... Figure 46 As shown, refer to Figure 45 A second sacrificial layer 221 is deposited to form a second sacrificial layer 221, which covers the fourth doped region 114 and fills the unfilled areas between the fourth doped regions 114 and the third isolation trench 343.

[0260] Reference Figures 16-35 As shown, the implementation methods of steps S260-S280 are the same as those of steps S160-S180 in the above embodiments, and will not be described again here.

[0261] The semiconductor device fabrication method of this embodiment forms an alternately stacked first sacrificial layer and semiconductor layer on a substrate. By processing the first sacrificial layer and semiconductor layer, memory cells arranged in a direction perpendicular to the substrate are formed. The memory cells are horizontal devices extending parallel to the substrate. By utilizing the third dimension perpendicular to the substrate, the integration density of the semiconductor device is improved, which is beneficial to improving the read and write speed of the semiconductor device and reducing the operating power consumption.

[0262] The method for fabricating the semiconductor device in this embodiment also includes the following steps:

[0263] Step S201: Form a bit line, which extends along the second horizontal direction and is connected to the second doped region.

[0264] Reference Figure 37 As shown, the implementation method for forming the bit line BL is the same as the above embodiment, and will not be repeated here.

[0265] Step S202: Form a first electrode line, which is vertically disposed on the substrate and connected to the first doped region.

[0266] Reference Figure 37 As shown, the implementation method for forming the first electrode line SL is the same as the above embodiment. The first ion implantation layer 411 in the first isolation trench 341 and the first trench portion 351 is removed to expose the first doped region 111. Then, a conductive material is deposited to fill the first isolation trench 341 and the first trench portion 351. Finally, the conductive material in the first isolation trench 341 is etched away, while the conductive material in the first trench portion 351 is etched and retained. The conductive material in the first trench portion 351 and the first doped region 111 are connected to form the first electrode line SL, which is disposed perpendicular to the substrate 100.

[0267] According to an exemplary embodiment, this embodiment provides a semiconductor device, such as... Figure 36 , Figure 37 , Figure 47 As shown, the semiconductor device includes a substrate 100 and a plurality of memory cells SU spaced apart on the substrate 100 along a direction perpendicular to the substrate 100; each memory cell SU includes a semiconductor layer 110, a floating gate dielectric layer 130, a semi-floating gate 140, a control gate dielectric layer 150, and a control gate 160. The semiconductor layer 110 includes a first doped region 111 and a second doped region 112 disposed at its two ends, and a first sub-region A11 disposed between the first doped region 111 and the second doped region 112; the floating gate dielectric layer 130 covers the semiconductor layer 110 between the first sub-region A11 and the first doped region 111; the semi-floating gate 140 covers the semiconductor layer 110 between the floating gate dielectric layer 130 and the first sub-region A11; the control gate dielectric layer 150 covers the semiconductor layer 110 between the first sub-region A11 and the second doped region 112 and the semi-floating gate 140; and the control gate 160 covers the control gate dielectric layer 150.

[0268] The semiconductor device in this embodiment utilizes the third dimension perpendicular to the substrate 100 to integrate the memory cell SU, thereby increasing the integration density of the semiconductor device and improving the read / write speed and reducing the operating power consumption of the semiconductor device.

[0269] The semiconductor device in this embodiment has a capacitor-free structure. The storage cell SU uses a semi-floating gate 140 to store charge, which can realize the function of traditional dynamic random access memory without capacitors, greatly reducing costs, increasing integration, and improving read and write speeds.

[0270] In this embodiment, the size of the memory cell SU is smaller than that of the DRAM cell with a capacitor structure, which is beneficial for breaking through the current bottleneck in the development of integrated circuits and sustainably continuing Moore's Law.

[0271] In some embodiments, such as Figure 36 , Figure 37 , Figure 47 As shown, the semiconductor layer 110 has a first conductivity type, and the first doped region 111, the second doped region 112 and the semiconductor layer 110 have the same conductivity type.

[0272] The first doped region 111 serves as the source (S) or drain (D) of the semiconductor device, and the second doped region 112 serves as the drain (D) or source (S) of the semiconductor device. Thus, the semiconductor device of this embodiment has a simpler structure, is easier to manufacture, and has a lower cost.

[0273] In some embodiments, such as Figure 37 , Figure 47As shown, the semiconductor layer 110 also includes a third doped region 113, which is disposed between the first sub-region A11 and the first doped region 111. The third doped region 113 is connected to the first doped region 111 and spaced apart from the first sub-region A11. The conductivity type of the third doped region 113 is opposite to that of the semiconductor layer 110.

[0274] In this embodiment, the semiconductor layer 110, the first doped region 111, and the second doped region 112 have N-type conductivity; the third doped region 113 has P-type conductivity.

[0275] In some embodiments, the semiconductor layer 110 further includes a fourth doped region 114, which is disposed on the surface of the semiconductor layer 110 in the first sub-region A11. The fourth doped region 114 is disposed spaced apart from the second doped region 112 and from the third doped region 113. The fourth doped region 114 and the semiconductor layer 110 have opposite conductivity types, and the fourth doped region 114 forms a PN junction with the semiconductor layer 110 inside it.

[0276] Thus, the third doped region 113 and the fourth doped region 114, which have the second conductivity type, are separated by a semiconductor layer 110 with the first conductivity type, which prevents the semiconductor device from performing a read operation. The fourth doped region 114 and the third doped region 113 are not connected, which leads to the problem that the read operation cannot be performed accurately.

[0277] The semiconductor device in this embodiment includes an integrated MOSFET and a semi-floating gate transistor with TFET and SFGT structures. The quantum tunneling bandgap of the semi-floating gate transistor occurs within a silicon material of only 1.1 eV. The tunneling barrier is low, making data erasure and writing of the semiconductor device easier and faster. The entire process can be completed under low voltage conditions, creating conditions for achieving low-power operation of the semiconductor device.

[0278] In some embodiments, the memory cells SU extend along a first horizontal direction D1, and a plurality of memory cells SU are arranged at intervals along a second horizontal direction D2; the semiconductor device further includes a bit line BL, which is disposed on one side of the memory cells SU along the first horizontal direction D1, extends along the second horizontal direction D2, and connects a row of second doped regions 112 of memory cells SU.

[0279] The semiconductor device also includes a first electrode line SL, which is disposed on the side of the memory cell SU away from the bit line BL. The first electrode line SL is perpendicularly disposed on the substrate 100 and connects to the first doped regions 111 of a plurality of memory cells SU disposed in a direction perpendicular to the substrate 100.

[0280] In some embodiments, the memory cells SU arranged in a direction perpendicular to the substrate 100 are connected to a control gate 160 to form a word line WL.

[0281] The semiconductor device of this embodiment makes full use of the application area of ​​the substrate 100 to arrange memory cells SU along the first horizontal direction D1, the second horizontal direction D2 and along the direction perpendicular to the substrate 100, thereby improving the integration density of the semiconductor device and reducing the cost of the semiconductor device.

[0282] According to an exemplary embodiment, this disclosure provides a method for accessing a semiconductor device, including performing write control operations and read operations on the semiconductor device.

[0283] The write control operations include:

[0284] A preset reference voltage is applied to the first doped region, such as grounding or applying a fixed reference voltage of 0V. A first write control voltage is applied to the second doped region, and a first reference voltage is applied to the control gate. If the first write control voltage is greater than the first reference voltage, holes tunnel from the second doped region through the first sub-region into the semi-floating gate, writing logic "1". If the first write control voltage is positive and the first reference voltage is 0 or negative, the second doped region is positively charged. If the voltage difference between the first write control voltage and the first reference voltage is greater than the tunneling voltage between the second doped region and the semiconductor layer covered by the semi-floating gate, holes from the second doped region are injected into the semiconductor layer covered by the semi-floating gate and into the semi-floating gate. The number of holes in the semi-floating gate increases, writing logic "1".

[0285] A preset reference voltage is applied to the first doped region, such as grounding or applying a fixed reference voltage of 0V. A second write control voltage is applied to the second doped region, and a second reference voltage is applied to the control gate. If the second write control voltage is less than the second reference voltage, electrons are injected from the second doped region into the semi-floating gate through the first sub-region, writing logic "0". If the second write control voltage is negative and the second reference voltage is positive, the second doped region becomes negatively charged. Electrons from the second doped region are injected into the semiconductor layer covered by the semi-floating gate and into the semi-floating gate, increasing the number of electrons in the semi-floating gate and writing logic "0".

[0286] Read operations include:

[0287] A preset reference voltage is applied to the first doped region, such as grounding or applying a fixed reference voltage of 0V. A third reference voltage is applied to the control gate, which is between the first and second reference voltages. A read control voltage is applied to the second doped region, which is a positive voltage less than the first write control voltage. The second doped region responds to whether the first sub-region is turned on to read the data written to the semiconductor device. If the semiconductor device is turned on, a logic "1" is read; if the semiconductor device is not turned on, a logic "0" is read.

[0288] According to an exemplary embodiment, this embodiment provides an electronic device, including a semiconductor device manufactured according to the semiconductor device manufacturing method in the above embodiments, or the semiconductor device in the above embodiments. The electronic device can be a mobile phone, computer, tablet computer, television, artificial intelligence device, etc.

[0289] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0290] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided on which a first sacrificial layer and a semiconductor layer are alternately formed to form a stacked structure, wherein at least one storage region is defined in the stacked structure; Etching removes part of the stacked structure, exposing the semiconductor layers at both ends of the memory region, and doping the semiconductor layers at both ends of the memory region to form a first doped region and a second doped region at both ends of the memory region; A first sub-region is defined between the first doped region and the second doped region, and the first sacrificial layer between the first sub-region and the first doped region is removed to expose the semiconductor layer between the first sub-region and the first doped region. A floating gate dielectric layer is formed, which covers the semiconductor layer between the first sub-region and the first doped region; The first sub-region is etched to expose the semiconductor layer of the first sub-region; A semi-floating gate is formed, the semi-floating gate covering the floating gate dielectric layer and the semiconductor layer of the first sub-region; Remove the first sacrificial layer between the first sub-region and the second doped region to expose the semiconductor layer between the first sub-region and the second doped region; A control gate dielectric layer and a control gate are formed sequentially. The control gate dielectric layer covers the semiconductor layer between the first sub-region and the second doped region and the semi-floating gate. The control gate covers the control gate dielectric layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The storage area extends along a first horizontal direction, and the plurality of storage areas are arranged at intervals along a second horizontal direction; Before etching away a portion of the stacked structure to expose the semiconductor layers at both ends of the memory region, the process further includes: A bit line region is defined on one side of the storage area along the first horizontal direction, and the bit line region is etched to form a first trench that penetrates the stacked structure. The first trench extends along the second horizontal direction. The semiconductor layer exposed by the first trench is etched to form a bit line groove on the sidewall of the first trench, the bit line groove extending along the second horizontal direction; A bit line extending along the second horizontal direction is formed in the bit line groove, and the bit line is used to connect with the second doped region.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, After forming a bit line extending along the second horizontal direction in the bit line groove, the method further includes: The first sacrificial layer exposed by the first trench is etched, and a first transverse trench is formed on the sidewall of the first trench. Along the first horizontal direction, the width of the first transverse trench is greater than the width of the bit line trench, and the first transverse trench extends to the storage area. A first isolation layer is filled into the first trench and the first transverse groove.

4. The method for fabricating a semiconductor device according to claim 2, characterized in that, After forming the control gate, the following is also included: The stacked structure is etched to expose the first doped region; A first electrode line is formed, which is vertically disposed on the substrate and connected to the first doped region.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The semiconductor layers at both ends of the memory region are doped to form a first doped region and a second doped region at both ends of the memory region, including: Etching removes a portion of the stacked structure between adjacent memory regions, forming a first isolation trench and a second isolation trench between adjacent memory regions; Based on the first isolation trench and the second isolation trench, the memory region is etched to expose the semiconductor layers at both ends of the memory region; The semiconductor layer exposed at both ends of the storage region is doped to form the first doped region and the second doped region.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, Before removing the first sacrificial layer between the first sub-region and the first doped region, the first sacrificial layer of the first sub-region is etched away to expose the semiconductor layer of the first sub-region, and a second sacrificial layer is formed to cover the semiconductor layer of the first sub-region. After the floating gate dielectric layer is formed, the second sacrificial layer is removed to expose the semiconductor layer of the first sub-region.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The manufacturing method further includes: The semiconductor layer between the first sub-region and the first doped region is doped to form a third doped region connected to the first doped region, and the third doped region is spaced apart from the first sub-region.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The manufacturing method further includes: The semiconductor layer of the first sub-region is doped to form a fourth doped region on the surface of the semiconductor layer of the first sub-region. The fourth doped region is spaced apart from the second doped region and from the third doped region.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The semiconductor layer deposited on the substrate has a first conductivity type; The first doped region and the second doped region have the same conductivity type as the semiconductor layer; The third doped region and the fourth doped region have the opposite conductivity type to the semiconductor layer, and the fourth doped region forms a PN junction with the semiconductor layer inside it.

10. The method for fabricating a semiconductor device according to claim 8, characterized in that, The manufacturing method includes: Etching removes part of the stacked structure, exposing the semiconductor layers at both ends of the memory region, and forming a first ion implantation layer covering the semiconductor layers at both ends of the memory region; Etching removes a portion of the stacked structure, exposing a portion of the semiconductor layer near one end of the storage region, and forming a second ion implantation layer to cover the exposed semiconductor layer; Etching removes part of the stacked structure, exposing the semiconductor layer of the first sub-region, and forming a third ion implantation layer to cover the semiconductor layer of the first sub-region; The structure formed after heat treatment to form the third ion implantation layer also forms the first doped region, the second doped region, the third doped region, and the fourth doped region.

11. A semiconductor device, characterized in that, The system includes a substrate and a plurality of memory cells spaced apart on the substrate along a direction perpendicular to the substrate, each memory cell comprising: A semiconductor layer, the semiconductor layer including a first doped region and a second doped region disposed at both ends thereon, and a first sub-region disposed between the first doped region and the second doped region; A floating gate dielectric layer, the floating gate dielectric layer covering the semiconductor layer between the first sub-region and the first doped region; A semi-floating gate, the semi-floating gate covering the floating gate dielectric layer and the semiconductor layer of the first sub-region; A control gate dielectric layer covers the semiconductor layer and the semi-floating gate between the first sub-region and the second doped region; A control gate, covering the control gate dielectric layer.

12. The semiconductor device according to claim 11, characterized in that, The semiconductor layer has a first conductivity type, and the first doped region, the second doped region, and the semiconductor layer have the same conductivity type.

13. The semiconductor device according to claim 12, characterized in that, The semiconductor layer further includes: A third doped region is disposed between the first sub-region and the first doped region. The third doped region is connected to the first doped region and spaced apart from the first sub-region. The conductivity type of the third doped region is opposite to that of the semiconductor layer.

14. The semiconductor device according to claim 13, characterized in that, The semiconductor layer further includes: A fourth doped region is disposed on the surface of the semiconductor layer in the first sub-region. The fourth doped region is spaced apart from the second doped region and from the third doped region. The fourth doped region has an opposite conductivity type to the semiconductor layer. The fourth doped region forms a PN junction with the semiconductor layer inside it.

15. The semiconductor device according to any one of claims 11-14, characterized in that, The memory cells extend along a first horizontal direction, and a plurality of the memory cells are spaced apart along a second horizontal direction; the semiconductor device further includes: Bit lines are disposed on one side of the memory cell along the first horizontal direction, the bit lines extend along the second horizontal direction, and the bit lines connect the second doped regions of the plurality of memory cells arranged along the second horizontal direction; A first electrode line is disposed on the side of the memory cell away from the bit line. The first electrode line is perpendicularly disposed on the substrate. The first electrode line connects to the first doped regions of a plurality of memory cells disposed in a direction perpendicular to the substrate.

16. The semiconductor device according to any one of claims 11-14, characterized in that, The memory cells are arranged in a direction perpendicular to the substrate, and the control gate connections form word lines.

17. A method for accessing a semiconductor device, characterized in that, This includes performing write control operations and read operations on the semiconductor device; The write control operation includes: A preset reference voltage is applied to the first doped region, a first write control voltage is applied to the second doped region, and a first reference voltage is applied to the control gate. The first write control voltage is greater than the first reference voltage. Holes tunnel through the first sub-region from the second doped region and inject into the semi-floating gate, writing logic "1". A preset reference voltage is applied to the first doped region, a second write control voltage is applied to the second doped region, and a second reference voltage is applied to the control gate. The second write control voltage is less than the second reference voltage. Electrons are injected from the second doped region through the first sub-region into the semi-floating gate to write logic "0". The read operation includes: A preset reference voltage is applied to the first doped region, and a third reference voltage is applied to the control gate, the third reference voltage being between the first reference voltage and the second reference voltage. A read control voltage is applied to the second doped region, the read control voltage being a positive voltage less than the first write control voltage. The second doped region responds to whether the first sub-region is turned on to read the data written to the semiconductor device.

18. An electronic device, characterized in that, This includes semiconductor devices manufactured by the method of manufacturing a semiconductor device according to any one of claims 1-10, or semiconductor devices according to any one of claims 11-16.

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