A back contact cell and a method for making a back contact cell

Abstract

The application belongs to the technical field of back contact cells, and particularly relates to a back contact cell back texturing manufacturing method and a cell thereof, which comprises the following steps: S2, forming a first semiconductor layer on the back of a silicon wafer, and simultaneously naturally forming a phosphorus silicon glass layer as a mask layer; S3, forming a second semiconductor opening area on the back; S4, performing full-face etching on the front of the silicon wafer by means of laser scribing, so as to remove the mask layer wrap layer on the front and dope at least part of phosphorus in the silicon wafer; and S5, performing texturing cleaning, and then removing the mask layer. The application can simplify the process flow (i.e. reduce one wet cleaning), reduce the material cost, ensure that the mask layer wrap layer on the front is completely etched without residue, effectively reduce the damage to the back film layer, effectively avoid the risk of wet etching of the back passivation film layer, and provide a certain field passivation effect for the front phosphorus doping of the cell, enhance the overall passivation effect of the front and back of the cell, and then improve the cell efficiency.

Description

Technical Field

[0001] This invention belongs to the field of back contact battery technology, specifically relating to a post-texturing method for manufacturing a back contact battery and the battery thereof. Background Technology

[0002] Currently, the lowest-cost manufacturing process for back-contact batteries is generally the post-texturing process, which includes:

[0003] S101, a silicon wafer with a double-sided polished structure;

[0004] S102. A first semiconductor layer is deposited on the back side of the silicon wafer, and the naturally formed PSG layer is removed. Then a mask layer is formed on the back side, during which a front-side wrap-around layer is naturally formed on the front side. The mask layer may include, for example, silicon nitride, silicon oxynitride, silicon oxide, etc.

[0005] S103. Laser or etch an opening on the back of the silicon wafer to remove the mask layer and part of the first semiconductor layer, forming a second semiconductor opening area; then use chain cleaning to clean the front-side coating.

[0006] S104. Silicon wafer texturing and cleaning: remove the first semiconductor layer and mask layer in the second semiconductor opening area, and form a textured surface on the front side of the silicon wafer and the second semiconductor opening area.

[0007] S105. A third semiconductor layer is formed on the front side, the third semiconductor layer including a front passivation layer and an anti-reflection layer;

[0008] S106. Remove the back-side coating and clean the second semiconductor opening area for further purification.

[0009] S107, A second semiconductor layer is formed on the back side of the silicon wafer;

[0010] S108, Laser or etched openings on the back of the silicon wafer to form first semiconductor opening regions that are alternately arranged with the second semiconductor opening region;

[0011] S109, Conductive film deposited on the back of silicon wafer;

[0012] S110. An isolation trench is formed between the first semiconductor opening region and the second semiconductor opening region by means of laser or etching.

[0013] S111, Metal electrodes are formed on the first semiconductor opening region and the second semiconductor opening region of the silicon wafer.

[0014] However, in the prior art, after the second semiconductor opening region is formed, the chain cleaning method used is a wet etching method to remove the mask layer around the plating layer on the front side. At the same time, the water film protection quality of the chain cleaning method directly affects the protection performance of the back mask layer on the first semiconductor layer corresponding to the non-second semiconductor opening region. It may damage the surface mask layer, causing damage to the first semiconductor layer during subsequent texturing and cleaning, thereby reducing the battery efficiency.

[0015] It should be noted that this part of the present invention only provides background technology related to the present invention, and does not necessarily constitute prior art or known technology. Summary of the Invention

[0016] The purpose of this invention is to overcome the shortcomings of existing back-contact battery texturing methods, which result in low battery efficiency due to the removal of the front-side coating in the process of removing the front-side coating. This invention provides a back-contact battery texturing method and battery thereof. This invention simplifies the process (i.e., reduces one wet cleaning step) and lowers material costs, while ensuring that the front-side mask coating is completely etched without residue, effectively reducing damage to the back-side film, effectively avoiding the risk of wet corrosion of the back-side passivation film, and also providing a certain field passivation effect for phosphorus doping on the front side of the battery, enhancing the overall passivation effect of the front and back sides of the battery, thereby improving battery efficiency.

[0017] To achieve the above objectives, in a first aspect, the present invention provides a method for fabricating a back contact battery by post-texturing, comprising the following steps:

[0018] S1. Provides double-sided polished silicon wafers;

[0019] S2. A first semiconductor layer containing an N-type doped layer is formed on the back side of the silicon wafer, and a phosphorosilicate glass layer is naturally formed as a mask layer.

[0020] S3. Make a first etching opening on the back film layer obtained in S2 to form a second semiconductor opening region;

[0021] S4. Using laser scribing, the entire front surface of the silicon wafer is etched to remove the mask layer coating and to dope at least a portion of the phosphorus in the mask layer into the silicon wafer; wherein the final overall area of ​​the laser scribing is controlled to be larger than the area of ​​the front surface of the silicon wafer, and during the entire surface etching process, the overlap rate of adjacent laser spots in the horizontal scribing direction is controlled to be ≥50%, and the overlap rate of two adjacent scribing lines in the vertical scribing direction is controlled to be ≥50%;

[0022] S5. Perform texturing and cleaning to form pyramidal textured surfaces on the front side of the silicon wafer and in the second semiconductor opening area, and then remove the mask layer.

[0023] S6. A passivation layer and an anti-reflection layer are deposited on the front side of the silicon wafer, and a second semiconductor layer is deposited on the back side.

[0024] In some preferred embodiments of the present invention, in S4, the conditions for laser marking include: the power of the laser is 80W-200W and the frequency is 400kHz-1000kHz.

[0025] In some preferred embodiments of the present invention, in S4, the laser pulse width used for laser marking is less than 20 ps.

[0026] In some preferred embodiments of the present invention, in S4, the laser wavelength is 350-550nm.

[0027] In some preferred embodiments of the present invention, in S4, the laser scribing employs a flat-top picosecond green laser or a flat-top picosecond ultraviolet laser.

[0028] In some preferred embodiments of the present invention, in S4, the laser marking speed is controlled to be 34800mm / s-55000mm / s.

[0029] In some preferred embodiments of the present invention, in S4, the length of the final overall area occupied by the laser etched is greater than the length of the front side of the silicon wafer, and the width of the final overall area occupied by the laser etched is greater than the width of the front side of the silicon wafer.

[0030] In some preferred embodiments of the present invention, the first semiconductor layer in S2 further includes a tunneling oxide layer disposed between the silicon wafer and the N-type doped layer, and / or, the second semiconductor layer in S6 is an intrinsic silicon layer and a P-type doped silicon layer.

[0031] In some preferred embodiments of the present invention, the post-texturing method for the back contact battery further includes:

[0032] S7. A second etching opening is made on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

[0033] S8. Clean the back side obtained in S7 and deposit a conductive film layer.

[0034] S9. A third etched opening is made on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench.

[0035] S10. Metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0036] Secondly, the present invention provides a back contact battery, which is manufactured by the post-texturing method for back contact batteries described in the first aspect.

[0037] Beneficial effects:

[0038] This invention, through the above-mentioned technical solution, particularly by using a phosphorosilicate glass layer naturally formed after diffusion during the formation of the N-type doped layer as a mask layer, eliminates the need for a rewash in step S2, thus ensuring PSG mask layers on both the front and back sides. Furthermore, after forming the second semiconductor opening region, step S4 removes the front-side coating using a dry method of laser etching and full-surface etching. By controlling the final overall area of ​​the laser etching to be larger than the front area of ​​the silicon wafer and ensuring that the lateral and longitudinal overlap rates are both ≥50%, it is possible to guarantee that the front-side mask layer is completely etched without residue. This method is significantly more efficient than conventional chain cleaning. This invention presents a dry etching method for removing the front-side coating. This method is entirely non-contact, effectively reducing mechanical damage to the back-side film and mitigating the risks of wet etching of the back-side passivation film, thus improving battery efficiency. Furthermore, the invention uses laser etching to etch the entire front side of the battery, and can also use laser to dope part of the phosphorus in the front-side phosphorus-silicon glass mask layer into the bulk silicon (silicon wafer), providing appropriate doping to the front side of the silicon wafer and offering a certain field passivation effect. This enhances the overall passivation effect of the front and back sides of the battery, further improving battery efficiency. Simultaneously, the dry etching method simplifies the process, eliminates the need for chemicals, and reduces one wet etching step, lowering material costs and better protecting the back-side passivation film (i.e., the first semiconductor layer). Under the same conditions, if the final total area of ​​the laser etching is less than or equal to the front-side area of ​​the silicon wafer, a complete textured surface cannot be formed on the front side, leading to a decrease in battery efficiency. Under the same conditions, if the lateral or longitudinal overlap rate is less than 50%, the front-side etching will be incomplete, leaving residue, thus reducing battery efficiency. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 These are schematic diagrams of laser spot distribution structures used in some specific embodiments of the present invention, wherein A is a schematic diagram of a single-row laser spot structure and B is a schematic diagram of a structure with a lateral overlap rate of 50% for laser spots.

[0041] Figure 2 This is a schematic diagram of the final overall area of ​​laser marking and the front area of ​​the silicon wafer in a specific embodiment of the present invention, where C is the edge of the front of the silicon wafer. Detailed Implementation

[0042] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0043] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0044] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of the ranges, the endpoint values ​​of the ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. The terms "optional" and "optional" mean that they may or may not be included (or may or may not be present).

[0045] In this invention, the area closer to the silicon wafer is considered the inside, and the area farther from the silicon wafer is considered the outside.

[0046] In a first aspect, the present invention provides a method for post-texturing a back contact battery, comprising the following steps:

[0047] S1. Provides double-sided polished silicon wafers;

[0048] S2. A first semiconductor layer containing an N-type doped layer is formed on the back side of the silicon wafer, and a phosphorosilicate glass layer is naturally formed as a mask layer.

[0049] S3. Make a first etching opening on the back film layer obtained in S2 to form a second semiconductor opening region;

[0050] S4. Using laser scribing, the entire front side of the silicon wafer is etched to remove the mask layer coating on the front side and to dope at least part of the phosphorus in the mask layer into the silicon wafer.

[0051] S5. Perform texturing and cleaning to form pyramidal textured surfaces on the front side of the silicon wafer and in the second semiconductor opening area, and then remove the mask layer.

[0052] S6. A passivation layer and an anti-reflection layer are deposited on the front side of the silicon wafer, and a second semiconductor layer is deposited on the back side.

[0053] In this invention, S4 uses laser etching to etch the entire front side of the battery. This not only removes the mask layer coating in a non-contact manner, but also uses laser to dope part of the phosphorus in the front phosphorus-silicon glass mask layer into the bulk silicon, i.e., the silicon wafer. This provides a suitable doping effect on the front side of the silicon wafer, provides a certain field passivation effect on the front side of the battery, enhances the overall passivation effect of the front and back of the battery, and further improves the battery efficiency.

[0054] Preferably, in step S4, the final overall area of ​​the laser marking is larger than the front area of ​​the silicon wafer, meaning the laser processing area is larger than the size of the silicon wafer. This preferred approach helps ensure complete processing of the front side of the silicon wafer.

[0055] In some preferred embodiments of the present invention, during the S4 full-surface etching process, the overlap rate of adjacent laser spots in the transverse scribing direction is controlled to be ≥50%. Using a preferred laser process with a suitable overlap rate of transverse spots facilitates complete opening of the transverse scribing.

[0056] Preferably, in this invention, the overlap rate of two adjacent scribing lines in the longitudinal scribing direction is ≥50%. Using a preferred laser process for longitudinal scribing with an appropriate overlap rate ensures complete openings between scribing lines without residue.

[0057] In this invention, the overlap rate is calculated as the ratio of the overlapping portion of two adjacent processing units (processing units are laser spots or scribing lines) to the size of a single processing unit.

[0058] In this invention, the overlap rate of adjacent laser spots in the horizontal scribing direction and the overlap rate of two adjacent scribing lines in the vertical scribing direction can be the same or different, preferably the same, which is more conducive to ensuring that the front side is processed in place and that there is no mask layer or coating residue.

[0059] In some preferred embodiments of the present invention, in S4, the conditions for laser marking include: the power of the laser is 80W-200W, specifically 80W, 90W, 100W, 110W, 120W, 130W, 140W, 150W, 160W, 170W, 180W, 190W or 200W, and the range between any two point values; and / or, the frequency of laser marking is controlled to be 400kHz-1000kHz, specifically 400kHz, 450kHz, 500kHz, 550kHz, 600kHz, 650kHz, 700kHz, 750kHz, 800kHz, 850kHz, 900kHz, 950kHz, 990kHz or 1000kHz, and the range between any two point values. This preferred approach allows for sufficient pulse energy to thoroughly remove the mask layer coating while minimizing damage to the front-side silicon.

[0060] Preferably, in S4, the laser pulse width used for laser marking is less than 20 ps.

[0061] Preferably, in S4, the laser wavelength is 350-550nm.

[0062] In some preferred embodiments of the present invention, in S4, the laser scribing uses a flat-top picosecond green laser or a flat-top picosecond ultraviolet laser, which is more conducive to reducing damage to the front-side silicon while removing the mask layer coating.

[0063] In some preferred embodiments of the present invention, in S4, the laser marking speed is controlled to be 34800mm / s-55000mm / s, specifically 34800mm / s, 35000mm / s, 35500mm / s, 36000mm / s, 36500mm / s, 37000mm / s, 37500mm / s, 38000mm / s, 38500mm / s, 39000mm / s, 40000mm / s, 42000mm / s, 45000mm / s, 47000mm / s, 50000mm / s, 51000mm / s, 52000mm / s, 53000mm / s, 54000mm / s, or 55000mm / s, as well as any range between two point values. The preferred embodiment of the present invention is more conducive to promoting appropriate doping of the front side of the silicon wafer, and provides a better field passivation effect on the front side of the battery.

[0064] In some preferred embodiments of the present invention, in S4, the length of the final overall area occupied by the laser marking is greater than the length of the front side of the silicon wafer, and the width of the final overall area occupied by the laser marking is greater than the width of the front side of the silicon wafer. This preferred approach facilitates a more thorough and complete removal of the front-side coating in both the length and thickness directions of the silicon wafer, while simultaneously achieving uniform phosphorus doping on the front side of the silicon wafer.

[0065] Preferably, in step S2, the first semiconductor layer further includes a tunneling oxide layer disposed between the silicon wafer and the N-type doped layer. More preferably, the N-type doped layer is an N-type doped polycrystalline silicon layer.

[0066] Preferably, in step S6, the second semiconductor layer is an intrinsic silicon layer and a P-type doped silicon layer. The P-type doped silicon layer can be doped amorphous silicon or microcrystalline silicon. The intrinsic silicon layer is preferably an intrinsic silicon layer.

[0067] In some preferred embodiments of the present invention, in S2, the first semiconductor layer is controlled to be a tunneling oxide layer and an N-type doped polycrystalline silicon layer, and in S6, the second semiconductor layer is an intrinsic silicon layer and a P-type doped silicon layer. This preferred passivation scheme employing a combined passivation structure is more conducive to improving battery efficiency. The intrinsic silicon layer is preferably an intrinsic amorphous silicon layer.

[0068] The thicknesses and corresponding doping concentrations of the tunneling oxide layer or intrinsic silicon layer, the N-type doped polysilicon layer, and the P-type doped silicon layer described in this invention can all refer to the ranges of existing technologies and can all be used in this invention. For example, the thickness of the tunneling oxide layer is 1-2 nm, the thickness of the intrinsic silicon layer is 5-15 nm, and the thickness of the P-type doped silicon layer is 7-45 nm with an effective doping concentration of 2e18 cm⁻¹. -3 -3e20cm -3 The thickness of the N-type doped polycrystalline silicon layer is 80-200 nm, and the effective doping concentration is greater than 5e18 cm⁻¹. -3 .

[0069] This invention may also include other conventional structures and steps. In some preferred embodiments of this invention, the post-texturing method for the back contact battery further includes:

[0070] S7. A second etching opening is made on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

[0071] S8. Clean the back side obtained in S7 and deposit a conductive film layer.

[0072] S9. A third etched opening is made on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench.

[0073] S10. Metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0074] Secondly, the present invention provides a back contact battery, which is manufactured by the post-texturing method for back contact batteries described in the first aspect. The back contact battery of the present invention has a completely intact back film layer and moderate doping on the front side, which is beneficial to improving the overall passivation effect of both the front and back sides, thereby improving battery efficiency.

[0075] The embodiments of the present invention described below are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0076] Example 1

[0077] A back-contact battery, the manufacturing method of which is as follows:

[0078] S1, Double-sided polishing of silicon wafers;

[0079] S2. A first semiconductor layer is deposited on the back of the silicon wafer. The first semiconductor layer is a tunneling oxide layer (1.5 nm thick) and an N-type doped polysilicon layer (100 nm thick, with an effective doping concentration of 9e19cm). -3 During the formation of the N-type doped polycrystalline silicon layer, phosphosilicate glass layers are naturally formed on both the front and back sides, with the phosphosilicate glass layer on the back side serving as a mask layer.

[0080] S3. An opening is made on the back side of the silicon wafer, and the mask layer and part of the first semiconductor layer are removed to form a second semiconductor opening region;

[0081] S4. The entire front side of the silicon wafer is etched. The etching requirements are: laser etching is performed on the entire front side of the silicon wafer to remove the mask layer and surrounding coating. The laser used is a flat-top picosecond green laser (wavelength 532nm), frequency 550kHz, laser power 120W, laser pulse width 15ps, and laser etching speed 52500mm / s. A single row of laser spots is shown below. Figure 1 As shown in structure A, the overlap rate of adjacent laser spots is 50% in the horizontal scribing direction, and the overlap rate between two adjacent scribing lines is 50% in the vertical scribing direction. The laser spot with a 50% overlap rate is as follows: Figure 1 As shown in the B-structure, the scribing processing range, i.e., the final overall area controlled by the laser scribing, is larger than the front area of ​​the silicon wafer, i.e., the wafer size, as shown. Figure 2 As shown, there is a certain distance between the front edge C of the silicon wafer and the edge of the scribing processing area;

[0082] S5. Silicon wafer texturing and cleaning: A pyramid textured surface is formed on the front side of the silicon wafer and in the second semiconductor opening area, and then the mask layer is removed.

[0083] S6. A passivation layer and an antireflection layer are deposited on the front side of the silicon wafer, and a second semiconductor layer is deposited on the back side. The second semiconductor layer is an intrinsic amorphous silicon layer with a thickness of 10 nm and a p-type doped amorphous silicon layer (with a thickness of 20 nm and an effective doping concentration of 3e19cm). -3 );

[0084] S7. Laser-drill openings are made on the back side of the silicon wafer to form first semiconductor opening regions that are alternately arranged with the second semiconductor opening region;

[0085] S8. The back of the silicon wafer is cleaned and a transparent conductive film layer, namely ITO, is deposited.

[0086] S9. An isolation trench is formed between the first semiconductor opening region and the second semiconductor opening region by etching. The isolation trench is formed at the junction of the two semiconductor regions.

[0087] S10. A silver paste gate electrode is formed on the outer surface of the corresponding transparent conductive film layer of the first semiconductor opening region and the second semiconductor opening region of the silicon wafer, serving as a metal electrode.

[0088] Example 2

[0089] The same procedure is followed as in Example 1, except that in S4, the overlap rate of adjacent laser spots in the horizontal scribbling direction is controlled to be 60%, and the overlap rate of two adjacent scribbling lines in the vertical scribbling direction is controlled to be 60%.

[0090] Example 3

[0091] The same procedure is followed as in Example 1, except that in S05, the overlap rate of adjacent laser spots in the horizontal scribbling direction is controlled to be 70%, and the overlap rate of two adjacent scribbling lines in the vertical scribbling direction is controlled to be 70%.

[0092] Example 4

[0093] The procedure is carried out in accordance with Example 1, except that in S4, the control frequency is 400 kHz, which corresponds to a laser marking speed of 38000 mm / s.

[0094] Example 5

[0095] The procedure is carried out with reference to Example 1, except that in S4, the power of the laser is controlled to be 80W, which corresponds to a laser marking speed of 34800mm / s.

[0096] Comparative Example 1

[0097] The procedure is carried out in accordance with Example 1, except that in S4, laser scribing is replaced by a conventional chain cleaning method, that is, a chain wet etching method to remove the mask layer around the coating on the front side.

[0098] Comparative Example 2

[0099] The procedure is carried out in accordance with Example 1, except that in S4, the final overall area of ​​laser marking is equal to the front area of ​​the silicon wafer, i.e., the edges overlap is the same.

[0100] Comparative Example 3

[0101] The same procedure is followed as in Example 1, except that in S4, the overlap rate of adjacent laser spots in the horizontal scribbling direction is controlled to be 40%, and the overlap rate of two adjacent scribbling lines in the vertical scribbling direction is controlled to be 40%.

[0102] Test case

[0103] The back contact batteries obtained in the above embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1.

[0104] Table 1

[0105] Performance indicators Minority birth lifetime (µs) Open circuit voltage (V) Battery efficiency (%) Example 1 3200 0.749 27.25 Example 2 3105 0.748 27.21 Example 3 3086 0.748 27.17 Example 4 3115 0.749 27.23 Example 5 3075 0.748 27.15 Comparative Example 1 2800 0.747 27.06 Comparative Example 2 2710 0.746 27.02 Comparative Example 3 2683 0.746 26.99

[0106] The results above show that, compared with the comparative example, the embodiment of the present invention can simplify the process and reduce material costs while enhancing the overall passivation effect of the front and back of the battery, thereby improving battery efficiency.

[0107] Furthermore, as can be seen from Examples 1 and 2-5, the preferred scheme of the present invention is more conducive to enhancing the overall passivation effect of the front and back of the battery and improving battery efficiency.

[0108] The preferred embodiments of the present invention have been described in detail above; however, the present invention is not limited thereto. Within the scope of the inventive concept, various simple modifications can be made to the technical solutions of the present invention, including combinations of various technical features in any other suitable manner. These simple modifications and combinations should also be considered as the content disclosed in the present invention and are all within the protection scope of the present invention.

Claims

1. A method of back-grinding a back-contact cell, characterized in that, Includes the following steps: S1. Provides double-sided polished silicon wafers; S2. A first semiconductor layer containing an N-type doped layer is formed on the back side of the silicon wafer, and a phosphorosilicate glass layer is naturally formed as a mask layer. S3. Make a first etching opening on the back film layer obtained in S2 to form a second semiconductor opening region; S4. Using laser scribing, the entire front side of the silicon wafer is etched to remove the mask layer coating on the front side and to dope at least part of the phosphorus in the mask layer into the silicon wafer. The final overall area of ​​the laser scribing is larger than the front area of ​​the silicon wafer. During the whole-surface etching process, the overlap rate of adjacent laser spots in the horizontal scribing direction is controlled to be ≥50%, and the overlap rate of two adjacent scribing lines in the vertical scribing direction is controlled to be ≥50%. S5. Perform texturing and cleaning to form pyramidal textured surfaces on the front side of the silicon wafer and in the second semiconductor opening area, and then remove the mask layer. S6. A passivation layer and an anti-reflection layer are deposited on the front side of the silicon wafer, and a second semiconductor layer is deposited on the back side.

2. The method of back-textured, back-contact cell fabrication of claim 1, wherein, In S4, the conditions for laser marking include: laser power of 80W-200W and frequency of 400kHz-1000kHz.

3. The method of back-textured etching of back contact cells according to claim 1 or 2, characterized in that, In S4, the laser pulse width used for laser marking is less than 20 ps.

4. The method of back-textured, back-contact cell fabrication of claim 1 or 2, wherein, In S4, the laser wavelength is 350-550nm.

5. The method of back-textured, back-contact cell fabrication of claim 1, wherein, In S4, laser scribing uses a flat-top picosecond green laser or a flat-top picosecond ultraviolet laser.

6. The method for texturing a back contact battery according to claim 1, characterized in that, In S4, the laser marking speed is controlled to be 34800mm / s-55000mm / s.

7. The method for texturing a back contact battery according to claim 1, characterized in that, In S4, the length of the final overall area occupied by the laser etched is greater than the length of the front side of the silicon wafer, and the width of the final overall area occupied by the laser etched is greater than the width of the front side of the silicon wafer.

8. The method for texturing a back contact battery according to claim 1, characterized in that, The first semiconductor layer in S2 also includes a tunneling oxide layer disposed between the silicon wafer and the N-type doped layer, and / or, the second semiconductor layer in S6 is an intrinsic silicon layer and a P-type doped silicon layer.

9. The method for texturing a back contact battery according to claim 1, characterized in that, The post-texturing process for back contact batteries also includes: S7. A second etching opening is made on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region. S8. Clean the back side obtained in S7 and deposit a conductive film layer. S9. A third etched opening is made on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench. S10. Metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

10. A back-contact battery, characterized in that, It is produced by the post-texturing method for back contact batteries as described in any one of claims 1-9.

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