Selective contact area buried solar cell and back contact structure thereof

Abstract

The invention is suitable for the technical field of solar cells, and provides a selective contact area buried solar cell and a back contact structure thereof, the back contact structure comprises grooves arranged on the back of a silicon substrate at intervals; the first dielectric layer is arranged on the back surface of the silicon substrate; the first doped region is arranged on the first dielectric layer and is arranged in the groove; the second doped region is arranged on the first dielectric layer and is arranged outside the groove; the second dielectric layer is arranged between the first doped region and the second doped region, and the number of the second dielectric layer is at least one; and a conductive layer disposed on the first doped region and the second doped region. According to the back contact structure provided by the invention, the problems of high control requirement on the width of the groove and poor passivation effect in the prior art are solved.

Description

Technical Field

[0001] This invention belongs to the field of solar cell technology, and particularly relates to a selective contact area buried solar cell and its back contact structure. Background Technology

[0002] In crystalline silicon solar cells, the efficiency loss of the cell can be divided into two aspects: electrical loss and optical loss. The important components of electrical loss are recombination loss and resistance loss caused by metal-semiconductor contact, while the important component of optical loss is the shading of the metal grid lines on the light-receiving surface.

[0003] Passivated metal contact structures exhibit superior electrical performance, simultaneously achieving low contact resistivity and low surface recombination. This structure consists of an ultrathin tunneling oxide layer and an N-type or P-type doped polycrystalline silicon layer. Since the absorption of light by the doped polycrystalline silicon layer is 'parasitic', meaning it contributes nothing to the photocurrent, passivated metal contact structures are primarily used on the back of the cell, completely eliminating the obstruction of the metal grid lines on the front surface. Solar radiation received on the solar cell generates electrons and holes, which migrate to the doped polycrystalline silicon layers, creating a voltage difference between the layers.

[0004] Currently, P-type and N-type doped polysilicon layers are deposited directly on the back side of a silicon wafer. However, when they are connected without any obstruction, leakage and other defects occur. Therefore, to solve this problem, a very narrow trench is created between the P-type and N-type doped polysilicon layers to separate them, thus preventing leakage and reducing the open-circuit voltage of the battery. However, existing trenches are fabricated using laser drilling or wet etching. In these cases, the trench width is only tens of micrometers, requiring strict width control, making fabrication difficult. Furthermore, a single dielectric layer is used for passivation, which results in poor passivation and poor internal back reflection. Summary of the Invention

[0005] The purpose of this invention is to provide a back contact structure for solar cells, which aims to solve the problems of high requirements for trench width control and poor passivation effect in existing technologies.

[0006] The present invention is implemented as follows: a back contact structure for a solar cell includes: Grooves spaced apart on the back side of the silicon substrate; A first dielectric layer disposed on the back side of the silicon substrate includes one or more combinations of a silicon oxide layer, an aluminum oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer. A first doped region is disposed on the first dielectric layer and within the groove, the first doped region comprising doped amorphous silicon. A second doped region is disposed on the first dielectric layer and outside the groove, the second doped region comprising doped polysilicon; A second dielectric layer is disposed between the first doped region and the second doped region, wherein the second dielectric layer is at least one layer; and A conductive layer disposed on the first doped region and the second doped region; The conductive layer disposed in the first doped region includes a TCO transparent conductive film and a metal electrode, and the conductive layer disposed in the second doped region includes a metal electrode, which passes through the second dielectric layer and contacts the second doped region.

[0007] Furthermore, the second doped region and the sidewalls of the groove are spaced apart.

[0008] Furthermore, a third doped region is provided inside the silicon substrate corresponding to the interval.

[0009] Furthermore, the silicon substrate surface corresponding to the interval has a textured surface.

[0010] Furthermore, the first doped region is a P-type doped region, and the second doped region is an N-type doped region; or The first doped region is an N-type doped region, and the second doped region is a P-type doped region.

[0011] Furthermore, the second doped region is located in a portion of the area outside the groove.

[0012] Furthermore, the total thickness of the first dielectric layer and the first doped region disposed in the groove is less than or equal to the depth of the groove.

[0013] Furthermore, the total thickness of the first dielectric layer and the first doped region disposed in the groove is greater than the depth of the groove. Furthermore, the second dielectric layer is one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer.

[0014] Furthermore, the second dielectric layer covers the region between the first doped region and the second doped region, or extends to cover the first doped region and / or the second doped region.

[0015] Furthermore, the back side of the silicon substrate located between the first doped region and the second doped region has a rough textured structure.

[0016] Furthermore, the width of the P-type doped region is 300-600 μm, the width of the N-type doped region is 100-500 μm, and the depth of the groove is 0.01-10 μm.

[0017] Furthermore, the horizontal distance between the first doped region and the second doped region is 0-500 μm.

[0018] Furthermore, the first dielectric layer covers the first doped region and the second doped region or covers the entire back side of the silicon substrate.

[0019] Furthermore, a third doped region is provided in the silicon substrate located between the first doped region and the second doped region.

[0020] Furthermore, the first dielectric layer is connected to the bottom wall and side wall of the groove.

[0021] Furthermore, the first dielectric layer is connected to the bottom wall of the groove, and the second dielectric layer is also connected to the side wall of the groove.

[0022] Furthermore, the groove is arc-shaped, trapezoidal, or square.

[0023] Furthermore, the thickness of the first dielectric layer is 1-20 nm, and the total thickness of the first dielectric layer and the first doped region or the second doped region is greater than 20 nm.

[0024] Furthermore, the second dielectric layer is an aluminum oxide layer and an intrinsic silicon carbide layer, or a silicon oxide layer and an intrinsic silicon carbide layer, and the thickness of the second dielectric layer is greater than 25 nm.

[0025] Furthermore, the thickness of the aluminum oxide layer or silicon oxide layer in the second dielectric layer is less than 25 nm, and the thickness of the intrinsic silicon carbide layer in the second dielectric layer is greater than 10 nm.

[0026] Furthermore, the intrinsic silicon carbide layer in the second dielectric layer is composed of at least one first intrinsic silicon carbide film with different refractive indices.

[0027] Furthermore, the refractive index of each layer of the first intrinsic silicon carbide film decreases sequentially from the back side of the silicon substrate outwards.

[0028] Furthermore, the outer layer of the second dielectric layer is also provided with a magnesium fluoride layer.

[0029] Furthermore, the metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-coated copper electrode, or a silver-coated copper electrode.

[0030] Furthermore, the copper electrode is an electroplated copper electrode prepared by an electroplating process or a copper electrode prepared by physical vapor deposition.

[0031] Furthermore, the first dielectric layer corresponding to the first doped region may be the same as or different from the first dielectric layer corresponding to the second doped region.

[0032] Furthermore, the first doped region extends to a portion of the area outside the groove and is not connected to the adjacent second doped region.

[0033] Another embodiment of the present invention aims to provide a selectively contacted buried solar cell, comprising: silicon substrate; A back contact structure as described above is disposed on the back side of a silicon substrate; and A third dielectric layer disposed on the front side of a silicon substrate.

[0034] Furthermore, the third dielectric layer is one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer.

[0035] Furthermore, the third dielectric layer is a silicon oxide layer and an intrinsic silicon carbide layer, or an aluminum oxide layer and an intrinsic silicon carbide layer, and the thickness of the third dielectric layer is greater than 50 nm.

[0036] Furthermore, the thickness of the aluminum oxide layer or silicon oxide layer in the third dielectric layer is less than 40 nm, and the thickness of the intrinsic silicon carbide layer in the third dielectric layer is greater than 10 nm.

[0037] Furthermore, the intrinsic silicon carbide layer in the third dielectric layer is composed of at least one second intrinsic silicon carbide film with different refractive indices.

[0038] Furthermore, the refractive index of each layer of the second intrinsic silicon carbide film decreases sequentially from the front side of the silicon substrate outwards.

[0039] Furthermore, the outer layer of the third dielectric layer is also provided with a magnesium fluoride layer.

[0040] Furthermore, an electric field layer or floating junction is provided between the front side of the silicon substrate and the third dielectric layer.

[0041] Another objective of this invention is to provide a battery assembly comprising the selective contact area buried solar cells described above.

[0042] Another objective of this invention is to provide a photovoltaic system comprising the battery module as described above.

[0043] The back contact structure provided in this invention provides a method to isolate the first doped region within a groove and the second doped region outside a groove by creating grooves at intervals on the back side of a silicon substrate. This is achieved by using silicon substrates that do not cover the first doped region within the groove or silicon substrates that do not cover the second doped region outside the groove. Furthermore, the grooves have more lenient width control requirements than existing trenches, making fabrication easier. The deposition effect is also better when depositing the first dielectric layer and the first doped region within the grooves. Additionally, the grooves allow for better contact between the first dielectric layer and the bottom wall of the grooves. Since the second dielectric layer is in contact with both the bottom and sidewalls, the charge carriers generated on the silicon substrate can be easily separated through the first dielectric layer on the sidewall of the trench and selectively collected into the corresponding first doped region. This not only reduces leakage current but also enables selective transport of charge carriers in both the longitudinal and lateral directions, which is beneficial for multi-dimensional collection of charge carriers in the bottom and sidewalls of the trench. Because the second dielectric layer is at least one layer, the back side of the silicon substrate is passivated in multiple layers through at least one second dielectric layer, resulting in better passivation effect and improved internal back reflection. This solves the existing problems of high requirements for trench width control and poor passivation effect. Attached Figure Description

[0044] Figures 1 to 10 This is a schematic diagram of the structure of a selective contact area buried solar cell in various embodiments of the present invention; Figure 11 This is a flowchart of a selective contact area buried solar cell manufacturing method provided in another embodiment of the present invention. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0046] In this invention, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items.

[0047] This invention provides a method to isolate the first doped region within a silicon substrate and the second doped region outside a silicon substrate by creating grooves at intervals on the back side of the substrate. This is achieved by placing a first doped region within the groove and a second doped region outside the groove onto the silicon substrate that does not cover the first doped region within the groove, or onto the silicon substrate that does not cover the second doped region outside the groove. Furthermore, the grooves offer more flexibility in width control compared to existing trenches, making fabrication easier. The deposition of the first dielectric layer and the first doped region within the grooves also yields better results. Additionally, the grooves ensure that the first dielectric layer is in contact with both the bottom and sidewalls of the grooves. Therefore, the charge carriers generated on the silicon substrate can be easily separated through the first dielectric layer on the sidewall of the trench and selectively collected into the corresponding first doped region. This not only reduces leakage current but also enables selective transport of charge carriers in both the longitudinal and lateral directions, which is beneficial for multi-dimensional collection of charge carriers in the bottom and sidewalls of the trench. Since the second dielectric layer is provided in at least one layer, the back side of the silicon substrate is passivated in multiple layers through at least one second dielectric layer, thereby bringing better passivation effect and improving internal back reflection. This solves the existing problems of high requirements for trench width control and poor passivation effect.

[0048] Example 1 The first embodiment of the present invention provides a back contact structure for a solar cell. For ease of explanation, only the parts relevant to the embodiment of the present invention are shown. Refer to... Figures 1-10 As shown, the back contact structure of the solar cell provided in this embodiment of the invention includes: Grooves spaced apart on the back side of the silicon substrate 10; A first dielectric layer 20 is disposed on the back side of the silicon substrate 10, the first dielectric layer comprising intrinsic amorphous silicon or silicon oxide; A first doped region 30 is disposed on the first dielectric layer 20 and disposed in the groove, the first doped region including doped amorphous silicon; The second doped region 40 is disposed on the first dielectric layer 20 and outside the groove, and the second doped region includes doped polysilicon. A second dielectric layer 50 is disposed between the first doped region 30 and the second doped region 40, the second dielectric layer 50 being at least one layer and having a decreasing refractive index from the back side of the silicon substrate 10 outwards; and Conductive layers 60 are disposed on the first doped region 30 and the second doped region 40. The conductive layer disposed in the first doped region includes a TCO transparent conductive film and a metal electrode. The conductive layer disposed in the second doped region includes a metal electrode. The metal electrode passes through the second dielectric layer and contacts the second doped region.

[0049] In one embodiment of the present invention, the silicon substrate 10 has a front side facing the sun during normal operation and a back side opposite to the front side, with the front side being the light-receiving surface; the back side is located on the opposite side of the silicon substrate 10 relative to the front side, that is, the aforementioned front side and back side are located on different sides of the silicon substrate 10 and are opposite sides. In this embodiment, the silicon substrate 10 is an N-type silicon wafer. It is understood that in other embodiments, the silicon substrate 10 may also be other types of silicon wafers. The back side of the silicon substrate 10 is provided with grooves spaced apart. The grooves can be formed by laser etching or by a combination of mask (such as hard mask, silicon oxide mask, silicon nitride mask, and photoresist mask) and wet / dry etching. In this case, due to the grooves spaced apart on the back side of the silicon substrate 10, the area between two adjacent grooves of the silicon substrate 10 is generally in the shape of a protrusion. Therefore, the pattern on the back side of the silicon substrate 10 generally presents a pattern formed by the alternating arrangement of grooves and protrusions.

[0050] Furthermore, such as Figure 9 As shown, the second doped region and the sidewall of the groove are spaced apart, and a third doped region is disposed inside the silicon substrate corresponding to the spaced interval, as shown. Figure 10 As shown, the silicon substrate surface corresponding to the interval has a textured structure.

[0051] Furthermore, in one embodiment of the present invention, the first dielectric layer 20 is located on the back side of the silicon substrate 10 and at least covers the first doped region 30 and the second doped region 40. Specifically, the first dielectric layer 20 may only cover the first doped region 30 and the second doped region 40, or it may cover the entire back side of the silicon substrate 10. In one embodiment of the present invention, referring to… Figure 1 As shown, the first dielectric layer 20 only covers the first doped region 30 and the second doped region 40. In this case, the back side of the silicon substrate 10 located between the first doped region 30 and the second doped region 40 is not covered by the first dielectric layer 20. In another embodiment of the invention, referring to… Figure 2 As shown, its first dielectric layer 20 covers the entire back side of the silicon substrate 10, that is, its first dielectric layer 20 covers the entire back side formed by the grooves and protrusions of its silicon substrate 10. It should be noted that, as... Figure 1 and Figure 2 As shown, when the first dielectric layer 20 covers the first doped region 30, the first dielectric layer 20 is connected to the bottom wall and side wall of the groove.

[0052] Furthermore, in one embodiment of the present invention, the first doped region 30 is a P-type doped region and the second doped region 40 is an N-type doped region; or the first doped region 30 is an N-type doped region and the second doped region 40 is a P-type doped region. That is to say, a first dielectric layer 20 and a P-type doped region can be disposed within the groove, and a first dielectric layer 20 and an N-type doped region can be disposed outside the groove; or a first dielectric layer 20 and an N-type doped region can be disposed within the groove, and a first dielectric layer 20 and a P-type doped region can be disposed outside the groove, such that the first dielectric layer 20 and the first doped region 30, and the first dielectric layer 20 and the second doped region 40 are alternately disposed inside and outside the groove. In this case, the first doped region 30 inside the groove and the second doped region 40 outside the groove are blocked by the silicon substrate inside the groove that does not cover the first doped region 30 or by the silicon substrate outside the groove that does not cover the second doped region 40.

[0053] The first dielectric layer 20 is located between the silicon substrate 10 and the first doped region 30 within the groove and the second doped region 40 outside the groove, serving as a tunneling structure. The first dielectric layer 20 and the highly doped first doped region 30 or second doped region 40 connected to and covered by it together form a passivation contact structure. This passivation contact structure provides good surface passivation for the back side of the silicon substrate 10. Generally, the first dielectric layer 20 has a sufficiently thin thickness, allowing selective transport of one type of charge carrier through tunneling, while another type of charge carrier is difficult to tunnel through the first dielectric layer 20 due to the potential barrier and the field effect of the doped region. Therefore, the first dielectric layer 20 allows one type of charge carrier to tunnel into the doped region while blocking the passage of another type of charge carrier, causing recombination. This significantly reduces interface recombination, resulting in higher open-circuit voltage and short-circuit current in the solar cell, thereby increasing photoelectric conversion efficiency. Furthermore, as... Figures 1 to 10 As shown, the surface where the silicon substrate 10 contacts the first dielectric layer 20 forms multiple internal diffusion regions corresponding to the first doped region 30 or the second doped region 40. Simultaneously, in this embodiment, due to the groove design, the first dielectric layer 20 contacts both the bottom wall and sidewalls of the groove. Therefore, the charge carriers generated on the silicon substrate 10 can be easily separated through the first dielectric layer 20 on the sidewalls of the groove and selectively collected into the corresponding first doped region 30, which facilitates multi-dimensional collection of charge carriers within the bottom and sidewalls of the groove.

[0054] Furthermore, in one embodiment of the present invention, the first dielectric layer 20 is preferably one or a combination of a tunneling oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer. As some examples of the present invention, the first dielectric layer 20 may be a tunneling oxide layer of a single material, a combination of a tunneling oxide layer and an intrinsic amorphous silicon layer of multiple materials, or a combination of multiple intrinsic amorphous silicon layers of a single material with different refractive indices. It is understood that the specific structural arrangement of the first dielectric layer 20 includes, but is not limited to, the above-listed methods. The first dielectric layer 20 is configured according to actual usage needs, and no specific limitation is made here.

[0055] In a preferred embodiment of the present invention, the first dielectric layer 20 is preferably a tunneling oxide layer and an intrinsic silicon carbide layer, wherein the tunneling oxide layer and the intrinsic silicon carbide layer are arranged sequentially from the silicon substrate 10 outwards, the tunneling oxide layer is in contact with the back side of the silicon substrate 10, and the intrinsic silicon carbide layer is in contact with the first doped region 30 or the second doped region 40. Further, the tunneling oxide layer is preferably composed of one or more layers of silicon oxide and aluminum oxide; therefore, the first dielectric layer 20 can also be a combination of silicon oxide and aluminum oxide layers in the tunneling oxide layer. The intrinsic silicon carbide layer in the first dielectric layer 20 includes an intrinsic hydrogenated silicon carbide layer. In this case, the tunneling oxide layer and the intrinsic silicon carbide layer reduce the interface state density between the silicon substrate 10 and the first doped region 30 and the second doped region 40 through chemical passivation. For example, hydrogen in the intrinsic hydrogenated silicon carbide layer enters the silicon substrate 10 under the action of diffusion mechanism and thermal effect, which neutralizes the dangling bonds on the back side of the silicon substrate 10, passivates the defects on the back side of the silicon substrate 10, and thus transfers the energy band in the bandgap to the valence band or conduction band, thereby increasing the probability of charge carriers entering the first doped region 30 or the second doped region 40 through the first dielectric layer 20.

[0056] Generally, as specific examples of the present invention, in practical use, the first dielectric layer 20 preferably adopts a 1-2 nm silicon oxide layer and a 2-5 nm intrinsic silicon carbide layer. Compared with using only a silicon oxide layer as the tunneling structure, the intrinsic silicon carbide layer can also provide an additional hydrogen passivation effect, increasing the fabrication process window of the tunneling structure without affecting the tunneling effect. Of course, a 1-2 nm silicon oxide layer, or a 1 nm silicon oxide layer and a 1 nm aluminum oxide layer, or two or more intrinsic amorphous silicon layers with different refractive indices can also be used directly. It is understood that the specific structural arrangement of the first dielectric layer 20 includes, but is not limited to, the specific examples listed above. In addition, the first dielectric layer 20 can also be an intrinsic microcrystalline silicon layer, an intrinsic microcrystalline silicon oxide layer, an intrinsic amorphous silicon oxide layer, etc. Among them, such as Figures 1-10As shown, it only shows the first dielectric layer 20 as a single layer. It can be understood that the specific structure of the first dielectric layer 20 is set according to actual needs and is not completely in accordance with the attached drawings in the specification.

[0057] It should be noted that when the first dielectric layer 20 only covers the first doped region 30 and the second doped region 40, since the first dielectric layers 20 are separated from each other, the structures of the first dielectric layers 20 disposed on the first doped region 30 and the second doped region 40 can be the same or different. Specifically, the first dielectric layer 20 corresponding to the first doped region 30 and the first dielectric layer 20 corresponding to the second doped region 40 can be the same or different. For example, the first dielectric layer 20 can be selected as a silicon oxide layer and an intrinsic silicon carbide layer; or the first dielectric layer 20 in the groove where the first doped region 30 is disposed can be a silicon oxide layer and an intrinsic silicon carbide layer, and the first dielectric layer 20 in the boss where the second doped region 40 is disposed can be an aluminum oxide layer and an intrinsic silicon carbide layer, etc. The film structure of the first dielectric layer 20 on each first doped region 30 and the second doped region 40 is set according to the actual use needs, and no specific limitation is made here.

[0058] Furthermore, in one embodiment of the present invention, the first doped region 30 and the second doped region 40 are respectively disposed inside and outside each groove. The first doped region 30 and the second doped region 40 preferably include doped polycrystalline silicon, doped silicon carbide, or doped amorphous silicon. The doped silicon carbide may include doped hydrogenated silicon carbide, specifically by adding hydrogen gas during silicon carbide deposition. It should be noted that when the first dielectric layer 20 is the aforementioned silicon oxide layer and intrinsic silicon carbide layer, the first doped region 30 and the second doped region 40 are specifically doped silicon carbide. When the first dielectric layer 20 is the aforementioned silicon oxide layer or other combinations, the first doped region 30 and the second doped region 40 may be doped polycrystalline silicon, etc. When the first dielectric layer 20 is the aforementioned intrinsic amorphous silicon layer, the first doped region 30 and the second doped region 40 are specifically doped amorphous silicon. It should also be noted that the first doped region 30 and the second doped region 40 can be the same or different. For example, the first doped region 30 and the second doped region 40 can both be doped polysilicon; or the first doped region 30 can be doped polysilicon and the second doped region 40 can be doped silicon carbide, etc. The first doped region 30 and the second doped region 40 can be set according to actual use needs, and no specific limitation is made here.

[0059] Furthermore, in one embodiment of the present invention, the second doped region 40 is disposed in a portion of the region outside the groove, such as... Figure 1As shown, since the second doped region 40 is only located in a portion of the boss, the isolation between the first doped region 30 and the second doped region 40 can be achieved through the silicon substrate 10 itself. In this case, the total thickness of the first dielectric layer 20 and the first doped region 30 disposed in the groove can be greater than, less than, or equal to the depth of the groove; that is, the first doped region 30 can be disposed within the groove or extend out of the groove. (Refer to...) Figure 1 and Figure 2 As shown, the total thickness of the first dielectric layer 20 and the first doped region 30 is less than the depth of the groove. (Referring to...) Figure 3 As shown, the total thickness of the first dielectric layer 20 and the first doped region 30 is equal to the depth of the groove. (Referring to...) Figure 4 As shown, the total thickness of the first dielectric layer 20 and the first doped region 30 is greater than the depth of the groove. It should also be noted that, in one embodiment of the invention, as... Figure 5 As shown, when the first dielectric layer 20 covers the entire back side of the silicon substrate 10, and the total thickness of the first dielectric layer 20 and the first doped region 30 is greater than the depth of the groove, the first doped region 30 can also extend to a portion of the protrusion region outside the groove, and is not connected to the adjacent second doped region 40. At this time, the first dielectric layer 20 and the first doped region 30 disposed on the protrusion region outside the groove also form a passivated contact structure, and are connected to the first dielectric layer 20 and the first doped region 30 in the groove, thereby increasing the contact area of ​​the first dielectric layer 20 through which charge carriers selectively pass.

[0060] Furthermore, in other embodiments of the present invention, the second doped region 40 is disposed in the entire area outside the groove, such as... Figure 6 As shown, since the second doped region 40 is located on the entire boss outside the groove, in order to achieve isolation between the first doped region 30 and the second doped region 40, the total thickness of the first dielectric layer 20 and the first doped region 30 located in the groove needs to be less than or equal to the depth of the groove, so that the isolation between the first doped region 30 and the second doped region 40 can be achieved through the silicon substrate inside the groove that does not cover the first doped region 30.

[0061] Furthermore, in one embodiment of the present invention, the thickness of the first dielectric layer 20 is 1-20 nm, the total thickness of the first dielectric layer 20 and the first doped region 30 is greater than 20 nm, and the total thickness of the first dielectric layer 20 and the second doped region 40 is greater than 20 nm. Simultaneously, the horizontal distance between the first doped region 30 and the second doped region 40 is 0-500 μm, meaning that the second doped region 40 can cover the entire boss and be horizontally adjacent to the first doped region 30, or the second doped region 40 can cover a portion of the area outside the groove. Wherein, when the first doped region 30 is a P-type doped region, the groove width of the P-type doped region is set to 300-600 μm, the width of the N-type doped region set in the boss is 100-500 μm, and the groove depth is 0.01-10 μm. When the first doped region 30 is an N-type doped region, the groove width of the N-type doped region is set to 100-500 μm, the width of the P-type doped region set in its boss is 300-600 μm, and the groove depth is 0.01-10 μm. In a preferred embodiment of the present invention, the width of the P-type doped region is preferably 500 μm; the width of the N-type doped region is preferably 300 μm; and the distance between the first doped region 30 and the second doped region 40 is preferably 100 μm. As can be seen from the above, the groove width is more leniently controlled than the tens of micrometers width of existing trenches, and the fabrication is easier than that of existing trenches.

[0062] Furthermore, in one embodiment of the present invention, the second dielectric layer 50 covers the region between the first doped region 30 and the second doped region 40, or extends to cover the first doped region 30 and / or the second doped region 40. That is to say, referring to... Figure 7 As shown, the second dielectric layer 50 can cover only the area between the first doped region 30 and the second doped region 40. Correspondingly, the conductive layer 60 covers the first doped region 30 and its entire back surface for electrical connection. (Refer to...) Figure 1As shown, the second dielectric layer 50 can also extend from the boss to cover the first doped region 30 and / or the second doped region 40. Correspondingly, the second dielectric layer 50 can extend to cover a portion of the first doped region 30, a portion of the second doped region 40, or a portion of both the first doped region 30 and the second doped region 40. In this case, the conductive layer 60 covers the remaining back sides of the first doped region 30 and the second doped region 40 that are not covered by the second dielectric layer 50, forming electrical connections with the first doped region 30 and the second doped region 40 respectively. Of course, the second dielectric layer 50 can also completely cover the entire back side of the back contact structure during the fabrication process. In this case, when fabricating the conductive layer 60, the conductive layer 60 is inserted through the second dielectric layer 50 by means of perforation or the like to form electrical connections with the first doped region 30 and the second doped region 40 respectively. It should be noted that when the first dielectric layer 20 only covers the first doped region 30 and the second doped region 40, the second dielectric layer 50 is in direct contact with the back surface of the silicon substrate 10, as can be seen from... Figure 1 As shown. When the first dielectric layer 20 covers the entire back surface of the silicon substrate 10, the second dielectric layer 50 is in contact with the first dielectric layer 20, as can be seen from... Figure 2 As shown.

[0063] Furthermore, in one embodiment of the present invention, the second dielectric layer 50 is preferably one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer. The second dielectric layer 50 serves a passivation function, and is configured as at least one layer with the refractive index of each layer decreasing sequentially from the silicon substrate 10 outwards. This allows the layers closer to the silicon substrate 10 to provide passivation, while the layers farther from the silicon substrate 10 provide anti-reflection, thereby enhancing the anti-reflection effect and increasing the absorption and utilization of light by the silicon substrate 10, thus increasing the short-circuit current density. In addition, the second dielectric layer 50 can also be a doped silicon layer (such as a doped microcrystalline silicon layer, a doped amorphous silicon layer, or a doped polycrystalline silicon layer), a doped silicon carbide layer (such as a doped polycrystalline silicon carbide layer), or a doped silicon oxide layer (such as a doped polycrystalline silicon oxide or a doped amorphous silicon oxide). Furthermore, each layer of the second dielectric layer 50 with a different structure may be composed of multiple layers with different refractive indices, and the refractive indices of each layer are arranged in a manner that decreases sequentially from the silicon substrate 10 outwards, as described above. For example, the silicon oxide layer in the second dielectric layer 50 may be composed of multiple layers of silicon oxide films with a refractive index that decreases sequentially from the silicon substrate 10 outwards.

[0064] Based on the above, as some specific examples of the present invention, for example, its second dielectric layer 50 can be a three-layer structure composed of a silicon oxide layer / alumina layer, an intrinsic silicon carbide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the silicon oxide layer / alumina layer in the inner first layer is greater than 0.5 nm, the thickness of the intrinsic silicon carbide layer in the second layer is greater than 1 nm, and the thickness of the silicon nitride layer / silicon oxynitride layer in the outer third layer is greater than 50 nm.

[0065] As some specific examples of the present invention, for example, its second dielectric layer 50 can also be a two-layer structure composed of an aluminum oxide layer and a silicon nitride layer / silicon oxynitride layer, in which case the thickness of the aluminum oxide layer in the inner first layer is greater than 1 nm; and the thickness of the silicon nitride layer / silicon oxynitride layer in the outer second layer is greater than 50 nm.

[0066] As some specific examples of the present invention, for example, its second dielectric layer 50 can also be a three-layer structure composed of a silicon oxide layer / alumina layer, a doped polycrystalline silicon layer / doped polycrystalline silicon carbide layer / doped polycrystalline silicon oxide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the silicon oxide layer / alumina layer in the inner first layer is 0.5-3nm, the thickness of the doped polycrystalline silicon layer / doped polycrystalline silicon carbide layer / doped polycrystalline silicon oxide layer in the second layer is 20-100nm, and the thickness of the silicon nitride layer / silicon oxynitride layer in the outer third layer is greater than 50nm.

[0067] As some specific examples of the present invention, for example, its second dielectric layer 50 can also be a three-layer structure composed of an intrinsic amorphous silicon layer, a doped amorphous silicon layer / doped amorphous silicon oxide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the intrinsic amorphous silicon layer in the inner first layer is 2-10 nm, the thickness of the doped amorphous silicon layer / doped amorphous silicon oxide layer in the second layer is 2-50 nm, and the thickness of the silicon nitride layer / silicon oxynitride layer in the outer third layer is greater than 50 nm.

[0068] As some specific examples of the present invention, for example, its second dielectric layer 50 can also be a three-layer structure composed of a silicon oxide layer / alumina layer, an intrinsic silicon carbide layer / doped amorphous silicon oxide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the silicon oxide layer / alumina layer in the inner first layer is 0.5-3nm, the thickness of the intrinsic silicon carbide layer / doped amorphous silicon oxide layer in the second layer is 10-50nm, and the thickness of the silicon nitride layer / silicon oxynitride layer in the outer third layer is greater than 50nm.

[0069] It is understood that the specific structural arrangement of the second dielectric layer 50 includes, but is not limited to, the specific examples listed above. In a preferred embodiment of the invention, refer to... Figure 1As shown, the second dielectric layer 50 preferably has a two-layer structure of an alumina layer and an intrinsic silicon carbide layer, or a two-layer structure of a silicon oxide layer and an intrinsic silicon carbide layer. In this case, the overall thickness of the second dielectric layer 50 is greater than 25 nm, while it is typically 70-80 nm during normal production. In this case, the intrinsic silicon carbide layer not only provides hydrogen passivation, but also, compared to intrinsic amorphous silicon layers and doped polycrystalline silicon layers, reduces parasitic light absorption due to its large optical band gap and small absorption coefficient. Furthermore, the thickness of the alumina layer or silicon oxide layer in the second dielectric layer 50 is less than 25 nm, and the thickness of the intrinsic silicon carbide layer in the second dielectric layer 50 is greater than 10 nm. It should be noted that in the multilayer structures indicated in the embodiments of the present invention, the arrangement order is from the silicon substrate 10 outwards. For example, when the second dielectric layer 50 is an alumina layer and an intrinsic silicon carbide layer, the alumina layer is closer to the silicon substrate 10, while the intrinsic silicon carbide layer is closer to the outside. It should also be noted that in the accompanying drawings, as shown... Figures 1-10 As shown, it only illustrates that the second dielectric layer 50 has a two-layer structure. It is understood that the second dielectric layer 50 can also have other layers, and its specific structure is set according to actual needs, and is not entirely consistent with the accompanying drawings. It should also be noted that the various drawings of this invention are only used to describe the specific structural distribution in the back contact structure, but do not represent the actual dimensions of each structure. For example, the thickness of the first dielectric layer 20 is 1-20 nm, and the thickness of the second dielectric layer 50 is greater than 25 nm. The drawings do not completely correspond to the specific actual dimensions in this embodiment; the dimensions should be based on the specific parameters provided in this embodiment.

[0070] Furthermore, the intrinsic silicon carbide layer in the second dielectric layer 50 is composed of at least one first intrinsic silicon carbide film with different refractive indices. The refractive index of each first intrinsic silicon carbide film decreases sequentially from the back side of the silicon substrate 10 outwards. Optionally, the refractive indices of the aforementioned materials can generally be selected as follows: 3.88 for monocrystalline silicon; 3.5-4.2 for amorphous silicon; 3.93 for polycrystalline silicon; 2-3.88 for silicon carbide; 1.9-3.88 for silicon nitride; 1.45-3.88 for silicon oxynitride; 1.45 for silicon oxide; and 1.63 for aluminum oxide. It is understood that the refractive indices of the aforementioned materials can also be set to other values ​​according to actual application needs, and no specific limitations are made here.

[0071] Furthermore, in one embodiment of the present invention, the outer layer of the second dielectric layer 50 is further provided with a magnesium fluoride layer. That is, based on one or more combinations of the selected aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic silicon carbide layer, intrinsic amorphous silicon layer, and silicon oxide layer for the second dielectric layer 50, a magnesium fluoride layer may also be provided on the outer layer of the second dielectric layer 50. The refractive index of the magnesium fluoride layer is required to be the lowest, generally set to 1.4, and it is used to enhance the optical function of anti-reflection.

[0072] Furthermore, in one embodiment of the present invention, the conductive layer 60 is a TCO transparent conductive film and / or a metal electrode. The metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-plated copper electrode, or a silver-plated copper electrode. Further, the copper electrode is electroplated copper prepared by electroplating or copper electrode prepared by physical vapor deposition. The electroplated copper uses nickel, chromium, titanium, or tungsten electrodes as its seed layer or protective layer. When this back contact structure is applied to a low-temperature HBC cell (interdigitated back contact heterojunction solar cell), its conductive layer 60 is a TCO transparent conductive film and a metal electrode; when this back contact structure is applied to a high-temperature POLO-IBC cell (passivated contact IBC cell), its conductive layer 60 is a metal electrode. However, it should be noted that the metal electrode using low-temperature silver paste can only be applied to low-temperature HBC cells.

[0073] Furthermore, in one embodiment of the invention, the groove is arc-shaped, trapezoidal, or square. For example... Figure 1 As shown, in one specific embodiment, the groove is square. (As illustrated...) Figure 8 As shown, in another specific embodiment, the groove is trapezoidal. Preferably, the groove is arc-shaped or trapezoidal, as this improves the light reflection effect of the inner wall of the groove and increases the surface area of ​​the first dielectric layer 20 (which serves as the tunneling structure) in contact with the silicon substrate 10. Of course, since a square groove simplifies the manufacturing process, the shape of the groove is determined according to actual usage requirements and is not specifically limited here.

[0074] It should be noted that in other embodiments of the present invention, the first dielectric layer 20 may be connected to the bottom wall of the groove, and the second dielectric layer 50 may also be connected to the side wall of the groove. This is mainly because when a mask is used to cover the groove area, the silicon in part of the silicon substrate 10 next to the first doped region 30 will be etched during subsequent mask removal, thereby increasing the width of the groove. When the second dielectric layer 50 is subsequently deposited, it will be deposited into the empty area, thus connecting the second dielectric layer 50 to the side wall of the groove. Alternatively, when fabricating an arc-shaped groove (such as an elliptical groove), it may be impossible to deposit the first dielectric layer 20 and the first doped region 30 onto the inner wall of the arc-shaped groove along its long axis. Therefore, when depositing the second dielectric layer 50, it may fill the empty area, causing the second dielectric layer 50 to connect with the sidewall of the arc-shaped groove. Alternatively, it may be impossible to deposit the second dielectric layer 50 into the empty area, resulting in a gap between the sidewall of the arc-shaped groove and the first dielectric layer 20 and the first doped region 30. It should be noted that, in this embodiment of the invention, the first dielectric layer 20 is preferably directly connected to the sidewall of the groove in the back contact structure. This allows the first dielectric layer 20 disposed on the sidewall of the groove to selectively collect charge carriers in multiple dimensions.

[0075] Furthermore, in one embodiment of the present invention, referring to Figure 9As shown, a third doped region 70 is provided in the silicon substrate 10 located between the first doped region 30 and the second doped region 40. That is to say, the third doped region 70 can be provided on the entire protrusion outside the groove, or it can be provided on a part of the protrusion. Specifically, the third doped region 70 is a diffusion layer, which is formed by doping the silicon substrate 10 of each protrusion with different types of diffusion sources. Therefore, it is a diffusion layer formed by partial diffusion of the silicon substrate 10 located on the protrusion. The diffusion layer can be a P-type diffusion layer or an N-type diffusion layer. The P-type diffusion layer is formed by diffusion with boron, aluminum, gallium, etc., and the N-type diffusion layer is formed by diffusion with nitrogen, phosphorus, arsenic, etc. In this case, the N-type diffusion layer is an N+ layer relative to the silicon substrate 10, which is specifically an N-type silicon wafer, that is, its diffusion layer is formed by local re-diffusion. It should be noted that each third doped region 70 provided on the silicon substrate 10 can be set as a P-type diffusion layer or an N-type diffusion layer according to actual use needs, and no specific limitation is made here. Preferably, different types of diffusion are alternately performed on the protrusions of the silicon substrate 10 to form P-type diffusion layers and N-type diffusion layers. At this time, since the sidewalls of the groove and the protrusions outside the groove are provided with a first dielectric layer 20, and since the third doped region 70 is formed by diffusion between the first doped region 30 and the second doped region 40 in the silicon substrate 10, the carriers in the third doped region 70 can more easily be selectively separated through the first dielectric layer 20 in the adjacent groove sidewall and collected into the corresponding first doped region 30, and selectively separated through the first dielectric layer 20 on the protrusion and collected into the corresponding second doped region 40.

[0076] Furthermore, in one embodiment of the present invention, referring to Figure 10As shown, the back surface of the silicon substrate 10 located between the first doped region 30 and the second doped region 40 has a rough texture structure 80. That is, the rough texture structure 80 is present on the protrusion surface of the silicon substrate 10. When the first dielectric layer 20 only covers the first doped region 30 and the second doped region 40, the rough texture structure 80 is located at the contact position between the second dielectric layer 50 and the back surface of the silicon substrate 10; when the first dielectric layer 20 covers the entire back surface of the silicon substrate 10, the rough texture structure 80 is located at the contact position between the first dielectric layer 20 and the back surface of the silicon substrate 10. The rough texture structure 80 is usually formed by texturing, which can be an irregular hemispherical texture formed by acid texturing, a pyramidal texture formed by alkaline texturing, or a pyramidal texture formed by alkaline texturing followed by acid texturing to smooth the pyramid tips. It is understandable that the rough texture structure 80 can also be set as the entire back side of the silicon substrate 10, that is, the silicon substrate 10 located in the groove also has a rough texture structure 80. In this case, the entire back side of the silicon substrate 10 after the groove is formed can be texturized directly, without the need for the subsequent process of removing the rough texture structure 80 in the first doped region 30 and the second doped region 40, thus simplifying the process. However, it should be noted that in this embodiment, it is preferable to only texturize the surface of the region between the first doped region 30 and the second doped region 40 of the silicon substrate 10, so as to increase the reflection of incident light inside the silicon substrate 10, thereby increasing the light absorption rate, while the surface of the silicon substrate 10 at the first doped region 30 and the second doped region 40 is not texturized.

[0077] Testing showed that the HBC and POLO-IBC batteries prepared using the back-contact structure provided in this embodiment of the invention exhibited significantly improved conversion efficiency (up to approximately 26.0%) compared to the control group POLO-IBC batteries prepared using existing trench methods, with greatly enhanced reliability. Their electrical performance results are shown in Table 1 below. Table 1 Among them, the beneficial effects of the embodiments of the present invention compared with the prior art are as follows: 1. By setting grooves at intervals on the back side of the silicon substrate, and setting a first doped region in each groove and a second doped region outside each groove, the first doped region in the groove and the second doped region outside the groove can be blocked by the silicon substrate that does not cover the first doped region in the groove or the silicon substrate that does not cover the second doped region outside the groove. The width control requirements of the grooves are more relaxed than those of existing trenches, and the fabrication is easier than that of existing trenches. Furthermore, the deposition effect is better when depositing the first dielectric layer and the first doped region in the grooves.

[0078] 2. Due to the design of the groove, the first dielectric layer is in contact with the bottom wall and side wall of the groove. Therefore, the charge carriers generated on the silicon substrate can be easily separated by the first dielectric layer on the side wall of the groove and selectively collected into the corresponding first doped region. This not only reduces the leakage current, but also enables selective transport of charge carriers in both the longitudinal and lateral directions, which is beneficial for multi-dimensional collection of charge carriers in the bottom wall and side wall of the groove.

[0079] 3. Since the second dielectric layer is set to at least one layer, the back side of the silicon substrate is passivated in multiple layers through at least one second dielectric layer, thereby bringing a better passivation effect. Furthermore, by controlling the refractive index of each layer to decrease sequentially from the silicon substrate outward, the reflection of long-wavelength light on the inner back side of the silicon substrate can be improved, thereby increasing the short-circuit current density.

[0080] 4. Because the grooves have a certain depth, the hard mask only directly contacts the protrusion between the two grooves, so that the hard mask will not directly contact the bottom of the groove, reducing impurity contamination. Therefore, it can play a certain role in protecting the silicon substrate on the bottom wall of the groove. There is no need to worry about the hard mask causing damage to the silicon substrate. The damage caused by the hard mask contacting the protrusion surface of the silicon substrate can also be removed by the subsequent texturing process.

[0081] 5. When selectively depositing the first or second doped region using a hard mask, if the first doped region is being deposited in a groove area, the hard mask can be used to cover the protrusions outside the groove. Because the groove has a certain depth, the hard mask will not directly contact the bottom of the groove, resulting in better deposition. Furthermore, since there are silicon substrate protrusion structures of a certain width separating the grooves, the alignment of the hard mask does not need to be extremely precise when depositing in the groove area under hard mask coverage; a moderate deviation can be allowed, simplifying the alignment and reducing the complexity of the process.

[0082] 6. In the prior art, due to the limitations of width and depth in the trench area, the chemical solution cannot fully wet the bottom of the trench for chemical wet texturing due to the hydrophobicity of water and silicon wafer. However, in this embodiment, due to the grooves provided and the opposite back surface of the silicon substrate between adjacent grooves being protrusions, it is easier to achieve texturing to obtain a rough texture structure than the existing trench structure. Furthermore, by texturing the protrusions on the back surface of the silicon substrate, the reflection of light on the inner back surface of the silicon substrate is increased, thereby increasing the light absorption rate of the silicon substrate.

[0083] 7. Because a third doped region is provided in the region between the first doped region and the second doped region in the silicon substrate, the carriers in the third doped region can more easily be selectively separated through the first dielectric layer in the adjacent groove sidewall and collected into the corresponding first doped region, and selectively separated through the first dielectric layer on the protrusion and collected into the corresponding second doped region.

[0084] Example 2 The second embodiment of the present invention provides a selectively contacted buried solar cell. For ease of explanation, only the parts relevant to the embodiments of the present invention are shown. Refer to... Figures 1-10 As shown, the selective contact area buried solar cell provided in this embodiment of the invention includes: Silicon substrate 10; The back contact structure described in the aforementioned embodiment is disposed on the back side of the silicon substrate 10; and A third dielectric layer 90 is disposed on the front side of the silicon substrate 10.

[0085] Furthermore, in one embodiment of the present invention, the second dielectric layer 50 and the third dielectric layer 90 can be fabricated on both sides of the silicon substrate 10 using the same process. In this case, the third dielectric layer 90 can have the same structure as the second dielectric layer 50 in the aforementioned embodiment. Therefore, referring to the aforementioned embodiments, the third dielectric layer 90 can also preferably be one or a combination of an alumina layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer.

[0086] As some examples of the present invention, the third dielectric layer 90 may also be a three-layer structure composed of a silicon oxide layer / alumina layer and a doped polycrystalline silicon layer / doped polycrystalline silicon carbide layer / doped polycrystalline silicon oxide layer and silicon nitride layer / silicon oxynitride layer, or a three-layer structure composed of an intrinsic amorphous silicon layer and a doped amorphous silicon layer / doped amorphous silicon oxide layer and silicon nitride layer / silicon oxynitride layer, or a three-layer structure composed of a silicon oxide layer / alumina layer and an intrinsic silicon carbide layer / doped amorphous silicon oxide layer and silicon nitride layer / silicon oxynitride layer.

[0087] Furthermore, in a preferred embodiment of the present invention, referring to Figure 1As shown, the third dielectric layer 90 is preferably a two-layer structure consisting of a silicon oxide layer and an intrinsic silicon carbide layer, or a two-layer structure consisting of an aluminum oxide layer and an intrinsic silicon carbide layer, with a thickness greater than 50 nm. Specifically, the thickness of the aluminum oxide layer or silicon oxide layer in the third dielectric layer 90 is less than 40 nm, and the thickness of the intrinsic silicon carbide layer in the third dielectric layer 90 is greater than 10 nm. In this case, the intrinsic silicon carbide layer not only provides hydrogen passivation, but also, compared to intrinsic amorphous silicon layers and doped polycrystalline silicon layers, has a large optical band gap and a small absorption coefficient, thus reducing parasitic light absorption. Furthermore, the intrinsic silicon carbide layer in the third dielectric layer 90 is composed of at least one second intrinsic silicon carbide film with different refractive indices. The refractive index of each second intrinsic silicon carbide film decreases sequentially from the front side of the silicon substrate 10 outwards. Furthermore, in one embodiment of the present invention, a magnesium fluoride layer is also provided on the outer layer of the third dielectric layer 90. The outermost magnesium fluoride layer has the lowest refractive index requirement, typically set to 1.4, which is used to enhance the optical function of anti-reflection.

[0088] Of course, the third dielectric layer 90 may also have a different structural arrangement than the second dielectric layer 50 in the aforementioned embodiments. The structure of each film layer of the second dielectric layer 50 and the third dielectric layer 90 may be set according to the actual use needs, and no specific limitation is made here.

[0089] Furthermore, in one embodiment of the present invention, an electric field layer or a floating junction is provided between the front side of the silicon substrate 10 and the third dielectric layer 90. Specifically, the silicon substrate 10 is subjected to phosphorus diffusion to obtain the electric field layer or to boron diffusion to obtain the floating junction. In this case, the electric field layer or floating junction serves as the front surface electric field (FSF) of the selective contact region buried solar cell.

[0090] In this embodiment, by creating grooves at intervals on the back side of the silicon substrate, and forming a first doped region within each groove and a second doped region outside each groove, the silicon substrate within the groove that does not cover the first doped region or outside the groove that does not cover the second doped region effectively blocks the first doped region within the groove and the second doped region outside the groove. The grooves provided have more lenient width control requirements than existing trenches, are easier to fabricate, and exhibit better deposition results when depositing the first dielectric layer and the first doped region within the grooves. Furthermore, the grooves ensure that the first dielectric layer is in contact with both the bottom and sidewalls of the grooves. Therefore, the charge carriers generated on the silicon substrate can be easily separated through the first dielectric layer on the sidewall of the trench and selectively collected into the corresponding first doped region. This not only reduces leakage current but also enables selective transport of charge carriers in both the longitudinal and lateral directions, which is beneficial for multi-dimensional collection of charge carriers in the bottom and sidewalls of the trench. Since the second dielectric layer is provided in at least one layer, the back side of the silicon substrate is passivated in multiple layers through at least one second dielectric layer, thereby bringing better passivation effect and improving internal back reflection. This solves the existing problems of high requirements for trench width control and poor passivation effect.

[0091] Example 3 The third embodiment of the present invention provides a method for fabricating a selectively contacted buried solar cell. For ease of explanation, only the parts related to the embodiments of the present invention are shown. Refer to... Figure 11 As shown, the selective contact area buried solar cell fabrication method provided in this embodiment of the invention is used to prepare the selective contact area buried solar cell as described in the foregoing embodiments. Specifically, the method includes: Step S11: A plurality of grooves spaced apart are formed on the back side of the silicon substrate; Prior to step S11, a pretreatment of the silicon substrate should also be performed. The aforementioned pretreatment includes cleaning the silicon substrate and removing the damaged layer. Specifically, it includes: (1) RCA standard cleaning to remove particles and organic matter from the surface of the silicon substrate; (2) After cleaning the silicon substrate, it is placed in a 2-5% KOH alkaline solution (potassium hydroxide) or TMAH solution (tetramethylammonium hydroxide, i.e., developer) at a temperature of 50-80℃ for 1-5 minutes to remove the surface damage layer caused by the slicing process. (3) Use HCl to pickle the surface of the silicon substrate to neutralize the alkaline solution remaining on the surface of the silicon substrate and remove the residual metal impurities on the surface of the silicon wafer; (4) The silicon substrate is cleaned with HF solution to remove the silicon dioxide layer on the surface of the silicon wafer and form Si-H passivation bonds with the dangling bonds on the surface of the silicon substrate. Finally, it is dried with nitrogen for later use.

[0092] Furthermore, after the silicon substrate has been pretreated, the trenches can be created using the following methods: Method 1: Directly groove the desired area on the back side of the silicon substrate using a laser to remove localized silicon crystals, forming the required grooves. Method 2: Perform thermal oxidation on the silicon substrate to form a layer of silicon oxide on the entire surface. Remove the silicon oxide from the front and back sides of the substrate using laser grooving, followed by wet etching and removal of the silicon oxide with acid (such as HF) to form the desired grooves. Method 3: Deposit a layer of silicon nitride on the back side of the silicon substrate using PECVD. Remove the silicon nitride from the back side using laser grooving, followed by wet etching and removal of the silicon nitride to form the desired grooves. Method 4: Deposit silicon nitride on the back of a silicon substrate or thermally oxidize the silicon substrate to form silicon oxide, then deposit a photoresist mask on the back, develop the developing area by patterning the screen and exposing it, remove the developing area by wet etching with a developer, remove the silicon nitride / silicon oxide in the developing area by acid (such as HF), and then remove the photoresist mask and silicon nitride / silicon oxide by wet etching to form the desired groove; Method 5: Print patterned paste on the back of a silicon substrate as a mask, then remove the paste by wet etching to form the desired groove.

[0093] In this embodiment of the invention, the second method described above is preferably used for creating the grooves. In this second method, the thermal oxidation process specifically includes: dry oxygen oxidation / water vapor oxidation / wet oxygen oxidation (i.e., dry oxygen + water vapor) in a quartz tube. The specific reactants are oxygen and / or high-purity water vapor. The reaction pressure is 50-1000 mbar, the reaction temperature is 900-1200℃, and the resulting silicon oxide thickness is greater than 10 nm. The laser grooving process for removing silicon oxide specifically includes: using a laser with a wavelength of 532 nm, a laser power of 10-60 W, a laser frequency of ≤250 to 1500 kHz, and a laser pulse width of 3-50 ns to remove the silicon oxide. The wet etching process uses an alkaline solution and isoacetone. The alkaline solution is KOH or TMAH, with a concentration of 1-5% and an isoacetone content of 1-10%. The reaction temperature is 60-85℃, and the reaction time is 10-30 min. The acid solution used in the step of removing silicon oxide is HF, with a concentration of 1-5%, a reaction temperature of room temperature, and a reaction time of 3-10 min.

[0094] Specifically, after creating the grooves using the second method described above, the depth of each groove is 0.01-10 μm. The grooves can be arc-shaped, trapezoidal, or square. In contrast, existing technologies using laser drilling or wet etching for groove fabrication require strict width control and are difficult to manufacture. The groove fabrication method in this embodiment is easier than existing methods and does not have the stringent width control requirements of existing methods.

[0095] Step S21: Prepare a first dielectric layer on the back side of the silicon substrate; Prior to step S21, the specific production process may include texturing the front side of the silicon substrate. In this embodiment, front-side texturing mainly employs alkaline etching, where the alkaline solution reacts with the silicon substrate to generate a water-soluble compound, simultaneously forming a pyramid-shaped textured surface. Due to the presence of this textured surface, after the incident light undergoes its first reflection, it does not directly enter the air. Instead, it encounters adjacent textured surfaces and undergoes a second or even third reflection before entering the air. This allows for multiple uses of the incident light, thereby reducing the front-side reflectivity. When the back side of the silicon substrate also requires a rough textured structure, both the front and back sides can be texturized simultaneously. Conversely, when the back side of the silicon substrate does not require a rough textured structure, a silicon nitride protective layer can be deposited on the back side first, followed by front-side texturing. The silicon nitride protective layer on the back side can then be removed using a laser, thus avoiding texturing the back side of the silicon substrate.

[0096] Specifically, a first dielectric layer is prepared on the back side of a silicon substrate using a high-temperature oxidation process or deposition process. The type of the first dielectric layer is determined according to the specific deposition process and is not specifically limited here. In this case, the first dielectric layer is one or more combinations of a tunneling oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer, and its thickness is 1-20 nm. At this time, the first dielectric layer covers the entire back side of the silicon substrate. When it is not necessary to set the first dielectric layer in the region between the first doped region and the second doped region in the silicon substrate, the first dielectric layer covering the region between the first doped region and the second doped region in the silicon substrate can be removed by laser.

[0097] Step S31: Prepare a first doped region and a second doped region inside and outside each groove, respectively; The preparation of the first doped region and the second doped region inside and outside each groove includes two deposition methods: in-situ deposition and non-in-situ deposition.

[0098] Specifically, in one embodiment of the present invention, when in-situ deposition is used, step S31 includes: Different types of doped amorphous silicon or doped amorphous silicon carbide are alternately deposited inside and outside each groove. High-temperature crystallization treatment is performed to transform doped amorphous silicon or doped amorphous silicon carbide into doped polycrystalline silicon or doped silicon carbide, thereby obtaining a first doped region disposed within the groove and a second doped region disposed outside the groove.

[0099] In one possible implementation, when depositing the first doped region (specifically, a P-type doped region) in situ on the groove, the position of the boss that does not need to be deposited is covered by a masking method. At this time, P-type amorphous silicon / P-type amorphous silicon carbide is deposited in situ on the groove. It should be noted that, since the groove has a certain depth, the mask is positioned to abut against the boss, rather than directly contacting the bottom of the groove, which reduces the contamination of the bottom of the groove by impurities. After the groove deposition is completed, the impurities caused by the mask (such as silicon nitride mask or silicon oxide mask) or mask (such as hard mask) on the boss can be removed by laser. Then, the groove is blocked by the mask so that N-type amorphous silicon / N-type amorphous silicon carbide is deposited in situ at part of the boss outside the groove where the second doped region is to be deposited. After P-type amorphous silicon / P-type amorphous silicon carbide and N-type amorphous silicon / N-type amorphous silicon carbide are deposited alternately inside and outside each groove, the temperature is raised to 700-1000℃ by direct high temperature or laser heating. Therefore, under high temperature crystallization treatment, the P-type amorphous silicon / P-type amorphous silicon carbide and N-type amorphous silicon / N-type amorphous silicon carbide inside and outside each groove are transformed into P-type polycrystalline silicon / P-type silicon carbide and N-type polycrystalline silicon / N-type silicon carbide, so as to obtain the first doped region (i.e., P-type doped region) set in the groove and the second doped region (i.e., N-type doped region) set outside the groove. The mask can be a hard mask, a silicon nitride mask, a silicon oxide mask, or a photoresist mask, etc. Since in-situ deposition of doped amorphous silicon or doped silicon carbide may deposit on the sides and front of the silicon substrate, a wet etching process is required after high-temperature crystallization to remove the plating.

[0100] In another possible implementation, specifically, an in-situ deposition of a first doped region (specifically, a P-type doped region) is performed on the entire back side of the silicon substrate. P-type amorphous silicon / P-type amorphous silicon carbide is deposited on the entire back side of the silicon substrate. Then, all P-type amorphous silicon / P-type amorphous silicon carbide in all regions outside the grooves in the silicon substrate is removed by laser etching. Next, N-type amorphous silicon / N-type amorphous silicon carbide is deposited on the entire back side of the silicon substrate. Then, all N-type amorphous silicon / N-type amorphous silicon carbide on the protrusions in the silicon substrate, except for the second doped region, is removed by laser etching. Then, by directly using high temperature or laser heating, the temperature is raised to 700-1000℃, thereby transforming the P-type amorphous silicon / P-type amorphous silicon carbide and N-type amorphous silicon / N-type amorphous silicon carbide inside and outside each groove into P-type polycrystalline silicon / P-type silicon carbide and N-type polycrystalline silicon / N-type silicon carbide, thus obtaining the first doped region disposed within the groove and the second doped region disposed outside the groove.

[0101] Specifically, in one embodiment of the present invention, when using non-in-situ deposition, step S31 includes: Intrinsic amorphous silicon or intrinsic silicon carbide is deposited inside and outside each groove; Different types of doping are alternately applied inside and outside each groove; High-temperature crystallization treatment is performed to transform intrinsic amorphous silicon or intrinsic silicon carbide into doped polycrystalline silicon or doped silicon carbide, thereby obtaining a first doped region disposed within the groove and a second doped region disposed outside the groove.

[0102] Specifically, the steps of alternating different doping types in each groove include: Alternately implant type I and type II ions into and around each groove for doping; or Doping is performed by alternately depositing type I and type II doping sources inside and outside each groove; or The first type of source gas and the second type of source gas are alternately introduced into the inside and outside of each groove for doping.

[0103] In one possible implementation, intrinsic amorphous silicon or intrinsic silicon carbide is first deposited in each groove. Then, different types of ions are implanted inside and outside the grooves. For example, if the first doped region within the groove is a P-type doped region, P-type ions containing elements such as boron, aluminum, and gallium are implanted inside the groove, while N-type ions containing elements such as nitrogen, phosphorus, and arsenic are locally implanted outside the groove. Then, a high-temperature crystallization process is performed to transform the intrinsic amorphous silicon or intrinsic silicon carbide into doped polycrystalline silicon or doped silicon carbide. Since the deposition of intrinsic amorphous silicon or intrinsic silicon carbide may occur on the sides and front of the silicon substrate, a wet etching process is required after high-temperature crystallization to remove the plating.

[0104] In one possible implementation, intrinsic amorphous silicon or intrinsic silicon carbide is first deposited inside and outside each groove. Then, different doping sources of different doping types are alternately deposited inside and outside the groove using a masking method. For example, if the first doping region is a P-type doping region, a P-type doping source containing boron, aluminum, gallium, etc. (such as borosilicate glass) is deposited inside the groove to form P-type amorphous silicon / P-type silicon carbide. Then, an N-type doping source containing nitrogen, phosphorus, arsenic, etc. (such as phosphosilicate glass) is locally deposited outside the groove to form N-type amorphous silicon / N-type silicon carbide. After alternating deposition of P-type and N-type doping sources inside and outside each groove, a high-temperature crystallization treatment is performed to transform the intrinsic amorphous silicon or intrinsic silicon carbide into doped polycrystalline silicon or doped silicon carbide. It should be noted that after depositing different doping sources and performing high-temperature crystallization, the doping sources also need to be removed by means of laser or other methods.

[0105] The masks include hard masks, silicon nitride masks, silicon oxide masks, and photoresist masks. Specifically, with a hard mask, for example, the bumps on the silicon substrate are first covered with the hard mask, then a first type of dopant source is deposited in the groove, and then the groove is covered again with the hard mask. Then, a second type of dopant source is locally deposited outside the groove, achieving doping with different dopant types deposited inside and outside the groove. Specifically, with a silicon nitride mask, for example, silicon nitride is first deposited on the back side, then the groove is opened using laser drilling to remove the silicon nitride within the groove. Then, a first type of dopant source is deposited in the groove. Next, silicon nitride is deposited on the back side to protect the first type of dopant source. Then, the bumps are opened using laser drilling to remove the silicon nitride and the first type of dopant source on the bump. Then, a second type of dopant source is deposited on the bump. Then, the second type of dopant source and silicon nitride deposited in the groove are removed using laser drilling, achieving doping with different dopant types deposited inside and outside the groove. Its silicon oxide mask is similar to that of silicon nitride mask, and will not be described in detail here.

[0106] In one possible implementation, specifically, intrinsic amorphous silicon or intrinsic silicon carbide is first deposited inside and outside each groove. Then, different types of source gases are introduced into the grooves using a masking method for doping. For example, when the first doping region is a P-type doping region, a P-type source gas containing elements such as boron, aluminum, and gallium (such as borane gas or a carrier gas carrying boron trichloride or boron tribromide) is introduced into the groove to dope and form P-type amorphous silicon / P-type silicon carbide. Outside the groove, an N-type source gas containing elements such as nitrogen, phosphorus, and arsenic (such as phosphine gas or a carrier gas carrying phosphorus oxychloride) is introduced locally to dope and form N-type amorphous silicon / N-type silicon carbide. After alternating doping with different types of first and second type source gases inside and outside each groove, high-temperature crystallization treatment is then performed to transform the intrinsic amorphous silicon or intrinsic silicon carbide into doped polycrystalline silicon or doped silicon carbide. The masks include hard masks, silicon nitride masks, silicon oxide masks, and photoresist masks, etc. For specific implementation, please refer to the above description.

[0107] Specifically, in another embodiment of the present invention, when using non-in-situ deposition, step S31 may further include: Intrinsic amorphous silicon or intrinsic silicon carbide is deposited inside and outside each groove; Different types of diffusion are carried out alternately through masks inside and outside each groove to transform intrinsic amorphous silicon or intrinsic silicon carbide into doped polycrystalline silicon or doped silicon carbide, so as to obtain a first doped region disposed inside the groove and a second doped region disposed outside the groove.

[0108] In one possible implementation, intrinsic amorphous silicon or intrinsic silicon carbide is first deposited inside and outside each groove. Then, a first type of diffusion is performed directly within the groove to form a first doped region using a masking method, and a second type of diffusion is performed locally outside the groove to form a second doped region. For example, if the first doped region is a P-type doped region, boron diffusion is performed within the groove to form a P-type doped region, and phosphorus diffusion is performed locally outside the groove to form an N-type doped region. The mask includes a hard mask, a silicon nitride mask, a silicon oxide mask, and a photoresist mask, etc., and the specific implementation can be referred to the above description.

[0109] It should be noted that during the alternating preparation of the first doped region and the second doped region, due to the need for a high-temperature crystallization process, the thinner first dielectric layer may partially break. At this time, during the high-temperature diffusion process, it will adhere to the break in the first dielectric layer and the back side of the silicon substrate, so that multiple internal diffusion regions corresponding to the first doped region or the second doped region are formed on the surface where the silicon substrate contacts the first dielectric layer.

[0110] Specifically, a first doped region and a second doped region are alternately prepared inside and outside each groove. The first doped region and the second doped region include doped polycrystalline silicon, doped silicon carbide, or doped amorphous silicon, and the total thickness of the first dielectric layer and the first doped region or the second doped region is greater than 20 nm.

[0111] Step S41: Prepare a second dielectric layer and a third dielectric layer on the back and front sides of the silicon substrate, respectively; Prior to step S41, the process may further include alternating different types of diffusion at a location on the back side of the silicon substrate between the first and second doped regions, so that different types of third doped regions are diffused at local locations on the back side protrusions of the silicon substrate. When the third doped region is a P-type diffusion layer, the specific fabrication process includes: Method 1: introducing a source gas containing elements such as boron, aluminum, and gallium (such as borane gas or a carrier gas carrying boron trichloride or boron tribromide) for thermal diffusion to form a P-type diffusion layer; Method 2: depositing a doped source containing elements such as boron, aluminum, and gallium (such as borosilicate glass) for thermal diffusion to form a P-type diffusion layer; Method 3: fabricating an aluminum electrode above the diffusion layer, and then forming an aluminum-doped P-type diffusion layer through a high-temperature process; Method 4: spin-coating a doped source containing elements such as boron, aluminum, and gallium (such as boron tribromide) for thermal diffusion to form a P-type diffusion layer; Method 5: implanting ions containing elements such as boron, aluminum, and gallium, and then forming a P-type diffusion layer through high-temperature diffusion.

[0112] When the third doped region is an N-type diffusion layer, the specific fabrication processes are as follows: Method 1: Introduce a source gas containing elements such as nitrogen, phosphorus, and arsenic (e.g., phosphine gas or a carrier gas carrying phosphorus oxychloride) for thermal diffusion to form an N-type diffusion layer; Method 2: Deposit a dopant source containing elements such as nitrogen, phosphorus, and arsenic (e.g., phosphosilicate glass) for thermal diffusion to form an N-type diffusion layer; Method 3: Spin-coat a dopant source containing elements such as nitrogen, phosphorus, and arsenic (e.g., phosphorus oxychloride) for thermal diffusion to form an N-type diffusion layer; Method 4: Implant ions containing elements such as nitrogen, phosphorus, and arsenic, and then diffuse them at high temperature to form an N-type diffusion layer. It should be noted that after thermal diffusion of the deposited dopant source, the dopant source needs to be removed using methods such as lasers.

[0113] Furthermore, prior to step S41, the process may include texturing the back side of the silicon substrate at a location between the first doped region and the second doped region to obtain a rough textured structure. The specific texturing process can be referred to the foregoing description.

[0114] Specifically, during the fabrication of the second and third dielectric layers on the back and front sides of the silicon substrate, the fabrication process is based on the specific composition of the second and third dielectric layers, without specific limitations. Correspondingly, the second and third dielectric layers can be one or more combinations of aluminum oxide, silicon nitride, silicon oxynitride, intrinsic silicon carbide, intrinsic amorphous silicon, and silicon oxide. Furthermore, when the second and third dielectric layers are configured as a multilayer structure, the refractive index of each layer decreases sequentially from the silicon substrate outwards, and the outermost layer may also contain a magnesium fluoride layer with the lowest required refractive index.

[0115] Simultaneously, before fabricating the third dielectric layer on the front side of the silicon substrate, an electric field layer or a floating junction can be fabricated first. Specifically, the electric field layer is obtained by phosphorus diffusion on the silicon substrate, or a floating junction is obtained by boron diffusion. At this time, the electric field layer or floating junction serves as the front surface electric field (FSF) of the selective contact area buried solar cell.

[0116] Step S51: Prepare a conductive layer on the first doped region and the second doped region.

[0117] Specifically, when the second dielectric layer only covers the area between the first doped region and the second doped region in the silicon substrate, the conductive layer covers the entire back side of the first doped region and the second doped region for electrical connection; when the second dielectric layer extends to cover the first doped region and the second doped region, the conductive layer covers the remaining back side of the first doped region and the second doped region that is not covered by the second dielectric layer for electrical connection; when the second dielectric layer covers the entire back side of the silicon substrate, the conductive layer is electrically connected to the first doped region and the second doped region by means of through-holes or the like, so that a first electrode is formed in the first doped region and a second electrode is formed in the second doped region.

[0118] Specifically, when fabricating HBC (interdigitated back contact heterojunction solar cells) for low-temperature processes, the conductive layer consists of a TCO transparent conductive film and a metal electrode. When fabricating POLO-IBC (passivated contact IBC) cells for high-temperature processes, the conductive layer is a metal electrode. The metal electrode includes silver, copper, aluminum, tin-plated copper, or silver-plated copper electrodes. Furthermore, the copper electrode is either electroplated copper or copper prepared by physical vapor deposition. The electroplated copper uses nickel, chromium, titanium, or tungsten electrodes as its seed layer or protective layer.

[0119] Among them, the beneficial effects of the embodiments of the present invention compared with the prior art are as follows: 1. By setting grooves at intervals on the back side of the silicon substrate, and setting a first doped region in each groove and a second doped region outside each groove, the first doped region in the groove and the second doped region outside the groove can be blocked by the silicon substrate that does not cover the first doped region in the groove or the silicon substrate that does not cover the second doped region outside the groove. The width control requirements of the grooves are more relaxed than those of existing trenches, and the fabrication is easier than that of existing trenches. Furthermore, the deposition effect is better when depositing the first dielectric layer and the first doped region in the grooves.

[0120] 2. Due to the design of the groove, the first dielectric layer is in contact with the bottom wall and side wall of the groove. Therefore, the charge carriers generated on the silicon substrate can be easily separated by the first dielectric layer on the side wall of the groove and selectively collected into the corresponding first doped region. This not only reduces the leakage current, but also enables selective transport of charge carriers in both the longitudinal and lateral directions, which is beneficial for multi-dimensional collection of charge carriers in the bottom wall and side wall of the groove.

[0121] 3. Since the second dielectric layer is set to at least one layer, the back side of the silicon substrate is passivated in multiple layers through at least one second dielectric layer, thereby bringing a better passivation effect. Furthermore, by controlling the refractive index of each layer to decrease sequentially from the silicon substrate outward, the reflection of long-wavelength light on the inner back side of the silicon substrate can be improved, thereby increasing the short-circuit current density.

[0122] 4. Because the grooves have a certain depth, the hard mask only directly contacts the protrusion between the two grooves, so that the hard mask will not directly contact the bottom of the groove, reducing impurity contamination. Therefore, it can play a certain role in protecting the silicon substrate on the bottom wall of the groove. There is no need to worry about the hard mask causing damage to the silicon substrate. The damage caused by the hard mask contacting the protrusion surface of the silicon substrate can also be removed by the subsequent texturing process.

[0123] 5. When selectively depositing the first or second doped region using a hard mask, if the first doped region is being deposited in a groove area, the hard mask can be used to cover the protrusions outside the groove. Because the groove has a certain depth, the hard mask will not directly contact the bottom of the groove, resulting in better deposition. Furthermore, since there are silicon substrate protrusion structures of a certain width separating the grooves, the alignment of the hard mask does not need to be extremely precise when depositing in the groove area under hard mask coverage; a moderate deviation can be allowed, simplifying the alignment and reducing the complexity of the process.

[0124] 6. In the prior art, due to the limitations of width and depth in the trench area, the chemical solution cannot fully wet the bottom of the trench for chemical wet texturing due to the hydrophobicity of water and silicon wafer. However, in this embodiment, due to the grooves provided and the opposite back surface of the silicon substrate between adjacent grooves being protrusions, it is easier to achieve texturing to obtain a rough texture structure than the existing trench structure. Furthermore, by texturing the protrusions on the back surface of the silicon substrate, the reflection of light on the inner back surface of the silicon substrate is increased, thereby increasing the light absorption rate of the silicon substrate.

[0125] 7. Because a third doped region is provided in the region between the first doped region and the second doped region in the silicon substrate, the carriers in the third doped region can more easily be selectively separated through the first dielectric layer in the adjacent groove sidewall and collected into the corresponding first doped region, and selectively separated through the first dielectric layer on the protrusion and collected into the corresponding second doped region.

[0126] Example 4 The fourth embodiment of the present invention also provides a battery assembly, which includes the selective contact area buried solar cell described in the foregoing embodiments.

[0127] In this embodiment, the battery assembly uses selectively contacted buried solar cells with grooves spaced apart on the back side of a silicon substrate. A first doped region is formed within each groove, and a second doped region is formed outside each groove. This allows the first doped region within the groove and the second doped region outside the groove to be blocked by either the silicon substrate within the groove that does not cover the first doped region or the silicon substrate outside the groove that does not cover the second doped region. The grooves have more lenient width control requirements than existing trenches, making fabrication easier. Furthermore, the deposition effect is better when depositing the first dielectric layer and the first doped region within the grooves. Simultaneously, the grooves allow for better deposition of the first dielectric layer... The second dielectric layer is in contact with both the bottom and sidewalls of the trench. Therefore, the charge carriers generated on the silicon substrate can be easily separated through the first dielectric layer on the sidewall of the trench and selectively collected into the corresponding first doped region. This not only reduces leakage current but also enables selective transport of charge carriers in both the longitudinal and lateral directions, which is beneficial for multi-dimensional collection of charge carriers in the bottom and sidewalls of the trench. Since there is at least one second dielectric layer, the back side of the silicon substrate is passivated through at least one second dielectric layer, resulting in better passivation and improved internal back reflection. This solves the existing problems of high requirements for trench width control and poor passivation effect.

[0128] Example 5 The fifth embodiment of the present invention also provides a photovoltaic system, including the battery module as described in the foregoing embodiments.

[0129] In this embodiment of the photovoltaic system, the selective contact area of ​​the buried solar cell in the battery module is provided with grooves spaced apart on the back side of the silicon substrate. A first doped region is formed within each groove, and a second doped region is formed outside each groove. This allows the first doped region within the groove and the second doped region outside the groove to be blocked by the silicon substrate that does not cover the first doped region within the groove or by the silicon substrate that does not cover the second doped region outside the groove. The grooves provided have more relaxed width control requirements than existing trenches, are easier to fabricate, and exhibit better deposition results when depositing the first dielectric layer and the first doped region within the grooves. Simultaneously, the grooves allow the first dielectric layer to be blocked by the second doped region outside the grooves. The dielectric layer is in contact with both the bottom and sidewalls of the trench. Therefore, the charge carriers generated on the silicon substrate can be easily separated through the first dielectric layer on the sidewall of the trench and selectively collected into the corresponding first doped region. This not only reduces leakage current but also enables selective transport of charge carriers in both the longitudinal and lateral directions, which is beneficial for multi-dimensional collection of charge carriers in the bottom and sidewalls of the trench. Since there is at least one second dielectric layer, the back side of the silicon substrate is passivated through at least one second dielectric layer, resulting in better passivation and improved internal back reflection. This solves the existing problems of high requirements for trench width control and poor passivation effect.

[0130] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A back contact structure for a solar cell, characterized in that, include: Grooves spaced apart on the back side of the silicon substrate; A first dielectric layer disposed on the back side of the silicon substrate includes one or more combinations of a silicon oxide layer, an aluminum oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer. A first doped region is disposed on the first dielectric layer and within the groove, the first doped region comprising doped amorphous silicon. A second doped region is disposed on the first dielectric layer and outside the groove, the second doped region comprising doped polysilicon; A second dielectric layer is disposed between the first doped region and the second doped region, wherein the second dielectric layer is at least one layer. and A conductive layer disposed on the first doped region and the second doped region; The conductive layer disposed in the first doped region includes a TCO transparent conductive film and a metal electrode, and the conductive layer disposed in the second doped region includes a metal electrode, which passes through the second dielectric layer and contacts the second doped region.

2. The back contact structure as described in claim 1, characterized in that, The second doped region and the sidewall of the groove are spaced apart.

3. The back contact structure as described in claim 2, characterized in that, A third doped region is provided inside the silicon substrate corresponding to the interval.

4. The back contact structure as described in claim 2, characterized in that, The silicon substrate surface corresponding to the interval has a textured surface.

5. The back contact structure as described in claim 1, characterized in that, The first doped region is a P-type doped region, and the second doped region is an N-type doped region; or The first doped region is an N-type doped region, and the second doped region is a P-type doped region.

6. The back contact structure as described in claim 1, characterized in that, The total thickness of the first dielectric layer and the first doped region disposed in the groove is less than or equal to the depth of the groove.

7. The back contact structure as described in claim 1, characterized in that, The total thickness of the first dielectric layer and the first doped region disposed in the groove is greater than the depth of the groove.

8. The back contact structure as described in claim 1, characterized in that, The second dielectric layer is one or more combinations of aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic silicon carbide layer, intrinsic amorphous silicon layer and silicon oxide layer.

9. The back contact structure as described in claim 1, characterized in that, The second dielectric layer covers the region between the first doped region and the second doped region, or extends to cover the first doped region and / or the second doped region.

10. The back contact structure as described in claim 1, characterized in that, The back side of the silicon substrate located between the first doped region and the second doped region has a rough textured structure.

11. The back contact structure as described in claim 5, characterized in that, The width of the P-type doped region is 300-600 μm, the width of the N-type doped region is 100-500 μm, and the depth of the groove is 0.01-10 μm.

12. The back contact structure as described in claim 1, characterized in that, The horizontal distance between the first doped region and the second doped region is 0-500 μm.

13. The back contact structure as described in claim 1, characterized in that, The first dielectric layer covers the first doped region and the second doped region or covers the entire back side of the silicon substrate.

14. The back contact structure as described in claim 1, characterized in that, A third doped region is provided in the silicon substrate located between the first doped region and the second doped region.

15. The back contact structure as described in claim 1, characterized in that, The first dielectric layer is connected to the bottom wall and side wall of the groove.

16. The back contact structure as described in claim 1, characterized in that, The first dielectric layer is connected to the bottom wall of the groove, and the second dielectric layer is also connected to the side wall of the groove.

17. The back contact structure as described in claim 1, characterized in that, The groove can be arc-shaped, trapezoidal, or square.

18. The back contact structure as described in claim 1, characterized in that, The thickness of the first dielectric layer is 1-20 nm, and the total thickness of the first dielectric layer and the first doped region or the second doped region is greater than 20 nm.

19. The back contact structure as described in claim 1, characterized in that, The second dielectric layer is an aluminum oxide layer and an intrinsic silicon carbide layer, or a silicon oxide layer and an intrinsic silicon carbide layer, and the thickness of the second dielectric layer is greater than 25 nm.

20. The back contact structure as described in claim 19, characterized in that, The thickness of the aluminum oxide layer or silicon oxide layer in the second dielectric layer is less than 25 nm, and the thickness of the intrinsic silicon carbide layer in the second dielectric layer is greater than 10 nm.

21. The back contact structure as described in claim 19, characterized in that, The intrinsic silicon carbide layer in the second dielectric layer is composed of at least one first intrinsic silicon carbide film with different refractive indices.

22. The back contact structure as described in claim 21, characterized in that, The refractive index of the first intrinsic silicon carbide film in each layer decreases sequentially from the back side of the silicon substrate outwards.

23. The back contact structure as described in claim 1, characterized in that, The outer layer of the second dielectric layer is also provided with a magnesium fluoride layer.

24. The back contact structure as described in claim 1, characterized in that, The metal electrodes include silver electrodes, copper electrodes, aluminum electrodes, tin-coated copper electrodes, or silver-coated copper electrodes.

25. The back contact structure as described in claim 24, characterized in that, The copper electrode is prepared by electroplating or by physical vapor deposition.

26. The back contact structure as described in claim 1, characterized in that, The first dielectric layer corresponding to the first doped region may be the same as or different from the first dielectric layer corresponding to the second doped region.

27. The back contact structure as described in claim 1, characterized in that, The first doped region extends to a portion of the area outside the groove and is not connected to the adjacent second doped region.

28. A selectively contacted buried solar cell, characterized in that, include: silicon substrate; A back contact structure as described in any one of claims 1-27, disposed on the back side of a silicon substrate; and A third dielectric layer disposed on the front side of a silicon substrate.

29. The selective contact area buried solar cell as described in claim 28, characterized in that, The third dielectric layer is one or more combinations of aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic silicon carbide layer, intrinsic amorphous silicon layer and silicon oxide layer.

30. The selective contact area buried solar cell as described in claim 28, characterized in that, The third dielectric layer is a silicon oxide layer and an intrinsic silicon carbide layer, or an aluminum oxide layer and an intrinsic silicon carbide layer, and the thickness of the third dielectric layer is greater than 50 nm.

31. The selective contact area buried solar cell as described in claim 30, characterized in that, The thickness of the aluminum oxide layer or silicon oxide layer in the third dielectric layer is less than 40 nm, and the thickness of the intrinsic silicon carbide layer in the third dielectric layer is greater than 10 nm.

32. The selective contact area buried solar cell as described in claim 31, characterized in that, The intrinsic silicon carbide layer in the third dielectric layer consists of at least one second intrinsic silicon carbide film with different refractive indices.

33. The selective contact area buried solar cell as described in claim 32, characterized in that, The refractive index of each layer of the second intrinsic silicon carbide film decreases sequentially from the front side of the silicon substrate outwards.

34. The selective contact area buried solar cell as described in claim 28, characterized in that, The outer layer of the third dielectric layer is also provided with a magnesium fluoride layer.

35. The selective contact area buried solar cell as described in claim 28, characterized in that, An electric field layer or floating junction is also provided between the front side of the silicon substrate and the third dielectric layer.

36. A battery assembly, characterized in that, The battery assembly includes a selective contact area buried solar cell as described in any one of claims 28-35.

37. A photovoltaic system, characterized in that, The photovoltaic system includes the battery module as described in claim 36.

Images