Mother substrate and method for manufacturing mother substrate

Abstract

The invention relates to a mother substrate and a method for manufacturing the mother substrate. In general, according to an embodiment, a mother substrate is provided with: a plurality of panel sections each including a display region and a peripheral region around the display region; a blank area around the plurality of panel parts; a lower electrode disposed in the display area; a rib layer having a pixel opening overlapping the lower electrode, the rib layer being disposed in the panel portion and the blank region; and a partition wall disposed in the blank region. The partition wall includes: a bottom layer disposed on the rib layer; a conductive axial layer disposed on the underlayer; and an upper portion disposed on the axial layer, the bottom layer having a protruding portion protruding from a side surface of the axial layer, the upper portion having an eave portion protruding from the side surface of the axial layer, the eave portion having a cutout overlapping the protruding portion in plan view, and the bottom layer having a protruding portion protruding from the side surface of the axial layer. The cutout overlaps the boundary between the bottom layer and the axial layer in plan view.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority based on Japanese Patent Application No. 2024-123120 filed on July 30, 2024, and incorporates by reference all of the disclosures made in the Japanese Patent Application. TECHNICAL FIELD

[0003] Embodiments of the present application relate to a mother substrate and a manufacturing method of a mother substrate. BACKGROUND

[0004] In recent years, a display device to which an organic light emitting diode (OLED) is applied as a display element has been put into practical use. When manufacturing such a display device, an inspection for confirming whether or not elements on a substrate are formed as designed is performed. A technique for efficiently performing such an inspection is required. SUMMARY

[0005] Generally, according to an embodiment, a mother substrate includes: a plurality of panel portions each including a display region and a peripheral region surrounding the display region; a blank region surrounding the plurality of panel portions; a lower electrode disposed in the display region; a rib layer having a pixel opening overlapping the lower electrode and disposed in the panel portions and the blank region; and a first partition wall disposed in the blank region, the first partition wall including: a first bottom layer disposed above the rib layer; a first shaft layer disposed above the first bottom layer and having conductivity; and a first upper portion disposed above the first shaft layer, the first bottom layer having a protruding portion protruding from a side surface of the first shaft layer, the first upper portion having a cornice portion protruding from a side surface of the first shaft layer, the cornice portion having a notch overlapping the protruding portion in a plan view, the notch overlapping a boundary between the first bottom layer and the first shaft layer in the plan view.

[0006] According to another embodiment, a mother substrate includes: a plurality of panel portions each including a display region and a peripheral region surrounding the display region; a blank region surrounding the plurality of panel portions; a lower electrode disposed in the display region; a rib layer having a pixel opening overlapping the lower electrode and disposed in the panel portions and the blank region; and a first partition wall disposed in the blank region, the first partition wall including: a first bottom layer disposed above the rib layer; a first shaft layer disposed above the first bottom layer and having conductivity; a first upper portion disposed above the first shaft layer; a first partition wall opening; a second partition wall opening adjacent to the first partition wall opening; and a first portion between the first partition wall opening and the second partition wall opening, the first bottom layer having a protruding portion protruding from a side surface of the first shaft layer, an upper surface of the first shaft layer being exposed in the first portion.

[0007] Generally, according to an embodiment, in a manufacturing method of a mother substrate, a substrate including a panel portion and a blank area around the panel portion is prepared, the panel portion includes a display area and a peripheral area around the display area, a lower electrode is formed in the display area, a rib layer covering the panel portion and the blank area is formed, a first partition wall is formed in the blank area, the first partition wall includes a first bottom layer formed on the rib layer, a first shaft layer formed on the first bottom layer and having conductivity, and a first upper portion formed on the first shaft layer, a laser is scanned in a second direction in which the laser is inclined with respect to a first direction in which the first partition wall extends, a portion of a cornice portion protruding from a side surface of the first shaft layer in the first upper portion is removed, and a length of a protruding portion protruding from the side surface of the first shaft layer in the first bottom layer is measured.

[0008] According to another embodiment, in a manufacturing method of a mother substrate, a substrate including a panel portion and a blank area around the panel portion is prepared, the panel portion includes a display area and a peripheral area around the display area, a lower electrode is formed in the display area, a rib layer covering the panel portion and the blank area is formed, a first partition wall is formed in the blank area, the first partition wall includes a first bottom layer formed on the rib layer, a first shaft layer formed on the first bottom layer and having conductivity, and a first upper portion formed on the first shaft layer, a resist covering the first partition wall is formed, a portion of a cornice portion protruding from a side surface of the first shaft layer in the first upper portion and a portion of the resist overlapping the cornice portion are simultaneously removed by a laser, and a length of a protruding portion protruding from the side surface of the first shaft layer in the first bottom layer is measured.

[0009] According to yet another embodiment, in a manufacturing method of a mother substrate, a substrate including a panel portion and a blank area around the panel portion is prepared, the panel portion includes a display area and a peripheral area around the display area, a lower electrode is formed in the display area, a rib layer covering the panel portion and the blank area is formed, a first partition wall is formed in the blank area, the first partition wall includes a first bottom layer formed on the rib layer, a first shaft layer formed on the first bottom layer and having conductivity, a first upper portion formed on the first shaft layer, a first partition wall opening, and a second partition wall opening adjacent to the first partition wall opening, a resist exposing at least a portion of the first upper portion between the first partition wall opening and the second partition wall opening is formed, the first upper portion exposed from the resist is removed by performing etching, and a length of a protruding portion protruding from a side surface of the first shaft layer in the first bottom layer is measured.

[0010] According to the embodiments, a mother substrate and a method for manufacturing the mother substrate can be provided that can effectively perform inspections during the manufacturing of a display device. Attached Figure Description

[0011] Figure 1 This is a diagram showing an example of the configuration of the display device according to the first embodiment.

[0012] Figure 2 This is a schematic top view showing an example of the layout of subpixels.

[0013] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display panel along line III-III.

[0014] Figure 4 This is a schematic top view of the mother substrate according to the first embodiment.

[0015] Figure 5 This is a schematic top view of a portion of the mother substrate.

[0016] Figure 6 This is a schematic top view showing an example of the configuration of a test pattern applicable to a mother substrate according to the first embodiment.

[0017] Figure 7 It is along Figure 6 A schematic cross-sectional view of the mother substrate along line VII-VII.

[0018] Figure 8 yes Figure 6 A magnified view of the area enclosed by the dashed-dot box VIII.

[0019] Figure 9 It is along Figure 8 A rough cross-sectional view of the partition of the IX-IX line.

[0020] Figure 10 It is along Figure 8 A rough cross-sectional view of the wall next to the XX line.

[0021] Figure 11 This is a flowchart illustrating an example of a method for manufacturing a display device according to the first embodiment.

[0022] Figure 12A This is a schematic cross-sectional view showing the process of forming a panel portion on a mother substrate according to the first embodiment.

[0023] Figure 12B It shows the next step. Figure 12A A rough cross-sectional view of the process.

[0024] Figure 12CIt shows the next step. Figure 12B A rough cross-sectional view of the process.

[0025] Figure 12D It shows the next step. Figure 12C A rough cross-sectional view of the process.

[0026] Figure 12E It shows the next step. Figure 12D A rough cross-sectional view of the process.

[0027] Figure 12F It shows the next step. Figure 12E A rough cross-sectional view of the process.

[0028] Figure 12G It shows the next step. Figure 12F A rough cross-sectional view of the process.

[0029] Figure 12H It shows the next step. Figure 12G A rough cross-sectional view of the process.

[0030] Figure 12I It shows the next step. Figure 12H A rough cross-sectional view of the process.

[0031] Figure 12J It shows the next step. Figure 12I A rough cross-sectional view of the process.

[0032] Figure 13A This is a schematic cross-sectional view showing the process of removing the rib layer in the terminal section.

[0033] Figure 13B It shows the next step. Figure 13A A rough cross-sectional view of the process.

[0034] Figure 14A This is a schematic cross-sectional view showing an example of the process of removing a portion of the upper part.

[0035] Figure 14B This is a schematic top view illustrating an example of the process of removing a portion of the upper part.

[0036] Figure 14C It shows the next step. Figure 14A A rough cross-sectional view of the process.

[0037] Figure 14D It shows the next step. Figure 14B A top-down view of the process.

[0038] Figure 15 This is a schematic top view showing an example of the configuration of a test pattern applicable to a mother substrate according to the second embodiment.

[0039] Figure 16 yes Figure 15 A magnified view of the area enclosed by the dashed-dot frame XVI.

[0040] Figure 17 This is a cross-sectional view showing an example of the process of removing a portion of the upper part.

[0041] Figure 18 This is a schematic top view showing an example of the configuration of a test pattern applicable to a mother substrate according to the third embodiment.

[0042] Figure 19 It is along Figure 18 A schematic cross-sectional view of the mother substrate of the XIX-XIX line.

[0043] Figure 20A This is a schematic cross-sectional view showing an example of the process of forming Part 1.

[0044] Figure 20B It shows the next step. Figure 20A A rough cross-sectional view of the process.

[0045] Figure 20C It shows the next step. Figure 20B A rough cross-sectional view of the process.

[0046] Figure 20D It shows the next step. Figure 20C A rough cross-sectional view of the process.

[0047] Figure 20E It shows the next step. Figure 20D A rough cross-sectional view of the process. Detailed Implementation

[0048] Several embodiments will be described with reference to the accompanying drawings.

[0049] The disclosed content is merely one example, and appropriate modifications that can be readily conceived by those skilled in the art while maintaining the spirit of the invention are naturally included within the scope of this invention. Furthermore, regarding the accompanying drawings, to make the description clearer, the width, thickness, shape, etc., of various parts are sometimes schematically shown compared to the actual form; however, this is merely an example and does not limit the interpretation of the invention. Additionally, in this specification and the various figures, the same reference numerals are used for constituent elements that perform the same or similar functions as those described with respect to previously presented figures, and sometimes repeated detailed descriptions are appropriately omitted.

[0050] It should be noted that the accompanying drawings include mutually orthogonal X-axis, Y-axis, and Z-axis for ease of understanding. The direction along the X-axis is referred to as the X-direction, the direction along the Y-axis as the Y-direction, and the direction along the Z-axis as the Z-direction. Furthermore, the method of observing various elements parallel to the Z-direction is called top-down observation.

[0051] The display devices involved in each embodiment are organic electroluminescent display devices that use organic light-emitting diodes (OLEDs) as display elements, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, portable telephone terminals, and wearable terminals.

[0052] [First Implementation]

[0053] Figure 1 This diagram illustrates a configuration example of the display device DSP according to the first embodiment. The display device DSP includes a display panel PNL comprising an insulating substrate 10. The display panel PNL has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be glass or a flexible resin film.

[0054] In this embodiment, the substrate 10 is rectangular when viewed from above. However, the shape of the substrate 10 when viewed from above is not limited to a rectangle; it can also be other shapes such as a square, a circle, or an ellipse.

[0055] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Pixel PX includes a plurality of sub-pixels SP displaying different colors. In this embodiment, pixel PX is assumed to include a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. However, pixel PX may also include sub-pixels SP of other colors such as white, either together with or replacing any of sub-pixels SP1, SP2, and SP3.

[0056] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are, for example, switching elements composed of thin-film transistors.

[0057] The display area DA is equipped with multiple scan lines GL that supply scan signals to the pixel circuit 1 of each sub-pixel SP, multiple signal lines SL that supply image signals to the pixel circuit 1 of each sub-pixel SP, and multiple power lines PL. Figure 1 In the example, the scan line GL and the power line PL extend in the X direction, and the signal line SL extends in the Y direction.

[0058] The gate electrode of pixel switch 2 is connected to scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to signal line SL, and the other is connected to the gate electrode of driving transistor 3 and capacitor 4. In driving transistor 3, one of the source and drain electrodes is connected to power line PL and capacitor 4, and the other is connected to display element DE.

[0059] It should be noted that the configuration of pixel circuit 1 is not limited to the example shown in the figure. For example, pixel circuit 1 may also have more thin-film transistors and capacitors.

[0060] The display device DSP also includes a terminal section T disposed in the peripheral area SA. A flexible circuit board is connected to the terminal section T, for example. Signals and voltages for driving the pixel circuit 1 are input to the display device DSP through the flexible circuit board and the terminal section T.

[0061] Figure 2 This is a schematic top view showing an example of the layout of subpixels SP1, SP2, and SP3. Figure 2 In the example, subpixels SP2 and SP3 are arranged in the X direction along with subpixel SP1, respectively. Furthermore, subpixels SP2 and SP3 are arranged in the Y direction.

[0062] With subpixels SP1, SP2, and SP3 arranged in this layout, the display area DA contains columns of subpixels SP2 and SP3 alternately arranged in the Y direction, as well as columns of multiple subpixels SP1 repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. It should be noted that the layout of subpixels SP1, SP2, and SP3 is not limited to... Figure 2 Examples.

[0063] A rib layer 5 is configured in the display area DA. Rib layer 5 has pixel openings AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. Figure 2 In the example, pixel aperture AP1 is larger than pixel aperture AP2, and pixel aperture AP2 is larger than pixel aperture AP3. That is, among sub-pixels SP1, SP2, and SP3, sub-pixel SP1 has the largest aperture ratio, and sub-pixel SP3 has the smallest aperture ratio. It should be noted that the size and shape of pixel apertures AP1, AP2, and AP3 are not limited to the example shown in the figure.

[0064] Sub-pixel SP1 has a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with pixel opening AP1. Sub-pixel SP2 has a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with pixel opening AP2. Sub-pixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with pixel opening AP3.

[0065] The portion of the lower electrode LE1, the upper electrode UE1, and the organic layer OR1 overlapping with the pixel opening AP1 constitutes the display element DE1 of sub-pixel SP1. The portion of the lower electrode LE2, the upper electrode UE2, and the organic layer OR2 overlapping with the pixel opening AP2 constitutes the display element DE2 of sub-pixel SP2. The portion of the lower electrode LE3, the upper electrode UE3, and the organic layer OR3 overlapping with the pixel opening AP3 constitutes the display element DE3 of sub-pixel SP3. Display elements DE1, DE2, and DE3 may also include a capping layer described later. Rib layer 5 surrounds each of the aforementioned display elements DE1, DE2, and DE3.

[0066] In the display area DA, a conductive partition 6 (second partition) is disposed above the rib layer 5. The partition 6 serves as a wiring to supply a common voltage to the upward electrodes UE1, UE2, and UE3. The partition 6 overlaps with the rib layer 5 as a whole and has the same planar shape as the rib layer 5.

[0067] Specifically, partition 6 has partition opening 601 in sub-pixel SP1, partition opening 602 in sub-pixel SP2, and partition opening 603 in sub-pixel SP3. Partition openings 601, 602, and 603 are larger than pixel openings AP1, AP2, and AP3, respectively, and respectively surround pixel openings AP1, AP2, and AP3. Partition openings 601, 602, and 603 completely overlap with display elements DE1, DE2, and DE3, respectively. That is, partition 6 surrounds display elements DE1, DE2, and DE3.

[0068] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display panel PNL along line III-III. A circuit layer 11 is disposed on the aforementioned substrate 10. The circuit layer 11 includes... Figure 1 The diagram shows various circuits and wiring, including pixel circuit 1, scan line GL, signal line SL, and power line PL. Circuit layer 11 is covered by an organic insulating layer 12. The organic insulating layer 12 functions as a planarization film to flatten the unevenness created by circuit layer 11.

[0069] Lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. Rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by rib layer 5. Figure 3 The cross-section is not shown. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the organic insulating layer 12.

[0070] The partition 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 (second upper portion) disposed on the lower portion 61. The upper portion 62 has a wider width than the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the sides of the lower portion 61. Such a shape of the partition 6 is called cantilevered.

[0071] exist Figure 3 In this example, the lower portion 61 has a bottom layer 63 (second bottom layer) disposed above the rib layer 5 and a conductive shaft layer 64 (second shaft layer) disposed above the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the shaft layer 64. Furthermore, in Figure 3 In the example, the two ends of the bottom layer 63 protrude from the sides of the shaft layer 64.

[0072] In addition, Figure 3 In this example, the upper part 62 has a first film 65 and a second film 66 disposed on the first film 65. For example, the width of the second film 66 is slightly smaller than the width of the first film 65. It is not limited to this, and the first film 65 and the second film 66 may also have the same width.

[0073] Organic layer OR1 is connected to lower electrode LE1 via pixel opening AP1. Upper electrode UE1 is disposed on organic layer OR1 and opposite to lower electrode LE1. Organic layer OR2 is connected to lower electrode LE2 via pixel opening AP2. Upper electrode UE2 is disposed on organic layer OR2 and opposite to lower electrode LE2. Organic layer OR3 is connected to lower electrode LE3 via pixel opening AP3. Upper electrode UE3 is disposed on organic layer OR3 and opposite to lower electrode LE3. Upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of partition 6.

[0074] Display element DE1 includes a capping layer CP1 disposed on the upper electrode UE1. Display element DE2 includes a capping layer CP2 disposed on the upper electrode UE2. Display element DE3 includes a capping layer CP3 disposed on the upper electrode UE3. The capping layers CP1, CP2, and CP3 respectively serve as optical adjustment layers to improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3.

[0075] In the following description, the multilayer comprising organic layer OR1, upper electrode UE1, and capping layer CP1 is referred to as laminated film FL1; the multilayer comprising organic layer OR2, upper electrode UE2, and capping layer CP2 is referred to as laminated film FL2; and the multilayer comprising organic layer OR3, upper electrode UE3, and capping layer CP3 is referred to as laminated film FL3. Spacer 6 surrounds laminated films FL1, FL2, and FL3.

[0076] Sub-pixels SP1, SP2, and SP3 are respectively provided with sealing layers SE11, SE12, and SE13 covering the laminated films FL1, FL2, and FL3. Sealing layer SE11 continuously covers display element DE1 and the surrounding partition 6. Sealing layer SE12 continuously covers display element DE2 and the surrounding partition 6. Sealing layer SE13 continuously covers display element DE3 and the surrounding partition 6.

[0077] exist Figure 3 In the example, the sealing layer SE11 on the partition 6 between sub-pixels SP1 and SP2 is separated from the sealing layer SE12 on the same partition 6. Additionally, the sealing layer SE11 on the partition 6 between sub-pixels SP1 and SP3 is separated from the sealing layer SE13 on the same partition 6. However, it is also possible that any two of the sealing layers SE11, SE12, and SE13 are in contact above the partition 6.

[0078] For example, gaps are formed between the sealing layers SE11, SE12, SE13 and the upper part 62 of the partition wall 6. Laminated films FL1, FL2, FL3 can be disposed in at least a portion of these gaps.

[0079] Sealing layers SE11, SE12, and SE13 are covered by resin layer RS1. Resin layer RS1 is covered by sealing layer SE2. Sealing layer SE2 is covered by resin layer RS2. Resin layers RS1, RS2, and sealing layer SE2 are continuously disposed over the entire display area DA, with a portion extending to the peripheral area SA.

[0080] A cover plate component, such as a polarizing plate, touch panel, protective film, or cover glass, can be further disposed above the resin layer RS2. Such a cover plate component can be bonded to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0081] The organic insulating layer 12 is formed of organic insulating materials such as polyimide. The rib layer 5 and sealing layers SE11, SE12, SE13, and SE2 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed, for example, of resin materials (organic insulating materials) such as epoxy resin and acrylic resin.

[0082] The lower electrodes LE1, LE2, and LE3 have, for example, a reflective layer formed of silver and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. Each conductive oxide layer can be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0083] The upper electrodes UE1, UE2, and UE3 are formed, for example, from metallic materials such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0084] Organic layers OR1, OR2, and OR3 are composed of multiple thin films, including a light-emitting layer. In one example, organic layers OR1, OR2, and OR3 have a structure formed by sequentially stacking a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer along the Z-direction. However, organic layers OR1, OR2, and OR3 may also have other structures, such as a so-called tandem structure including multiple light-emitting layers.

[0085] The capping layers CP1, CP2, and CP3 have a stacked structure, for example, formed by overlapping multiple transparent layers. The transparent layers may include layers formed of inorganic materials and layers formed of organic materials. Furthermore, the transparent layers have different refractive indices than each other. For example, the refractive index of the transparent layers differs from the refractive index of the upper electrodes UE1, UE2, and UE3, and the refractive index of the sealing layers SE11, SE12, and SE13. It should be noted that at least one of the capping layers CP1, CP2, and CP3 may be omitted.

[0086] The bottom layer 63 and the axial layer 64 of the lower portion 61 of the partition 6 are formed of, for example, metallic materials. For example, molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb) can be used as the metallic material for the bottom layer 63. For example, aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi) can be used as the metallic material for the axial layer 64. It should be noted that at least one of the bottom layer 63 and the axial layer 64 may have a multilayered structure. Additionally, the axial layer 64 may include a layer formed of an insulating material.

[0087] The first thin film 65 of the partition 6 is formed, for example, of a metallic material. The second thin film 66 of the partition 6 is formed, for example, of a conductive oxide. As the metallic material forming the first thin film 65, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy can be used, for example. As the conductive oxide forming the second thin film 66, ITO or IZO can be used, for example. It should be noted that the upper portion 62 can have three or more layers, or it can be formed from a single layer. Furthermore, the upper portion 62 may also include a layer formed of an insulating material.

[0088] A common voltage is supplied to the adjacent 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the lower part 61, respectively. Pixel voltages corresponding to the image signals of signal line SL are supplied to the lower electrodes LE1, LE2, and LE3, respectively, through the pixel circuits 1 of sub-pixels SP1, SP2, and SP3.

[0089] Organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is established between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of organic layer OR1 emits light in the blue wavelength region. When a potential difference is established between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of organic layer OR2 emits light in the green wavelength region. When a potential difference is established between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of organic layer OR3 emits light in the red wavelength region.

[0090] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 can also emit light of the same color (e.g., white). In this case, the display device DSP can include a color filter that converts the light emitted by the light-emitting layers into light corresponding to the colors of sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP can also include a layer containing quantum dots, which are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the sub-pixels SP1, SP2, and SP3.

[0091] When manufacturing a display device DSP, a large mother substrate is made having multiple regions (panel sections) that each correspond to a display panel PNL. The following describes the configuration applicable to this mother substrate.

[0092] Figure 4 This is a schematic top view of the mother substrate MB (mother substrate for display device) according to the first embodiment. The mother substrate MB is rectangular, as shown in the figure, but it can also be other shapes such as circles.

[0093] The mother substrate MB has multiple panel portions PP arranged in a matrix and blank areas BA surrounding these panel portions PP. Figure 4In the example, the panel portions PP are arranged in the X and Y directions with a blank area BA between them. However, it is also possible that at least two of the multiple panel portions PP of the mother substrate MB are adjacent to each other without a blank area BA between them.

[0094] The mother substrate MB also has at least one test pattern TG. Figure 4 In the example, multiple test patterns TG are arranged in the blank area BA. The arrangement position and number of the test patterns TG are not particularly limited. In one example, it is preferred that the test patterns TG are distributed near the ends, center and other positions of the mother substrate MB.

[0095] Figure 5 This is a schematic top view of a portion of the mother substrate MB. In this figure, focus is on a panel portion PP. The shape of the panel portion PP corresponds to the cutting line CL1 used to cut the panel portion PP from the mother substrate MB.

[0096] Each panel (PP) has the aforementioned display area (DA) and peripheral area (SA). Furthermore, the peripheral area (SA) includes an inspection area (TA). The inspection area (TA) contains inspection pads and other components for inspecting the operation of the display panel's PNL (Parallel Link Module).

[0097] A cutting line CL2 is formed on each panel portion PP. The panel portion PP is divided by the cutting line CL2 into a portion including the display area DA and a portion including the inspection area TA.

[0098] When manufacturing the display device DSP, the panel portion PP is first cut out from the mother substrate MB along the cutting line CL1. Then, the cut panel portion PP is inspected using the aforementioned inspection pads. After this inspection, the inspection area TA is cut off from the panel portion PP along the cutting line CL2.

[0099] Figure 4 The test pattern TG shown can be configured not only in the blank area BA, but also in the surrounding area SA. For example, the test pattern TG can be configured in the inspection area TA. In this case, no test pattern TG remains in the panel portion PP after the inspection area TA is cut off along the cutting line CL2. Figure 4 As shown, when the test pattern TG is placed in the blank area BA, no test pattern TG remains in the panel PP after the inspection area TA is cut off along the cutting line CL2.

[0100] As another example, the test pattern TG can also be configured in the peripheral area SA, excluding the inspection area TA. In this case, the test pattern TG remains in the panel portion PP after the inspection area TA is cut off along the cutting line CL2.

[0101] Figure 6This is a schematic top view showing an example of the configuration of a test pattern TG applicable to a mother substrate MB according to the first embodiment. Figure 7 It is along Figure 6 A schematic cross-sectional view of the mother substrate MB along line VII-VII. Figure 7 Elements below the organic insulating layer 12 are omitted.

[0102] like Figure 6 As shown, the test pattern TG consists of rib layer 5 and septum 7 (first septum). Rib layer 5 covers the entire surface. Figure 4 The panel portion PP and the blank area BA are arranged as shown. A partition 7 is arranged in the blank area BA. It should be noted that the partition 7 can also be arranged in the peripheral area SA. The partition 7 extends in the X and Y directions (first direction) and is formed in a grid pattern. Figure 6 In the example, the partition 7 has partition openings 701, 702, and 703.

[0103] For example, the shape and layout of the adjacent openings 701, 702, and 703 are similar to... Figure 2 The partition openings 601, 602, and 603 shown have the same shape and layout. However, the partition 7 may also have one or more openings with different shapes than the partition openings 601, 602, and 603.

[0104] like Figure 6 and Figure 7 As shown, the partition 7 includes a conductive lower portion 71 disposed on the rib layer 5 and an upper portion 72 (first upper portion) disposed on the lower portion 71. The upper portion 72 has a wider width than the lower portion 71. As a result, both ends of the upper portion 72 protrude beyond the sides of the lower portion 71.

[0105] The lower part 71 has a bottom layer 73 (first bottom layer) disposed on the rib layer 5 and a conductive shaft layer 74 (first shaft layer) disposed on the bottom layer 73. For example, the bottom layer 73 is formed to be thinner than the shaft layer 74.

[0106] The bottom layer 73 has a protrusion 77 projecting from the side surface 74S of the shaft layer 74. The length of the protrusion 77 in the X direction is defined as length L. Length L corresponds to the length of the side surface 74S of the shaft layer 74 and the end of the bottom layer 73 in the X direction. More specifically, length L corresponds to the length of the side surface 74S and the boundary 71B of the bottom layer 73 and the end of the bottom layer 73 in the X direction. Figure 7 In the example shown, the side 74S is formed into a cone shape. Figure 6 In the middle, the overlapping parts of the bottom layer 73 and the shaft layer 74 with the top layer 72 are indicated by dashed lines.

[0107] The upper portion 72 has a first film 75 and a second film 76 disposed on the first film 75. For example, the width of the second film 76 is slightly smaller than the width of the first film 75. However, it is not limited to this; the first film 75 and the second film 76 may also have the same width.

[0108] The thickness of the first thin film 75 is defined as thickness T. In the first embodiment, the thickness T is, in one example, 100 nm or less.

[0109] The upper part 72 has an eave 78 that protrudes from the side 74S of the axial layer 74. Figure 7 In the example shown, the length of the eaves 78 in the X direction is greater than the length L. That is, the protrusion 77 is completely covered by the eaves 78 when viewed from above.

[0110] The partition 7 can be formed in the same process as the partition 6 described above. In this case, the bottom layer 73 and the bottom layer 63 are formed of the same material, the shaft layer 74 and the shaft layer 64 are formed of the same material, the first film 75 and the first film 65 are formed of the same material, and the second film 76 and the second film 66 are formed of the same material.

[0111] like Figure 6 As shown, the upper part 72 has a groove 79 extending in a direction D1 (the second direction) that is inclined counterclockwise at an angle θ1 relative to the Y direction. The angle θ1 is, for example, an acute angle. Figure 6 In the example shown, the groove 79 is positioned between the partition openings 701 and 702 (the first partition opening and the second partition opening). It should be noted that the extension direction of the groove 79 is not limited to this example. For instance, the groove 79 may also extend in a direction inclined at an angle θ1 clockwise relative to the Y direction. Furthermore, the position of the groove 79 is not limited to the example shown.

[0112] The groove 79 has an end E1 that overlaps with the shaft layer 74 when viewed from above. The end E1 is formed in an arc shape. The groove 79 reaches the partition opening 702. Between the groove 79 and the partition opening 702, a portion of the upper part 72 is missing, and a portion of the bottom part 73 (the part marked with a diagonal line pattern) is exposed.

[0113] The groove 79 is formed by irradiating the upper part 72 with a laser. By irradiating the eaves 78 with the same laser, a portion of the eaves 78 is removed, exposing a portion of the bottom layer 73.

[0114] Figure 8 yes Figure 6 A magnified view of the area enclosed by the dashed-dot box VIII. Figure 8 In the middle, the parts of the bottom layer 73 and the shaft layer 74 that do not overlap with the top layer 72 are marked with diagonal lines.

[0115] The eaves 78 has a notch 78N and a protrusion 78V. The notch 78N corresponds to the portion removed from the eaves 78 using the aforementioned laser. In a top view, the notch 78N overlaps with the protrusion 77 and is adjacent to the groove 79 in direction D1. Furthermore, in a top view, the notch 78N overlaps with the boundary 71B of the bottom layer 73 and the shaft layer 74.

[0116] The protrusion 78V is formed in a convex shape in the Y direction and is adjacent to the notch 78N in the Y direction. The protrusion 78V is separated from the shaft layer 74, and a portion of the notch 78N is disposed between the protrusion 78V and the shaft layer 74. Figure 8 In the example shown, a portion of the protrusion 78V overlaps with the groove 79. The protrusion 78V is formed by scanning the laser described above in direction D1.

[0117] Figure 9 It is along Figure 8 A schematic cross-sectional view of the partition 7 along line IX-IX. The groove 79 is formed concavely towards the lower part 71. Figure 9 In this example, the groove 79 is formed on the first thin film 75 and the second thin film 76. It should be noted that the groove 79 can also reach the axial layer 74. The width and depth of the groove 79 vary depending on the output of the laser forming the groove 79, etc.

[0118] Figure 10 It is along Figure 8 A schematic cross-sectional view of the partition 7 along line XX. Figure 10 In the middle, the groove 79 reaches the boundary between the lower surface of the upper part 72 and the side surface 74S of the shaft layer 74. Therefore, in Figure 10 In the middle, the partition 7 does not have an eave 78 on the side of the partition opening 702.

[0119] Next, an example of a manufacturing method for a display device DSP will be described. Figure 11 This is a flowchart illustrating an example of a manufacturing method for a display device DSP. Figure 12A to Figure 12J This is a schematic cross-sectional view showing the process of forming the panel portion PP on the mother substrate MB. Figure 12A to Figure 12J In this paper, the focus is on the display area DA, and elements below the organic insulating layer 12 are omitted.

[0120] When forming the panel portion PP, a circuit layer 11 and an organic insulating layer 12 are first formed on the substrate 10 of the mother substrate MB. Figure 11 The next step is as follows (PR1). Figure 12A As shown, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12. Figure 11 Process PR2).

[0121] Next, as Figure 12BAs shown, the rib layer 5 of electrodes LE1, LE2, and LE3 is formed and covered by the entire mother substrate MB. Figure 11 (Process PR3). At this point in time, pixel openings AP1, AP2, and AP3 are not set in the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0122] After the rib layer 5 is formed, the process for forming the partition wall 6 is carried out. Figure 11 (Processes PR4 and PR5). In process PR4, such as... Figure 12C As shown, a first layer L1 for forming the bottom layer 63, a second layer L2 for forming the axial layer 64, a third layer L3 for forming the first thin film 65, and a fourth layer L4 for forming the second thin film 66 are sequentially formed on the entire mother substrate MB. Furthermore, a photoresist R1 is disposed on the fourth layer L4. The photoresist R1 is patterned into the shape of a partition 6. The first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 can be formed, for example, by sputtering.

[0123] In the subsequent step PR5, resist R1 is used as a mask, and layers L1, L2, L3, and L4 are patterned. In one example, layer L1 is formed of titanium nitride, layer L2 is formed of aluminum, layer L3 is formed of titanium, and layer L4 is formed of ITO. In this case, step PR5 may include: wet etching to remove the portion of layer L4 exposed from resist R1; dry etching to remove the portions of layers L1, L2, and L3 exposed from resist R1; and wet etching to reduce the width of layer L2. It should be noted that the etching performed in step PR5 is appropriately selected based on the structure and material of partition 6.

[0124] After process PR5, such as Figure 12D As shown, a partition 6 is formed in the display area DA. After the partition 6 is formed, the resist R1 is removed (stripped). In the wet etching process that reduces the width of the second layer L2 described above, the second film 66 (the fourth layer L4) may also be slightly etched. When this etch occurs, the width of the second film 66 becomes smaller than the width of the first film 65.

[0125] Next, the process for setting pixel apertures AP1, AP2, and AP3 is carried out. Figure 11 Process PR6). In process PR6, such as Figure 12E As shown, a photoresist R2 is formed covering the partition 6. Furthermore, using the photoresist R2 as a mask, dry etching is performed on the rib layer 5. Thus, as... Figure 12FAs shown, pixel openings AP1, AP2, and AP3 are formed in the rib layer 5 to expose the lower electrodes LE1, LE2, and LE3. After the above dry etching, the resist R2 is removed (stripped).

[0126] After process PR6, an action is taken to remove... Figure 1 The process of the rib layer 5 in the terminal part T shown ( Figure 11 Process PR7).

[0127] Figure 13A and Figure 13B This is a schematic cross-sectional view of the terminal portion T used to illustrate process PR7. As shown in the figure above, the terminal portion T has conductive pads PD (conductive layer). The pads PD are disposed, for example, on an insulating layer 110 formed of an inorganic insulating material. The pads PD and the insulating layer 110 include, for example, […]. Figure 3 In the circuit layer 11 shown, for example, the periphery of the pad PD is covered by an organic insulating layer 12.

[0128] Before process PR3, which forms rib layer 5, pad PD is formed in the peripheral area SA. In process PR3, pad PD is covered by rib layer 5. Therefore, at the point when process PR6 is completed, such as... Figure 13A As shown, the pad PD is covered by the rib layer 5. In process PR7, a photoresist R3 with an opening above the pad PD is disposed on the rib layer 5. Furthermore, the photoresist R3 is used as a mask to perform dry etching on the rib layer 5. Thus, as... Figure 13B As shown, a terminal opening APt, overlapping with and exposing the pad PD, is formed in the rib layer 5. After the above dry etching, the resist R3 is removed (stripped).

[0129] After process PR7, a process for forming display element DE1 is performed. Figure 11 Process PR8). When forming the display element DE1, firstly as... Figure 12G As shown, a laminated film FL1 and a sealing layer SE11 are formed. Figure 3 As shown, the laminated film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a capping layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the capping layer CP1 can be formed, for example, by vapor deposition. In addition, the sealing layer SE11 can be formed, for example, by CVD.

[0130] The laminated film FL1 and the sealing layer SE11 are formed not only in the display area DA of each panel portion PP, but also on the entire mother substrate MB, including the peripheral area SA and the blank area BA. The laminated film FL1 is divided into multiple parts by cantilevered partitions 6. The sealing layer SE11 continuously covers each of the partitioned parts of the laminated film FL1 and the partitions 6.

[0131] Next, the laminated film FL1 and the sealing layer SE11 are patterned. In this patterning, as... Figure 12G As shown, resist R4 is disposed on top of the sealing layer SE11. Resist R4 covers a portion of the sub-pixel SP1 and the surrounding partition 6.

[0132] Then, an etching process is performed using resist R4 as a mask. Thus, as... Figure 12H As shown, the portions of the laminated film FL1 and the sealing layer SE11 exposed from the resist R4 are removed. In other words, the portions of the laminated film FL1 and the sealing layer SE11 that overlap with the lower electrode LE1 remain, while the rest are removed. Thus, the display element DE1 is formed in the sub-pixel SP1. For example, in the peripheral area SA and the blank area BA, the laminated film FL1 and the sealing layer SE11 are removed by this etching process. This etching process may include wet etching and dry etching performed sequentially on the sealing layer SE11, the capping layer CP1, the upper electrode UE1, and the organic layer OR1. After the above etching, the resist R4 is removed (stripped off).

[0133] It should be noted that during the wet etching of the laminated film FL1, the laminated film FL1 above the partition wall 6 and below the sealing layer SE11 is also removed. This creates a gap between the sealing layer SE11 above the partition wall 6 and the partition wall 6. The laminated film FL1 constituting the display element DE1 is completely surrounded by the sealing layer SE11 and the partition wall 6, and therefore is not eroded by the aforementioned wet etching.

[0134] After process PR8, a process for forming display element DE2 is performed. Figure 11 The process PR9). Display element DE2 can be formed through the same steps as display element DE1. That is, when forming display element DE2, the laminated film FL2 and the sealing layer SE12 are formed integrally on the mother substrate MB. Figure 3 As shown, the laminated film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a capping layer CP2 covering the upper electrode UE2.

[0135] The organic layer OR2, the upper electrode UE2, and the capping layer CP2 can be formed, for example, by vapor deposition. Additionally, the sealing layer SE12 can be formed, for example, by CVD. The laminated film FL2 is divided into multiple portions by cantilevered partitions 6. The sealing layer SE12 continuously covers each of the separated portions of the laminated film FL2 and the partitions 6. Figure 12I As shown, display element DE2 is formed on sub-pixel SP2 by patterning such a laminated film FL2 and sealing layer SE2. For example, in the peripheral area SA and the blank area BA, the laminated film FL2 and sealing layer SE12 are removed by etching during this patterning.

[0136] After process PR9, a process for forming display element DE3 is performed. Figure 11 The process PR10). Display element DE3 can be formed through the same steps as display elements DE1 and DE2. That is, when forming display element DE3, the laminated film FL3 and the sealing layer SE13 are formed integrally on the mother substrate MB. Figure 3 As shown, the laminated film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a capping layer CP3 covering the upper electrode UE3.

[0137] The organic layer OR3, the upper electrode UE3, and the capping layer CP3 can be formed, for example, by vapor deposition. Additionally, the sealing layer SE13 can be formed, for example, by CVD. The laminated film FL3 is divided into multiple portions by cantilevered partitions 6. The sealing layer SE13 continuously covers each of the separated portions of the laminated film FL3 and the partitions 6. Figure 12J As shown, a display element DE3 is formed on a sub-pixel SP3 by patterning such a laminated film FL3 and sealing layer SE13. For example, in the peripheral region SA and the blank region BA, the laminated film FL3 and sealing layer SE13 are removed by etching during the patterning process.

[0138] It should be noted that this is an example of display elements DE1, DE2, and DE3 being formed in this order, but display elements DE1, DE2, and DE3 can also be formed in other orders.

[0139] After forming display elements DE1, DE2, and DE3, they are formed sequentially. Figure 3 The resin layer RS1, sealing layer SE2, and resin layer RS2 shown are shown. Figure 11 The process PR11). Then, each panel portion PP is cut from the mother substrate MB along the cutting line CL1 ( Figure 11 Process PR12).

[0140] Then, an inspection of each panel PP is carried out. Figure 11The process PR13). This inspection includes lighting checks of each display element DE1, DE2, and DE3 using inspection pads configured in the inspection area TA. After the inspection, the inspection area TA is cut along the cutting line CL2. Figure 11 (Process PR14). Thus, the display panel PNL is completed.

[0141] Similar to partition 6, partition 7 is formed in the peripheral region SA and the blank region BA through processes PR4 and PR5. That is, through processes PR4 and PR5, a bottom layer 73 is formed on the rib layer 5, a axial layer 74 is formed on the bottom layer 73, a first thin film 75 is formed on the axial layer 74, and a second thin film 76 is formed on the first thin film 75. However, the groove 79 is not formed immediately after process PR5 in the upper part 72 of partition 7. In the first embodiment, for example, the third layer L3 (first thin film 65) is formed with a thickness of 100 nm or less.

[0142] Figure 14A to Figure 14D This is a diagram illustrating an example of the process of removing a portion of the upper part 72. Figure 14A and Figure 14C This is a rough cross-sectional view of the process. Figure 14B and Figure 14D This is a general top view of the process. Figure 14B Is with Figure 14A Cross-sectional views at the same time point, Figure 14D Is with Figure 14C Cross-sectional views at the same point in time. Figure 14A and Figure 14C Elements below the rib layer 5 are omitted.

[0143] like Figure 14A As shown, laser device 100 is used to irradiate the upper part 72 with laser LS. At this time, as... Figure 14B As shown, the starting point for processing using laser LS overlaps with the shaft layer 74. Then, the laser LS scans in direction D1. That is, the laser LS scans from the position overlapping with the shaft layer 74 toward the eaves 78 on the side of the partition opening 702. The laser device 100 is configured, for example, to emit a laser LS with an infrared wavelength.

[0144] like Figure 14C and Figure 14D As shown, a groove 79 is formed in the upper part 72 by scanning with a laser LS. Additionally, a portion of the eaves 78 is removed using the laser LS, forming a notch 78N and a protrusion 78V in the eaves 78. Thus, the bottom layer 73 and the protrusion 77 can be seen from above. Then, the length L of the protrusion 77 is measured using a measuring device 200. The length L can be measured, for example, by analyzing an image obtained from a top-view photograph of the protrusion 77.

[0145] Figure 14A to Figure 14D The process shown can be performed, for example, after process PR7, which forms the terminal opening APt in the rib layer 5. However, it is not limited to this. Figure 14A to Figure 14D The process shown can also be performed after process PR6, which is used to set pixel openings AP1, AP2, and AP3 in rib layer 5.

[0146] like Figure 4 As shown, the measurement process can also be performed separately on multiple test patterns TG dispersed on the mother substrate MB. In this case, measurement deviations corresponding to the positions of the mother substrate MB can be suppressed. As another example, the measurement process can also be performed on a portion of the multiple test patterns TG.

[0147] As described above, in this embodiment, after a portion of the eaves 78 is removed using a laser LS, the length L of the protrusion 77 is measured. If the eaves 78 were not removed, the length L would need to be measured through a destructive inspection to observe the cross-section of the partition 7. Destructive inspection is difficult to perform during the manufacturing process of the display device DSP, and it is time-consuming and labor-intensive.

[0148] In contrast, as in this embodiment, by simply setting a test pattern TG that removes a portion of the eaves 78 using a laser LS, destructive inspection is not required, and the length L of the protrusion 77 can be measured by observation from above the mother substrate MB. Such measurement can be easily performed during the manufacturing of the display device DSP, and if the measurement results are deemed defective during inspection, manufacturing can be stopped without performing subsequent processes.

[0149] Furthermore, in this embodiment, a portion of the eaves 78 is removed by scanning the laser LS in a direction D1 inclined at an angle θ1 relative to the extension direction (Y direction) of the partition wall 7. Assuming that the laser LS is scanned parallel to the extension direction of the partition wall 7, it is difficult to aim the laser LS at the base of the eaves 78 (the boundary between the upper part 72 and the shaft layer 74) due to the influence of the processing accuracy and positioning accuracy of the laser device 100.

[0150] In contrast, according to this embodiment, the laser LS reliably transverses the base of the eaves 78. Therefore, high-precision machining and positioning are not required, enabling cost reduction and increased yield.

[0151] Furthermore, in this embodiment, the laser LS scans in direction D1 from a position overlapping with the axial layer 74 toward the eaves 78. Assuming the laser LS is scanned from the eaves 78 side toward the axial layer 74 in the opposite direction to D1, the laser LS first reaches the end of the eaves 78 in the partition 7. Therefore, the energy of the laser LS is concentrated at the end of the eaves 78, and the laser LS may penetrate the eaves 78 to process the bottom layer 73.

[0152] In contrast, according to this embodiment, the laser LS scans from the position overlapping with the shaft layer 74 toward the partition opening 702. Therefore, the energy of the laser LS is dispersed in the upper part 72, and the energy of the laser LS is not concentrated in the eaves 78. This prevents the laser LS from processing the bottom layer 73, and allows for accurate measurement of the length L of the protrusion 77.

[0153] Thus, according to this embodiment, inspection during the manufacturing process of the display device DSP can be effectively implemented. In addition to those described herein, various other suitable effects can be obtained according to this embodiment.

[0154] [Second Implementation]

[0155] Next, the second embodiment will be described. Figure 15 This is a schematic top view illustrating an example of the configuration of a test pattern TG applicable to a mother substrate MB according to the second embodiment. Elements that are the same or similar to those in the first embodiment are labeled with the same reference numerals, and repeated descriptions are omitted where appropriate.

[0156] like Figure 15 As shown, the upper part 72 has a groove 79 located on one side of the partition wall opening 702. Figure 15 In the example shown, the groove 79 is positioned between the partition openings 701 and 702. Between the groove 79 and the partition opening 702, a portion of the upper part 72 is missing, and a portion of the bottom part 73 (the part marked with a diagonal line) is exposed. It should be noted that the position of the groove 79 is not limited to the example shown. Alternatively, multiple grooves 79 and exposed portions of the bottom part 73 may be provided between the partition openings 701 and 702.

[0157] The groove 79 is formed by irradiating the upper part 72 with a laser. By irradiating the eaves 78 with the same laser, a portion of the eaves 78 is removed, exposing a portion of the bottom layer 73.

[0158] Figure 16 yes Figure 15 A magnified view of the area enclosed by the dashed-dot frame XVI. Figure 16 In the middle, the parts of the bottom layer 73 and the shaft layer 74 that do not overlap with the top layer 72 are marked with diagonal lines.

[0159] The eaves 78 has a notch 78N. The notch 78N corresponds to the portion removed from the eaves 78 by a laser that forms the groove 79. The boundary between the eaves 78 and the notch 78N is rounded. When viewed from above, the notch 78N overlaps with the boundary 71B between the bottom layer 73 and the axial layer 74. The groove 79 is formed along the notch 78N.

[0160] It should be noted that the cross-sectional structure of the partition wall 7, including the notch 78N and the groove 79, is similar to...Figure 10 The cross-section shown is constructed in the same manner. Additionally, in one example, the thickness T of the first thin film 75 in this embodiment is greater than 100 nm.

[0161] Figure 17 This is a cross-sectional view illustrating an example of the process of removing a portion of the upper part 72. Figure 17 Elements below the rib layer 5 are omitted.

[0162] like Figure 17 As shown, a photoresist R is formed covering the partition 7. Then, dry etching is performed using the photoresist R as a mask. After this dry etching, a laser LS is applied to a certain area encompassed by the eaves 78 using a laser device 100. This removes the portion of the eaves 78 and the photoresist R that was irradiated by the laser LS, forming a notch 78N in the eaves 78. Then, the photoresist R is removed (stripped off). After removing the photoresist R, [the process continues with...] Figure 14C The procedure shown also uses measuring device 200 to measure the length L of protrusion 77.

[0163] As Figure 17 The process shown can utilize process PR7, which forms the terminal opening Apt in rib layer 5. In this case, the resist R is equivalent to... Figure 13A and Figure 13B The resist R3 is shown. Additionally, the dry etching performed before laser LS irradiation is equivalent to the dry etching used to form the terminal opening APt in the rib layer 5.

[0164] It should be noted that, as Figure 17 The process shown can also utilize processes other than PR7. As an example, as... Figure 17 The process shown can utilize process PR6, which is used to form pixel openings AP1, AP2, and AP3 in rib layer 5. In this case, the resist R is equivalent to... Figure 12E and Figure 12F The resist R2 is shown. Additionally, the dry etching performed before irradiation with laser LS is equivalent to the dry etching used to form pixel openings AP1, AP2, and AP3 in rib layer 5.

[0165] In this embodiment, the removal process of the eaves 78 using laser LS is performed while the resist R covers the partition wall 7. Therefore, a portion of the energy of the laser LS is used for processing the resist R. In this case, compared to the case without resist R, the eaves 78 can be removed with almost no damage to the substrate 73.

[0166] Furthermore, in this embodiment, the removal process of the edge 78 using laser LS is performed after dry etching. Through this dry etching, the properties of the resist R change, therefore, compared to the case where laser LS is applied before dry etching, more energy from the laser LS is used to process the resist R. Thus, damage to the underlying layer 73 can be further reduced.

[0167] Furthermore, in the first embodiment, the laser LS is scanned in one direction, while in this embodiment, the laser LS is irradiated within a certain range. Therefore, in this embodiment, even if the thickness T of the first thin film 75 is thicker than that in the first embodiment, the eaves 78 can still be removed. For example, in this embodiment, even if the thickness T of the first thin film 75 is greater than 100 nm, the eaves 78 can still be removed.

[0168] Furthermore, the mother substrate MB and the manufacturing method of the mother substrate MB according to the second embodiment achieve the same effect as the mother substrate MB and the manufacturing method of the mother substrate MB according to the first embodiment described above.

[0169] [Third Implementation]

[0170] Next, the third embodiment will be described. Figure 18 This is a schematic top view showing an example of the configuration of a test pattern TG applicable to a mother substrate MB according to the third embodiment. Figure 19 It is along Figure 18 A schematic cross-sectional view of the mother substrate MB of the XIX-XIX line. Figure 19 Elements below the organic insulating layer 12 are omitted.

[0171] Part 7 has Part 1 P1 (the part marked with diagonal lines) and Part 2 P2 (the part marked with dots). Figure 18 In this example, part 1, P1, is located between the partition openings 701 and 702. The portion of partition 7 excluding part 1, P1, is equivalent to part 2, P2. It should be noted that the location of part 1, P1, is not limited to this example.

[0172] like Figure 18 and Figure 19 As shown, the first part P1 includes a lower part 71 (bottom layer 73 and axial layer 74) similar to the partition 6. However, the first part P1 does not include the upper part 72 (first film 75 and second film 76). Therefore, the upper surface 74U of the axial layer 74 is exposed in the first part P1.

[0173] On the other hand, such as Figure 19As shown, the second part P2 includes a lower part 71 (bottom layer 73 and axial layer 74) and an upper part 72 (first thin film 75 and second thin film 76). Therefore, the upper surface 74U of the axial layer 74 is covered by the upper part 72 in the second part P2. In one example, the thickness T of the first thin film 75 of the second part P2 is greater than 100 nm.

[0174] exist Figure 18 In the diagram, the outlines of the bottom layer 73 and the shaft layer 74 of part P2 are represented by dashed lines. For example, the bottom layer 73 of part P2 is connected to the bottom layer 73 of part P1. Similarly, the shaft layer 74 of part P2 is connected to the shaft layer 74 of part P1.

[0175] like Figure 19 As shown, the lower part 71 of part 1 P1 and part 2 P2 is disposed on the rib layer 5. Figure 18 and Figure 19 In the example, the rib layer 5 is flat between the partition opening 701 and the first part P1, and between the partition opening 702 and the first part P1. However, the rib layer 5 may also have openings located around the first part P1, for example.

[0176] Figure 20A to Figure 20E This is a schematic cross-sectional view showing an example of the process of forming part P1. The above cross-sectional view shows... Figure 19 The same position is used, and elements below the organic insulating layer 12 are omitted. In the following description, the portion of partition 7 in which the first part P1 is formed is designated as partition 7A, and the portion of partition 7 in which the second part P2 is formed is designated as partition 7B.

[0177] When forming part P1, as follows Figure 20A As shown, a photoresist R is formed covering partitions 7A and 7B. Furthermore, as indicated by several arrows, a mask MK is used to expose the photoresist R. The mask MK has an opening MA above partition 7A. The width W2 of the opening MA is smaller than the width W1 of the upper part 72 (in... Figure 20A (W2 is the width of the first thin film 75). In one example, the width W2 is about 2 μm smaller than the width W1. In another example, the width W2 is almost the same as the width W3 of the axial layer 74.

[0178] The resist R is, for example, a positive type. Therefore, as... Figure 20B As shown, the exposed portion of the resist R is removed during the developing process. Consequently, between the partition openings 701 and 702, a portion of the upper part 72 of the partition 7A is exposed from the resist R. The width of the portion removed during the developing process is almost equal to the width W2 of the opening MA of the mask MK.

[0179] exist Figure 20BIn the middle, partition wall 7B is entirely covered by resist R. Additionally, a portion of the second film 76 of partition wall 7A is exposed from the resist R. Furthermore, both ends of the upper portion 72 of partition wall 7A are covered by resist R. Figure 20B In the partition wall 7A, the two ends of the first film 75 and the second film 76 are each covered by the resist R. The rib layer 5 around the partition wall 7A is not exposed from the resist R.

[0180] Next, an etching process is performed with the resist R applied. This etching process includes... Figure 20C The wet etching (first etching) shown and Figure 20D The dry etching shown is the second etching.

[0181] like Figure 20C As shown, the second film 76 of partition 7A is removed by wet etching, exposing the upper surface of the first film 75 of partition 7A. The upper part 72 of partition 7B is covered by resist R and therefore will not be removed by this wet etching.

[0182] After wet etching, such as Figure 20C As shown, the two ends of the first film 75 of the partition wall 7A can be covered by the resist R or exposed from the resist R.

[0183] After the above wet etching, as Figure 20D As shown, the first thin film 75 of partition 7A is removed by dry etching. As a result, the upper portion 72 of partition 7A is removed, exposing the upper surface of the axial layer 74 of partition 7A. The upper portion 72 of partition 7B is covered by resist R and therefore is not removed by this dry etching.

[0184] After the above etching process, such as Figure 20E As shown, the resist R is removed (stripped). After the above process, part 1 P1 and part 2 P2 are formed. The portion of the rib layer 5 located around part 1 P1 is covered by the resist R and is therefore flat. Specifically, the rib layer 5 is flat between the partition wall opening 701 and part 1 P1, and between the partition wall opening 702 and part 1 P1.

[0185] Using the first part P1 formed in this way, the length L of the protrusion 77 is measured in the same manner as in the first and second embodiments.

[0186] As Figure 20A to Figure 20E The process shown can utilize process PR7, which forms the terminal opening Apt in rib layer 5. In this case, the resist R is equivalent to... Figure 13A and Figure 13BThe resist R3 is shown. Furthermore, the dry etching for removing the first thin film 75 of the partition wall 7A is equivalent to the dry etching for forming the terminal opening APt in the rib layer 5. It should be noted that the dry etching for removing the first thin film 75 of the partition wall 7A and the dry etching for forming the terminal opening APt in the rib layer 5 can be performed simultaneously or separately. That is, the dry etching for forming the terminal opening APt in the rib layer 5 (the third etching) can be performed after the dry etching for removing the first thin film 75 of the partition wall 7A. Compared to performing dry etching simultaneously, performing dry etching separately allows for more accurate and precise removal of the first thin film 75 and formation of the terminal opening APt. On the other hand, performing dry etching simultaneously can suppress the increase in workload.

[0187] In this embodiment, the upper portion 72 of the first part P1 is removed by performing an etching process. Therefore, even when the thickness T of the first film 75 is relatively thick, the upper portion 72 (eaves 78) can be removed. For example, in this embodiment, even if the thickness T of the first film 75 is greater than 100 nm, the upper portion 72 can be removed.

[0188] Furthermore, in this embodiment, the width W2 of the opening MA of the mask MK is smaller than the width W1 of the upper part 72. It is assumed that if the width W2 is greater than the width W1, the protrusion 77 may be etched. Therefore, by making the width W2 smaller than the width W1, the erosion of the protrusion 77 can be suppressed.

[0189] Furthermore, if the width W2 is too small compared to the width W1, the eaves 78 may not be completely removed, leaving residue. If the residual eaves 78 separates from the mother substrate MB during the manufacturing process, it will adversely affect other products and equipment, and the yield will deteriorate. In this embodiment, the width W2 is about 2 μm smaller than the width W1. In another example, the width W2 is almost equal to the width W3 of the shaft layer 74. Under these conditions, the eaves 78 can be completely removed by etching, thereby suppressing the deterioration of the yield.

[0190] Furthermore, the mother substrate MB and the manufacturing method of the mother substrate MB according to the third embodiment achieve the same effects as the mother substrate MB and the manufacturing method of the mother substrate MB according to the first and second embodiments described above.

[0191] Any mother substrate and mother substrate manufacturing method that can be implemented by those skilled in the art by making appropriate design modifications based on the mother substrate and mother substrate manufacturing method described above as embodiments of the present invention, as long as they contain the spirit of the present invention, are also within the scope of the present invention.

[0192] Within the scope of the present invention, various modifications will be conceived by those skilled in the art, and these modifications should also be understood to fall within the scope of the present invention. For example, solutions obtained by appropriately adding, deleting, or designing the constituent elements of the above-described embodiments, or solutions obtained by adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention as long as they possess the spirit of the present invention.

[0193] Furthermore, any other effects resulting from the solutions described in the above embodiments, effects that are clearly known from the description in this specification or technical effects that can be reasonably conceived by those skilled in the art, should of course be understood as effects resulting from the present invention.

Claims

1. A mother substrate, which comprises: Each panel includes a display area and a surrounding area of ​​the display area; The blank area around the plurality of panels; The lower electrode is configured in the display area; A rib layer having pixel openings overlapping the lower electrode and disposed in the panel portion and the blank area; and Located in the first partition of the blank area, The first partition wall includes: a first bottom layer disposed on the rib layer; and a first axial layer disposed on the first bottom layer and having electrical conductivity; and the first upper part configured above the first axis layer, The first bottom layer has a protrusion that extends from the side of the first axial layer. The first upper part has an eave that protrudes from the side of the first axial layer. The eaves have a notch that overlaps with the protrusion when viewed from above. The gap overlaps with the boundary between the first bottom layer and the first axis layer when viewed from above.

2. The mother substrate as claimed in claim 1, wherein, The first upper part also has a groove extending in a second direction that is inclined relative to a first direction extending from the first partition wall. The notch is adjacent to the groove.

3. The mother substrate as described in claim 2, wherein, The eaves also have a convex protrusion in the first direction. The protrusion is adjacent to the notch.

4. The mother substrate as described in claim 2, wherein, One end of the groove overlaps with the first axis layer when viewed from above.

5. The mother substrate as described in claim 2, wherein, The second direction is inclined at an acute angle relative to the first direction.

6. The mother substrate as claimed in claim 2, wherein, The first upper portion includes: a first thin film disposed on the first axial layer and formed of a material comprising titanium; and a second thin film disposed on the first thin film and formed of ITO. The thickness of the first thin film is less than 100 nm.

7. The mother substrate as claimed in claim 1, wherein, The first upper part also has a groove along the notch.

8. The mother substrate as claimed in claim 7, wherein, The boundary between the eaves and the notch is rounded.

9. The mother substrate as claimed in claim 2 or 7, wherein, The first partition also includes a first partition opening and a second partition opening adjacent to the first partition opening. The groove is disposed between the first partition opening and the second partition opening.

10. A mother substrate, which comprises: Each panel includes a display area and a surrounding area of ​​the display area; The blank area around the plurality of panels; The lower electrode is configured in the display area; A rib layer having a pixel opening overlapping the lower electrode and disposed in the panel portion and the blank area; and Located in the first partition of the blank area, The first partition wall includes: a first bottom layer disposed above the rib layer; a first axial layer disposed above the first bottom layer and having conductivity; a first upper portion disposed above the first axial layer; a first partition wall opening; a second partition wall opening adjacent to the first partition wall opening; and a first portion located between the first partition wall opening and the second partition wall opening. The first bottom layer has a protrusion that extends from the side of the first axial layer. The upper surface of the first axial layer is exposed in the first part.

11. The mother substrate as claimed in claim 10, wherein, The rib layer is flat between the first partition opening and the first part, and between the second partition opening and the first part.

12. The mother substrate as claimed in claim 7 or 10, wherein, The first upper portion includes: a first thin film disposed on the first axial layer and formed of a material comprising titanium; and a second thin film disposed on the first thin film and formed of ITO. The thickness of the first thin film is greater than 100 nm.

13. The mother substrate as claimed in claim 1 or 10, further comprising a second partition wall disposed in the display area and surrounding the pixel opening. The second partition includes: A second bottom layer disposed above the rib layer; a second axis layer disposed above the second bottom layer; And the second upper part configured above the second axis layer.

14. The mother substrate as claimed in claim 13, further comprising: An organic layer that is connected to the lower electrode through the pixel opening; An upper electrode disposed on the organic layer and connected to the second axial layer; A capping layer disposed above the upper electrode; and A sealing layer disposed on the cover layer, The second partition wall surrounds the lower electrode, the organic layer, the upper electrode, and the capping layer.

15. A method for manufacturing a mother substrate, wherein, A substrate is prepared comprising a panel portion and a surrounding blank area, wherein the panel portion includes a display area and a surrounding peripheral area. A lower electrode is formed in the display area. A rib layer is formed to cover the panel portion and the blank area. A first partition wall is formed in the blank area, the first partition wall comprising: a first bottom layer formed on the rib layer; a first axial layer formed on the first bottom layer and having conductivity; and a first upper portion formed on the first axial layer. The laser is scanned in a second direction, inclined relative to a first direction extending from the first partition wall, to remove a portion of the eaves protruding from the side of the first axial layer in the first upper part. The length of the protrusion protruding from the side of the first axial layer in the first bottom layer is measured.

16. The method for manufacturing a mother substrate as described in claim 15, wherein, In the process of removing a portion of the eaves, the laser is used to scan from the portion of the first upper part that overlaps with the first axial layer toward the eaves.

17. The method for manufacturing a mother substrate as described in claim 15, wherein, Prior to the process of forming the rib layer, a conductive layer is formed in the peripheral region. In the process of forming the rib layer, the rib layer covering the conductive layer is formed. Between the process of forming the first partition wall and the process of removing a portion of the eaves, a terminal opening overlapping the conductive layer is formed in the rib layer.

18. The method for manufacturing a mother substrate as described in claim 15, wherein, The process of forming the first upper part includes: a process of forming a first thin film on the first axial layer using a material containing titanium; and a process of forming a second thin film on the first thin film using ITO. The first thin film is formed with a thickness of less than 100 nm.

19. A method for manufacturing a mother substrate, wherein, A substrate is prepared comprising a panel portion and a surrounding blank area, wherein the panel portion includes a display area and a surrounding peripheral area. A lower electrode is formed in the display area. A rib layer is formed to cover the panel portion and the blank area. A first partition wall is formed in the blank area, the first partition wall comprising: a first bottom layer formed on the rib layer; a first axial layer formed on the first bottom layer and having conductivity; and a first upper portion formed on the first axial layer. A resist agent is formed covering the first partition wall. A portion of the eaves protruding from the side of the first axial layer in the first upper part and the portion of the resist that overlaps with the eaves are simultaneously removed using a laser. The length of the protrusion protruding from the side of the first axial layer in the first bottom layer is measured.

20. The method for manufacturing a mother substrate as described in claim 19, wherein, Prior to the process of forming the rib layer, a conductive layer is formed in the peripheral region. In the process of forming the rib layer, the rib layer covering the conductive layer is formed. Between the process of forming the resist and the process of removing a portion of the eaves, dry etching is performed to form terminal openings in the rib layer that overlap with the conductive layer.

21. The method for manufacturing a mother substrate as described in claim 19, wherein, The process of forming the first upper part includes: a process of forming a first thin film on the first axial layer using a material containing titanium; and a process of forming a second thin film on the first thin film using ITO. The first thin film is formed with a thickness greater than 100 nm.

22. A method for manufacturing a mother substrate, wherein, A substrate is prepared comprising a panel portion and a surrounding blank area, wherein the panel portion includes a display area and a surrounding peripheral area. A lower electrode is formed in the display area. A rib layer is formed to cover the panel portion and the blank area. A first partition wall is formed in the blank area, the first partition wall comprising: a first bottom layer formed on the rib layer; a first axial layer formed on the first bottom layer and having conductivity; a first upper portion formed on the first axial layer; a first partition wall opening; and a second partition wall opening adjacent to the first partition wall opening. At least a portion of the upper part of the first partition wall is exposed as resist between the opening of the first partition wall and the opening of the second partition wall. The first upper portion exposed from the resist is removed by etching. The length of the protrusion protruding from the side of the first axial layer in the first bottom layer is measured.

23. The method for manufacturing a mother substrate as described in claim 22, wherein, The process of forming the first upper part includes: a process of forming a first thin film on the first axial layer using a material containing titanium; and a process of forming a second thin film on the first thin film using ITO. The first thin film is formed with a thickness greater than 100 nm.

24. The method for manufacturing a mother substrate as described in claim 23, wherein, The process of removing the first upper portion includes: a process of removing the second film exposed from the resist by performing a first etching; and a process of removing the first film exposed from the resist by performing a second etching.

25. The method for manufacturing a mother substrate as described in claim 24, wherein, Prior to the process of forming the rib layer, a conductive layer is formed in the peripheral region. In the process of forming the rib layer, the rib layer covering the conductive layer is formed. By performing the second etching, a terminal opening overlapping the conductive layer is formed in the rib layer.

26. The method for manufacturing a mother substrate as described in claim 24 or 25, wherein, The first etching is a wet etching. The second etching is a dry etching.

27. The method for manufacturing a mother substrate as described in claim 24, wherein, Prior to the process of forming the rib layer, a conductive layer is formed in the peripheral region. In the process of forming the rib layer, the rib layer covering the conductive layer is formed. After the second etching, a third etching is performed to form a terminal opening in the rib layer that overlaps with the conductive layer.

28. The method for manufacturing a mother substrate as described in claim 27, wherein, The first etching is a wet etching. The second etching is a dry etching. The third etching is a dry etching.

29. The method for manufacturing a mother substrate as described in claim 22, wherein, In the process of forming the resist, the resist is exposed using a mask having an opening with a width smaller than that of the first upper part.

30. The method for manufacturing a mother substrate as described in claim 15, 19, or 22, wherein, In the process of forming the first partition wall, a second partition wall is formed in the display area, the second partition wall comprising: a second bottom layer formed on the rib layer; a second axial layer formed on the second bottom layer and having conductivity; and a second upper portion formed on the second axial layer.

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