Semiconductor structure and method of fabricating the same

Abstract

The application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, an etching stop layer arranged on the surface of the substrate, a plurality of implantation masks arranged on the surface of the etching stop layer, and an opening between two adjacent implantation masks. The etching stop layer comprises a first part exposed from the bottom of the opening and a second part below the implantation mask. The thickness of the first part gradually decreases from the middle to both sides. The special morphology of the first part can compensate the bottom profile of the ion implantation region in advance when the ion implantation is performed through the opening, which can significantly reduce the inconsistency of the implantation depth in the substrate, make the bottom profile of the ion implantation region more flat, and avoid the electric property problems such as leakage, thereby improving the reliability of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor processing, and in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] In semiconductor manufacturing, ion implantation process is often performed on a substrate to form a specific region in the substrate that meets certain performance requirements. In order to perform ion implantation on a specific region in the substrate, an implantation mask is usually formed on the surface of the substrate first to shield the region on the substrate that does not need to be subjected to ion implantation, and the substrate is subjected to the required ion implantation through an opening (implantation window) formed between two adjacent implantation masks. The method of forming the implantation mask generally comprises sequentially forming an etching stop layer and an implantation mask layer on the surface of the substrate, performing patterned etching on the implantation mask layer, and using the etching stop layer to stop etching on the etching stop layer by virtue of the etching stop effect of the etching stop layer, so as to avoid exposing the underlying substrate surface and thus protect the substrate, thereby forming the implantation mask on the etching stop layer.

[0003] In the current implantation mask layer etching process in semiconductor manufacturing, when etching is terminated, the topography of the etching stop layer located at the bottom of the opening region is generally flat or thin in the middle and thick on both sides. As a result, due to the certain blocking effect of the etching stop layer on implantation ions, after the subsequent ion implantation process, the bottom profile of the ion implantation region formed in the underlying substrate will be arc-shaped, i.e., the problem of inconsistent implantation depth occurs, which may cause the arc bottom of the bottom profile of the ion implantation region to be too close to the back surface of the substrate, thus easily causing electrical problems such as substrate leakage. Therefore, it is necessary to study a process method that can significantly reduce the inconsistency of implantation depth in the substrate. SUMMARY

[0004] The present application aims to overcome the above-mentioned problems existing in the prior art, and provides a semiconductor structure and a manufacturing method thereof to significantly reduce the inconsistency of implantation depth in the substrate and make the bottom profile of the formed ion implantation region more flat.

[0005] To achieve the above-mentioned purpose, the technical solutions of the present application are as follows:

[0006] According to a first aspect of the present application, an embodiment of the present application provides a semiconductor structure, comprising:

[0007] a substrate;

[0008] an etching stop layer arranged on the surface of the substrate;

[0009] a plurality of implantation masks arranged on the surface of the etching stop layer, and having an opening between two adjacent implantation masks;

[0010] The etching stop layer includes a first portion exposed from a bottom of the opening and a second portion located below the implantation mask, the first portion gradually decreases in thickness from the middle to both sides.

[0011] In some embodiments, further comprising: an ion implantation region in the substrate, wherein the ion implantation region is formed by ion implantation to the substrate through the opening, and the first portion is used to compensate the bottom profile of the ion implantation region in advance when the ion implantation is performed.

[0012] In some embodiments, the surface of the first portion includes a curved surface.

[0013] In some embodiments, the surface of the first portion includes an inclined surface.

[0014] In some embodiments, a ratio of the maximum thickness to the minimum thickness of the first portion is 5:1 to 1.5:1.

[0015] In some embodiments, the maximum thickness of the first portion is less than the thickness of the second portion.

[0016] In some embodiments, the first portion and the second portion are connected to a bottom end of a sidewall of the opening, and a part of an end surface of the second portion connected to the first portion is exposed from the sidewall of the opening.

[0017] In some embodiments, a protective layer is further provided on the surface of the substrate, and the protective layer is located between the substrate and the etching stop layer, and the material of the protective layer is different from the material of the etching stop layer.

[0018] In some embodiments, the material of the protective layer is the same as or different from the material of the implantation mask.

[0019] In some embodiments, the implantation mask is a hard mask.

[0020] According to a second aspect of the present application, the embodiments of the present application further provide a semiconductor structure manufacturing method, comprising:

[0021] providing a substrate;

[0022] forming an etching stop layer and a mask layer on the surface of the substrate in sequence;

[0023] performing an etching process to pattern the mask layer, and forming a plurality of implantation masks on the surface of the etching stop layer, adjacent two implantation masks have an opening therebetween, the etching stop layer includes a first portion exposed from a bottom of the opening and a second portion located below the implantation mask;

[0024] The thickness of the first portion is gradually reduced from the middle to both sides by adjusting a process menu of the etching process and using over-etching.

[0025] In some embodiments, the adjusting of the process menu of the etching process includes adjusting at least one of pressure, flow rate of a reaction gas, and bias power, at the latest when the etching reaches the surface of the etching stop layer.

[0026] In some embodiments, the adjusting of at least one of pressure, flow rate of a reaction gas, and bias power includes at least one of reducing pressure, reducing flow rate of a reaction gas, and increasing bias power.

[0027] In some embodiments, the reducing of pressure includes reducing pressure from 140mTorr to 120mTorr to 90mTorr to 70mTorr.

[0028] In some embodiments, the reducing of flow rate of a reaction gas includes reducing flow rate of a reaction gas from 130sccm to 110sccm to 90sccm to 70sccm.

[0029] In some embodiments, the increasing of bias power includes increasing bias power from 190W to 210W to 390W to 410W.

[0030] In some embodiments, the method further includes ion implantation through the opening to the substrate to form an ion implantation region in the substrate, and the first portion is used to compensate in advance a bottom profile of the formed ion implantation region when ion implantation is performed.

[0031] In some embodiments, before forming the etching stop layer, the method further includes forming a protection layer on a surface of the substrate, and then forming the etching stop layer on a surface of the protection layer.

[0032] In some embodiments, a material of the protection layer includes silicon oxide.

[0033] In some embodiments, a material of the mask layer includes silicon oxide.

[0034] In some embodiments, a material of the etching stop layer includes silicon nitride.

[0035] In some embodiments, a reaction gas used in the etching process includes CHF3.

[0036] The embodiment of the present application sets the thickness of the etching stop layer exposed on the bottom of the opening as the implantation window to gradually decrease from the middle to both sides, so that when the ion implantation is performed on the substrate through the opening, the special morphology of the etching stop layer on the bottom of the opening is used to compensate the bottom profile of the formed ion implantation region in advance, which can significantly reduce the inconsistency of the implantation depth in the substrate, make the bottom profile of the formed ion implantation region more flat, thereby improving the morphology after ion implantation, and effectively avoiding the electrical problems such as leakage caused by the arc bottom of the ion implantation region being too close to the back surface of the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 It is a structure diagram of the etching stop layer on the bottom of the existing implantation window having a morphology of thin in the middle and thick on both sides.

[0038] Figure 2 It is a bottom profile structure diagram of the ion implantation region obtained by performing ion implantation through the implantation window in Figure 1 .

[0039] Figure 3 It is a structure diagram of the etching stop layer on the bottom of the existing implantation window having a flat morphology.

[0040] Figure 4 It is a bottom profile structure diagram of the ion implantation region obtained by performing ion implantation through the implantation window in Figure 3 .

[0041] Figures 5-6 It is a schematic diagram of a semiconductor structure of a preferred embodiment of the present application.

[0042] Figure 7 It is a flowchart of a semiconductor structure manufacturing method provided by a preferred embodiment of the present application.

[0043] Figure 8 It is a structure diagram provided by a preferred embodiment of the present application after forming the etching stop layer and the mask layer on the substrate.

[0044] Figure 9 It is a structure diagram provided by a preferred embodiment of the present application after forming a photoetching pattern on the mask layer.

[0045] Figure 10 It is a structure diagram provided by a preferred embodiment of the present application after forming an implantation window on the substrate.

[0046] Figure 11 It is a structure diagram provided by a preferred embodiment of the present application after forming an ion implantation region in the substrate.

[0047] Figure 12This is an electron microscope schematic diagram showing the etch stop layer at the bottom of the injection window, which has a thick middle and thin sides, according to a preferred embodiment of this application. Detailed Implementation

[0048] refer to Figure 1 and Figure 2 .like Figure 1 As shown, this illustrates the structure when two implantation masks 11 are formed on a substrate 10 using a conventional implantation mask etching process. An opening 12, serving as an implantation window, is located between the two implantation masks 11, allowing ion implantation into the substrate 10. In this example, the etch stop layer 13 at the bottom of the opening 12 has a morphology that is thin in the middle and thick at the edges. After subsequent ion implantation processes, the bottom contour 141 of the ion implantation region 14 formed in the lower substrate 10 is arc-shaped. That is, the distance from each point on the bottom contour 141 of the ion implantation region 14 to the back surface (lower surface) of the substrate 10 gradually increases from the lowest point of the arc to both sides (the distance a from the arc bottom to the back surface of the substrate 10 is less than the distance b from any point on the bottom contour 141 of the ion implantation region 14 outside the arc bottom to the back surface of the substrate 10, i.e., a < b). Figure 2 As shown, this results in inconsistent implantation depths, which may cause the bottom of the arc-shaped contour 141 of the ion implantation region 14 to be too close to the back surface of the substrate 10, thus easily leading to electrical problems such as substrate leakage.

[0049] refer to Figure 3 and Figure 4 .like Figure 3 As shown, this illustrates the structure when two implantation masks 11 are formed on substrate 10 using a conventional implantation mask etching process. In this example, the morphology of the etching stop layer 13 located at the bottom of the opening 12 has a flat morphology. After subsequent ion implantation processes, the bottom contour 141 of the ion implantation region 14 formed in the lower substrate 10 is arc-shaped, meaning that the distance from each point on the bottom contour of the ion implantation region 14 to the back surface of the substrate 10 gradually increases from the lowest arc bottom to both sides (the distance a from the arc bottom to the back surface of the substrate 10 is less than the distance b from any point on the bottom contour 141 of the ion implantation region 14 outside the arc bottom to the back surface of the substrate 10, i.e., a < b). Figure 4 As shown. Figure 4 The bottom contour 141 of the ion implantation region 14 and Figure 2 Compared to the bottom contour 141 of the ion implantation region 14, the difference lies in the relatively smaller curvature of the arc. However, since there is still a problem of inconsistent implantation depth, it is still possible to cause electrical problems such as substrate leakage due to the arc bottom of the bottom contour 141 of the ion implantation region 14 being too close to the back side of the substrate 10.

[0050] In view of the above problems existing in the prior art, the embodiment of the present application provides a semiconductor structure, comprising:

[0051] a substrate;

[0052] an etching stop layer arranged on the surface of the substrate;

[0053] a plurality of implantation masks arranged on the surface of the etching stop layer, and adjacent two implantation masks have an opening therebetween;

[0054] the etching stop layer comprises a first part exposed from the bottom of the opening and a second part located below the implantation mask, and the thickness of the first part gradually decreases from the middle to both sides.

[0055] Furthermore, the embodiment of the present application also provides a semiconductor structure manufacturing method, comprising:

[0056] providing a substrate;

[0057] forming an etching stop layer and a mask layer on the surface of the substrate in sequence;

[0058] performing an etching process to pattern the mask layer and form a plurality of implantation masks on the surface of the etching stop layer, and adjacent two implantation masks have an opening therebetween, and the etching stop layer comprises a first part exposed from the bottom of the opening and a second part located below the implantation mask;

[0059] wherein the thickness of the first part gradually decreases from the middle to both sides by adjusting the process menu of the etching process and using over-etching.

[0060] The embodiment of the present application can compensate the bottom profile of the formed ion implantation region in advance by using the special morphology of the etching stop layer on the bottom of the opening when performing ion implantation on the substrate through the opening, can significantly reduce the inconsistency of the implantation depth in the substrate, and can make the bottom profile of the formed ion implantation region more flat, thereby improving the morphology after ion implantation and effectively avoiding the electrical problems such as leakage caused by the arc-shaped bottom profile of the ion implantation region.

[0061] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0062] Reference Figure 5A semiconductor structure according to an embodiment of the present application includes a substrate 20, an etching stop layer 23 disposed on an upper surface of the substrate 20, and a plurality of implantation masks 21 disposed on an upper surface of the etching stop layer 23. Adjacent two implantation masks 21 have an opening 22 therebetween, which serves as an implantation window for ion implantation on the underlying substrate 20.

[0063] It should be noted that, Figure 5 In the above embodiment, only a case where two implantation masks 21 are formed on the upper surface of the etching stop layer 23 is shown. However, it should be understood that more implantation masks can be formed on the upper surface of the etching stop layer 23, such as three implantation masks, four implantation masks, ten implantation masks, etc., and the number of implantation masks is not limited thereto.

[0064] The etching stop layer 23 includes a first portion 231 exposed from a bottom of the opening 22, and a second portion 232 located below any one of the implantation masks 21. In addition, the thickness of the first portion 231 of the etching stop layer 23 gradually decreases (thins) from the middle to both sides. For example, the thickness of the first portion 231 of the etching stop layer 23 gradually decreases from the middle to both sides of the opening 22.

[0065] In some embodiments, the first portion 231 and the second portion 232 are connected as a whole by an end portion in a horizontal direction along the upper surface of the substrate 20, and jointly constitute the etching stop layer 23.

[0066] In some embodiments, the film thickness of the second portion 232 is uniform (or substantially uniform) everywhere.

[0067] In some embodiments, the upper surface and the lower surface of the second portion 232 are planar (or substantially planar).

[0068] In some embodiments, the upper surface and the lower surface of the second portion 232 are parallel (or substantially parallel) to the upper surface of the substrate 20.

[0069] In some embodiments, the lower surface of the first portion 231 is planar (or substantially planar).

[0070] In some embodiments, the lower surface of the first portion 231 is parallel (or substantially parallel) to the upper surface of the substrate 20.

[0071] In some embodiments, the lower surface of the first portion 231 is coplanar (or substantially coplanar) with the lower surface of the second portion 232.

[0072] In some embodiments, the surface of the first portion 231 includes a curved surface. For example, the surface of the first portion 231 can be a circular arc surface with the apex of the arc located in the middle, as shown in FIGS. 1A and 1B. Figure 5 and Figure 6 In some embodiments, the surface of the first portion 231 includes a curved surface. For example, the surface of the first portion 231 can be a circular arc surface with the apex of the arc located in the middle, as shown in FIGS. 1A and 1B.

[0073] In some embodiments, the surface of the first portion includes a slope. For example, the surface of the first portion may include two connected slopes, which are arranged to slope downwards from the middle of the opening to both sides, so that the thickness of the first portion gradually decreases from the middle of the opening to both sides.

[0074] In some embodiments, the ratio of the maximum thickness to the minimum thickness of the first portion 231 is 5:1 to 1.5:1. The maximum thickness of the first portion 231 is generally located in the middle of the opening 22 (or approximately in the middle of the opening 22), while the minimum thickness of the first portion 231 is located at or near the two sidewalls of the opening 22 (due to certain process deviations). In this state, the ratio between the thickness located in the middle of the first portion 231 (maximum thickness) and the thickness located on both sides of the first portion 231 (minimum thickness) is 5:1 to 1.5:1. For example, the ratio of the maximum thickness to the minimum thickness of the first portion 231 can be 5:1, 4.5:1, 4:1, 3.5:1, 3:1, 2.5:1, 2:1, or 1.5:1, or any ratio between any two of the aforementioned thickness ratios.

[0075] In some embodiments, the maximum thickness of the first portion 231 is less than the thickness of the second portion 232. In other words, the thickness of the first portion 231 at any point along the direction of the upper surface of the substrate 20 is less than the thickness of the second portion 232.

[0076] In some embodiments, the first portion 231 and the second portion 232 are connected to the bottom end of one side wall of the opening 22, and a portion of the end face of the connection end between the second portion 232 and the first portion 231 protrudes from that side wall of the opening 22. For example, with Figure 5 Taking a second part 232 located below the injection mask 21 on the left as an example, the right end of the second part 232 on the left is connected to the left end of the first part 231 and to the bottom end of the left sidewall of the opening 22. Since the thickness of the second part 232 is greater than the thickness of the first part 231, and the lower surface of the second part 232 is coplanar with the lower surface of the first part 231, at the connection point, the right end of the second part 232 will be higher than the left end of the first part 231, forming a stepped structure. This causes the protruding end face of the right end of the second part 232 to protrude from the left sidewall of the opening 22. In other words, the protruding end face of the right end of the second part 232 is coplanar with the surface of the left sidewall of the opening 22.

[0077] In some embodiments, the angle θ between the sidewall of any one side of the opening 22 and the lower surface of the first portion 231 (i.e. the upper surface of the substrate 20) is equal to or slightly greater than a right angle. For example, the angle θ can be 90°-91°, 90°-92°, 90°-93°, 90°-94°, 90°-95°, 90°-96°, 90°-97°, 90°-98°, 90°-99° or 90°-100°.

[0078] In some embodiments, the angle θ between the sidewall of any one side of the opening 22 and the lower surface of the first portion 231 (i.e. the upper surface of the substrate 20) can be 88°, 89°, 90°, 91°, 92°, 93°, 94°, 95°, 96°, 97°, 98°, 99° or 100°, or any angle between any two of the aforementioned angles.

[0079] In some embodiments, a protective layer 25 is further provided on the surface of the substrate 20, and the protective layer 25 is located between the substrate 20 and the etching stop layer 23.

[0080] In some embodiments, the lower surface of the protective layer 25 is in direct contact with the upper surface of the substrate 20.

[0081] In some embodiments, the upper surface of the protective layer 25 is in direct contact with the lower surface of the etching stop layer 23.

[0082] In some embodiments, the upper surface of the second portion 232 is in direct contact with the lower surface of the implantation mask 21.

[0083] In some embodiments, the material of the protective layer 25 is different from the material of the etching stop layer 23.

[0084] In some embodiments, the material of the implantation mask 21 is different from the material of the etching stop layer 23.

[0085] In some embodiments, the material of the protective layer 25 is the same as the material of the implantation mask 21.

[0086] In some embodiments, the material of the protective layer 25 is different from the material of the implantation mask 21.

[0087] In some embodiments, the implantation mask 21 is a hard mask.

[0088] In some embodiments, the material of the substrate 20 is silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate 20 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0089] In some embodiments, the material of the protective layer 25 is a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride, etc.

[0090] In some embodiments, the material of the etching stop layer 23 is a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride, etc.

[0091] In some embodiments, the material of the implantation mask 21 is a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride, etc.

[0092] In some embodiments, the material of the protective layer 25 is silicon oxide, the material of the etching stop layer 23 is silicon nitride, and the material of the implantation mask 21 is silicon oxide.

[0093] Reference Figure 6 The semiconductor structure of the embodiment of the present application is used to form an ion implantation region in a substrate. Figure 5 Based on the embodiment, the semiconductor structure further comprises an ion implantation region 24 in the substrate 20. The ion implantation region 24 is formed by ion implantation on the substrate 20 through the openings 22 between the adjacent implantation masks 21 and the first part 231 of the etching stop layer 23 exposed in the openings 22. The first part 231 is used to compensate the bottom profile 241 of the ion implantation region 24 in advance when the ion implantation is performed.

[0094] The embodiment of the present application gradually reduces the thickness of the first part 231 of the etching stop layer 23 exposed on the bottom of the opening 22 serving as the implantation window from the middle to the two sides. When the ion implantation is performed on the substrate 20 through the opening 22, the special profile of the first part 231 of the etching stop layer 23 on the bottom of the opening 22 is used to compensate the bottom profile 241 of the ion implantation region 24 in advance when the ion implantation region 24 is formed, so as to prevent the bottom profile of the ion implantation region from being in the form of a circular arc (see Figure 2 and Figure 4 ). Therefore, the inconsistency of the implantation depth in the substrate 20 can be significantly reduced, and the bottom profile 241 of the ion implantation region 24 is more flat (the distance c from the midpoint of the bottom profile 241 of the ion implantation region 24 to the back surface of the substrate 20 is consistent with the distance d from any point on the bottom profile 241 of the ion implantation region 24 to the back surface of the substrate 20, i.e. c≌d). Thus, the profile after ion implantation is improved, and the electrical problems such as leakage caused by the bottom profile of the ion implantation region in the form of a circular arc and the arc bottom being too close to the back surface of the substrate are effectively avoided.

[0095] The semiconductor structure manufacturing method of the embodiment of the present application will be described in detail below with reference to the specific embodiments and the accompanying drawings.

[0096] Reference Figure 7 The semiconductor structure manufacturing method of the embodiment of the present application can be used to manufacture the above-mentioned semiconductor structure of the embodiment of the present application.Figure 5 or Figure 6 a semiconductor structure as shown in FIG. 1, and comprises the following steps:

[0097] Step S11: providing a substrate.

[0098] Referring to FIG. 1, in some embodiments, a substrate 20 of silicon material (i.e. a silicon substrate) can be used, for example, a silicon wafer (crystal wafer) is used as the substrate 20 for further manufacturing a semiconductor structure of the embodiments of the present application on the substrate 20. However, the substrate 20 can not be limited to a silicon substrate. Figure 8 Referring to FIG. 1, in some embodiments, a substrate 20 of silicon material (i.e. a silicon substrate) can be used, for example, a silicon wafer (crystal wafer) is used as the substrate 20 for further manufacturing a semiconductor structure of the embodiments of the present application on the substrate 20. However, the substrate 20 can not be limited to a silicon substrate.

[0099] Step S12: sequentially forming an etching stop layer and a mask layer on the surface of the substrate.

[0100] Referring to FIG. 1, in some embodiments, a substrate 20 of silicon material (i.e. a silicon substrate) can be used, for example, a silicon wafer (crystal wafer) is used as the substrate 20 for further manufacturing a semiconductor structure of the embodiments of the present application on the substrate 20. However, the substrate 20 can not be limited to a silicon substrate. Figure 8 Referring to FIG. 1, in some embodiments, a substrate 20 of silicon material (i.e. a silicon substrate) can be used, for example, a silicon wafer (crystal wafer) is used as the substrate 20 for further manufacturing a semiconductor structure of the embodiments of the present application on the substrate 20. However, the substrate 20 can not be limited to a silicon substrate.

[0101] In the embodiments, the material of the protection layer 25 is silicon oxide, the material of the etching stop layer 23 is silicon nitride, and the material of the mask layer 211 is silicon oxide. That is, a first silicon oxide layer is formed on the upper surface of the substrate 20 as the protection layer 25, a silicon nitride layer is formed on the upper surface of the protection layer 25 as the etching stop layer 23, and a second silicon oxide layer is formed on the upper surface of the etching stop layer 23 as the mask layer 211. The protection layer 25 is used to protect the surface of the substrate 20 in subsequent etching to form the implantation mask 21 and ion implantation. Moreover, by using the different selectivity between the material of the silicon nitride layer and the material of the second silicon oxide layer, the silicon nitride layer can be used as an etching stop layer (i.e. etching stop layer) of the second silicon oxide layer when etching the second silicon oxide layer to form the implantation mask 21.

[0102] In some embodiments, a thermal oxidation process or a CVD process can be used to form the first silicon oxide layer on the upper surface of the substrate 20 as the protection layer 25.

[0103] In some embodiments, the thickness of the first silicon oxide layer is 20 nm to 100 nm. For example, the thickness of the first silicon oxide layer can be 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm, or any value between any two of the foregoing thickness values.

[0104] Then, a CVD process can be used to form a silicon nitride layer on the upper surface of the first silicon oxide layer (the protection layer 25) as the etching stop layer 23.

[0105] In some embodiments, the thickness of the silicon nitride layer is 50-200 nm. For example, the thickness of the silicon nitride layer can be 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, or 200 nm, or any value between any two of the aforementioned thickness values.

[0106] Next, a second silicon oxide layer is formed on the upper surface of the silicon nitride layer (etch stop layer 23) as a mask layer 211 by using a CVD process.

[0107] In some embodiments, the thickness of the second silicon oxide layer is 800-3500 nm. For example, the thickness of the second silicon oxide layer can be 800 nm, 1000 nm, 1300 nm, 1500 nm, 1800 nm, 2000 nm, 2200 nm, 2500 nm, 3000 nm, or 3500 nm, or any value between any two of the aforementioned thickness values.

[0108] Step S13: The mask layer is patterned to form a plurality of implantation masks on the surface of the etch stop layer, adjacent two implantation masks have an opening therebetween, and the thickness of the etch stop layer exposed from the bottom of the opening gradually decreases from the middle to both sides.

[0109] Reference Figure 9 and Figure 10 In some embodiments, the mask layer 211 is patterned by performing an etching process to form a plurality of implantation masks 21 of silicon oxide material on the upper surface of the etch stop layer 23.

[0110] In some embodiments, before the mask layer 211 is patterned by performing an etching process, a photoresist layer is first formed on the upper surface of the mask layer 211. Then, a plurality of photoresist patterns 26 are formed on the upper surface of the mask layer 211 by using a photolithography process as a photoresist mask for patterning the mask layer 211, as shown in FIG. 6A. Figure 9 Next, the mask layer 211 below is etched and patterned by using an etching process and taking the photoresist patterns 26 as a mask, thereby forming a plurality of implantation masks 21 of silicon oxide material on the upper surface of the etch stop layer 23, and then the remaining photoresist patterns 26 are removed, resulting in a structure as shown in FIG. 6B. Figure 10

[0111] Reference Figure 10 ​After the mask layer 211 is etched to form the implantation mask 21, the opening 22 as an implantation window is formed between two adjacent implantation masks 21. Moreover, the silicon nitride layer functions as an etching stop layer when etching the second silicon oxide layer, so that the surface of the silicon nitride layer (the etching stop layer 23) is exposed from the bottom of the opening 22.

[0112] The first part of the silicon nitride layer exposed from the bottom of the opening 22 becomes the first part 231 of the etching stop layer 23, and the second part of the silicon nitride layer under the implantation mask 21 becomes the second part 232 of the etching stop layer 23. The second part 232 has a thickness consistent with the original thickness of the silicon nitride layer because it is shielded by the implantation mask 21, and the surface of the first part 231 is exposed when etching to the bottom of the second silicon oxide layer, and the thickness of the first part 231 gradually decreases (thins) from the middle to both sides of the opening 22 under the effect of over-etching, as shown in Figure 10 .

[0113] In some embodiments, the mask layer 211 is etched to form the implantation mask 21 by using a plasma dry etching process.

[0114] In some embodiments, the reaction gas used in the etching process includes CHF3.

[0115] In some embodiments, the thickness of the first part 231 of the etching stop layer 23 exposed by adjusting the process menu of the etching process and over-etching the second silicon oxide layer gradually decreases from the middle to both sides.

[0116] In some embodiments, adjusting the process menu of the etching process includes adjusting at least one of the pressure, the flow rate of the reaction gas (e.g., CHF3), and the bias power, at the latest when the etching reaches the surface of the etching stop layer 23. For example, when the remaining thickness of the second silicon oxide layer is 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, 10 nm or less, 5 nm or less, or 0 nm, the thickness of the first part 231 of the etching stop layer 23 exposed by adjusting at least one of the pressure, the flow rate of the reaction gas, and the bias power gradually decreases from the middle to both sides, forming, for example, the first part 231 with a curved surface (refer to Figure 10 ) or the first part with a beveled surface.

[0117] In some embodiments, the method of adjusting at least one of the pressure, the flow rate of the reactive gas, and the bias power includes at least one of reducing the pressure, reducing the flow rate of the reactive gas, and increasing the bias power. For example, the adjustment of reducing the pressure, reducing the flow rate of the reactive gas, or increasing the bias power can be employed. Alternatively, the adjustment of reducing the pressure and reducing the flow rate of the reactive gas can be employed. Alternatively, the adjustment of reducing the pressure and increasing the bias power can be employed. Alternatively, the adjustment of reducing the flow rate of the reactive gas and increasing the bias power can be employed. Alternatively, the adjustment of reducing the pressure, reducing the flow rate of the reactive gas, and increasing the bias power can be employed. When the adjustment of reducing the pressure, reducing the flow rate of the reactive gas, and increasing the bias power is simultaneously employed, the adjustment effect of making the thickness of the first portion 231 of the etching stop layer 23 gradually decrease from the middle to the both sides is most obvious, and the difference between the maximum thickness and the minimum thickness of the first portion 231 can be maximized.

[0118] It is worth noting that, generally in the process of plasma dry etching the mask layer and forming the opening, not all the physical bombardment effects of the particles generated in the etching process are vertical, some of the particles (such as Ar, He, etc.) participating in the bombardment will rebound along the sidewall downward when hitting the sidewall of the opening, resulting in a greater bombardment density on both sides of the bottom of the opening than in the middle. With the increase of the depth of the opening, this bombardment effect is more and more obvious.

[0119] When the pressure is reduced on the basis of the conventional pressure, the generated bottom protection byproducts can be removed as much as possible, so as to deliberately cause insufficient protection of the bottom, so that the above-mentioned bombardment effect is more obvious, and the etching rate on both sides of the bottom of the opening is greater than that in the middle of the bottom of the opening, which is beneficial to form the morphology of the first portion of the etching stop layer with the thickness gradually decreasing from the middle to the both sides.

[0120] When the flow rate of the reactive gas is reduced on the basis of the conventional flow rate of the reactive gas, the generated bottom protection byproducts can be reduced, and the bottom protection can also be insufficient, so that the above-mentioned bombardment effect is more obvious, and the etching rate on both sides of the bottom of the opening is greater than that in the middle of the bottom of the opening, which is beneficial to form the morphology of the first portion of the etching stop layer with the thickness gradually decreasing from the middle to the both sides. Reducing the flow rate of the reactive gas means reducing the concentration of the reactive gas in the whole etching process gas (the process gas includes the reactive gas (such as CHF3, etc.) and the dilution and dissociation gas (such as Ar, He, etc.) participating in the bombardment.

[0121] When the bias power is increased on the basis of the conventional bias power, the physical bombardment effect can be directly increased, which also means that the particles rebounding downward on the opening sidewall further promote the bombardment intensity on both sides of the opening bottom, so that the bombardment effect is more obvious, and the etching rate on both sides of the opening bottom is greater than that on the middle of the opening bottom, which is beneficial to form the morphology of the first part of the etching stop layer with gradually decreasing thickness from the middle to both sides.

[0122] By using the above characteristics, when the etching is close to the surface of the etching stop layer 23 (i.e., the maximum remaining thickness of the mask layer 211 is 50 nm to 0 nm), the etching behavior of the opening 22 bottom can be adjusted by reducing the pressure, reducing the flow of the reaction gas, and / or increasing the bias power, so as to adjust the morphology of the etching stop layer 23 exposed on the opening 22 bottom, and achieve the purpose of gradually decreasing the thickness of the first part 231 of the etching stop layer 23 exposed from the middle to both sides.

[0123] In some embodiments, when the adjustment mode of reducing the pressure is used, the pressure can be reduced from the conventional 140 mTorr to 120 mTorr to 90 mTorr to 70 mTorr. For example, the pressure can be reduced from the conventional 140 mTorr to 90 mTorr; or the pressure can be reduced from the conventional 140 mTorr to 80 mTorr; or the pressure can be reduced from the conventional 140 mTorr to 70 mTorr; or the pressure can be reduced from the conventional 130 mTorr to 90 mTorr; or the pressure can be reduced from the conventional 130 mTorr to 80 mTorr; or the pressure can be reduced from the conventional 130 mTorr to 70 mTorr; or the pressure can be reduced from the conventional 120 mTorr to 90 mTorr; or the pressure can be reduced from the conventional 120 mTorr to 80 mTorr; or the pressure can be reduced from the conventional 120 mTorr to 70 mTorr. But it can not be limited to this.

[0124] In some embodiments, when the adjustment mode of reducing the flow rate of the reaction gas is adopted, the flow rate of the reaction gas can be reduced from the conventional 130sccm to 90sccm to 70sccm. For example, the flow rate of the reaction gas can be reduced from the conventional 130sccm to 90sccm; or the flow rate of the reaction gas can be reduced from the conventional 130sccm to 80sccm; or the flow rate of the reaction gas can be reduced from the conventional 130sccm to 70sccm; or the flow rate of the reaction gas can be reduced from the conventional 120sccm to 90sccm; or the flow rate of the reaction gas can be reduced from the conventional 120sccm to 80sccm; or the flow rate of the reaction gas can be reduced from the conventional 120sccm to 70sccm; or the flow rate of the reaction gas can be reduced from the conventional 110sccm to 90sccm; or the flow rate of the reaction gas can be reduced from the conventional 110sccm to 80sccm; or the flow rate of the reaction gas can be reduced from the conventional 110sccm to 70sccm. But it can not be limited to this.

[0125] In some embodiments, when the adjustment mode of increasing the bias power is adopted, the bias power can be increased from the conventional 190W to 390W to 410W. For example, the bias power can be increased from the conventional 190W to 390W; or the bias power can be increased from the conventional 190W to 400W; or the bias power can be increased from the conventional 190W to 410W; or the bias power can be increased from the conventional 200W to 390W; or the bias power can be increased from the conventional 200W to 400W; or the bias power can be increased from the conventional 200W to 410W; or the bias power can be increased from the conventional 210W to 390W; or the bias power can be increased from the conventional 210W to 400W; or the bias power can be increased from the conventional 210W to 410W. But it can not be limited to this.

[0126] In some embodiments, when the above adjustment mode is adopted and the etching process is ended, the thickness of the first part 231 of the exposed etching stop layer 23 gradually decreases from the middle to both sides, and the maximum thickness and the minimum thickness of the first part 231 are both less than the original deposition thickness of the etching stop layer 23. And the minimum thickness of the first part 231 is greater than zero. That is, the protective layer 25 below the etching stop layer 23 is still completely covered by the etching stop layer 23 (the protective layer 25 is not exposed in the opening 22).

[0127] In some embodiments, the semiconductor structure manufacturing method provided by the embodiments of the present application can further include the following step S14.

[0128] Step S14: ion implantation is performed on the substrate through the opening to form an ion implantation region in the substrate.

[0129] Reference is made to Fig. 1, which shows a partial structure of an etch stop layer exposed on the bottom of an injection window (opening) obtained by using the method for manufacturing a semiconductor structure provided in the above embodiment of the present application and adjusting the etching process by simultaneously reducing the pressure, reducing the flow rate of the reaction gas and increasing the bias power. Figure 11 After the injection mask 21 is formed, the ion implantation is performed on the substrate 20 by taking the injection mask 21 as the barrier layer during the ion implantation and taking the first portion 231 of the etch stop layer 23 exposed through the opening 22 formed between two adjacent injection masks 21 as the injection window, so as to form an ion implantation region 24 in the substrate 20. Moreover, the first portion 231 obtained in the above step has a thickness gradually decreasing from the middle to the two sides, which can compensate the bottom profile 241 of the ion implantation region 24 formed during the ion implantation in advance, so as to form the ion implantation region 24 with a more even bottom profile 241 in the substrate 20, and make the distance between each point on the bottom profile 241 of the ion implantation region 24 and the lower surface of the substrate 20 (the distance c or d in Fig. 1) tend to be consistent, thereby improving the topography after the ion implantation and improving the reliability of the device. Figure 6

[0130] In some embodiments, the ion implantation is performed on the substrate 20 by using a conventional ion implantation process, which is not specifically limited in the present application.

[0131] Reference is made to Fig. 1, which shows a partial structure of an etch stop layer exposed on the bottom of an injection window (opening) obtained by using the method for manufacturing a semiconductor structure provided in the above embodiment of the present application and adjusting the etching process by simultaneously reducing the pressure, reducing the flow rate of the reaction gas and increasing the bias power. Figure 12 Reference is made to Fig. 1, which shows a partial structure of an etch stop layer exposed on the bottom of an injection window (opening) obtained by using the method for manufacturing a semiconductor structure provided in the above embodiment of the present application and adjusting the etching process by simultaneously reducing the pressure, reducing the flow rate of the reaction gas and increasing the bias power. Figure 12 In Fig. 1, the light-colored part from bottom to top is a substrate (the material is silicon), a first silicon oxide layer (a protective layer), a silicon nitride layer (an etch stop layer) and a second silicon oxide layer (an injection mask). The thickness of the silicon nitride layer (the second portion) located below the second silicon oxide layer is 107 nm, and the thickness of the silicon nitride layer (the first portion) located above the first silicon oxide layer is 40.3 nm on the left side of the figure (close to the maximum thickness) and 24.2 nm on the right side of the figure (close to the minimum thickness). Figure 12 In Fig. 1, the light-colored part from bottom to top is a substrate (the material is silicon), a first silicon oxide layer (a protective layer), a silicon nitride layer (an etch stop layer) and a second silicon oxide layer (an injection mask). The thickness of the silicon nitride layer (the second portion) located below the second silicon oxide layer is 107 nm, and the thickness of the silicon nitride layer (the first portion) located above the first silicon oxide layer is 40.3 nm on the left side of the figure (close to the maximum thickness) and 24.2 nm on the right side of the figure (close to the minimum thickness). Figure 12 In Fig. 1, the light-colored part from bottom to top is a substrate (the material is silicon), a first silicon oxide layer (a protective layer), a silicon nitride layer (an etch stop layer) and a second silicon oxide layer (an injection mask). The thickness of the silicon nitride layer (the second portion) located below the second silicon oxide layer is 107 nm, and the thickness of the silicon nitride layer (the first portion) located above the first silicon oxide layer is 40.3 nm on the left side of the figure (close to the maximum thickness) and 24.2 nm on the right side of the figure (close to the minimum thickness).

[0132] ​In summary, by setting the thickness of the etching stop layer 23 (the first part 231) exposed on the bottom of the opening 22 as the implantation window to gradually decrease from the middle to both sides, the special topography of the etching stop layer 23 on the bottom of the opening 22 can be used to compensate the bottom profile 241 of the ion implantation region 24 formed in advance when the substrate 20 is ion implanted through the opening 22. The inconsistency of the implantation depth in the substrate 20 can be significantly reduced, the bottom profile 241 of the ion implantation region 24 formed is more flat, and the morphology after ion implantation is improved. The electrical problems such as leakage caused by the arc-shaped bottom profile of the ion implantation region, which makes the arc bottom too close to the back surface of the substrate, are effectively avoided, and the reliability of the device is improved.

[0133] The above is only the preferred embodiment of the present application, and the embodiment is not used to limit the protection scope of the present application. Therefore, any equivalent changes made according to the content of the specification and drawings of the present application should also be included in the protection scope of the present application.

Claims

1. A method of fabricating a semiconductor structure, comprising: The method comprises: providing a substrate; forming an etching stop layer and a mask layer on the surface of the substrate in sequence; performing an etching process to pattern the mask layer and form a plurality of implantation masks on the surface of the etching stop layer, two adjacent implantation masks having an opening therebetween, the etching stop layer comprising a first part exposed from the bottom of the opening and a second part located below the implantation masks; wherein the thickness of the first part is gradually reduced from the middle to the two sides by adjusting the process menu of the etching process and using over-etching, so that the special topography of the first part is used to compensate the bottom profile of the ion implantation region in advance when ion implantation is performed on the substrate through the opening, to reduce the inconsistency of implantation depth in the substrate and make the bottom profile of the ion implantation region flat; the adjustment of the process menu of the etching process comprises at least one of reducing the pressure, reducing the flow rate of the reaction gas, and increasing the bias power, at the latest when the etching process reaches the surface of the etching stop layer; wherein the pressure is reduced on the basis of the normal pressure of 140mTorr-120mTorr, so that the generated bottom protection by-products are removed as much as possible, to deliberately cause insufficient protection of the bottom, so that the etching rate on the two sides of the opening bottom is greater than that on the middle of the opening bottom; the flow rate of the reaction gas is reduced on the basis of the normal flow rate of 130sccm-110sccm of the reaction gas, so that the generated bottom protection by-products are reduced, to make the bottom protection insufficient, so that the etching rate on the two sides of the opening bottom is greater than that on the middle of the opening bottom; the bias power is increased on the basis of the normal bias power of 190W-210W, to directly increase the physical bombardment effect, to further promote the bombardment intensity of the particles rebounding downward on the opening sidewall on the two sides of the opening bottom, so that the etching rate on the two sides of the opening bottom is greater than that on the middle of the opening bottom.

2. The method of fabricating a semiconductor structure of claim 1, wherein, The pressure is reduced to 90mTorr-70mTorr from 140mTorr-120mTorr; and / or, the flow rate of the reaction gas is reduced to 90sccm-70sccm from 130sccm-110sccm; and / or, the bias power is increased to 390W-410W from 190W-210W.

3. The method of claim 1, wherein The method further comprises: performing ion implantation on the substrate through the opening to form an ion implantation region in the substrate.

4. The method of claim 1, wherein Before forming the etching stop layer, the method further comprises forming a protection layer on the surface of the substrate first, and then forming the etching stop layer on the surface of the protection layer, the material of the protection layer and / or the material of the mask layer comprising silicon oxide, and / or the material of the etching stop layer comprising silicon nitride; and / or the reaction gas used in the etching process comprising CHF3.

5. A semiconductor structure, characterized by The method comprises: a substrate; an etching stop layer provided on the surface of the substrate; A plurality of implantation masks are arranged on the surface of the etching stop layer, and two adjacent implantation masks have an opening therebetween; The etching stop layer comprises a first part exposed from the bottom of the opening and a second part located below the implantation mask, and the thickness of the first part gradually decreases from the middle to both sides; The semiconductor structure is manufactured by the semiconductor structure manufacturing method of any one of claims 1-4.

6. The semiconductor structure of claim 5, wherein, Further comprising: An ion implantation region is arranged in the substrate, wherein the ion implantation region is formed by ion implantation on the substrate through the opening, and the first part is used to compensate the bottom profile of the ion implantation region in advance when ion implantation is performed.

7. The semiconductor structure of claim 5, wherein, The surface of the first part comprises a curved surface or an inclined surface; and / or, the ratio of the maximum thickness to the minimum thickness of the first part is 5:1-1.5:1; and / or, the maximum thickness of the first part is less than the thickness of the second part; and / or, the first part is connected with the second part at the bottom end of the sidewall of the opening, and part of the end surface of the connection end of the second part and the first part is exposed from the sidewall of the opening.

8. The semiconductor structure of claim 5, wherein, A protective layer is further arranged on the surface of the substrate, and the protective layer is located between the substrate and the etching stop layer, the material of the protective layer is different from the material of the etching stop layer, and / or the material of the protective layer is the same as or different from the material of the implantation mask; And / or, the implantation mask is a hard mask.

Images