Semiconductor device with ultrathin bonding layer embedded heat dissipation structure and preparation method thereof

Abstract

The invention discloses a semiconductor device with an ultrathin bonding layer embedded heat dissipation structure and a preparation method of the semiconductor device. The back side of a substrate layer of the semiconductor device comprises a flow channel region with a plurality of micro flow channels arranged in parallel and a non-flow channel region surrounding the outer side of the flow channel region; a manifold structure is arranged on one side, away from the semiconductor device functional layer, of the substrate layer; a first bonding layer is arranged between the manifold structure and the substrate layer; the first bonding layer is made of any one of silicon, aluminum oxide, aluminum nitride, boron nitride, silicon carbide, aluminum, copper, silver, gold or titanium; the thickness of the first bonding layer is 5 nm to 50 nm; and the manifold structure is made of a semiconductor material. According to the semiconductor device provided by the invention, the manifold structure and the bonding layer are both made of semiconductor materials, so that the thermal expansion coefficient matching degree with the substrate layer is improved, the interface thermal resistance is remarkably reduced, the high heat-conducting property of the semiconductor materials is better played, and the heat dissipation efficiency of the whole structure is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device heat dissipation structure technology, specifically relating to a semiconductor device with an ultrathin bonding layer embedded heat dissipation structure and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), as a wide-bandgap semiconductor material, is ideal for high-voltage, high-power applications due to its excellent electron mobility and breakdown voltage performance. However, its relatively low thermal conductivity (approximately 130 W / m·K) poses a significant challenge. This thermal characteristic makes it difficult to efficiently transfer heat generated inside the device to the external cooling system, resulting in a severe "self-heating effect." This effect significantly degrades key performance indicators of the device, including saturation current, transconductance, output power, and power-added efficiency (PAE), and in severe cases, can even lead to device failure.

[0003] As gallium nitride microwave power devices evolve towards miniaturization, high power, and high frequency, thermal management has become a core bottleneck restricting their performance improvement—the self-heating effect caused by internal heat accumulation leads to saturation current decay and reduced output power. Current heat dissipation solutions are divided into passive and active modes: passive heat dissipation relies on natural thermodynamic processes (such as heat conduction / convection) and optimizes the thermal path through high thermal conductivity materials or three-dimensional heat sink structures, but is limited by thermodynamic equilibrium and has insufficient heat flux carrying capacity; active heat dissipation, on the other hand, uses external energy to drive forced heat exchange, breaking through the physical limits of passive cooling. For example, microchannel cold plate technology uses a manifold structure to guide the single-phase flow of coolant, which can extract a large amount of heat flux.

[0004] Currently, the manifold structure of microfluidic devices is generally manufactured in separate metal blocks such as copper or copper-tungsten alloys, and connected by a relatively thick intermediate layer. This results in an excessively thick bonding layer, forming a high thermal resistance bottleneck and significantly weakening the intrinsic thermal conductivity of the material. The high-temperature bonding process damages the GaN gate metal structure, leading to a deterioration in device reliability. The thermal expansion coefficient of the metal manifold is more than 3.8 times that of the semiconductor substrate, which easily generates shear stress at high temperature rises, causing channel misalignment and blockage, and reducing the effective cross-sectional area. The phonon spectrum mismatch at the metal-semiconductor interface further reduces heat transfer efficiency, and the difference in thermal expansion coefficients easily leads to thermal stress separation.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a semiconductor device with an ultrathin bonding layer embedded heat dissipation structure and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: The present invention provides a semiconductor device with an ultrathin bonding layer embedded heat dissipation structure, including a substrate layer and a semiconductor device functional layer located on one side of the substrate layer, wherein the other side of the substrate layer includes a channel region and a non-channel region surrounding the channel region; the channel region has a plurality of parallel microchannels; A manifold structure is provided on the side of the substrate layer away from the functional layer of the semiconductor device. The manifold structure is used to provide an inlet and an outlet for the coolant, so that the coolant can flow through the microchannel to achieve heat dissipation. A first bonding layer is disposed between the manifold structure and the substrate layer; The material of the first bonding layer is any one of silicon, aluminum oxide, aluminum nitride, boron nitride, silicon carbide, aluminum, copper, silver, gold or titanium; and the thickness of the first bonding layer is 5nm to 50nm. The manifold structure is made of semiconductor material.

[0007] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The manifold structure of the semiconductor device of this invention uses semiconductor materials. Compared with traditional metal manifold structures (copper or copper-tungsten alloy), the thermal expansion coefficient of the semiconductor material naturally matches that of the semiconductor device substrate, avoiding thermal stress separation and thus improving the service life of the semiconductor device. Furthermore, in the semiconductor device provided by this invention, the connection between the substrate (microchannel side) and the manifold structure is bonded using a nano-silicon interlayer (a silicon layer with a thickness of less than 10 nm), significantly reducing interfacial thermal resistance and better utilizing the high thermal conductivity of the semiconductor material, thereby improving the overall heat dissipation efficiency of the structure.

[0008] 2. The method for fabricating a semiconductor device with an ultra-thin bonding layer embedded heat dissipation structure provided by this invention employs low-temperature bonding to prepare a silicon nanolayer as the first bonding layer. On the one hand, the low-temperature bonding process avoids damage to the GaN gate metal structure during high-temperature bonding, which would lead to a deterioration in device reliability. On the other hand, the nanometer-thickness of the first bonding layer is closer to the thermal expansion coefficient of the semiconductor device's substrate layer, avoiding the shear stress generated during large temperature rises caused by the use of thicker bonding layers in the prior art, which leads to channel misalignment and blockage, reducing the effective cross-sectional area, and the thermal stress separation problem easily caused by differences in thermal expansion coefficients.

[0009] 3. This invention manufactures the manifold structure (including the inlet layer, the flow layer, and the support layer) using all-semiconductor materials and combines it with room temperature low-temperature bonding technology, using a silicon interlayer of less than 10 nm. This makes the manifold structure-microchannel an integral semiconductor structure, which significantly reduces the interfacial thermal resistance, effectively utilizes the intrinsic high thermal conductivity of the material, avoids thermal stress peeling, and improves heat dissipation efficiency.

[0010] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0011] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device with an ultrathin bonding layer embedded heat dissipation structure provided in an embodiment of the present invention; Figure 2 This is a three-dimensional perspective schematic diagram of a semiconductor device with an ultra-thin bonding layer embedded heat dissipation structure provided in an embodiment of the present invention; Figure 3 This is a cross-sectional schematic diagram of the semiconductor device before the fabrication of the heat dissipation structure, as provided in an embodiment of the present invention. Figure 4 This is a simplified schematic diagram of the semiconductor device before the fabrication of the heat dissipation structure provided in the embodiments of the present invention; Figure 5 This is a cross-sectional schematic diagram of a semiconductor device with a temporary substrate protective layer in step two of embodiment three of the present invention; Figure 6 This is a cross-sectional schematic diagram of the semiconductor device with microchannels in step two of embodiment three of the present invention; Figure 7 These are the top view (A) and side view (B) of the water inlet layer in step three of the present invention. Figure 8 These are the top view (A) and side view (B) of the water layer in step three of the present invention. Figure 9 This is a cross-sectional schematic diagram of the manifold structure in step three of embodiment three of the present invention; Figure 10 This is a top view schematic diagram of the interface position between the manifold structure and the semiconductor device with microchannels in step three of embodiment three of the present invention.

[0012] Explanation of reference numerals in the attached figures: 1-Substrate layer; 11-Microchannel; 2-Semiconductor device functional layer; 21-Temporary substrate protective layer; 3-Water inlet layer; 31-External water inlet; 32-Internal water inlet; 33-Internal water outlet; 34-External water outlet; 4-Flow layer; 41-Water inlet buffer tank; 42-Water outlet buffer tank; 5-Support layer; 6-First bonding layer; 7-Second bonding layer; 8-Third bonding layer. Detailed Implementation

[0013] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail, with reference to the accompanying drawings and specific embodiments, a semiconductor device with an ultrathin bonding layer embedded heat dissipation structure and its preparation method according to the present invention.

[0014] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0015] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. It should be understood that the terms "thickness," "upper," "lower," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0016] Example 1 This embodiment provides a semiconductor device with an ultrathin bonding layer embedded heat dissipation structure, such as Figure 1 and Figure 2 As shown, the semiconductor device includes a substrate layer 1 and a semiconductor device functional layer 2 located on one side of the substrate layer 1. The other side of the substrate layer 1 includes a flow channel region and a non-flow channel region surrounding the flow channel region. The flow channel region has multiple parallel microchannels 11. A manifold structure is provided on the side of the substrate layer 1 away from the semiconductor device functional layer 2. The manifold structure provides an inlet and outlet for the coolant, allowing the coolant to flow through the microchannels 11 to achieve heat dissipation. A first bonding layer 6 is provided between the manifold structure and the substrate layer 1. The material of the first bonding layer 6 is any one of silicon (Si), aluminum oxide (Al2O3), aluminum nitride (AlN), boron nitride (BN), silicon carbide (SiC), aluminum (Al), copper (Cu), silver (Ag), gold (Au), or titanium (Ti). The thickness of the first bonding layer 6 is 5nm to 50nm. The material of the manifold structure is a semiconductor material.

[0017] In this embodiment, a manifold structure is fabricated using semiconductor materials. Compared to traditional metal manifolds (copper or copper-tungsten alloy), the thermal expansion coefficient of the semiconductor material naturally matches that of the semiconductor device substrate, avoiding thermal stress separation and improving the lifespan of the semiconductor device. Furthermore, in the semiconductor device provided by this invention, the connection between the substrate layer 1 (microchannel side) and the manifold structure is bonded using a nano-silicon interlayer (thickness less than 10 nm), significantly reducing interfacial thermal resistance and effectively utilizing the high thermal conductivity of the semiconductor material, thereby improving the overall heat dissipation efficiency of the structure.

[0018] For example, the surface roughness of the microchannel 11 is less than 1 nm.

[0019] For example, the ratio of the depth of the microchannel 11 to the thickness of the substrate layer 1 is 1:(1.5~2). That is, the greater the depth of the microchannel 11, the closer it is to the heat source, allowing the coolant to carry away more heat as it passes through, thus improving heat dissipation efficiency. Simultaneously, the substrate layer 1 must retain sufficient thickness to withstand the pressure of the coolant and the mechanical stress of the chip. Thus, within the range of a 1:(1.5~2) ratio of the depth of the microchannel 11 to the thickness of the substrate layer 1, a balance between heat dissipation and support can be achieved.

[0020] For example, the material of substrate 1 includes, but is not limited to, Si, SiC, GaN, diamond or sapphire substrates.

[0021] In one embodiment of the present invention, the manifold structure includes a support layer 5, a third bonding layer 8, a water flow layer 4, a second bonding layer 7, and a water inlet layer 3 stacked sequentially; a first bonding layer 6 is located between the water inlet layer 3 and the substrate layer 1. The water inlet layer 3 includes a first semiconductor substrate, on which an external water inlet 31, an internal water inlet 32, an external water outlet 34, and an internal water outlet 33 are disposed. The external water inlet 31 is used to receive coolant, and the external water outlet 34 is used to discharge coolant; the internal water inlet 32 ​​is connected to the first end of each microchannel 11, and the internal water outlet 33 is connected to the second end of each microchannel 11. The water flow layer 4 includes a second semiconductor substrate, on which an inlet buffer tank 41 and an outlet buffer tank 42 are disposed; the inlet buffer tank 41 is simultaneously connected to the external water inlet 31 and the internal water inlet 32, and the outlet buffer tank 42 is simultaneously connected to the external water outlet 34 and the internal water outlet 33. The support layer 5 includes a third semiconductor substrate, which supports the manifold structure. Thus, as... Figure 1 The circulation diagram shown shows that coolant (e.g., water) flows in from the outer inlet 31, diffuses and buffers in the inlet buffer tank 41, and then enters the first end of each microchannel 11 through the inner inlet 32. After heat exchange in the microchannel 11, the coolant flows out from the second end of each microchannel 11, passes through the inner outlet 33 to the outlet buffer tank 42 for diffusion and buffering, and is then discharged from the outer outlet 34.

[0022] In one example, the outer inlet 31 and the outer outlet 34 are cylindrical holes; the inner inlet 32 ​​and the inner outlet 33 are rectangular holes. The inner inlet 32 ​​is connected to the first end of all microchannels 11, so that water in the inlet buffer tank 41 can enter each microchannel 11; the inner outlet 33 is connected to the second end of all microchannels 11, so that the water after heat exchange in all microchannels 11 can be discharged into the outlet buffer tank 42 in a timely manner.

[0023] In one example, the orthographic projections of the outer inlet 31 and the inner inlet 32 ​​onto the support layer 5 are both within the orthographic projection range of the inlet buffer tank 41 onto the support layer 5, and the size of the inlet buffer tank 41 gradually increases along the extension direction from the orthographic projection of the outer inlet 31 to the orthographic projection of the inner inlet 32. Similarly, the orthographic projections of the outer inlet 34 and the inner outlet 33 onto the support layer 5 are both within the orthographic projection range of the outlet buffer tank 42 onto the support layer 5, and the size of the outlet buffer tank 42 gradually increases along the extension direction from the orthographic projection of the outer inlet 34 to the orthographic projection of the inner outlet 33.

[0024] In one example, both the inlet buffer tank 41 and the outlet buffer tank 42 are disposed through the second semiconductor substrate. In this way, while ensuring that the projected area of ​​the inlet buffer tank 41 and the outlet buffer tank 42 on the support layer 5 remains unchanged, the space of the inlet buffer tank 41 and the outlet buffer tank 42 is increased, which can ensure that there is sufficient diffusion space when water flows through (in or out) and reduce the impact of water flow pressure; at the same time, penetrating the second semiconductor substrate can also simplify the fabrication process of the water flow layer 4.

[0025] In one example, both the second bonding layer 7 and the third bonding layer 8 are selected from any one of silicon, aluminum oxide, aluminum nitride, boron nitride, silicon carbide, aluminum, copper, silver, gold, or titanium, and have a thickness of 5 nm to 50 nm. This allows for compatibility with the manifold structure of semiconductor materials, achieving high thermal conductivity and improving the adaptability of the coefficient of thermal expansion.

[0026] For example, the materials of the first semiconductor substrate, the second semiconductor substrate and the third semiconductor substrate are single crystal silicon or SiC.

[0027] In one example, the surface roughness of the external water inlet 31, the internal water inlet 32, the external water inlet 34, the internal water outlet 33, the water inlet buffer tank 41, and the water outlet buffer tank 42 is all less than 1 nm.

[0028] Example 2 This embodiment provides a method for fabricating a semiconductor device with an embedded heat dissipation structure having an ultrathin bonding layer, the method comprising: S1. Prepare substrate layer 1 and semiconductor device functional layer 2, and form temporary substrate protection layer 21 on the side of semiconductor device functional layer 2 away from substrate layer 1.

[0029] S2 forms multiple parallel microchannels 11 on a preset microchannel region on the side of the substrate away from the semiconductor device functional layer 2, thereby obtaining a semiconductor device with microchannels; wherein, the preset microchannel region is surrounded by a preset non-channel region.

[0030] S3. Obtain a first semiconductor substrate and, using inductively coupled plasma etching (ICP-ED), form an external water inlet 31, an internal water inlet 32, an external water outlet 34, and an internal water outlet 33 penetrating the first semiconductor substrate at predetermined positions to obtain a water inlet layer 3. Obtain a second semiconductor substrate and, using ICP-ED, form a water inlet buffer trench 41 and a water outlet buffer trench 42 penetrating the second semiconductor substrate at predetermined positions to obtain a water flow layer 4. Obtain a third semiconductor substrate as a support layer 5.

[0031] In one example, the materials of the first semiconductor substrate, the second semiconductor substrate, and the third semiconductor substrate are monocrystalline silicon or SiC.

[0032] In one example, the third semiconductor substrate also includes a surface polishing process to a roughness of less than 1 nm.

[0033] S4. A second bonding layer 7 and a third bonding layer 8 are formed by magnetron sputtering. The second bonding layer 7 is located between the water flow layer 4 and the water inlet layer 3 to connect the water flow layer 4 and the water inlet layer 3. The third bonding layer 8 is located between the support layer 5 and the water flow layer 4 to connect the water flow layer 4 and the support layer 5, thus obtaining a manifold structure. The water inlet buffer tank 41 is simultaneously connected to the outer water inlet 31 and the inner water inlet 32, and the water outlet buffer tank 42 is simultaneously connected to the outer water outlet 34 and the inner water outlet 33. In one example, the formation of the second bonding layer 7 and the third bonding layer 8 by magnetron sputtering includes: The bonding surfaces were activated using an argon atomic beam. A sputtering layer is formed on each surface to be bonded using magnetron sputtering, and the sputtering layer is activated using an argon atom beam. The water inlet layer 3, the water flow layer 4, and the support layer 5 are stacked and aligned with each surface to be bonded. At 20-30°C, a pressure of 0.1-20 MPa is applied, and the bonding time is 200-500 s to form the second bonding layer 7 and the third bonding layer 8.

[0034] For example, the material of the sputtered layer is selected from any one of silicon, aluminum oxide, aluminum nitride, boron nitride, silicon carbide, aluminum, copper, silver, gold or titanium.

[0035] S5. A first bonding layer 6 is formed by magnetron sputtering. The first bonding layer 6 is located between the water inlet layer 3 and the substrate layer 1 of the manifold structure, and is used to connect the manifold structure to a semiconductor device with microchannels. The inner water inlet 32 ​​is connected to the first end of each microchannel 11, and the inner water outlet 33 is connected to the second end of each microchannel 11. The outer water inlet 31 is used to receive coolant, and the outer water outlet 34 is used to discharge coolant. The thicknesses of the first bonding layer 6, the second bonding layer 7, and the third bonding layer 8 are all less than 10 nm.

[0036] In one example, forming the first bonding layer 6 via magnetron sputtering includes: The bonding surfaces were activated using an argon atomic beam.

[0037] A sputtering layer is formed on each surface to be bonded using magnetron sputtering, and the sputtering layer is activated using an argon atom beam.

[0038] The water inlet layer 3 of the manifold structure is stacked and aligned with the substrate layer 1 of the semiconductor device with microchannels, and the bonding surfaces are aligned. The first bonding layer 6 is formed by applying a pressure of 0.1 to 20 MPa at 20 to 30°C and a bonding time of 200 to 500 s.

[0039] For example, the material of the sputtered layer is selected from any one of silicon, aluminum oxide, aluminum nitride, boron nitride, silicon carbide, aluminum, copper, silver, gold or titanium.

[0040] S6. Remove the temporary substrate protective layer 21 to obtain a semiconductor device with an ultra-thin bonding layer embedded heat dissipation structure.

[0041] The fabrication method provided in this embodiment uses a low-temperature bonding process to prepare a silicon nanolayer as the first bonding layer 6. On the one hand, the low-temperature bonding process avoids damage to the GaN gate metal structure caused by the high-temperature bonding process, which leads to a deterioration in device reliability. On the other hand, the first bonding layer with a nanometer thickness has a thermal expansion coefficient that is closer to that of the substrate layer 1 of the semiconductor device. This avoids the shear stress generated during the large temperature rise caused by the use of a thicker bonding layer in the prior art, which leads to channel misalignment and blockage, a reduction in effective cross-sectional area, and the problem of thermal stress separation caused by the difference in thermal expansion coefficients. Thus, this invention uses an all-semiconductor material (such as single-crystal silicon or SiC) to fabricate the manifold structure (including the water inlet layer 3, the water flow layer 4, and the support layer 5), and combines it with a room-temperature low-temperature bonding process, using a silicon intermediate layer of less than 10 nm. This makes the manifold structure-microchannel an integral semiconductor structure, which significantly reduces the interfacial thermal resistance, effectively utilizes the intrinsic high thermal conductivity of the material, avoids thermal stress peeling, and improves heat dissipation efficiency.

[0042] Example 3 The following uses a gallium nitride (GaN) device based on a Si substrate as an example to further illustrate the fabrication method of the semiconductor device with an ultrathin bonding layer embedded heat dissipation structure provided by the present invention. The specific steps are as follows: Step 1: Fabrication of substrate layer 1 and semiconductor device functional layer 2 1a) Growing AlGaN / GaN epitaxial structures on Si substrates using MOCVD An AlGaN / GaN epitaxial structure was grown on a silicon substrate using MOCVD. The epitaxial layers grown sequentially included an AlN nucleation layer, a GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer.

[0043] 1b) Photolithography of source and drain electrode regions on the AlGaN barrier layer First, place the sample obtained in step 1a) on a hot plate at 200°C and bake for 5 minutes.

[0044] Then, the release adhesive was coated and spun onto the AlGaN barrier layer. The thickness of the release adhesive was 0.35 μm. After spun coating, the release adhesive was placed on a hot plate at 200 °C and baked for 5 min.

[0045] Next, photoresist was coated and spun onto the release agent. The spun photoresist thickness was 0.77 μm. After spun photoresist, it was placed on a hot plate at 90°C and baked for 1 min.

[0046] Subsequently, the samples that have completed the coating and spin coating are placed in a photolithography machine to expose the photoresist in the source electrode area and the drain electrode area.

[0047] Finally, the exposed sample is placed in the developer to remove the photoresist and stripper in the source electrode and drain electrode areas. It is then rinsed with ultrapure water and dried with nitrogen to obtain a sample with photolithographic patterns of source and drain electrodes.

[0048] 1c) Performing ohmic electrode metal evaporation First, the sample with source and drain electrode photolithographic patterns obtained in step 1b) is placed in a plasma resist remover for bottom film treatment for 5 minutes.

[0049] Then, the sample is placed in the electron beam evaporation stage, and the vacuum degree of the reaction chamber of the electron beam evaporation stage reaches 2×10⁻⁶. -6 After Torr, ohmic metal is evaporated on the SiN dielectric layer in the source and drain electrode regions and on the photoresist outside the source and drain electrode regions. The ohmic metal is a metal stack structure consisting of four metal layers, Ti, Al, Ni and Au, arranged sequentially from bottom to top.

[0050] Next, the sample after ohmic metal evaporation is stripped to remove the ohmic metal, photoresist, and release adhesive outside the source and drain electrode regions.

[0051] Finally, rinse the sample with ultrapure water and dry it with nitrogen.

[0052] 1d) The sample obtained in step 1c) after ohmic metal evaporation and stripping is placed in a rapid thermal annealing furnace for annealing treatment, so that the ohmic metal in the source electrode and drain electrode regions sinks into the GaN buffer layer, thereby forming an ohmic contact between the ohmic metal and the heterojunction channel. The annealing process conditions are: annealing atmosphere is N2, annealing temperature is 830 ℃, and annealing time is 30 s, to obtain a sample with source electrode and drain electrode.

[0053] 1e) Perform surface cleaning on samples with source and drain electrodes. First, the sample with source and drain electrodes obtained in step 1d) is placed in acetone solution and ultrasonically cleaned for 3 min with an ultrasonic intensity of 3.0.

[0054] Then, the sample was placed in a stripping solution at 60°C and heated in a water bath for 5 minutes.

[0055] Next, the sample was placed in acetone solution and ethanol solution in sequence and ultrasonically cleaned for 3 minutes with an ultrasonic intensity of 3.0.

[0056] Finally, rinse the sample with ultrapure water and dry it with nitrogen.

[0057] 1f) Growing SiN dielectric layers using PECVD process For the sample cleaned in step 1e), a SiN dielectric layer with a thickness of 120 nm was grown on the AlGaN barrier layer using PECVD process. The growth process conditions were: NH3 and SiH4 were used as reaction gases, the substrate temperature was 250 ℃, the reaction chamber pressure was 600 mTorr, and the RF power was 22 W; a sample with a SiN dielectric layer was obtained.

[0058] 1g) Photolithographically etched gate trench region on SiN dielectric layer First, place the sample with the SiN dielectric layer prepared in step 1f) on a hot plate at 200°C and bake for 5 minutes.

[0059] Then, the photoresist was coated and spun off. The spin speed was 3500 r / min, and the sample after spin-spinning was placed on a hot plate at 90 ℃ and baked for 1 min.

[0060] Next, the sample is placed in a lithography machine to expose the photoresist in the gate trench area.

[0061] Finally, the exposed sample is placed in the developer to remove the photoresist in the grid trench area, and then rinsed with ultrapure water and dried with nitrogen.

[0062] 1h) The SiN dielectric layer in the gate trench area was removed using ICP (Inductively Coupled Plasma) etching process. The etching conditions were: the reaction gases were CF4 and O2, the reaction chamber pressure was 10 mTorr, the RF power of the upper electrode and the lower electrode was 100 W and 10 W, respectively, and the etching depth was 120 nm to expose the AlGaN barrier layer.

[0063] Then, the sample is sequentially placed in acetone solution, stripping solution, acetone solution and ethanol solution for cleaning to remove the photoresist outside the gate trench area and obtain a sample with the gate trench area.

[0064] 1i) Photolithographic gate electrode region: First, the sample with the grid groove region prepared in step 1h) is placed on a hot plate at 200°C and baked for 5 min.

[0065] Then, the release adhesive was applied and spun to a thickness of 0.35 μm, and the sample was baked on a hot plate at 200°C for 5 min.

[0066] Next, photoresist was coated and spun onto the release agent. The photoresist spun thickness was 0.77 μm, and the sample was baked on a hot plate at 90 °C for 1 min.

[0067] Afterwards, the sample with the completed coating and spin coating is placed in a photolithography machine to expose the photoresist in the gate electrode area.

[0068] Finally, the exposed sample is placed in the developer to remove the photoresist and stripper in the gate electrode area, and then rinsed with ultrapure water and dried with nitrogen to obtain a sample with a gate electrode photolithography pattern.

[0069] 1j) Evaporating the gate electrode on the photoresist within and outside the gate electrode region. First, the sample with the gate electrode photolithography pattern obtained in step 1i) is placed in a plasma resist remover for bottom film treatment, which takes 5 minutes.

[0070] Then, the sample is placed in the electron beam evaporation stage, and the vacuum degree of the reaction chamber of the electron beam evaporation stage reaches 2×10⁻⁶. -6 After Torr, gate metal is evaporated on the photoresist within and outside the gate electrode region. This gate metal is a metal stack structure consisting of two layers of metal, Ni and Au, arranged sequentially from bottom to top.

[0071] Then, the sample is immersed in acetone solution and sonicated until the metal is completely stripped off. It is then washed in stripping solution, acetone solution and ethanol solution in sequence to remove the photoresist outside the gate electrode area.

[0072] 1k) Photolithographically etched interconnect regions on the SiN dielectric layer First, place the sample obtained in step 1j) on a hot plate at 200 ℃ and bake for 5 min.

[0073] Then, the photoresist was coated and spun at a speed of 3500 r / min, and the sample was baked on a hot plate at 90 ℃ for 1 min.

[0074] Next, the sample is placed in a lithography machine to expose the photoresist in the interconnect area.

[0075] Finally, the exposed sample is placed in the developer to remove the photoresist in the interconnect area, and then rinsed with ultrapure water and dried with nitrogen.

[0076] 1l) Evaporating gate electrodes on photoresist within and outside the interconnect region: First, the sample with the gate electrode photolithography pattern is placed in a plasma resist remover for bottom film treatment, which takes 5 minutes.

[0077] Then, the sample is placed in the electron beam evaporation stage, and the vacuum degree of the reaction chamber of the electron beam evaporation stage reaches 2×10⁻⁶. -6 Following Torr, gate metal is evaporated onto the photoresist within and outside the interconnect region. This gate metal is a metal stack structure consisting of two layers of metal, Ni and Au, arranged sequentially from bottom to top.

[0078] Finally, the sample is immersed in acetone solution and sonicated until the metal is completely removed. It is then sequentially cleaned with a stripping solution, acetone solution, and ethanol solution to remove the photoresist outside the interconnect regions. Figure 3 As shown, a semiconductor device is obtained. The AlN nucleation layer, GaN buffer layer, GaN channel layer, AlGaN barrier layer, SiN dielectric layer, source electrode, drain electrode, and gate electrode formed on the substrate in the semiconductor device obtained in step one are collectively defined as the gallium nitride device functional layer (semiconductor device functional layer 2), as shown. Figure 4 As shown.

[0079] Step 2: Fabricate microchannels on the side of the substrate away from the functional layer of the gallium nitride device (the back side of the substrate). 2a) Temporary substrate support and protection on the device surface First, a heat-release adhesive is spin-coated onto one surface of the temporary substrate protective layer 21 (polished silicon wafer), with a spin coating thickness of 20 μm, and pre-baked at 80°C for 5 min to cure. Then, the side of the gallium nitride device functional layer furthest from the substrate layer is aligned and bonded to the adhesive side of the temporary substrate protective layer 21. A pressure greater than 0.5 MPa is applied, and bonding is performed at 150°C for at least 10 min to form a temporary rigid support. Figure 5 As shown.

[0080] 2b) Photolithography preset non-flow channel region First, place the sample obtained in step 2a) on a hot plate at 200°C and bake for 5 minutes.

[0081] Then, the release adhesive was applied and spun on the side of the substrate away from the functional layer of the gallium nitride device. The thickness of the release adhesive was 0.35 μm. The sample after spun adhesive was then baked on a hot plate at 200°C for 5 min.

[0082] Next, photoresist was coated and spun onto the release agent. The spun photoresist thickness was 0.77 μm. The sample after spun photoresist was then baked on a hot plate at 90°C for 1 min.

[0083] Afterwards, the sample with completed stripping, photoresist coating, and spin coating is placed in a photolithography machine to expose the photoresist in the non-flow channel area.

[0084] Finally, the exposed sample is placed in the developer to remove the photoresist and stripper in the non-channel areas, and then rinsed with ultrapure water and dried with nitrogen.

[0085] 2c) Backside sputtering of metal mask layer on substrate A nickel-chromium alloy (Ni-Cr, mass ratio 80:20) was sputtered on the back of a Si substrate as an etching mask. The sputtering power was 200W, the working pressure was 0.5Pa, and the sputtering time was 30 seconds to form a uniform metal film with a thickness of 200nm.

[0086] The sample was immersed in acetone solution and sonicated until the metal film layer in the microchannel region was completely peeled off. Then it was sequentially immersed in stripping solution, acetone solution and ethanol solution for cleaning to remove the photoresist in the microchannel region.

[0087] 2d) Re-lithography of the non-flow channel region First, place the sample obtained in step 2c) on a hot plate at 200°C and bake for 5 minutes.

[0088] Then, the release adhesive was applied and spun to a thickness of 0.35 μm, and the sample was baked on a hot plate at 200°C for 5 minutes.

[0089] Next, photoresist was coated and spun onto the release agent. The spun photoresist thickness was 0.77 μm, and the sample was baked on a hot plate at 90°C for 1 min.

[0090] Afterwards, the sample with the completed coating and spin coating is placed in the photolithography machine to expose the photoresist in the non-flow channel area; Finally, the exposed sample is placed in the developer to remove the photoresist and stripper in the non-channel areas, and then rinsed with ultrapure water and dried with nitrogen.

[0091] 2e) Electroplated thickened nickel-chromium alloy mask: First, the back side of the substrate (the side with the sputtered nickel-chromium alloy layer) is used as the cathode, and a pure nickel plate is used as the anode, and is placed in the nickel-chromium alloy electroplating solution. Then, the electroplating time is greater than 60 minutes, so that the total thickness of the nickel-chromium alloy mask is greater than 1.5 μm (sputtered layer + electroplated layer), and the electroplating solution is continuously stirred during the electroplating process.

[0092] Then, the sample was taken out and rinsed three times with ultrapure water and dried with nitrogen.

[0093] Finally, the sample was immersed in acetone solution and sonicated until the metal film layer in the microchannel region was completely peeled off. Then, it was sequentially immersed in stripping solution, acetone solution and ethanol solution for cleaning to remove the photoresist in the microchannel region.

[0094] 2f) Etching microchannels First, the sample with the photolithographic pattern obtained in step 2e) is placed in an inductively coupled plasma (ICP) etching apparatus. The etching conditions are: the reaction gases are SF6 and O2, the reaction chamber pressure is 10 mTorr, the upper electrode RF power is 100 W, and the lower electrode RF power is 10 W. The etching depth is controlled at 100 μm to form a microchannel structure. After etching, the surface roughness of the microchannel is less than 1 nm.

[0095] Finally, the sample was placed in acetone solution, stripping solution and isopropanol solution in sequence and ultrasonically cleaned for 3 minutes (ultrasonic intensity 3.0) to remove residual photoresist, and then rinsed with ultrapure water and dried with nitrogen.

[0096] 2g) Etching to remove exposed metal mask: First, immerse the sample obtained in step 2f) in an etching solution of nitric acid and hydrofluoric acid. The etching time is controlled to be no less than 45 seconds (observe every 15 seconds during the etching process until the nickel-chromium alloy layer in the non-flow channel pattern area is completely removed). Then, use tweezers to remove the sample and immediately rinse the surface with ultrapure water to remove any residual corrosive liquid for at least 30 seconds. Finally, the sample surface was dried with a nitrogen gun to ensure that no metal residue remained in the non-flow channel areas, obtaining the desired result. Figure 6The semiconductor device shown has a substrate layer with a microchannel structure.

[0097] Step 3: Manifold Structure Fabrication 3a) The first non-channel etching area preset by photolithography in the water inlet layer 3 First, the first semiconductor substrate (made of single-crystal silicon wafer) is placed on a hot plate at 200°C and baked for 5 minutes.

[0098] Then, a release adhesive is applied and spun onto one side of the first semiconductor substrate. The thickness of the release adhesive is 0.35 μm. The first semiconductor substrate after spun adhesive is then placed on a hot plate at 200 °C and baked for 5 min.

[0099] Next, photoresist is coated and spin-coated onto the release adhesive. The spin-coated photoresist thickness is 0.77 μm. The first semiconductor substrate after spin-coating is then placed on a hot plate at 90°C and baked for 1 minute.

[0100] Afterwards, the first semiconductor substrate, which has been coated and spin-coated with stripping adhesive and photoresist, is placed in a photolithography machine to expose the photoresist in the first non-channel etching area. Finally, the first semiconductor substrate that has been exposed is placed in the developer to remove the photoresist and stripper in the first non-channel etched area, and then rinsed with ultrapure water and dried with nitrogen.

[0101] 3b) Sputtered metal mask layer A nickel-chromium alloy (Ni-Cr, mass ratio 80:20) was sputtered as an etching mask on one side of the first semiconductor substrate coated with photoresist and release agent. The sputtering power was 200W, the working pressure was 0.5Pa, and the sputtering time was 30 seconds to form a uniform metal film with a thickness of 200nm.

[0102] Finally, the first semiconductor substrate is immersed in acetone solution and sonicated until the metal is completely stripped off. Then, it is sequentially immersed in stripping solution, acetone solution and ethanol solution for cleaning to remove the photoresist of the first channel etched area.

[0103] 3c) Re-lithographically etch the first non-channel etch area First, the first semiconductor substrate obtained in step 3b) is placed on a hot plate at 200°C and baked for 5 minutes.

[0104] Then, the release adhesive was applied and spun to a thickness of 0.35 μm, and the sample was baked on a hot plate at 200°C for 5 minutes.

[0105] Next, photoresist was coated and spun onto the release agent. The spun photoresist thickness was 0.77 μm, and the sample was baked on a hot plate at 90°C for 1 min.

[0106] Afterwards, the sample with completed coating and spin coating is placed in a photolithography machine to expose the photoresist in the first non-channel etching area.

[0107] Finally, the exposed sample is placed in the developer to remove the photoresist and stripper in the first non-channel etched area, and then rinsed with ultrapure water and dried with nitrogen.

[0108] 3d) Electroplated thickened nickel-chromium alloy mask: First, the side of the first semiconductor substrate sputtered with a nickel-chromium alloy layer is used as the cathode, and a pure nickel plate is used as the anode, and the substrate is placed in a nickel-chromium alloy electroplating solution. Then, the electroplating time is greater than 60 minutes, so that the total thickness of the nickel-chromium alloy mask is greater than 1.5 μm (sputtered layer + electroplated layer), and the electroplating solution is continuously stirred during the electroplating process.

[0109] Then, the sample was taken out and rinsed three times with ultrapure water and dried with nitrogen.

[0110] Finally, the sample was immersed in acetone solution and sonicated until the metal film layer of the first channel etched area was completely peeled off. Then, it was sequentially immersed in stripping solution, acetone solution and ethanol solution for cleaning to remove the photoresist of the first channel etched area.

[0111] 3e) Etching the coolant channels of the water inlet layer 3 First, the sample with photolithographic pattern obtained in step 3d) is placed in an inductively coupled plasma (ICP) etching apparatus. The etching conditions are: the reaction gases are SF6 and O2, the reaction chamber pressure is 10 mTorr, the upper electrode RF power is 100 W, and the lower electrode RF power is 10 W.

[0112] Then, based on the location of the first channel etching area, multiple coolant channels penetrating the first semiconductor substrate are etched to form. The coolant channels include an external inlet 31, an internal inlet 32, an external outlet 34, and an internal outlet 33. After etching, the surface roughness of each coolant channel is less than 1 nm.

[0113] Finally, the etched sample was sequentially placed in acetone solution, stripping solution and isopropanol solution for ultrasonic cleaning for 3 minutes (ultrasonic intensity 3.0) to remove residual photoresist, and then rinsed with ultrapure water and dried with nitrogen.

[0114] 3f) Etching to remove exposed metal mask First, immerse the sample obtained in step 3e) in an etching solution of nitric acid and hydrofluoric acid. The etching time is controlled to be no less than 45 seconds (observe every 15 seconds during the etching process until the nickel-chromium alloy layer of the first non-channel etching area is completely removed). Then, use tweezers to remove the sample and immediately rinse the surface with ultrapure water to remove any residual corrosive liquid for at least 30 seconds. Finally, the sample surface was dried with a nitrogen gun to ensure that there was no metal residue in the first non-channel etched area, such as... Figure 7 As shown, the influent layer 3 was obtained.

[0115] It should be noted that steps 3a) to 3f) are the process steps for preparing the water inlet layer 3, and the sample is the first semiconductor substrate in the process.

[0116] Steps 3g) to 3l) are the process steps for preparing the water layer 4, wherein the sample is the second semiconductor substrate in the process of the process.

[0117] 3g) Flow layer 4 photolithography second non-channel etching area First, the second semiconductor substrate (made of single-crystal silicon wafer) is placed on a hot plate at 200°C and baked for 5 minutes; Then, the release adhesive was applied and spun on one side of the second semiconductor substrate. The thickness of the release adhesive was 0.35 μm. The sample was then baked on a hot plate at 200 °C for 5 min.

[0118] Next, photoresist was coated and spun onto the release agent. The spun photoresist thickness was 0.77 μm, and the sample was baked on a hot plate at 90°C for 1 min.

[0119] Afterwards, the sample with the completed coating and spin coating is placed in the photolithography machine to expose the photoresist in the second non-channel etching area.

[0120] Finally, the exposed sample is placed in the developer to remove the photoresist and stripper in the second non-channel etched area, and then rinsed with ultrapure water and dried with nitrogen.

[0121] 3h) Sputtering metal mask layer A nickel-chromium alloy (Ni-Cr, mass ratio 80:20) was sputtered as an etching mask on the side of the second semiconductor substrate coated with release adhesive and photoresist. The sputtering power was 200W, the working pressure was 0.5Pa, and the sputtering time was 30 seconds to form a uniform metal film with a thickness of 200nm.

[0122] Finally, the sample was immersed in acetone solution and sonicated until the metal film layer of the second channel etched area was completely peeled off. Then, it was sequentially immersed in stripping solution, acetone solution and ethanol solution for cleaning to remove the photoresist of the second channel etched area.

[0123] 3i) Photolithography is performed again on the second non-channel etched area. First, place the sample obtained in step 3h) on a hot plate at 200°C and bake for 5 minutes.

[0124] Then, the release adhesive was applied and spun to a thickness of 0.35 μm, and the sample was baked on a hot plate at 200°C for 5 minutes.

[0125] Next, photoresist was coated and spun onto the release agent. The spun photoresist thickness was 0.77 μm, and the sample was baked on a hot plate at 90°C for 1 min.

[0126] Afterwards, the sample with the completed coating and spin coating is placed in the photolithography machine to expose the photoresist in the second non-channel etching area.

[0127] Finally, the exposed sample is placed in the developer to remove the photoresist and stripper in the second non-channel etched area, and then rinsed with ultrapure water and dried with nitrogen.

[0128] 3j) Electroplated thickened nickel-chromium alloy mask First, the side of the sample prepared in step 3i) with the sputtered nickel-chromium alloy layer is used as the cathode, and a pure nickel plate is used as the anode, and the sample is placed in the nickel-chromium alloy electroplating solution. Then, the electroplating time is greater than 60 minutes, so that the total thickness of the nickel-chromium alloy mask is greater than 1.5 μm (sputtered layer + electroplated layer), and the electroplating solution is continuously stirred during the electroplating process.

[0129] Then, the sample was taken out and rinsed three times with ultrapure water and dried with nitrogen.

[0130] Finally, the sample was immersed in acetone solution and sonicated until the metal film layer of the second channel etched area was completely peeled off. Then, it was sequentially immersed in stripping solution, acetone solution and ethanol solution for cleaning to remove the photoresist of the second channel etched area.

[0131] 3k) Etching the coolant channels of the water flow layer First, the sample with photolithographic pattern obtained in step 3j) is placed in an inductively coupled plasma (ICP) etching apparatus. The etching conditions are: the reaction gases are SF6 and O2, the reaction chamber pressure is 10 mTorr, the upper electrode RF power is 100 W, and the lower electrode RF power is 10 W.

[0132] Then, based on the location of the second channel etching area, multiple coolant channels penetrating the second semiconductor substrate are etched to form. The coolant channels include an inlet buffer tank 41 and an outlet buffer tank 42. After etching, the surface roughness of each coolant channel is less than 1 nm.

[0133] Finally, the sample was placed in acetone solution, stripping solution and isopropanol solution in sequence and ultrasonically cleaned for 3 minutes (ultrasonic intensity 3.0) to remove residual photoresist, and then rinsed with ultrapure water and dried with nitrogen.

[0134] 3l) Water layer 4 corrosion removal of exposed metal mask First, immerse the sample obtained in step 3k) in an etching solution of nitric acid and hydrofluoric acid. The etching time is controlled to be no less than 45 seconds (observe every 15 seconds during the etching process until the nickel-chromium alloy layer in the second non-channel etching area is completely removed). Then, use tweezers to remove the sample and immediately rinse the surface with ultrapure water to remove any residual corrosive liquid for at least 30 seconds. Finally, the sample surface was dried with a nitrogen gun to ensure that no metal residue remained in the second non-channel etched area. Figure 8 As shown, the water layer 4 was obtained.

[0135] 3m) Support layer 5 treatment A single-crystal silicon wafer with a thickness of 400μm was selected as the support layer 5. No etching was performed, and only the surface was polished to a roughness of less than 1 nm to provide mechanical support.

[0136] 3n) Low-temperature bonding connection of inlet layer 3, flow layer 4, and support layer 5: First, the bonding surfaces of the water inlet layer 3, the water flow layer 4, and the support layer 5 are activated for 5 minutes using an argon atomic beam to remove surface contaminants; wherein, the bonding surfaces in step 3n) include the lower surface of the water inlet layer 3, the upper surface of the water flow layer 4, the lower surface of the water flow layer 4, and the upper surface of the support layer 5.

[0137] Then, magnetron sputtering was used to sputter amorphous silicon with a thickness of less than 5 nm onto each bonding surface to form a nano-sputtered layer on each bonding surface. Next, the nano-sputtered layer was activated again using an argon atom beam; Finally, the inlet layer 3, the flow layer 4, and the support layer 5 (three silicon wafers) are aligned and stacked, so that the inlet buffer tank 41 is connected to both the outer inlet 31 and the inner inlet 32, and the outlet buffer tank 42 is connected to both the outer outlet 34 and the inner outlet 33. The mixture is then placed in a bonding machine under a pressure of 5 MPa, maintained at room temperature (20–30°C), and a bonding time of 300 seconds to form the second bonding layer 7 and the third bonding layer 8, thus obtaining an integrated manifold structure, such as... Figure 9 As shown.

[0138] Step 4: The semiconductor device with microfluidic structure obtained in Step 2 and the manifold structure obtained in Step 3 are connected by low-temperature bonding. First, the bonding surfaces of the semiconductor device with microfluidic structure and the manifold structure are activated for 5 minutes using an argon atomic beam to remove surface contaminants. The bonding surfaces in step four include the back side of the substrate layer of the semiconductor device with microfluidic structure (the side with microfluidic channel 11) and the upper surface of the water inlet layer 3 in the manifold structure.

[0139] Then, magnetron sputtering is used to sputter amorphous silicon with a thickness of less than 5 nm onto the bonding surface to form a nano-sputtered layer on the bonding surface.

[0140] Next, the nanosputtered layer was activated again using an argon atom beam.

[0141] Finally, the semiconductor devices with microchannel structures and the manifold structure are aligned and stacked (with the semiconductor devices with microchannel structures on top and the manifold structure on the bottom, such as...). Figure 10 As shown, the liquid is placed in a bonding machine and subjected to a pressure of 5 MPa. The temperature is kept at room temperature, and the bonding time is 300 seconds to form the first bonding layer 6. This allows the inner inlet 32 ​​to be connected to the first end of each microchannel 11, the inner outlet 33 to be connected to the second end of each microchannel 11, the outer inlet 31 to receive coolant, and the outer outlet 34 to discharge coolant.

[0142] Step 5: Remove the temporary substrate protective layer 21 First, the sample obtained in step four is placed on a heating stage and heated to 200°C for at least 2 minutes. Next, the edge of the temporary substrate protective layer 21 is held by a vacuum pen and slowly peeled vertically upwards. Finally, the side of the semiconductor device away from the substrate is immersed in a 60°C acetone solution, ultrasonically cleaned for at least 3 minutes, treated with oxygen plasma for 30 seconds (100W power, O2 flow rate 50 sccm) to thoroughly decompose residual colloids, and then rinsed with ultrapure water and dried with nitrogen to obtain a semiconductor device with an ultrathin bonding layer embedded heat dissipation structure.

[0143] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A semiconductor device having an ultra-thin bonding layer embedded heat dissipation structure, comprising a substrate layer (1) and a semiconductor device functional layer (2) located on one side of the substrate layer (1), characterized in that, The other side of the substrate layer (1) comprises a flow channel area and a non-flow channel area surrounding the outside of the flow channel area; the flow channel area has a plurality of micro flow channels (11) arranged in parallel; The substrate layer (1) is provided with a manifold structure away from the semiconductor device functional layer (2), the manifold structure is used for providing the inlet and outlet of the cooling liquid, so that the cooling liquid can flow through the micro flow channel (11) to achieve heat dissipation; The first bonding layer (6) is arranged between the manifold structure and the substrate layer (1); The material of the first bonding layer (6) is any one of silicon, aluminum oxide, aluminum nitride, boron nitride, silicon carbide, aluminum, copper, silver, gold or titanium; the thickness of the first bonding layer (6) is 5nm-50nm; The material of the manifold structure is a semiconductor material.

2. The semiconductor device having an ultra-thin bonding layer embedded heat spreading structure according to claim 1, wherein, The manifold structure comprises a support layer (5), a third bonding layer (8), a water flow layer (4), a second bonding layer (7) and a water inlet layer (3) arranged in sequence; the first bonding layer (6) is located between the water inlet layer (3) and the substrate layer (1); The water inlet layer (3) comprises a first semiconductor substrate, and the first semiconductor substrate is provided with an outer water inlet (31), an inner water inlet (32), an inner water outlet (33) and an outer water outlet (34) penetratingly arranged; the outer water inlet (31) is used for receiving the cooling liquid, and the outer water outlet (34) is used for discharging the cooling liquid; the inner water inlet (32) is communicated with the first end of each micro flow channel (11), and the inner water outlet (33) is communicated with the second end of each micro flow channel (11); The water flow layer (4) comprises a second semiconductor substrate, and the second semiconductor substrate is provided with a water inlet buffer groove (41) and a water outlet buffer groove (42); the water inlet buffer groove (41) is communicated with the outer water inlet (31) and the inner water inlet (32) at the same time, and the water outlet buffer groove (42) is communicated with the outer water outlet (34) and the inner water outlet (33) at the same time; The support layer (5) comprises a third semiconductor substrate, and the third semiconductor substrate is used for supporting the manifold structure.

3. The semiconductor device with ultra-thin bonding layer embedded heat spreading structure of claim 2, wherein, The water inlet buffer groove (41) and the water outlet buffer groove (42) are both penetratingly arranged on the second semiconductor substrate.

4. The semiconductor device with ultra-thin bonding layer embedded heat spreading structure of claim 3, wherein, The materials of the second bonding layer (7) and the third bonding layer (8) are selected from any one of silicon, aluminum oxide, aluminum nitride, boron nitride, silicon carbide, aluminum, copper, silver, gold or titanium, and the thickness is 5nm-50nm.

5. The semiconductor device with ultra-thin bonding layer embedded heat spreading structure of claim 4, wherein, The materials of the first semiconductor substrate, the second semiconductor substrate and the third semiconductor substrate are single crystal silicon or SiC.

6. The semiconductor device with ultra-thin bonding layer embedded heat spreading structure of claim 5, wherein, The surface roughness of the micro flow channel (11), the outer water inlet (31), the inner water inlet (32), the outer water outlet (34), the inner water outlet (33), the water inlet buffer groove (41) and the water outlet buffer groove (42) is less than 1nm.

7. The semiconductor device with ultra-thin bonding layer embedded heat spreading structure of claim 1, wherein, The ratio of the depth of the micro flow channel (11) to the thickness of the substrate layer (1) is 1: (1.5-2).

8. A method for fabricating a semiconductor device with an ultrathin bonding layer embedded heat dissipation structure, characterized in that, It comprises: Preparation of substrate layer (1) and semiconductor device functional layer (2), forming a temporary substrate protection layer (21) on the side of the semiconductor device functional layer (2) away from the substrate layer (1); Forming a plurality of parallel micro flow channels (11) on the preset micro flow channel area of the substrate layer (1) far from the semiconductor device functional layer (2) side, to obtain a semiconductor device with micro flow channels; wherein the outer periphery of the preset micro flow channel area surrounds the preset non-flow channel area; A first semiconductor substrate is obtained, and an inductively coupled plasma etching process is used to form an external water inlet (31), an internal water inlet (32), an external water outlet (34), and an internal water outlet (33) that penetrate the first semiconductor substrate according to a preset position on the first semiconductor substrate, to obtain a water inlet layer (3); a second semiconductor substrate is obtained, and an inductively coupled plasma etching process is used to form a water inlet buffer groove (41) and a water outlet buffer groove (42) that penetrate the second semiconductor substrate according to a preset position on the second semiconductor substrate, to obtain a water flow layer (4); a third semiconductor substrate is obtained as a support layer (5); A second bonding layer (7) and a third bonding layer (8) are respectively formed by a magnetron sputtering process; the second bonding layer (7) is located between the water flow layer (4) and the water inlet layer (3) for connecting the water flow layer (4) and the water inlet layer (3), and the third bonding layer (8) is located between the water flow layer (4) and the support layer (5) for connecting the water flow layer (4) and the support layer (5), to obtain a manifold structure; wherein the water inlet buffer groove (41) is in communication with the external water inlet (31) and the internal water inlet (32) at the same time, and the water outlet buffer groove (42) is in communication with the external water outlet (34) and the internal water outlet (33) at the same time; A first bonding layer (6) is formed by a magnetron sputtering process, which is located between the water inlet layer (3) and the substrate layer (1) of the manifold structure, for connecting the manifold structure and the semiconductor device with micro flow channels (11); wherein the internal water inlet (32) is in communication with the first end of each micro flow channel (11), and the internal water outlet (33) is in communication with the second end of each micro flow channel (11); the external water inlet (31) is used to receive cooling liquid, and the external water outlet (34) is used to discharge cooling liquid; and the thickness of the first bonding layer (6), the second bonding layer (7), and the third bonding layer (8) is 5nm-50nm; The temporary substrate protection layer (21) is removed to obtain a semiconductor device with an ultrathin bonding layer embedded heat dissipation structure.

9. The method of claim 8, wherein the method further comprises: In the step of forming the second bonding layer (7) and the third bonding layer (8) by a magnetron sputtering process, and forming the first bonding layer (6) by a magnetron sputtering process, the following steps are included: Using an argon atom beam to activate the bonding surface; Using a magnetron sputtering process to form a sputtering layer on each bonding surface, and using an argon atom beam to activate the sputtering layer; Stacking and aligning each bonding surface, bonding for 200s-500s at 20-30℃ under a pressure of 0.1MPa-20MPa to form the corresponding bonding layer; the bonding layer includes the first bonding layer (6), the second bonding layer (7), and the third bonding layer (8).

10. The method of claim 8, wherein the method further comprises: The third semiconductor substrate also includes a surface polishing process with a roughness less than 1nm. The material of the first semiconductor substrate, the second semiconductor substrate and the third semiconductor substrate is single crystal silicon or SiC; The material of the sputtering layer is selected from any one of silicon, aluminum oxide, aluminum nitride, boron nitride, silicon carbide, aluminum, copper, silver, gold or titanium.

Images