Display panel and display device

Abstract

The invention discloses a display panel and a display device, the display panel comprises a substrate, a plurality of pixel driving circuits (Pi) and a control circuit (K), orthographic projections of the plurality of pixel driving circuits (Pi) on the substrate are distributed in an array along a first direction (X) and a second direction (Y), and the first direction (X) and the second direction (Y) intersect; wherein the pixel driving circuit (Pi) comprises a driving transistor (T3) and a switching transistor (Tx), and a first electrode of the switching transistor (Tx) is connected with a grid electrode of the driving transistor (T3); the control circuit (K) and at least one pixel driving circuit (Pi) are correspondingly arranged, the control circuit (K) is connected with the grid electrode of the switching transistor (Tx) in the corresponding pixel driving circuit (Pi), and the control circuit (K) is used for controlling the switching-on and switching-off of the switching transistor (Tx) connected with the control circuit (K). The display panel can realize adjustment of the refreshing frequency of the local area of the display panel.

Description

Display panel and display device

[0001] Cross Reference to Related Applications

[0002] This application claims priority to PCT Application No. PCT / CN2024 / 096815, filed May 31, 2024, entitled “Display panel and display device”, the disclosure of which is incorporated herein in its entirety by this reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0004] In the related art, in order to improve the display effect of the display panel, the display panel has a high refresh frequency. However, the high refresh frequency of the display panel leads to high power consumption of the display panel.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art.

[0006] SUMMARY

[0007] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel comprises:

[0008] a substrate substrate;

[0009] a plurality of pixel driving circuits, the orthogonal projection of the plurality of pixel driving circuits on the substrate substrate is arrayed along a first direction and a second direction, and the first direction and the second direction intersect;

[0010] wherein the pixel driving circuit comprises a driving transistor and a switching transistor, and the first electrode of the switching transistor is connected to the gate of the driving transistor;

[0011] a control circuit, the control circuit and at least one pixel driving circuit correspondingly arranged, the control circuit is connected to the gate of the switching transistor in the pixel driving circuit corresponding thereto, and the control circuit is used to control the on-off of the switching transistor connected thereto.

[0012] In an exemplary embodiment of the present disclosure, the plurality of pixel driving circuits distributed along the first direction form a pixel driving circuit row, and the display panel further comprises:

[0013] a gate line, the orthogonal projection of the gate line on the substrate substrate extends along the first direction, and the gate line is used to provide a gate driving signal to the plurality of switching transistors located in the same pixel driving circuit row.

[0014] The control circuit is connected to the gate line, and the control circuit is configured to connect the gate of the switch transistor to the gate line in response to a control signal or to disconnect the gate of the switch transistor from the gate line in response to a control signal.

[0015] In an example embodiment of the present disclosure, the display panel further comprises:

[0016] A fourth gate line, a projection of the fourth gate line on the substrate substrate extends along the second direction;

[0017] The control circuit is configured to transmit a gate drive signal on the gate line to the gate of the switch transistor in response to a signal of the fourth gate line.

[0018] In an example embodiment of the present disclosure, the display panel further comprises:

[0019] A gate line, a projection of the gate line on the substrate substrate extends along the first direction;

[0020] A fourth gate line, a projection of the fourth gate line on the substrate substrate extends along the second direction;

[0021] The control circuit is connected to the gate line and the fourth gate line, and the control circuit is configured to transmit a control signal of the fourth gate line to the gate of the switch transistor in response to a signal on the gate line, and the switch transistor can be turned off or turned on in response to the control signal of the fourth gate line.

[0022] In an example embodiment of the present disclosure, the pixel driving circuit comprises one or more of the switch transistors, and one or more of the switch transistors comprises a second transistor, a first electrode of the second transistor is connected to a gate of a driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor.

[0023] One or more of the gate lines correspondingly provided in the same pixel driving circuit row comprises a first gate line, and the first gate line is configured to provide a gate drive signal to a plurality of the second transistors in the same pixel driving circuit row.

[0024] In an example embodiment of the present disclosure, the control circuit is further configured to transmit an off signal to the gate of the switch transistor in response to a control signal.

[0025] In an example embodiment of the present disclosure, the control circuit comprises:

[0026] A ninth transistor, a first electrode of the ninth transistor is connected to a first gate line, a second electrode of the ninth transistor is connected to the gate of the switch transistor, and a gate of the ninth transistor is connected to a fourth gate line.

[0027] A tenth transistor has a first electrode connected to the off signal line, a second electrode connected to the gate of the switch transistor, and a gate connected to the fourth gate line, the off signal line being configured to provide the off signal to the control circuit.

[0028] The ninth transistor and the tenth transistor have opposite polarities of the conduction signals.

[0029] In an example embodiment of the present disclosure, the display panel further includes:

[0030] A second bridge portion is connected to the gate of the ninth transistor and the gate of the tenth transistor through vias, respectively.

[0031] The second bridge portion includes a first sub-bridge portion connected to the gate of the ninth transistor through a via, and a projection of the first sub-bridge portion on the substrate extends in the second direction.

[0032] A projection of the fourth gate line on the substrate and a projection of the off signal line on the substrate extend in the second direction, and in the same control circuit, the projection of the fourth gate line on the substrate is located between the projection of the off signal line on the substrate and the projection of the first sub-bridge portion on the substrate.

[0033] In an example embodiment of the present disclosure, the display panel further includes:

[0034] A first sub-bridge portion is connected to the gate of the ninth transistor through a via.

[0035] A second sub-bridge portion is spaced apart from the first sub-bridge portion and is connected to the gate of the tenth transistor through a via.

[0036] A projection of the fourth gate line on the substrate extends in the second direction, and the fourth gate line is connected to the first sub-bridge portion and the second sub-bridge portion through vias, respectively.

[0037] In an example embodiment of the present disclosure, the display panel further includes:

[0038] A protruding portion is located in the same conductive layer as the fourth gate line, and the protruding portion is connected to the fourth gate line, a projection of the protruding portion on the substrate is located on one side of a projection of the fourth gate line on the substrate in the first direction, and the fourth gate line is connected to the first sub-bridge portion through the protruding portion.

[0039] Alternatively, the fourth gate line is directly connected to the first sub-bridge portion through a via.

[0040] In an example embodiment of the present disclosure, the display panel further comprises:

[0041] The second bridge portion is connected to the gate of the ninth transistor and the gate of the tenth transistor through vias, respectively.

[0042] The second bridge portion comprises two first bridge sub-portions and a second bridge sub-portion, the two first bridge sub-portions are connected to the gate of the ninth transistor through vias, respectively, and the second bridge sub-portion is connected between the two first bridge sub-portions and connected to the gate of the tenth transistor through a via.

[0043] The orthographic projection of the two first bridge sub-portions on the substrate substrate extends along the second direction and is arranged in the first direction.

[0044] In an example embodiment of the present disclosure, the display panel further comprises:

[0045] The twelfth bridge portion is connected to the second electrode of the ninth transistor and the second electrode of the tenth transistor through vias, respectively.

[0046] The orthographic projection of the twelfth bridge portion on the substrate substrate is located between the orthographic projection of the two first bridge sub-portions on the substrate substrate in the same second bridge portion.

[0047] In an example embodiment of the present disclosure, the display panel comprises:

[0048] At least two of the turn-off signal lines are arranged corresponding to the two first bridge sub-portions in the same second bridge portion, respectively.

[0049] The conductive layer where the turn-off signal line is located is located on the side of the conductive layer where the second bridge portion is located away from the substrate substrate, and the orthographic projection of the turn-off signal line on the substrate substrate and the orthographic projection of the corresponding first bridge sub-portion on the substrate substrate at least partially overlap.

[0050] In an example embodiment of the present disclosure, the display panel further comprises:

[0051] At least two turn-off signal lines, the orthographic projection of the two turn-off signal lines on the substrate substrate extends along the second direction and is arranged in the first direction, and the turn-off signal line is used to provide the turn-off signal to the control circuit.

[0052] The eleventh bridge portion is connected to the two turn-off signal lines through vias, respectively.

[0053] In an example embodiment of the present disclosure, the display panel further comprises:

[0054] a plurality of turn-off signal lines, a projection of the plurality of turn-off signal lines on the substrate substrate extends along the second direction and is spaced apart along the first direction, the turn-off signal lines being configured to provide the turn-off signal to the control circuit;

[0055] a plurality of turn-off signal connection lines, a projection of the plurality of turn-off signal connection lines on the substrate substrate extends along the first direction and is spaced apart along the second direction;

[0056] the turn-off signal lines and the turn-off signal connection lines are located in different conductive layers, at least part of the turn-off signal lines are connected to at least part of the turn-off signal connection lines intersected by the via.

[0057] In an example embodiment of the present disclosure, the display panel further comprises:

[0058] a first source-drain layer located on one side of the substrate substrate, the first source-drain layer comprising an eleventh bridge portion, a seventeenth bridge portion, and the turn-off signal connection lines, the eleventh bridge portion being connected to the turn-off signal lines by a via, the seventeenth bridge portion being connected between the turn-off signal connection lines and the eleventh bridge portion, a projection of the seventeenth bridge portion on the substrate substrate extending along the second direction;

[0059] a second source-drain layer located on the side of the first source-drain layer away from the substrate substrate, the second source-drain layer comprising a fourth gate line, a projection of the fourth gate line on the substrate substrate extending along the second direction, the control circuit being configured to transmit the turn-off signal to the gate of the switching transistor in response to a control signal on the fourth gate line;

[0060] wherein a projection of the seventeenth bridge portion on the substrate substrate and a projection of the fourth gate line on the substrate substrate at least partially overlap.

[0061] In an example embodiment of the present disclosure, the pixel driving circuit comprises one or more of the switching transistors, and one or more of the switching transistors comprises a second transistor, a first electrode of the second transistor being connected to a gate of a driving transistor, and a second electrode of the second transistor being connected to a second electrode of the driving transistor.

[0062] one or more of the gate lines comprises a first gate line, the first gate line being configured to provide a gate driving signal to a plurality of the second transistors in the same row of pixel driving circuits;

[0063] wherein a projection of the turn-off signal connection lines on the substrate substrate and a projection of the first gate line on the substrate substrate at least partially overlap.

[0064] In one exemplary embodiment of this disclosure, the control circuit includes:

[0065] The ninth transistor has its first terminal connected to the first gate line, its second terminal connected to the gate of the second transistor, and its gate connected to the fourth gate line.

[0066] The first gate line includes first gate line segments that extend along the first direction and are spaced apart;

[0067] The display panel also includes:

[0068] The first active layer includes a ninth active portion and a twenty-first active portion, wherein the ninth active portion is used to form the channel region of the ninth transistor, and the twenty-first active portion is connected to the ninth active portion.

[0069] Wherein, the orthographic projection of the 21st active part on the substrate is located between the orthographic projections of two adjacent first gate line segments on the substrate in the same first gate line;

[0070] The eighteenth bridging section is connected via vias to two adjacent first gate line segments and the twenty-first active section between the two adjacent first gate line segments.

[0071] In one exemplary embodiment of this disclosure, the control circuit includes:

[0072] The ninth transistor has a first terminal connected to the first gate line, a second terminal connected to the gate of the second transistor, and the gate connected to the fourth gate line. The orthogonal projection of the first gate line on the substrate extends continuously along the first direction.

[0073] The display panel also includes:

[0074] The first active layer includes a ninth active portion and a twenty-first active portion, wherein the ninth active portion is used to form the channel region of the ninth transistor, and the twenty-first active portion is connected to the ninth active portion.

[0075] Wherein, the orthographic projection of the 21st active part on the substrate is located on the side where the orthographic projection of the first gate line on the substrate is in the second direction;

[0076] The eighteenth bridging section connects the first gate line and the twenty-first active section via vias.

[0077] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a capacitor;

[0078] The display panel also includes:

[0079] A first gate layer is located on the side of the first active layer away from the substrate, and a portion of the structure of the first gate layer is used to form the first electrode of the capacitor.

[0080] The second gate layer is located on the side of the first gate layer away from the substrate. A portion of the structure of the second gate layer is used to form the second electrode of the capacitor. The first gate line is located in the second gate layer.

[0081] In one exemplary embodiment of this disclosure, the display panel further includes:

[0082] A first source / drain layer is located on one side of the substrate. The first source / drain layer includes a first bridging portion, which is connected to the gate of the driving transistor and the first electrode of the second transistor through vias.

[0083] The first gate line is located in the first source / drain layer.

[0084] In one exemplary embodiment of this disclosure, a plurality of pixel driving circuits distributed in the second direction form a pixel driving circuit column, and one or more adjacent pixel driving circuit columns form a pixel driving circuit group.

[0085] The display panel includes a plurality of pixel driving circuit groups, and the pixel driving circuit groups are correspondingly provided with a plurality of control circuits;

[0086] In the same pixel driving circuit group: the control circuit and the pixel driving circuit located in the same pixel driving circuit row are set up accordingly.

[0087] In one exemplary embodiment of this disclosure, the display panel further includes:

[0088] The fifth gate line includes fifth gate line segments extending along the first direction and spaced apart along the first direction. The fifth gate line segments are correspondingly disposed with the pixel driving circuit group. The fifth gate line segments are connected to the gates of the same type of switching transistors located in the same pixel driving circuit row in the pixel driving circuit group corresponding to them.

[0089] The control circuit is connected to the gate of the switching transistor in its corresponding pixel driving circuit via the fifth gate segment.

[0090] In one exemplary embodiment of this disclosure, the pixel driving circuit group includes two pixel driving circuit subgroups;

[0091] In the corresponding pixel driving circuit group and the control circuit, the orthographic projection of the control circuit on the substrate is located between the orthographic projections of the two pixel driving circuit subgroups on the substrate.

[0092] In one exemplary embodiment of this disclosure, the pixel driving circuit includes one or more of the switching transistors, one or more of the switching transistors including a second transistor, the first terminal of the second transistor being connected to the gate of the driving transistor, and the second terminal of the second transistor being connected to the second terminal of the driving transistor;

[0093] The pixel driving circuit also includes a fifth transistor;

[0094] The first terminal of the fifth transistor is connected to the first power supply line, the second terminal is connected to the first terminal of the driving transistor, and the gate is connected to the enable signal line.

[0095] The display panel also includes:

[0096] The second active layer is located on one side of the substrate. The second active layer includes a tenth active portion, which is used to form the channel region of the tenth transistor.

[0097] A third gate layer is located on the side of the second active layer away from the substrate. The third gate layer includes a fifth gate line, a portion of which is used to form the gate of the second transistor.

[0098] In the same pixel driving circuit row, the orthographic projection of the tenth active part on the substrate is located between the orthographic projection of the fifth gate line on the substrate and the orthographic projection of the enable signal line on the substrate.

[0099] In one exemplary embodiment of this disclosure, the display panel further includes: a fourth gate line, the fourth gate line extending along the second direction by its orthogonal projection on the substrate;

[0100] The fourth gate line is used to provide control signals to multiple control circuits corresponding to the same pixel driving circuit group.

[0101] In one exemplary embodiment of this disclosure, the pixel driving circuit group includes two pixel driving circuit subgroups;

[0102] The orthographic projection of the fourth gate line on the substrate lies between the orthographic projections of the two pixel driving circuit subgroups in the same pixel driving circuit group on the substrate.

[0103] In one exemplary embodiment of this disclosure, the control circuit is further configured to respond to a control signal to transmit a turn-off signal to the gate of the switching transistor;

[0104] The display panel further includes a shutdown signal line, the shutdown signal line extending along the second direction by its orthogonal projection on the substrate, and the shutdown signal line being used to provide shutdown signals to multiple control circuits corresponding to the same pixel driving circuit group.

[0105] The orthographic projection of the shutdown signal line on the substrate is located between the orthographic projections of the two pixel driving circuit subgroups in the same pixel driving circuit group on the substrate, and the orthographic projection of the shutdown signal line on the substrate is located between the orthographic projection of the fourth gate line on the substrate and the orthographic projection of the pixel driving circuit subgroup on the substrate.

[0106] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0107] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0108] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0109] Figure 1 is a schematic diagram of an exemplary embodiment of a display panel in the related art;

[0110] Figure 2 is a schematic diagram of the structure of an exemplary embodiment of the display panel of this disclosure;

[0111] Figure 3 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0112] Figure 4 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0113] Figure 5 is a structural schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0114] Figure 6 is a schematic diagram of an exemplary embodiment of the pixel driving circuit of this disclosure;

[0115] Figure 7 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in Figure 6;

[0116] Figure 8 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0117] Figure 9 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0118] Figure 10 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0119] Figure 11 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0120] Figure 12 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0121] Figure 13 is a structural layout of the shielding layer in Figure 12;

[0122] Figure 14 is the structural layout of the first active layer in Figure 12;

[0123] Figure 15 is a structural layout of the first gate layer in Figure 12;

[0124] Figure 16 is a structural layout of the second gate layer in Figure 12;

[0125] Figure 17 shows the structural layout of the second active layer in Figure 12;

[0126] Figure 18 is a structural layout of the third gate layer in Figure 12;

[0127] Figure 19 is a structural layout of the first source / drain layer in Figure 12;

[0128] Figure 20 is a structural layout of the second source / drain layer in Figure 12;

[0129] Figure 21 is a structural layout of the third source / drain layer in Figure 12;

[0130] Figure 22 is a structural layout of the shielding layer and the first active layer in Figure 12;

[0131] Figure 23 is a structural layout of the shielding layer, the first active layer, and the first gate layer in Figure 12;

[0132] Figure 24 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in Figure 12;

[0133] Figure 25 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in Figure 12;

[0134] Figure 26 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in Figure 12;

[0135] Figure 27 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in Figure 12;

[0136] Figure 28 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, and the second source / drain layer in Figure 12.

[0137] Figure 29 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in another exemplary embodiment of the display panel of this disclosure;

[0138] Figure 30 is a structural layout of the first active layer in the display panel shown in Figure 29;

[0139] Figure 31 is a structural layout of the shielding layer, the first active layer, and the first gate layer in the display panel shown in Figure 29;

[0140] Figure 32 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 29;

[0141] Figure 33 is a partial cross-sectional view of the display panel shown in Figure 12, cut along the dashed line AA;

[0142] Figure 34 is a structural layout of another exemplary embodiment of the display panel of this disclosure;

[0143] Figure 35 is a structural layout of the first gate layer in the display panel shown in Figure 34;

[0144] Figure 36 is a structural layout of the second gate layer in the display panel shown in Figure 34;

[0145] Figure 37 is a structural layout of the first source / drain layer in the display panel shown in Figure 34;

[0146] Figure 38 is a structural layout of the second source / drain layer in the display panel shown in Figure 34;

[0147] Figure 39 is a structural layout of the shielding layer, the first active layer, and the first gate layer in the display panel shown in Figure 34;

[0148] Figure 40 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 34.

[0149] Figure 41 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in the display panel shown in Figure 34.

[0150] Figure 42 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0151] Figure 43 is a structural layout of the second gate layer in the display panel shown in Figure 42;

[0152] Figure 44 is a structural layout of the first source / drain layer in the display panel shown in Figure 42;

[0153] Figure 45 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 42.

[0154] Figure 46 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0155] Figure 47 is a structural layout of the first gate layer in the display panel shown in Figure 46;

[0156] Figure 48 is a structural layout of the second gate layer in the display panel shown in Figure 46;

[0157] Figure 49 is a structural layout of the first source / drain layer in the display panel shown in Figure 46;

[0158] Figure 50 is a structural layout of the second source / drain layer in the display panel shown in Figure 46;

[0159] Figure 51 is a structural layout of the shielding layer, the first active layer, and the first gate layer in the display panel shown in Figure 46.

[0160] Figure 52 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 46.

[0161] Figure 53 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in the display panel shown in Figure 46.

[0162] Figure 54 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0163] Figure 55 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in the display panel shown in Figure 54.

[0164] Figure 56 is a structural layout of the first source / drain layer in the display panel shown in Figure 54;

[0165] Figure 57 is a structural layout of the second source / drain layer in the display panel shown in Figure 54;

[0166] Figure 58 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0167] Figure 59 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in the display panel shown in Figure 58. Detailed Implementation

[0168] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0169] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0170] In the description of this disclosure, unless otherwise expressly specified and limited, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term “multiple” refers to two or more; and the term “and / or” includes any and all combinations of one or more associated listed items. In particular, references to “the / described” object or “a” object are also intended to indicate one of a possible plurality of such objects.

[0171] Unless otherwise specified or stated, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, an integral connection, an electrical connection, or a signal connection; "connection" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0172] Furthermore, it should be understood that the directional terms such as "upper," "lower," "inner," and "outer" described in the exemplary embodiments of this disclosure are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the exemplary embodiments of this disclosure. It should also be understood that, in the context of an element or feature being connected to one or more "upper," "lower," "inner," or "outer" elements, it can be directly connected to one or more "upper," "lower," "inner," or "outer" elements, or indirectly connected to one or more "upper," "lower," "inner," or "outer" elements through intermediate elements.

[0173] Figure 1 shows a schematic diagram of an exemplary embodiment of a display panel in the related art. The display panel may include a timing controller, a source driving circuit, a gate driving circuit, and a pixel array. The timing controller is connected to both the source driving circuit and the gate driving circuit. The source driving circuit is connected to multiple data lines (Da1 to Dan). The gate driving circuit includes a scan driving circuit and a light-emitting driving circuit. The scan driving circuit is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driving circuit is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. Each sub-pixel Pxij may include a pixel driving circuit and a light-emitting unit connected to the pixel driving circuit. The pixel driving circuit may be connected to the scan signal lines, light-emitting signal lines, and data lines. The data lines can be used to provide the data signal terminals described above, and the light-emitting signal lines can be used to provide the enable signal terminals described above. This exemplary embodiment only shows one scan signal line connected to the pixel driving circuit. Each row of pixel driving circuits can be connected to multiple scan signal lines, which can be used to provide the first gate driving signal terminal, the second gate driving signal terminal, the first reset signal terminal, and the second reset signal terminal described above, respectively. In the exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the source driving circuit to the source driving circuit, provide clock signals, scan start signals, etc. of specifications suitable for the scan driving circuit to the scan driving circuit, and provide clock signals, emission stop signals, etc. of specifications suitable for the light-emitting driving circuit to the light-emitting driving circuit. The source driving circuit can use the grayscale values ​​and control signals received from the timing controller to generate data signals to be provided to the data lines Da1, Da2, Da3, ... and Dan. For example, the source driver circuit can sample grayscale values ​​using a clock signal and apply data signals corresponding to the grayscale values ​​to data lines Da1 to Dan in pixel rows, where n can be a natural number. The scan driver circuit can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from a timing controller. For example, the scan driver circuit can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver circuit can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the light-emitting driver circuit can sequentially provide transmit signals with off-level pulses to light-emitting signal lines E1 to Eo.For example, the light-emitting driving circuit can be configured as a shift register, and can generate a transmission signal by sequentially transmitting a transmit stop signal provided in the form of a cutoff level pulse to the next stage circuit under the control of a clock signal, where 0 can be a natural number. Thus, the display panel can achieve line-by-line scanning and driving.

[0174] Figure 2 shows a schematic diagram of an exemplary embodiment of the display panel of this disclosure. The display panel includes a substrate, a plurality of pixel driving circuits Pi, gate lines Gx, and a control circuit K. The orthographic projections of the plurality of pixel driving circuits Pi on the substrate are distributed in an array along a first direction X and a second direction Y. The first direction X and the second direction Y intersect; for example, the first direction X and the second direction Y can be perpendicular. A plurality of pixel driving circuits distributed along the first direction X form a pixel driving circuit row Pih; wherein, the pixel driving circuit Pih includes a driving transistor T3 and a switching transistor Tx, the first terminal of the switching transistor Tx being connected to the gate of the driving transistor T3; a gate line Gx is projected onto the substrate along the first direction X, and the gate line Gx is used to provide a gate driving signal to a plurality of switching transistors Tx located in the same pixel driving circuit row Pih; a control circuit K is correspondingly disposed with at least one pixel driving circuit; the control circuit K is connected to the gate of the switching transistor Tx and the gate line Gx in the corresponding pixel driving circuit, and the control circuit K is used to respond to a control signal to connect the gate of the switching transistor Tx and the gate line Gx, or to respond to a control signal to disconnect the gate of the switching transistor Tx from the gate line Gx.

[0175] This exemplary embodiment allows control of the driving state of the switching transistor Tx in the pixel driving circuit connected to it via control circuit K. When control circuit K controls the gate of switching transistor Tx to connect to gate line Gx, switching transistor Tx normally receives the gate driving signal on gate line Gx, and the pixel driving circuit can scan normally; when control circuit K controls the gate of switching transistor Tx to receive a turn-off signal, switching transistor Tx is in the turn-off state, and the pixel driving circuit cannot scan. That is, this exemplary embodiment allows adjustment of the refresh rate of the pixel driving circuit connected to it via control circuit K, and multiple control circuits K can adjust the refresh rate of different areas of the display panel.

[0176] It should be noted that the first electrode of the switching transistor being connected to the gate of the driving transistor can include: the first electrode of the switching transistor being directly electrically connected to the gate of the driving transistor, or the first electrode of the switching transistor being connected to the gate of the driving transistor through a capacitor, that is, the two electrodes of the capacitor being connected to the first electrode of the switching transistor and the gate of the driving transistor, respectively.

[0177] In this exemplary embodiment, the control circuit K and a portion of the pixel driving circuits in the same row of pixel driving circuits are correspondingly configured. When the display panel is driven row by row, the control circuit can control the switching transistor Tx row by row. It should be understood that in other exemplary embodiments, the display panel can be driven in other ways, and correspondingly, the control circuit and pixel driving circuits can also have other corresponding configurations. For example, when the display panel is driven in two rows, the control circuit can be correspondingly configured with a portion of the pixel driving circuits in the two rows of pixel driving circuits.

[0178] In this exemplary embodiment, as shown in FIG2, a plurality of pixel driving circuits Pi distributed in the second direction Y form a pixel driving circuit column Piv, and one or more adjacent pixel driving circuit columns Piv form a pixel driving circuit group Pivz; the display panel includes a plurality of pixel driving circuit groups Pivz, and a plurality of control circuits K are correspondingly arranged in the pixel driving circuit groups Pivz. In the same pixel driving circuit group Pivz: the control circuit K is correspondingly arranged with the pixel driving circuit located in the same pixel driving circuit row Pih, and different control circuits K can correspond to pixel driving circuits in different pixel driving circuit rows Pih respectively.

[0179] In this exemplary embodiment, as shown in FIG2, the display panel further includes a fifth gate line G5, which includes fifth gate line segments G51 extending along the first direction X and spaced apart along the first direction X. The fifth gate line segments G51 are correspondingly disposed with the pixel driving circuit group Pivz. The fifth gate line segments G51 can be connected to the gates of the same type of switching transistors located in the same pixel driving circuit row in the corresponding pixel driving circuit group. For example, a portion of the structure of the fifth gate line segment G51 is used to form the gates of the switching transistors located in the same pixel driving circuit row in the corresponding pixel driving circuit group. The control circuit K can be connected to the gate of its corresponding switching transistor Tx through the fifth gate segment G51. The same type of switching transistors are switching transistors with the same function in different pixel driving circuits. For example, as shown in FIG6, the second transistors located in the same pixel driving circuit row are the same type of switching transistors, and the first transistors located in the same pixel driving circuit row are the same type of switching transistors.

[0180] In this exemplary embodiment, as shown in FIG2, the display panel further includes: a fourth gate line G4, the fourth gate line G4 extending along the second direction Y by its orthogonal projection on the substrate; the fourth gate line G4 can be used to provide control signals to multiple control circuits K corresponding to the same pixel driving circuit group Pivz.

[0181] In this exemplary embodiment, as shown in FIG2, the control circuit may include a ninth transistor T9. The first terminal of the ninth transistor T9 is connected to the gate line Gx, and the second terminal is connected to the gate of the switching transistor Tx. The gate is connected to the fourth gate line G4. The ninth transistor may be a P-type transistor or an N-type transistor.

[0182] In this exemplary embodiment, as shown in FIG2, the fourth gate line G4 connects to multiple control circuits K corresponding to the same pixel driving circuit group Pivz. The fourth gate line G4 is used to provide control signals to the multiple control circuits corresponding to the same pixel driving circuit group. It should be understood that in other exemplary embodiments, the fourth gate line may also connect to control circuits K corresponding to different pixel driving circuit groups Pivz.

[0183] In this exemplary embodiment, as shown in FIG2, the number of pixel driving circuit columns Piv in each pixel driving circuit group Pivz is the same. It should be understood that in other exemplary embodiments, the number of pixel driving circuit columns Piv in at least some pixel driving circuit groups Pivz may be different.

[0184] Figure 3 shows a schematic diagram of another exemplary embodiment of the display panel of this disclosure. The display panel further includes: a shutdown signal line VGL, the shutdown signal line VGL extending along the second direction Y in its orthogonal projection on the substrate, the shutdown signal line VGL being used to provide shutdown signals to a plurality of control circuits K corresponding to the same pixel driving circuit group Pivz, and the control circuit K being able to respond to a control signal to transmit the shutdown signal provided by the shutdown signal line VGL to the gate of its corresponding switching transistor Tx.

[0185] In this exemplary embodiment, as shown in FIG3, the control circuit K may further include a tenth transistor T10. The first terminal of the tenth transistor T10 is connected to the turn-off signal line VGL, and the second terminal is connected to the gate of the switching transistor Tx, the gate being connected to the fourth gate line G4; wherein, the polarity of the turn-on signals of the ninth transistor T9 and the tenth transistor T10 is opposite, for example, the ninth transistor T9 may be a P-type transistor, and the tenth transistor T10 may be an N-type transistor.

[0186] It should be noted that the shutdown signal is the signal that shuts down the target circuit. For example, the shutdown signal for a P-type transistor is a high-level signal, and the shutdown signal for an N-type transistor is a low-level signal. The turn-on signal is the signal that turns on the target circuit. For example, the turn-on signal for a P-type transistor is a low-level signal, and the turn-on signal for an N-type transistor is a high-level signal. Furthermore, the control signal responding to the connection between the gate of the switching transistor Tx and the gate line Gx by the control circuit K, and the control signal responding to the shutdown signal provided by the control circuit K to the gate of the switching transistor Tx, can be provided by the same signal line or by different signal lines. This exemplary embodiment only shows a portion of the pixel driving circuitry of the display panel; this disclosure does not limit the number of pixel driving circuits in the display panel.

[0187] In this exemplary embodiment, as shown in FIG3, the conduction signals of the ninth transistor T9 and the tenth transistor T10 have different polarities; that is, the conduction signals of the ninth transistor T9 and the tenth transistor T10 are one high level and the other low level. It should be understood that in other exemplary embodiments, the conduction signals of the ninth transistor T9 and the tenth transistor T10 may also have the same polarity, and correspondingly, the ninth transistor and the tenth transistor can be turned on and off respectively by two gate lines.

[0188] Figure 4 shows a schematic diagram of another exemplary embodiment of the display panel of this disclosure. The pixel driving circuit may include one or more switching transistors Tx, and one or more switching transistors Tx may include a second transistor T2. The first terminal of the second transistor T2 is connected to the gate of a driving transistor T3, and the second terminal is connected to the second terminal of the driving transistor T3. The same pixel driving circuit may have one or more gate lines, one or more of which include a first gate line G1. The first gate line G1 is used to provide gate driving signals to multiple second transistors T2 in the same pixel driving circuit row.

[0189] This exemplary embodiment can control the driving state of the second transistor T2 in the pixel driving circuit connected to it via the control circuit K. When the control circuit K controls the gate of the second transistor T2 to connect to the first gate line G1, the second transistor T2 normally receives the gate driving signal on the first gate line G1, and the second transistor T2 can write a compensation voltage to the gate of the driving transistor T3 in each frame; when the control circuit K controls the gate of the second transistor T2 to receive a turn-off signal, the second transistor T2 is in the turn-off state, and the second transistor T2 cannot write a compensation voltage to the gate of the driving transistor T3. That is, this exemplary embodiment can adjust the refresh frequency of the pixel driving circuit connected to it via the control circuit K, and multiple control circuits K can adjust the refresh frequency of different areas of the display panel.

[0190] In this exemplary embodiment, as shown in Figures 2-4, the pixel driving circuit group Pivz includes two pixel driving circuit columns Piv. It should be understood that in other exemplary embodiments, the pixel driving circuit group Pivz may also include other numbers of pixel driving circuit columns Piv. For example, Figure 5 shows a schematic diagram of the structure of another exemplary embodiment of the display panel of this disclosure. The pixel driving circuit group Pivz may include four pixel driving circuit columns Piv. Furthermore, in other exemplary embodiments, the pixel driving circuit group Pivz may also include one pixel driving circuit column Piv. Correspondingly, a turn-off signal line and a column of pixel driving circuits are correspondingly arranged. The voltages on each turn-off signal line may be the same or different. For example, the voltage of the turn-off signal line corresponding to the R pixel column (or B pixel column) may be less than the voltage of the turn-off signal line corresponding to the G pixel column. Based on the different turn-on speeds of the light-emitting units in different color pixel units, this arrangement can reduce the power consumption of the display panel while ensuring the display effect.

[0191] Furthermore, in other exemplary embodiments, based on the display panel shown in Figures 2-5, the control circuit may further include a first capacitor. The first electrode of the first capacitor is connected to the constant voltage power supply line, and the second electrode of the first capacitor is connected to the second electrode of the ninth transistor T9. The first capacitor can control the potential of the second electrode of the ninth transistor T9 to remain stable during the time period when the fourth gate line G4 turns off the ninth transistor T9, and can prevent large fluctuations in the voltage of the second electrode of the ninth transistor T9 due to leakage current. The constant voltage power supply line can be a DC signal, for example, it can be one of the first power supply line VDD, an initial signal line (e.g., one of the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3), a turn-off signal line VGL, and a high-voltage power supply line VGH.

[0192] This exemplary embodiment provides a pixel driving circuit, as shown in Figures 6 and 7. Figure 6 is a schematic diagram of the structure of an exemplary embodiment of the pixel driving circuit of this disclosure, and Figure 7 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in Figure 6.

[0193] The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. Specifically, the first terminal of the fourth transistor T4 is connected to the data signal terminal Da, the second terminal of the fourth transistor T4 is connected to the first terminal of the driving transistor T3, and the gate of the fourth transistor T4 is connected to the second gate driving signal terminal G2. The first terminal of the fifth transistor T5 is connected to the first power supply terminal VDD, the second terminal of the fifth transistor T5 is connected to the first terminal of the driving transistor T3, and the gate of the fifth transistor T5 is connected to the enable signal terminal EM. The gate of the driving transistor T3 is connected to node N. The first terminal of the second transistor T2 is connected to node N, the second terminal of the second transistor T2 is connected to the second terminal of the driving transistor T3, and the gate of the second transistor T2 is connected to the first gate driving signal terminal G1. The first terminal of the sixth transistor T6 is connected to the second terminal of the driving transistor T3, and the second terminal of the sixth transistor T6 is connected to the seventh transistor T8. The second electrode of transistor T7 and the gate of the sixth transistor T6 are connected to the enable signal terminal EM. The first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate of the seventh transistor T7 is connected to the second reset signal terminal Re2. The first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, and the second electrode of the first transistor T1 is connected to the second electrode of the driving transistor T3. The gate of the first transistor T1 is connected to the first reset signal terminal Re1. The first electrode of the eighth transistor T8 is connected to the third initial signal terminal Vinit3, and the second electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor T3. The gate of the eighth transistor T8 is connected to the second reset signal terminal Re2. The first electrode of capacitor C is connected to node N, and the second electrode of capacitor C is connected to the first power supply terminal VDD. This pixel driving circuit can be used to drive a light-emitting unit L. The first electrode of the light-emitting unit L can be connected to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting unit can be connected to the second power supply terminal VSS. The first electrode of the light-emitting unit can be the anode of the light-emitting unit, and the second electrode of the light-emitting unit can be the cathode of the light-emitting unit. In this design, the second transistor T2 can be an N-type transistor, such as an N-type metal-oxide-semiconductor transistor. N-type transistors have lower leakage current, which reduces the leakage current through the second transistor T2 at node N during the light-emitting stage. Meanwhile, the first transistor T1, driving transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8 can be P-type transistors, such as P-type low-temperature polysilicon transistors. P-type transistors have higher carrier mobility, which is beneficial for achieving display panels with high resolution, high response speed, high pixel density, and high aperture ratio.The first initial signal terminal, the second initial signal terminal, and the third initial signal terminal can output the same or different voltage signals according to the actual situation.

[0194] The first power line VDD can be used to provide a first power terminal, the first initial signal line Vinit1 can be used to provide a first initial signal terminal, the second initial signal line Vinit2 can be used to provide a second initial signal terminal, and the third initial signal line Vinit3 can be used to provide a third initial signal terminal.

[0195] As shown in Figure 7, G1 represents the timing of the first gate drive signal terminal G1, G2 represents the timing of the second gate drive signal terminal G2, Re2 represents the timing of the second reset signal terminal Re2, Re1 represents the timing of the first reset signal terminal Re1, and EM represents the timing of the enable signal terminal EM. One driving cycle of this pixel driving circuit may include a first reset phase t1, a data writing phase t2, a second reset phase t3, and a light emission phase t4.

[0196] In the first reset phase t1: the first gate drive signal terminal G1 outputs a high level, the first reset signal terminal Re1 outputs a low level signal, the first transistor T1 and the second transistor T2 are turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to node N through the first transistor T1 and the second transistor T2. In the data writing phase t2: the second gate drive signal terminal G2 outputs a low level signal, the first gate drive signal terminal G1 outputs a high level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da writes the compensation voltage Vdata+Vth to node N through the fourth transistor T4 and the second transistor T2, where Vdata is the voltage of the data signal on the data signal terminal, and Vth is the threshold voltage of the driving transistor T3. In the second reset phase t3: the second reset signal terminal Re2 outputs a low level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit L, and the third initial signal terminal Vinit3 inputs the third initial signal to the first electrode of the driving transistor T3. During the light-emitting stage t4: the enable signal terminal EM outputs a low-level signal, turning on the sixth transistor T6 and the fifth transistor T5. This drives the light-emitting unit to emit light under the compensation voltage Vdata + Vth stored in capacitor C, controlled by the driving transistor T3. The formula for the output current of the driving transistor is as follows: I = (μWCox / 2L)(Vgs - Vth) 2

[0197] Where I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the threshold voltage of the driving transistor. In the pixel driving circuit described above, the output current of the driving transistor I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0198] It should be understood that in other exemplary embodiments, the pixel driving circuit Pi may also have other structures. For example, the pixel driving circuit Pi may be the structure shown in FIG6. For another example, based on the pixel driving circuit shown in FIG6, the pixel driving circuit Pi may not include the eighth transistor T8. For yet another example, based on the pixel driving circuit shown in FIG6, the first transistor T1 may be connected to the gate of the driving transistor T3. Correspondingly, the first transistor T1 may also be an N-type transistor.

[0199] It should be understood that, in other exemplary embodiments, the control circuit K is connected to the gate of the switching transistor. As long as the control circuit K can control the switching transistor's on / off state, it can adjust the local refresh rate of the display panel. Correspondingly, the control circuit K can also have other structures and connection methods. For example, the first gate line can be connected to the control terminal of the control circuit, and the fourth gate line can be connected to the input terminal of the control circuit.

[0200] Figure 8 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure. Figure 8 only shows one pixel driving circuit.

[0201] As shown in Figure 8, the pixel driving circuit, based on Figure 6, sets the second transistor T2 as a P-type transistor. The control circuit K may include a ninth transistor T9 and a tenth transistor T10. The first terminal of the ninth transistor T9 is connected to the fourth gate line G4, and the second terminal of the ninth transistor T9 is connected to the gate of the second transistor T2. The gate of the ninth transistor T9 is connected to an additional first gate line G1-1. The first terminal of the tenth transistor T10 is connected to the turn-off signal line, and the second terminal of the tenth transistor T10 is connected to the gate of the second transistor T2. The gate of the tenth transistor T10 is connected to the first gate line G1. Both the ninth transistor T9 and the tenth transistor T10 can be P-type transistors.

[0202] As shown in Figure 8, the turn-off signal line connected to the first terminal of the tenth transistor T10 can be any one of the first power supply line VDD, the third initial signal line Vinit3, or the high-voltage power supply line VGH. The signal provided by the turn-off signal line can be used to turn off the second transistor T2.

[0203] When the signal of the fourth gate line G4 is at the second level (high level), the second transistor T2 is disconnected under the control of the signal of the fourth gate line G4 or the high voltage power supply line VGH, and the pixel driving circuit drives the corresponding light-emitting unit to maintain the original brightness.

[0204] When the signal on the fourth gate line G4 is at the first level (low level), the pixel driving circuit, under the control of the first gate line G1, the additional first gate line G1-1, and the control circuit K, drives the corresponding light-emitting unit to maintain its original brightness or refresh its brightness. The signal polarities on the first gate line G1 and the additional first gate line G1-1 are opposite. The orthographic projections of the first gate line G1 and the additional first gate line G1-1 onto the substrate can extend along a first direction, and the orthographic projection of the fourth gate line G4 onto the substrate can extend along a second direction.

[0205] As shown in Figure 8, when the signal of the fourth gate line G4 is at the first level, and the first gate line G1 is at the first level in the first reset stage and data writing stage of a working frame of the pixel driving circuit, the control circuit provides the signal of the fourth gate line G4 to the gate of the second transistor T2 in the first reset stage and data writing stage of a working frame of the pixel driving circuit. The second transistor T2 is turned on under the control of the signal of the fourth gate line G4, and the pixel driving circuit drives the corresponding light-emitting unit to refresh the brightness in this working frame.

[0206] In this exemplary embodiment, the timing of the signal on the first gate line G1 in FIG8 can be the same as the timing of the first gate line in the display panel shown in FIG2-5.

[0207] When the signal of the fourth gate line G4 is at the first level and the first gate line G1 is at the second level in one working frame of the pixel driving circuit, the control circuit provides the signal of the high voltage power supply line VGH to the gate of the second transistor T2. The second transistor T2 is turned off under the control of the signal of the high voltage power supply line, and the pixel driving circuit drives the corresponding light-emitting unit to maintain the original brightness.

[0208] In this exemplary embodiment, there can be one or more switching transistors. When there are multiple switching transistors, there can also be multiple control circuits. The control circuits and switching transistors are configured accordingly, and the control circuits are used to control the on / off state of their corresponding switching transistors.

[0209] For example, Figure 9 shows a schematic diagram of another exemplary embodiment of the display panel of this disclosure. The pixel driving circuit in this display panel includes a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, an eleventh transistor T11, a first capacitor C11, and a second capacitor C12. Specifically, the first terminal of the fourth transistor T4 is connected to the data signal terminal Da, and the second terminal of the fourth transistor T4 is connected to the first terminal of the driving transistor T3; the first terminal of the fifth transistor T5 is connected to the first power supply terminal VDD, and the second terminal of the fifth transistor T5 is connected to the first terminal of the driving transistor T3, with its gate connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to the first node N1; the first terminal of the second transistor T2 is connected to the first node N1, and the second terminal of the second transistor T2 is connected to the second terminal of the driving transistor T3; the first terminal of the sixth transistor T6 is connected to the second terminal of the driving transistor T3, and the second terminal of the sixth transistor T6 is connected to the second terminal of the seventh transistor T7, with its gate connected to the enable signal terminal EM; the first terminal of the seventh transistor T7 is connected to... The second initial signal terminal Vinit2 is connected to the second initial signal terminal, and the gate of the seventh transistor T7 is connected to the second reset signal terminal Re2. The first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, and the second electrode of the first transistor T1 is connected to the first node N1. The first electrode of the eighth transistor T8 is connected to the third initial signal terminal Vinit3, and the second electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor T3. The gate of the eighth transistor T8 is connected to the second reset signal terminal Re2. The first electrode of the eleventh transistor T11 is connected to the reference voltage terminal Vref, and the second electrode of the eleventh transistor T11 is connected to the sixth node N6. The first capacitor C11 is connected between the sixth node N6 and the first power supply terminal VDD. The second capacitor C12 is connected between the sixth node N6 and the first node N1. This pixel driving circuit can be used to drive a light-emitting unit L. The first electrode of the light-emitting unit L can be connected to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting unit can be connected to the second power supply terminal VSS. The first electrode of the light-emitting unit can be the anode of the light-emitting unit, and the second electrode of the light-emitting unit can be the cathode of the light-emitting unit. The second transistor T2 can be an N-type transistor, for example, an N-type metal-oxide transistor. N-type transistors have a smaller leakage current, which can reduce the leakage current of the first node N1 through the second transistor T2 during the light-emitting stage.Meanwhile, the first transistor T1, driving transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, eighth transistor T8, and eleventh transistor T11 can be P-type transistors. For example, driving transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, eighth transistor T8, and eleventh transistor T11 can be P-type low-temperature polysilicon transistors. P-type transistors have higher carrier mobility, which is beneficial for achieving display panels with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal, second initial signal terminal, and third initial signal terminal can output the same or different voltage signals according to actual conditions.

[0210] In this exemplary embodiment, as shown in FIG9, a driving cycle of the pixel driving circuit may include a first reset stage, a threshold compensation stage, a data writing stage, and a light emission stage.

[0211] In the first reset phase: the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the gate of the driving transistor T3 through the first transistor T1; in the threshold compensation phase: the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, and at the same time the second transistor T2 is turned on, the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit L, and the third initial signal terminal Vinit3 inputs the compensation voltage V3+Vth to the first node N1 through the driving transistor T3 and the second transistor T2, where Vth is the threshold voltage of the driving transistor T3 and V3 is the third initial voltage. During the signal terminal Vinit3 voltage, the eleventh transistor T11 is turned on, and the reference power supply terminal Vref inputs the reference voltage Vf to the sixth node N6; during the data writing stage: the fourth transistor T4 is turned on, and the data signal terminal Da inputs the data signal to the sixth node N6 through the fourth transistor T4. The voltage of the sixth node N6 changes from Vf to Vdata. Under the coupling effect of the second capacitor C12, the voltage of the first node becomes V3+Vth+Vdata-Vf; during the light emission stage: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light emission unit L to emit light under the action of the first node.

[0212] The formula for the output current of the driving transistor is as follows: I=(μWCox / 2L)(Vgs-Vth) 2

[0213] Where I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the threshold voltage of the driving transistor. In the pixel driving circuit described above, the output current of the driving transistor I = (μWCox / 2L)(V3 + Vth + Vdata - Vf - Vth) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. It should be understood that the pixel driving circuit shown in Figure 9 can also be driven by other methods.

[0214] In this exemplary embodiment, as shown in FIG9, the plurality of switching transistors include a first transistor T1, a second transistor T2, a fourth transistor T4, and an eleventh transistor T11, and the plurality of control circuits may include a first control circuit 601 to a fourth control circuit 604. The gate of the first transistor T1 is connected to the first control circuit 601, the gate of the second transistor T2 is connected to the second control circuit 602, the gate of the fourth transistor T4 is connected to the third control circuit 603, and the gate of the eleventh transistor T11 is connected to the fourth control circuit 604. The structure of the first control circuit 601 to the fourth control circuit 604 can be the structure of the control circuit described in any of the above embodiments, and the circuit structures of the first control circuit 601 to the fourth control circuit 604 can be the same or different. In an exemplary embodiment, the first control circuit 601 to the fourth control circuit 604 can be the same control circuit connected to the control electrodes of the first transistor T1, the second transistor T2, the fourth transistor T4, and the eleventh transistor T11, respectively.

[0215] For example, as shown in Figure 10, which is a schematic diagram of another exemplary embodiment of the display panel of this disclosure, the plurality of control circuits may include a first control circuit 601 to a third control circuit 603. The pixel driving circuit Pi may include a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, and a capacitor C. The first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 may be P-type transistors, and the driving transistor T3 may be an N-type transistor.

[0216] In this exemplary embodiment, as shown in FIG10, the driving method of the pixel driving circuit may include a reset phase, a data writing phase, and a light-emitting phase. In the reset phase: the first transistor T1 and the second transistor T2 are turned on, the first low-voltage power supply line VSS1 inputs a first low-level signal to the third node N3 through the first transistor T1, and the second low-voltage power supply line VSS2 inputs a second low-level signal to the first node N1 through the second transistor T2; in the data writing phase: the fourth transistor T4 is turned on, and the data line Da inputs a data signal to the first node N1 through the fourth transistor T4; in the light-emitting phase: the fifth transistor T5 is turned on, and the driving transistor T3 drives the light-emitting unit L to emit light under the action of the data signal on the first node N1. It should be understood that in other exemplary embodiments, the pixel driving circuit may also have other driving methods.

[0217] In this exemplary embodiment, as shown in FIG10, the plurality of switching transistors include a first transistor T1, a second transistor T2, and a fourth transistor T4. The gate of the first transistor T1 is connected to the first control circuit 601, the first terminal of the first transistor T1 is connected to the first low-voltage power supply line VSS1, and the second terminal of the first transistor T1 is connected to the third node N3. The gate of the second transistor T2 is connected to the second control circuit 602, the first terminal of the second transistor T2 is connected to the second low-voltage power supply line VSS2, and the second terminal of the second transistor T2 is connected to the first node N1. The gate of the driving transistor is connected to the first node N1. N1 is connected; the first terminal of the driving transistor is connected to the second node N2, and the second terminal of the driving transistor is connected to the third node N3; the gate of the fourth transistor T4 is connected to the third control circuit 603; the first terminal of the fourth transistor T4 is connected to the data line Da, and the second terminal of the fourth transistor T4 is connected to the first node N1; the gate of the fifth transistor T5 is connected to the enable signal line EM; the first terminal of the fifth transistor T5 is connected to the first power supply line VDD, and the second terminal of the fifth transistor T5 is connected to the second node N2; the first electrode of capacitor C is connected to the first node N1, and the second electrode of capacitor C is connected to the third node N3. The structure of the first control circuit 601 to the third control circuit 603 can be the structure of the control circuit described in any of the above embodiments, and the circuit structures of the first control circuit 601 to the third control circuit 603 can be the same or different; in an exemplary embodiment, the first control circuit 601 to the third control circuit 603 can be the same control circuit connected to the gates of the first transistor T1, the second transistor T2, and the fourth transistor T4 respectively. As can be seen from the above, the threshold compensation of the gate of the driving transistor T3 can be controlled by controlling the gate of the transistor connected to the driving transistor T3 in the pixel driving circuit Pi, thereby controlling the refresh of pixels in a local area of ​​the display panel.

[0218] For example, as shown in Figure 10, in this embodiment of the present disclosure, a light-emitting control transistor can be added between the N3 node and the anode of the light-emitting unit, thereby isolating the influence of the voltage of the N3 node on the anode of the light-emitting unit before light emission. Other working processes are the same as those in the above embodiments, and will not be repeated here.

[0219] Figure 11 shows a schematic diagram of another exemplary embodiment of the display panel of this disclosure. Figure 11 illustrates the adjustment method of the local refresh rate of the display panel using nine display areas as an example. The display panel includes nine display areas P1-P9. Each display area includes multiple pixel driving circuits located in the same pixel driving circuit group and in the same pixel driving circuit row. For example, each display area may include one row and four columns of pixel driving circuits, and a control circuit is correspondingly provided in each display area. Accordingly, the display panel may be provided with three fourth gate lines G41, G42, and G43, and three first gate lines G11, G12, and G13.

[0220] The fourth gate line G41 controls the on / off state of the ninth transistor T9 in display areas P1, P4, and P7 along the column direction; the fourth gate line G42 controls the on / off state of the ninth transistor T9 in display areas P2, P5, and P8 along the column direction; and the fourth gate line G43 controls the on / off state of the ninth transistor T9 in display areas P3, P6, and P9 along the column direction. If the fourth gate lines G41 and G43 control the ninth transistor T9 in display areas P1, P4, P7, P3, P6, and P9 to be off, then the second transistor T2 in display areas P1, P4, P7, P3, P6, and P9 will be off. At this time, regardless of whether the first gate lines G11, G12, and G13 in display areas P1, P4, P7, P3, P6, and P9 output on or off signals, display areas P1, P4, P7, P3, P6, and P9 will not refresh, and the corresponding display areas P1, P4, P7, P3, P6, and P9 can achieve low-frequency display. If the fourth gate line G42 controls the ninth transistor T9 in display areas P2, P5, and P8 to turn on, then the second transistor T2 in display areas P2, P5, and P8 can receive signals from the first gate lines G11, G12, and G13 to control pixel scanning. At this time, the refresh frequency of display areas P2, P5, and P8 can be controlled by controlling the frequency of the gate drive signals output by the first gate lines G11, G12, and G13. For example, if the first gate line G11 outputs a valid level every frame, then display area P2 will refresh every frame; if the first gate line G12 outputs a valid level every three frames, then display area P5 will refresh every three frames. This method controls the refresh frequency of different display areas by controlling the frequency of the valid levels output by the fourth and first gate lines.

[0221] The display panel can also control the refresh rate of local areas through other driving methods. For example, the frequency of the effective level output of each first gate line can be the same. When the display panel scans each row of pixel driving circuits, the fourth gate line can select the on / off state of the ninth transistor T9 in the control circuit connected to it, so as to control whether the pixel driving circuits of different areas write data signals. For example, during the scanning of display areas P1, P2, and P3, the fourth gate line G41 can control the ninth transistor in display area P1 to turn on, the fourth gate line G42 can control the ninth transistor in display area P2 to turn on, and the fourth gate line G43 can control the ninth transistor in display area P3 to turn off, thereby controlling the refresh of display areas P1 and P2, while display area P3 does not refresh; during the scanning of display areas P4, P5, and P6, the fourth gate line G41 can control the ninth transistor in display area P4 to turn off, the fourth gate line G42 can control the ninth transistor in display area P5 to turn on, and the fourth gate line G43 can control the ninth transistor in display area P6 to turn off, thereby controlling the refresh of display area P5, while display areas P4 and P6 do not refresh.

[0222] The pixel driving circuit and control circuit in Figure 11 can be any of the pixel driving circuits and control circuits mentioned above. VGL / VGH in Figure 11 can be the shutdown signal line VGL in Figure 4 or the high-voltage power supply line VGH in Figure 8.

[0223] Furthermore, the voltage of the low-level constant voltage signal in the low-frequency display area can be greater than the voltage of the same low-level constant voltage signal in the high-frequency display area; the voltage of the high-level constant voltage signal in the low-frequency display area can be less than the voltage of the same high-level constant voltage signal in the high-frequency display area. This setting can further reduce the power consumption of the display panel. The low-level constant voltage signal may include signals on the first initial signal line Vinit1, the second initial signal line Vinit2, the second power supply terminal VSS, and the turn-off signal line VGL; the high-level constant voltage signal may include signals on the third initial signal line Vinit3, the first power supply line VDD, and the high-voltage power supply line VGH. The first initial signal line Vinit1 is used to provide the first initial signal terminal, the second initial signal line Vinit2 is used to provide the second initial signal terminal, the third initial signal line Vinit3 is used to provide the third initial signal terminal, and the first power supply line VDD is used to provide the first power supply terminal.

[0224] In this exemplary embodiment, the shutdown signal line VGL can be configured to correspond to one column of pixel driving circuits or multiple columns of pixel driving circuits. The switching transistor Tx can be an N-type transistor, and the shutdown signal line VGL can share a signal line with other signal lines in the display panel. For example, the first initial signal line Vinit1, the second initial signal line Vinit2, and the low-level power line VSS in the display panel can all be multiplexed as the shutdown signal line VGL. The low-level power line VSS is used to provide a second power supply terminal.

[0225] It should be understood that in other exemplary embodiments, the switching transistor Tx can also be a P-type transistor, and correspondingly, the turn-off signal line is a high-level power supply signal line, and the first power supply line VDD in the display panel can be multiplexed as the turn-off signal line. Similarly, the voltages on each turn-off signal line can be the same or different; for example, the voltage on the turn-off signal line corresponding to the R pixel column (or G pixel column) can be less than the voltage on the turn-off signal line corresponding to the B pixel column. This can further save power consumption.

[0226] This exemplary embodiment also provides a display panel, which may include a substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source / drain layer, a second source / drain layer, and a third source / drain layer stacked sequentially. An insulating layer may be disposed between adjacent layers. As shown in Figures 12-28, Figure 12 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure; Figure 13 is a structural layout diagram of the shielding layer in Figure 12; Figure 14 is a structural layout diagram of the first active layer in Figure 12; Figure 15 is a structural layout diagram of the first gate layer in Figure 12; Figure 16 is a structural layout diagram of the second gate layer in Figure 12; Figure 17 is a structural layout diagram of the second active layer in Figure 12; Figure 18 is a structural layout diagram of the third gate layer in Figure 12; Figure 19 is a structural layout diagram of the first source / drain layer in Figure 12; Figure 20 is a structural layout diagram of the second source / drain layer in Figure 12; Figure 21 is a structural layout diagram of the third source / drain layer in Figure 12; Figure 22 is a structural layout diagram of the shielding layer and the first active layer in Figure 12; Figure 23 is a structural layout diagram of the shielding layer and the first active layer in Figure 12. Figure 24 shows the structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in Figure 12. Figure 25 shows the structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in Figure 12. Figure 26 shows the structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in Figure 12. Figure 27 shows the structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in Figure 12. Figure 28 shows the structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, and the second source / drain layer in Figure 12.

[0227] The difference between this display panel and the display panel shown in Figure 5 is that the pixel driving circuit in this display panel is shown in Figure 6.

[0228] As shown in Figure 12, in this exemplary embodiment, the pixel driving circuit group Pivz may include two pixel driving circuit subgroups Pivz1; in the corresponding pixel driving circuit group Pivz and the control circuit K, the orthographic projection of the control circuit K on the substrate is located between the orthographic projections of the two pixel driving circuit subgroups Pivz1 on the substrate. As shown in Figure 12, each pixel driving circuit subgroup Pivz1 includes two pixel driving circuit columns Piv. It should be understood that in other exemplary embodiments, the number of pixel driving circuit columns Piv in each pixel driving circuit subgroup Pivz1 may be the same or different.

[0229] As shown in Figures 12, 13, and 22, the shielding layer includes multiple shielding portions 81 distributed in an array along the first direction X and the second direction Y, and the shielding portions 81 are interconnected.

[0230] As shown in Figures 6, 8, 16, and 17, the first active layer may include: a first active section 71, a third active section 73, a fourth active section 74, a fifth active section 75, a sixth active section 76, a seventh active section 77, an eighth active section 78, a ninth active section 79, an eleventh active section 711, a twelfth active section 712, a thirteenth active section 713, a fourteenth active section 714, a fifteenth active section 715, a sixteenth active section 716, a seventeenth active section 717, an eighteenth active section 718, a nineteenth active section 719, a twentieth active section 720, a twenty-first active section 721, and a twenty-second active section 722. The first active portion 71 is used to form the channel region of the first transistor T1; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the ninth active portion 79 can be used to form the channel region of the ninth transistor T9; the twenty-second active portion 722 and the twelfth active portion 712 are connected to the two ends of the eighth active portion 78. In the same pixel driving circuit subgroup, adjacent pixel driving circuits in the first direction X can share the same twelfth active portion 712; the eleventh active portion 711 is connected between the fourth active portion 74 and the third active portion 73; the thirteenth active portion 713 is connected to... The fourth active part 74 is located on the side away from the third active part 73; the fourteenth active part 714 is connected to the seventh active part 77 on the side away from the sixth active part 76; the fifteenth active part 715 is connected to the fifth active part 75 on the side away from the third active part 73; the sixteenth active part 716 is connected between the seventh active part 77 and the sixth active part 76; the seventeenth active part 717 and the eighteenth active part 718 are connected to the two ends of the first active part 71, and the pixel driving circuits located in adjacent pixel driving circuit groups Pivz and adjacent in the first direction can share the same eighteenth active part 718. In the same pixel driving circuit group Pivz, the eighteenth active parts 718 adjacent in the first direction X in two adjacent pixel driving circuit subgroups Pivz1 can be arranged at intervals; the nineteenth active part 719 is connected between the third active part 73 and the sixth active part 76; the twentieth active part 720 and the twenty-first active part 721 are connected to the two ends of the ninth active part 79. The first active layer can be formed of polycrystalline silicon material. Correspondingly, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be P-type low-temperature polycrystalline silicon thin-film transistors.

[0231] The orthographic projection of the shielding portion 81 on the substrate can at least partially overlap with the orthographic projection of the third active portion 73 on the substrate. The shielding portion 81 can block light from the third active portion 73 to improve the stability of the output characteristics of the driving transistor. The shielding layer can be a conductive structure, and the shielding layer can be connected to a stable voltage source. The shielding layer can also act as a signal shield for the pixel driving circuit.

[0232] As shown in Figures 12, 14, 22, and 23, the first gate layer may include: a first conductive portion 11, a second conductive portion 12, a second gate line G2, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal in Figure 6; the enable signal line EM can be used to provide the enable signal terminal in Figure 6; the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 6; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 6. The orthographic projections of the second gate line G2, the enable signal line EM, the first reset signal line Re1, and the second reset signal line Re2 on the substrate can all extend along the first direction X. The orthographic projection of the second gate line G2 on the substrate covers the orthographic projection of the fourth active portion 74 on the substrate, and a portion of the structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM onto the substrate covers the orthographic projections of the fifth active portion 75 and the sixth active portion 76 onto the substrate. A portion of the structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 onto the substrate covers the orthographic projection of the first active portion 71 onto the substrate. A portion of the structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 onto the substrate covers the orthographic projections of the seventh active portion 77 and the eighth active portion 78 onto the substrate. A portion of the structure of the first reset signal line Re1 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 onto the substrate covers the orthographic projection of the third active portion 73 onto the substrate. The first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The orthographic projection of the second conductive portion 12 on the substrate covers the orthographic projection of the ninth active portion 79 on the substrate. The second conductive portion 12 can be used to form the gate of the ninth transistor T9. The display panel can use the first gate layer as a mask to perform a conductor treatment on the first active layer, that is, the area of ​​the first active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first gate layer forms a conductor structure.

[0233] As shown in Figures 12, 15, and 24, the second gate layer may include: a first gate line G1, a third gate line G3, a third conductive portion 23, and a fourth conductive portion 24. The third gate line G3 includes third gate line segments G31 extending along the first direction X and spaced apart along the first direction X. The third gate line segments G31 are correspondingly disposed with the pixel driving circuit group Pivz. A portion of the structure of the third gate line segment G31 is used to form the bottom gate of the second transistor in the corresponding pixel driving circuit group. The control circuit can be connected to the gate of its corresponding second transistor through the third gate line segment G31. The first gate line G1 includes first gate line segments G11 extending along the first direction X and spaced apart along the first direction X. The first gate line G1 can be used to provide the first gate driving signal terminal in Figure 6. The orthographic projection of the third conductive portion 23 on the substrate may at least partially overlap with the orthographic projection of the first conductive portion 11 on the substrate. The third conductive portion 23 can be used to form the second electrode of the capacitor C.

[0234] As shown in Figures 12, 15, and 24, in the same pixel driving circuit subgroup Pivz1, adjacent third conductive parts 23 in the first direction X can be connected to each other through the first connecting part 21; adjacent third conductive parts 23 in the first direction X but located in different pixel driving circuit subgroups Pivz1 can be arranged at intervals.

[0235] As shown in Figures 12, 16, and 25, the second active layer may include a second active portion 92, a twenty-third active portion 923, a twenty-fourth active portion 924, a tenth active portion 910, a twenty-fifth active portion 925, and a twenty-sixth active portion 926. The twenty-third active portion 923 and the twenty-fourth active portion 924 are connected to the two ends of the second active portion 92; the twenty-fifth active portion 925 and the twenty-sixth active portion 926 are connected to the two ends of the tenth active portion 910. The second active portion 92 is used to form the channel region of the second transistor T2. The tenth active portion 910 is used to form the channel region of the tenth transistor T10. The second active layer may be formed of indium gallium zinc oxide (IGaZn), and correspondingly, the second transistor T2 and the tenth transistor T10 may be N-type metal-oxide thin-film transistors. The orthogonal projection of the third gate line G3 onto the substrate may cover the orthogonal projection of the second active portion 92 onto the substrate, and a portion of the structure of the third gate line G3 may be used to form the bottom gate of the second transistor T2. The orthographic projection of the fourth conductive portion 24 on the substrate covers the orthographic projection of the tenth active portion 910 on the substrate, and at least a portion of the fourth conductive portion 24 can be used to form the bottom gate of the tenth transistor T10.

[0236] As shown in Figures 12, 17, and 26, the third gate layer may include a fifth gate line G5, a first initial signal line Vinit1, a second initial signal line Vinit2, a third initial signal line Vinit3, and a sixth conductive portion 36. The fifth gate line G5 includes fifth gate line segments G51 extending along the first direction X and spaced apart along the first direction X. The fifth gate line segments G51 and the pixel driving circuit group Pivz are correspondingly disposed. The orthographic projection of the fifth gate line segments G51 on the substrate covers the orthographic projection of the second active portion 92 on the substrate. A portion of the structure of the fifth gate line segments G51 is used to form the gate of the second transistor located in the same pixel driving circuit row in the corresponding pixel driving circuit group. The control circuit K can be connected to the gate of its corresponding second transistor through the fifth gate segment G51. The orthographic projections of the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 on the substrate can all extend along the first direction X. The first initial signal line Vinit1 can be used to provide the first initial signal terminal in FIG. 6, the second initial signal line Vinit2 can be used to provide the second initial signal terminal in FIG. 6, and the third initial signal line Vinit3 can be used to provide the third initial signal terminal in FIG. 6. The orthographic projection of the first initial signal line Vinit1 on the substrate can at least partially coincide with the orthographic projection of the second reset signal line Re2 in the adjacent previous row pixel driving circuit on the substrate. The orthographic projection of the second initial signal line Vinit2 on the substrate can at least partially coincide with the orthographic projection of the first reset signal line Re1 in the adjacent next row pixel driving circuit on the substrate. The orthographic projection of the third initial signal line Vinit3 on the substrate at least partially coincides with the orthographic projection of the enable signal line EM in the current row pixel driving circuit on the substrate. This arrangement can improve the light transmittance and integration of the display panel. The orthographic projection of the sixth conductive part 36 on the substrate covers the orthographic projection of the tenth active part 910 on the substrate. At least a portion of the structure of the sixth conductive part 36 is used to form the top gate of the tenth transistor T10.

[0237] Furthermore, the display panel can use the third gate layer as a mask to conduct the second active layer, that is, the area of ​​the second active layer covered by the third gate layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third gate layer forms a conductor structure.

[0238] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in other conductive layers. For example, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in the second gate layer, the first source / drain layer, etc.

[0239] As shown in Figures 12, 18, and 27, the first source / drain layer may include a first bridging portion 41, a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, a fifth bridging portion 45, a sixth bridging portion 46, a seventh bridging portion 47, an eighth bridging portion 48, a ninth bridging portion 49, a tenth bridging portion 410, an eleventh bridging portion 411, a twelfth bridging portion 412, an eighteenth bridging portion 418, and a turn-off signal connection line 4VL. The first bridging portion 41 can be connected to the twenty-fourth active portion 924 and the first conductive portion 11 respectively through vias to connect the gate of the driving transistor T3 and the first electrode of the second transistor T2. An opening 231 may be formed on the third conductive portion 23, and a via connecting the first bridging portion 41 and the first conductive portion 11 is disposed through the opening 231. The second bridging portion 42 connects to the second conductive portion 12, the fourth conductive portion 24, and the sixth conductive portion 36 via vias to connect the gates of the ninth transistor T9 and the tenth transistor T10. The third bridging portion 43 connects to the first connecting portion 21 and the fifteenth active portion 715 via vias to connect the second electrode of capacitor C and the first electrode of the fifth transistor T5. The fourth bridging portion 44 connects to the eleventh active portion 711 and the twenty-second active portion 722 via vias to connect the second electrode of the eighth transistor T8 and the first electrode of the driving transistor T3. The fifth bridging portion 45 connects to the third initial signal line Vinit3 and the twelfth active portion 712 via vias to connect the first electrode of the eighth transistor and the third initial signal line Vinit3. The sixth bridging portion 46 connects to the thirteenth active portion 713 via vias to connect the first electrode of the fourth transistor T4. The seventh bridging section 47 can be connected via vias to the nineteenth active section 719, the twenty-third active section 923, and the seventeenth active section 717 to connect the second terminals of the first transistor T1, the second transistor T2, and the driving transistor T3. The eighth bridging section 48 can be connected vias to the eighteenth active section 718 and the first initial signal line Vinit1 to connect the first terminal of the first transistor T1 and the first initial signal terminal. The ninth bridging section 49 can be connected via vias to the fourteenth active section 714 and the second initial signal line Vinit2 to connect the first terminal of the seventh transistor T7 and the second initial signal line. The tenth bridging section 410 can be connected via vias to the sixteenth active section 716 to connect the second terminal of the seventh transistor T7 and the second terminal of the sixth transistor T6. The eleventh bridging section 411 can be connected via vias to the twenty-sixth active section 926 to connect the first terminal of the tenth transistor T10. The orthographic projection of the off signal connection line 4VL on the substrate extends along the first direction X. The off signal connection line 4VL and the eleventh bridging portion 411 are connected in the same layer. The orthographic projection of the off signal connection line 4VL on the substrate can at least partially overlap with the orthographic projection of the first gate line G1 on the substrate, thereby improving the integration of the display panel.The twelfth bridging section 412 can be connected via vias to the twentieth active section 720, the fifth gate line segment G51, the third gate line segment G31, and the twenty-fifth active section 925, respectively, to connect the second terminal of the ninth transistor T9, the second terminal of the tenth transistor T10, and the gate of the second transistor T2. The eighteenth bridging section 418 can be connected via vias to two adjacent first gate line segments G1 and the twenty-first active section 721 in the first direction X, respectively, to connect the first terminal of the ninth transistor T9 and the first gate line G1.

[0240] In this exemplary embodiment, the first gate segments G11 are spaced apart, and the twenty-first active part 721 can be located in the gap between two adjacent first gate segments G11 in the first direction X, so that the eighteenth bridging part 418 can bridge the twenty-first active part 721 and the first gate segments G11.

[0241] As shown in Figures 12, 19, and 28, the second source / drain layer may include: a fifth conductive portion 55, a thirteenth bridging portion 513, a fourteenth bridging portion 514, a fourth gate line G4, and a turn-off signal line VGL. The fifth conductive portion 55 can be connected to the third bridging portion 43 via a via to connect to the first terminal of the fifth transistor T5. In the same pixel driving circuit group Pivz, the orthographic projections of the fifth conductive portions 55 located in different pixel driving circuit subgroups and adjacent in the first direction X are spaced apart on the substrate, and other adjacent fifth conductive portions 55 in the first direction X can be interconnected. The orthographic projection of the fifth conductive portion 55 on the substrate can at least partially overlap with the orthographic projection of the second active portion 92 on the substrate; for example, the orthographic projection of the fifth conductive portion 55 on the substrate can cover the orthographic projection of the second active portion 92 on the substrate. The fifth conductive portion 55 can shield the second active portion 92 to reduce the influence of light on the characteristics of the second transistor T2. The orthographic projection of the fifth conductive portion 55 on the substrate can at least partially overlap with the orthographic projection of the first bridging portion 41 on the substrate. For example, the orthographic projection of the fifth conductive portion 55 on the substrate can cover the orthographic projection of the first bridging portion 41 on the substrate. The fifth conductive portion 55 can shield the interference of other signals to the first bridging portion 41, thereby improving the voltage stability of the driving transistor gate.

[0242] The thirteenth bridge section 513 can be connected to the tenth bridge section 410 via a via to connect to the second terminal of the sixth transistor T6. The fourteenth bridge section 514 can be connected to the sixth bridge section 46 via a via to connect to the first terminal of the fourth transistor T4.

[0243] The orthographic projection of the fourth gate line G4 on the substrate and the orthographic projection of the turn-off signal line VGL on the substrate can extend along the second direction Y. The fourth gate line G4 can be connected to the second bridging portion 42 via a via to connect to the gates of the ninth transistor T9 and the tenth transistor T10. The turn-off signal line VGL can be connected to the eleventh bridging portion 411 via a via to connect to the first terminal of the tenth transistor T10. The turn-off signal line VGL and the turn-off signal connection line 4VL can form a mesh structure. The mesh structure of the turn-off signal line VGL has a smaller resistance, thereby improving the uniformity of the voltage of the turn-off signal line VGL at different positions on the display panel, and thus improving the uniformity of the display panel display.

[0244] As shown in Figures 12, 18, 19, and 28, the second bridging portion 42 may include a first sub-bridging portion 421 and a second sub-bridging portion 423. The orthographic projection of the first sub-bridging portion 421 on the substrate extends along the second direction Y, and the orthographic projection of the second sub-bridging portion 423 on the substrate extends along the first direction X. The first sub-bridging portion 421 is connected to the second conductive portion 12 through a via, and the second sub-bridging portion 423 is connected to the fourth conductive portion 24 and the sixth conductive portion 36 through vias, respectively. The orthographic projection of the first sub-bridging portion 421 on the substrate and the orthographic projection of the turn-off signal line VGL on the substrate are located on opposite sides of the orthographic projection of the fourth gate line G4 on the substrate. In contrast, the orthographic projection of the first sub-bridging portion 421 on the substrate is located between the orthographic projection of the turn-off signal line VGL and the orthographic projection of the fourth gate line G4 on the substrate. This arrangement can reduce the parasitic capacitance between the fourth gate line G4, the turn-off signal line VGL, and the first sub-bridging portion 421.

[0245] As shown in Figures 12, 18, 19, and 28, the turn-off signal connection line 4VL can be connected through the seventeenth bridging portion 417 and the eleventh bridging portion 411. The orthographic projection of the seventeenth bridging portion 417 on the substrate can extend along the second direction Y, and the orthographic projection of the seventeenth bridging portion 417 on the substrate can at least partially overlap with the orthographic projection of the fourth gate line G4 on the substrate. For example, the orthographic projection of the fourth gate line G4 on the substrate can cover the orthographic projection of the seventeenth bridging portion 417 on the substrate. The seventeenth bridging portion 417 can shield the interference of the fourth gate line G4 to the signal nodes in the pixel driving circuit.

[0246] As shown in Figures 12 and 20, the third source / drain layer may include: a data line Da, a first power line VDD, a fifteenth bridging portion 615, and a sixteenth bridging portion 616. The orthographic projections of the data line Da and the first power line VDD on the substrate can extend along the second direction Y. The data line Da is used to provide the data signal terminal in Figure 6, and the first power line VDD is used to provide the first power terminal in Figure 6. The data line Da can be connected to the fourteenth bridging portion 514 through a via to connect the data signal terminal and the first terminal of the fourth transistor. There can be multiple first power lines VDD, and the orthographic projections of the multiple first power lines VDD on the substrate extend along the second direction Y and are spaced apart along the first direction X. One first power line VDD can be provided for each of two adjacent pixel driving circuit columns. The first power line VDD can be connected to the fifth conductive portion 55, which intersects with its orthographic projection on the substrate, through a via. In the same pixel driving circuit group Pivz, the first power line VDD may not be provided on two adjacent pixel driving circuit columns located in different pixel driving circuit subgroups. In the same pixel driving circuit group Pivz, the fifth conductive part 55 located in different pixel driving circuit subgroups and adjacent in the first direction X can be bridged by the sixteenth bridging part 616. The fifteenth bridging part 615 can be connected to the thirteenth bridging part 513 through a via.

[0247] As shown in Figures 12 and 20, the orthographic projection of the sixteenth bridging portion 616 on the substrate and the orthographic projection of the tenth active portion 910 on the substrate at least partially overlap. For example, the orthographic projection of the sixteenth bridging portion 616 on the substrate may cover the orthographic projection of the tenth active portion 910 on the substrate. The sixteenth bridging portion 616 can shield the tenth active portion 910 from light to reduce the influence of light on the characteristics of the tenth transistor T10.

[0248] As shown in Figures 12 and 20, the first power line VDD can be connected via a via to the fifth conductive portion 55, which intersects with its orthographic projection on the substrate. The first power line VDD, the fifth conductive portion 55, and the third conductive portion 23 can form a grid structure. This arrangement can reduce the voltage difference of the first power line at different locations on the display panel, thereby improving the uniformity of the display panel.

[0249] It should be understood that in other exemplary embodiments, the first gate segment G1 can be continuously arranged. For example, as shown in Figures 29-32, Figure 29 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in another exemplary embodiment of the display panel of this disclosure; Figure 30 is a structural layout of the first active layer in the display panel shown in Figure 29; Figure 31 is a structural layout of the shielding layer, the first active layer, and the first gate layer in the display panel shown in Figure 29; and Figure 32 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 29.

[0250] The display panel shown in Figure 29 differs from the display panel shown in Figure 12 in that the twenty-first active part 721 is located on one side of the ninth active part 79 in the first direction X. The orthographic projection of the twenty-first active part 721 on the substrate is located on the side where the orthographic projection of the first gate line G1 on the substrate is in the second direction Y. This arrangement allows the via between the eighteenth bridging part 418 and the first gate line G1 to be misaligned with the via between the eighteenth bridging part 418 and the twenty-first active part 721 in the second direction Y, so that the first gate line G1 can be continuously arranged in the first direction X.

[0251] In addition, the first gate segment G1 can also be located in other conductive layers, for example, the first gate segment G1 can be located in the third gate layer, the first source / drain layer, etc.

[0252] It should be noted that the other structures of the display panel shown in Figure 29 and the display panel shown in Figure 12 can be the same.

[0253] Figure 33 shows a partial cross-sectional view of the display panel shown in Figure 12, cut along the dashed line AA. The display panel may further include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, a first planarization layer 108, and a second planarization layer 109. The substrate 100, shielding layer, buffer layer 101, first active layer, second insulating layer 102, first gate layer, third insulating layer 103, second gate layer, fourth insulating layer 104, second active layer, fifth insulating layer 105, third gate layer, first dielectric layer 106, first source / drain layer, passivation layer 107, first planarization layer 108, second source / drain layer, second planarization layer 109, and third source / drain layer are sequentially stacked. The buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be single-layer or multi-layer structures, and the materials of the buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 106 can be a silicon nitride layer; the materials of the first planarization layer 108 and the second planarization layer 109 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The passivation layer 107 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer, second gate layer, and third gate layer can be molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacked conductive layers. The materials of the first source / drain layer, second source / drain layer, and third source / drain layer can include metallic materials, for example, molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacked layers, or titanium / aluminum / titanium stacked conductive layers. The sheet resistance of any one of the first source / drain layer, second source / drain layer, and third source / drain layer can be less than the sheet resistance of any one of the first gate layer, second gate layer, and third gate layer.

[0254] This exemplary embodiment also provides a structural layout of another exemplary embodiment, wherein the display panel may include a substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source / drain layer, a second source / drain layer, and a third source / drain layer stacked sequentially. An insulating layer may be disposed between adjacent layers. As shown in Figures 34-41, Figure 34 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, Figure 35 is a structural layout diagram of the first gate layer in the display panel shown in Figure 34, Figure 36 is a structural layout diagram of the second gate layer in the display panel shown in Figure 34, Figure 37 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 34, Figure 38 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 34, Figure 39 is a structural layout diagram of the shielding layer, the first active layer, and the first gate layer in the display panel shown in Figure 34, Figure 40 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 34, and Figure 41 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in the display panel shown in Figure 34.

[0255] The difference between the display panel shown in Figure 34 and the display panel shown in Figure 12 is:

[0256] As shown in Figures 34, 35, and 39, compared to the display panel shown in Figure 12, the second conductive part 12 in the display panel shown in Figure 34 includes two first via connection parts 121. The orthographic projections of the two first via connection parts 121 on the substrate are located on both sides of the orthographic projection of the ninth active part 79 on the substrate in the first direction X.

[0257] As shown in Figures 34, 36, and 40, compared to the display panel shown in Figure 12, the second via bridge 29 connected to the third grid line segment G31 in the display panel shown in Figure 34 is slightly offset to the right.

[0258] As shown in Figures 34, 37, and 41, compared to the display panel shown in Figure 12, the second bridging portion 42 in the display panel shown in Figure 34 includes two first sub-bridging portions 421. The orthographic projections of the two first sub-bridging portions 421 on the substrate extend along the second direction Y. The orthographic projection of the second sub-bridging portion 423 on the substrate extends along the first direction X. The second sub-bridging portion 423 connects the two first sub-bridging portions 421. The two first sub-bridging portions 421 are respectively connected to the two first via connection portions 121 of the same second conductive portion 12 through vias. The second sub-bridging portion 423 is respectively connected to the fourth conductive portion 24 and the sixth conductive portion 36 through vias. This arrangement connects the gates of the ninth transistor T9 and the tenth transistor T10 through the two first sub-bridging portions 421, thereby reducing the resistance between the gates of the ninth transistor T9 and the tenth transistor T10, and thus enhancing the control over the gate voltages of the ninth transistor T9 and the tenth transistor T10. Furthermore, the orthographic projections of the two first sub-bridge portions 421 on the substrate can be located on either side of the orthographic projection of the twelfth bridge portion 412 on the substrate.

[0259] As shown in Figures 34, 37, and 41, compared to the display panel shown in Figure 12, the eleventh bridging portion 411 in the display panel shown in Figure 34 includes two third via connection portions 4113.

[0260] As shown in Figures 34 and 38, compared to the display panel shown in Figure 12, the pixel driving circuit group Pivz in the display panel shown in Figure 34 can be provided with two shutdown signal lines VGL. The orthographic projections of the two shutdown signal lines VGL on the substrate can extend along the second direction Y and are respectively located on both sides of the orthographic projection of the fourth gate line G4 on the substrate. The two shutdown signal lines VGL can be respectively connected to two third via connection portions 4113 in the same eleventh bridge portion 411 through vias. This arrangement can further reduce the resistance of the shutdown signal lines, thereby improving the uniformity of the display panel. At the same time, this arrangement can also shield the signal interference between the pixel driving circuit and the fourth gate line G4 through the two shutdown signal lines VGL.

[0261] As shown in Figures 34 and 38, two turn-off signal lines VGL are respectively provided corresponding to two first sub-bridge portions 421 in the same second bridge portion. The orthographic projection of the turn-off signal line VGL on the substrate and the orthographic projection of its corresponding first sub-bridge portion 421 on the substrate at least partially overlap, for example, the orthographic projection of the turn-off signal line VGL on the substrate covers the orthographic projection of its corresponding first sub-bridge portion 421 on the substrate. The two turn-off signal lines VGL can simultaneously shield the second bridge portion 42 to reduce interference between the second bridge portion 42 and other signals.

[0262] It should be noted that the other structures of the display panel shown in Figure 34 can be the same as those of the display panel shown in Figure 12.

[0263] This exemplary embodiment also provides a structural layout of another exemplary embodiment. The display panel may include a substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source / drain layer, a second source / drain layer, and a third source / drain layer, which are sequentially stacked. An insulating layer may be disposed between adjacent layers. As shown in Figures 42-45, Figure 42 is a structural layout of another exemplary embodiment of the display panel of this disclosure, Figure 43 is a structural layout of the second gate layer in the display panel shown in Figure 42, Figure 44 is a structural layout of the first source / drain layer in the display panel shown in Figure 42, and Figure 45 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 42.

[0264] The difference between the display panel shown in Figure 42 and the display panel shown in Figure 34 is:

[0265] As shown in Figures 42, 43, 44, and 45, compared to the display panel shown in Figure 34, the display panel shown in Figure 42 does not have a first gate line on the second gate layer, but has a first gate line G1 on the first source / drain layer. The first gate line G1 can be directly connected to the twenty-first active part 721 through a via to connect to the first electrode of the ninth transistor. The first gate line G1 can be used to provide the first gate drive signal terminal in Figure 6.

[0266] As shown in Figures 42, 43, 44, and 45, compared to the display panel shown in Figure 34, the display panel in Figure 42 does not have a turn-off signal connection line 4VL in the first source / drain layer, while the first gate line G1 is positioned at the location of the turn-off signal connection line 4VL in Figure 34. In this exemplary embodiment, since the sheet resistance of the first source / drain layer is less than the sheet resistance of the second gate layer, this setting can reduce the self-resistance of the first gate line G1, thereby reducing the voltage drop of the first gate line G1 and improving the uniformity of the display panel.

[0267] This exemplary embodiment also provides a structural layout of another exemplary embodiment, wherein the display panel may include a substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source / drain layer, a second source / drain layer, and a third source / drain layer stacked sequentially. An insulating layer may be disposed between adjacent layers. As shown in Figures 46-53, Figure 46 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, Figure 47 is a structural layout diagram of the first gate layer in the display panel shown in Figure 46, Figure 48 is a structural layout diagram of the second gate layer in the display panel shown in Figure 46, Figure 49 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 46, Figure 50 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 46, Figure 51 is a structural layout diagram of the shielding layer, the first active layer, and the first gate layer in the display panel shown in Figure 46, Figure 52 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 46, and Figure 53 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in the display panel shown in Figure 46.

[0268] The difference between the display panel shown in Figure 46 and the display panel shown in Figure 42 is:

[0269] As shown in Figures 46, 47, and 51, compared to the display panel shown in Figure 42, the second conductive part 12 in the display panel shown in Figure 46 includes a first through-hole connection part 121.

[0270] As shown in Figures 46, 48, and 52, compared to the display panel shown in Figure 42, the second via bridge 29 connected to the third grid line segment G31 in the display panel shown in Figure 46 is slightly offset to the left.

[0271] As shown in Figures 46, 49, and 53, compared to the display panel shown in Figure 42, the second bridging portion 42 in the display panel shown in Figure 46 includes a first sub-bridging portion 421 and a second sub-bridging portion 423. The orthographic projection of the first sub-bridging portion 421 on the substrate extends along the second direction Y, and the orthographic projection of the second sub-bridging portion 423 on the substrate extends along the first direction X. The first sub-bridging portion 421 is connected to the first via connection portion 121 through a via, and the second sub-bridging portion 423 is connected to the fourth conductive portion 24 and the sixth conductive portion 36 through vias, respectively.

[0272] As shown in Figures 46, 49, and 53, compared to the display panel shown in Figure 42, the eleventh bridging portion 411 in the display panel shown in Figure 46 includes a third via connection portion 4113.

[0273] As shown in Figures 46 and 50, compared to the display panel shown in Figure 42, the pixel driving circuit group Pivz in the display panel shown in Figure 46 is provided with a corresponding shutdown signal line VGL. The orthogonal projection of the shutdown signal line VGL on the substrate can extend along the second direction Y. The shutdown signal line VGL can be connected to the third via connection part 4113 through a via.

[0274] As shown in Figures 46 and 50, the orthographic projection of the turn-off signal line VGL on the substrate and the orthographic projection of the first sub-bridge portion 421 on the substrate are located on opposite sides of the orthographic projection of the fourth gate line G4 on the substrate. In contrast, the orthographic projection of the first sub-bridge portion 421 on the substrate is located between the orthographic projections of the turn-off signal line VGL and the fourth gate line G4 on the substrate. This arrangement can reduce the parasitic capacitance of the fourth gate line G4, the turn-off signal line VGL, and the first sub-bridge portion 421.

[0275] It should be noted that the other structures of the display panel shown in Figure 46 can be the same as those of the display panel shown in Figure 42.

[0276] In this exemplary embodiment, as shown in Figures 12-53, in the same pixel driving circuit subgroup, two pixel driving circuits located in the same pixel driving circuit row are at least partially mirror-symmetrically arranged. The mirror symmetry plane of the two pixel driving circuits may be perpendicular to the substrate. Furthermore, the orthographic projections of the two pixel driving circuits onto the substrate may at least partially be symmetrically arranged with the intersection of the mirror symmetry plane and the substrate as the axis of symmetry.

[0277] In this exemplary embodiment, as shown in FIG12-53, in the same pixel driving circuit row, the orthographic projection of the ninth active portion 79 on the substrate is located between the orthographic projection of the second gate line G2 on the substrate and the orthographic projection of the first reset signal line Re1 on the substrate. In the same pixel driving circuit row, the orthographic projection of the tenth active portion 910 on the substrate is located between the orthographic projection of the fifth gate line G5 on the substrate and the orthographic projection of the enable signal line EM on the substrate.

[0278] In this exemplary embodiment, as shown in Figures 12-53, the orthographic projection of the fourth gate line G4 on the substrate lies between the orthographic projections of the two pixel driving circuit subgroups Pivz1 within the same pixel driving circuit group Pivz on the substrate. The orthographic projection of the turn-off signal line VGL on the substrate lies between the orthographic projections of the two pixel driving circuit subgroups Pivz1 within the same pixel driving circuit group Pivz on the substrate, and the orthographic projection of the turn-off signal line VGL on the substrate lies between the orthographic projection of the fourth gate line G4 on the substrate and the orthographic projection of the pixel driving circuit subgroup Pivz1 on the substrate. This exemplary embodiment can shield the coupling effect of the fourth gate line G4 on each node in the pixel driving circuit through the turn-off signal line VGL.

[0279] In this exemplary embodiment, as shown in Figures 12-53, the pixel driving circuit group can be compressed in the first direction X to free up space for setting the control circuit K. Correspondingly, the distance between the orthographic projections of two adjacent pixel driving circuit columns Piv located in different pixel driving circuit groups Pivz on the substrate is less than the distance between the orthographic projections of two adjacent pixel driving circuit columns Piv located in different pixel driving circuit groups Pivz within the same pixel driving circuit group Pivz on the substrate. The distance between the orthographic projections of adjacent pixel driving circuit columns on the substrate can be understood as the distance between the orthographic projections of the channel regions of the two nearest transistors in adjacent pixel driving circuit columns on the substrate in the first direction.

[0280] In this exemplary embodiment, as shown in Figures 12-53, the second bridging portion 42 and the shutdown signal line VGL are located on different conductive layers, and the orthographic projection of the shutdown signal line VGL on the substrate and the orthographic projection of the second bridging portion 42 on the substrate at least partially overlap. The shutdown signal line VGL can shield the second bridging portion 42. It should be understood that in other exemplary embodiments, the second bridging portion 42 may also be located at other positions.

[0281] It should be noted that, as shown in Figure 12-53, the black squares with chamfers drawn on the side of the first source / drain layer away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black squares drawn on the side of the second source / drain layer away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate; and the black circles drawn on the side of the third source / drain layer away from the substrate represent vias connecting the third source / drain layer to other layers facing the substrate. Vias at different positions can penetrate different insulating layers.

[0282] It should be understood that, in other exemplary embodiments, the first gate line can be a multi-layer structure, i.e., the first gate line includes multiple sub-gate lines, each located in a different conductive layer, and the sub-gate lines located in different conductive layers can be connected via vias. This arrangement can further reduce the resistance of the first gate line. For example, at least two sub-gate lines in the same first gate line are located in a second gate layer and a first source / drain layer, respectively. Multiple sub-gate lines in the same first gate line can be connected via vias in the bezel area of ​​the display panel, and multiple sub-gate lines in the same first gate line can be connected via vias in the display area of ​​the display panel.

[0283] It should be understood that in other exemplary embodiments, the fourth gate line G4 and the turn-off signal line VGL may also be located in other positions. For example, the fourth gate line G4 and the turn-off signal line VGL may also be located in the third source-drain layer. Accordingly, the fifth conductive portions 55 distributed at intervals in the first direction may be connected in the same layer, and the sixteenth bridging portion 616 may not be provided in the third source-drain layer.

[0284] As shown in Figures 54-57, Figure 54 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, Figure 55 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in the display panel shown in Figure 54, Figure 56 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 54, and Figure 57 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 54.

[0285] As shown in Figures 54-57, the first source / drain layer includes a first sub-bridge portion 421 and a second sub-bridge portion 423. The first sub-bridge portion 421 is connected to the gate of the ninth transistor T9 through a via; the second sub-bridge portion 423 is spaced apart from the first sub-bridge portion 421, and the second sub-bridge portion 423 is connected to the gate of the tenth transistor T10 through a via; wherein, the orthographic projection of the fourth gate line G4 on the substrate extends along the second direction Y, and the fourth gate line G4 is connected to the first sub-bridge portion 421 and the second sub-bridge portion 423 through vias respectively.

[0286] Unlike the display panel shown in Figure 12, in the display panel shown in Figure 54, the second sub-bridging portion 423 and the first sub-bridging portion 421 are spaced apart. The first sub-bridging portion 421 does not need to be a long strip extending along the second direction Y. This arrangement can reduce the parasitic capacitance between the fourth gate line G4 and the first sub-bridging portion 421, thereby reducing the overall parasitic capacitance of the fourth gate line G4. As shown in Figures 54-57, the first sub-bridging portion 421 can be square, circular, polygonal, or other shapes. The ratio of the size of the orthographic projection of the first sub-bridging portion 421 on the substrate in the second direction Y to the size of the orthographic projection of the first sub-bridging portion 421 on the substrate in the first direction X can be greater than or equal to 0.5 and less than or equal to 2. For example, this ratio can be equal to 0.4, 0.6, 0.8, 1, 1.2, 1.4, 1.6, 1.8, 2, etc.

[0287] As shown in Figures 54-57, the second source / drain layer may further include a protrusion 510, and the protrusion 510 is connected to the fourth gate line G4. The orthographic projection of the protrusion 510 on the substrate is located on the side where the orthographic projection of the fourth gate line G4 on the substrate is in the first direction X. The fourth gate line G4 is connected to the first sub-bridge portion 421 through the via of the protrusion 510. That is, the orthographic projection of the fourth gate line G4 on the substrate and the orthographic projection of the via connecting the fourth gate line G4 and the protrusion 510 on the substrate do not overlap.

[0288] As shown in Figures 58 and 59, Figure 58 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, and Figure 59 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in the display panel shown in Figure 58.

[0289] Unlike the display panel shown in Figure 54, in the display panel shown in Figure 58, the first sub-bridge portion 421 can extend below the fourth gate line G4, so that the fourth gate line G4 can be directly connected to the first sub-bridge portion 421 through a via. That is, the orthographic projection of the fourth gate line G4 on the substrate overlaps with the orthographic projection of the via connecting the first sub-bridge portion 421 and the fourth gate line G4 on the substrate. This arrangement can eliminate the need for the protrusion portion 510, thereby further reducing the parasitic capacitance of the fourth gate line G4.

[0290] As shown in Figures 54-59, the orthographic projection of the via connecting the first sub-bridge portion 421 and the gate of the ninth transistor T9 on the substrate and the orthographic projection of the fourth gate line G4 on the substrate do not overlap. It should be understood that in other exemplary embodiments, the orthographic projection of the via connecting the first sub-bridge portion 421 and the gate of the ninth transistor T9 on the substrate and the orthographic projection of the fourth gate line G4 on the substrate may also overlap.

[0291] It should be noted that the scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The accompanying drawings described in this disclosure are only schematic diagrams of the structure. In addition, the terms "first," "second," etc., are only used to define different structural names and do not have a specific order meaning. The same structural layer can be formed by the same patterning process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction.

[0292] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0293] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0294] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0295] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel comprises: a substrate substrate; a plurality of pixel driving circuits, the orthogonal projection of the plurality of pixel driving circuits on the substrate substrate is arrayed along a first direction and a second direction, and the first direction and the second direction intersect; wherein the pixel driving circuit comprises a driving transistor and a switching transistor, the first electrode of the switching transistor is connected to the gate electrode of the driving transistor; a control circuit, the control circuit and at least one pixel driving circuit are correspondingly arranged, the control circuit is connected to the gate electrode of the switching transistor in the pixel driving circuit corresponding to the control circuit, and the control circuit is used to control the on-off of the switching transistor connected to the control circuit.

2. The display panel of claim 1, wherein, The plurality of pixel driving circuits distributed along the first direction form a pixel driving circuit row, and the display panel further comprises: a gate line, the orthogonal projection of the gate line on the substrate substrate extends along the first direction, and the gate line is used to provide a gate driving signal to the plurality of switching transistors located in the same pixel driving circuit row; the control circuit is connected to the gate line, and the control circuit is used to connect the gate electrode of the switching transistor to the gate line in response to a control signal or disconnect the gate electrode of the switching transistor from the gate line in response to a control signal.

3. The display panel of claim 2, wherein, The display panel further comprises: a fourth gate line, the orthogonal projection of the fourth gate line on the substrate substrate extends along the second direction; the control circuit is used to transmit the gate driving signal on the gate line to the gate electrode of the switching transistor in response to the signal of the fourth gate line.

4. The display panel of claim 1, wherein, The display panel further comprises: a gate line, the orthogonal projection of the gate line on the substrate substrate extends along the first direction; a fourth gate line, the orthogonal projection of the fourth gate line on the substrate substrate extends along the second direction; the control circuit is connected to the gate line and the fourth gate line, and the control circuit is used to transmit the control signal of the fourth gate line to the gate electrode of the switching transistor in response to the signal on the gate line, and the switching transistor can be turned off or turned on in response to the control signal of the fourth gate line.

5. The display panel of claim 2, wherein, The pixel driving circuit comprises one or more switching transistors, and one or more switching transistors comprise a second transistor, the first electrode of the second transistor is connected to the gate electrode of the driving transistor, and the second electrode of the second transistor is connected to the second electrode of the driving transistor; the pixel driving circuit row is correspondingly provided with one or more gate lines, and one or more gate lines comprise a first gate line, and the first gate line is used to provide a gate driving signal to the plurality of second transistors in the same pixel driving circuit row.

6. The display panel of claim 2, wherein, The control circuit is further used to transmit an off signal to the gate electrode of the switching transistor in response to a control signal.

7. The display panel of claim 6, wherein, The control circuit comprises: a ninth transistor, the first electrode of the ninth transistor is connected to the first gate line, the second electrode of the ninth transistor is connected to the gate electrode of the switching transistor, and the gate electrode of the ninth transistor is connected to the fourth gate line; a tenth transistor, the first electrode of the tenth transistor is connected to an off signal line, the second electrode of the tenth transistor is connected to the gate electrode of the switching transistor, and the gate electrode of the tenth transistor is connected to the fourth gate line, and the off signal line is used to provide the off signal to the control circuit; wherein the conduction signal polarities of the ninth transistor and the tenth transistor are opposite.

8. The display panel of claim 7, wherein, The display panel further comprises: A second bridge portion respectively connects the gate of the ninth transistor and the gate of the tenth transistor through a via hole; The second bridge portion comprises a first sub-bridge portion, the first sub-bridge portion connects the gate of the ninth transistor through a via hole, and a projection of the first sub-bridge portion on the substrate substrate extends along the second direction. A projection of the fourth gate line on the substrate substrate and a projection of the off signal line on the substrate substrate extend along the second direction, and in the same control circuit, the projection of the fourth gate line on the substrate substrate is located between the projection of the off signal line on the substrate substrate and the projection of the first sub-bridge portion on the substrate substrate.

9. The display panel of claim 7, wherein, The display panel further comprises: A first sub-bridge portion connects the gate of the ninth transistor through a via hole; A second sub-bridge portion is spaced apart from the first sub-bridge portion, and the second sub-bridge portion connects the gate of the tenth transistor through a via hole; The projection of the fourth gate line on the substrate substrate extends along the second direction, and the fourth gate line respectively connects the first sub-bridge portion and the second sub-bridge portion through a via hole.

10. The display panel of claim 9, wherein, The display panel further comprises: A protruding portion and the fourth gate line are located in the same conductive layer, and the protruding portion is connected to the fourth gate line, a projection of the protruding portion on the substrate substrate is located on one side of the projection of the fourth gate line on the substrate substrate in the first direction, and the fourth gate line connects the first sub-bridge portion through the protruding portion via hole; Or, the fourth gate line directly connects the first sub-bridge portion through a via hole.

11. The display panel of claim 7, wherein, The display panel further comprises: A second bridge portion respectively connects the gate of the ninth transistor and the gate of the tenth transistor through a via hole; The second bridge portion comprises two first sub-bridge portions and a second sub-bridge portion, the two first sub-bridge portions respectively connect the gate of the ninth transistor through a via hole, and the second sub-bridge portion is connected between the two first sub-bridge portions and connects the gate of the tenth transistor through a via hole; Wherein, the projections of the two first sub-bridge portions on the substrate substrate extend along the second direction and are spaced apart in the first direction.

12. The display panel of claim 11, wherein, The display panel further comprises: A twelfth bridge portion respectively connects the second electrode of the ninth transistor and the second electrode of the tenth transistor through a via hole; The projection of the twelfth bridge portion on the substrate substrate is located between the projections of the two first sub-bridge portions on the substrate substrate in the same second bridge portion.

13. The display panel of claim 11, wherein, The display panel comprises: At least two off signal lines, two off signal lines are respectively arranged corresponding to two first sub-bridge portions in the same second bridge portion; The conductive layer where the turn-off signal line is located is located on the side of the conductive layer where the second bridge portion is located away from the substrate, and the orthogonal projection of the turn-off signal line on the substrate and the orthogonal projection of the corresponding first sub-bridge portion on the substrate at least partially overlap.

14. The display panel according to any one of claims 6-13, wherein, The display panel further comprises: At least two turn-off signal lines, the orthogonal projections of the two turn-off signal lines on the substrate extend along the second direction and are arranged at intervals in the first direction, and the turn-off signal lines are used to provide the control circuit with the turn-off signal; The eleventh bridge portion is connected to the two turn-off signal lines through vias.

15. The display panel according to any one of claims 6-14, wherein, The display panel further comprises: A plurality of turn-off signal lines, the orthogonal projections of the plurality of turn-off signal lines on the substrate extend along the second direction and are arranged at intervals along the first direction, and the turn-off signal lines are used to provide the control circuit with the turn-off signal; A plurality of turn-off signal connection lines, the orthogonal projections of the turn-off signal connection lines on the substrate extend along the first direction and are arranged at intervals along the second direction; The turn-off signal lines and the turn-off signal connection lines are located in different conductive layers, and at least part of the turn-off signal lines are connected to at least part of the turn-off signal connection lines intersecting therewith through vias.

16. The display panel of claim 15, wherein, The display panel further comprises: A first source-drain layer located on one side of the substrate, the first source-drain layer comprising an eleventh bridge portion, a seventeenth bridge portion, and the turn-off signal connection line, the eleventh bridge portion being connected to the turn-off signal line through a via, the seventeenth bridge portion being connected between the turn-off signal connection line and the eleventh bridge portion, and the orthogonal projection of the seventeenth bridge portion on the substrate extending along the second direction; A second source-drain layer located on the side of the first source-drain layer away from the substrate, the second source-drain layer comprising a fourth gate line, the orthogonal projection of the fourth gate line on the substrate extending along the second direction, and the control circuit being used to transmit the turn-off signal to the gate of the switching transistor in response to a control signal on the fourth gate line; The orthogonal projection of the seventeenth bridge portion on the substrate and the orthogonal projection of the fourth gate line on the substrate at least partially overlap.

17. The display panel of claim 15, wherein, The pixel drive circuit comprises one or more switching transistors, and the one or more switching transistors comprise a second transistor, the first electrode of the second transistor being connected to the gate of a drive transistor, and the second electrode of the second transistor being connected to the second electrode of the drive transistor; One or more gate lines are arranged corresponding to the pixel drive circuit row, and the one or more gate lines comprise a first gate line, the first gate line being used to provide a gate drive signal to the plurality of second transistors in the same pixel drive circuit row; The orthogonal projection of the turn-off signal connection line on the substrate and the orthogonal projection of the first gate line on the substrate at least partially overlap.

18. The display panel of claim 5, wherein, The control circuit comprises: A ninth transistor, the first electrode of the ninth transistor being connected to the first gate line, the second electrode of the ninth transistor being connected to the gate of the second transistor, and the gate of the ninth transistor being connected to the fourth gate line; The first gate line comprises first gate line segments extending along the first direction and being spaced apart; The display panel further comprises: The first active layer comprises a ninth active part and a twenty-first active part, the ninth active part is used for forming a channel region of the ninth transistor, and the twenty-first active part is connected to the ninth active part; The orthogonal projection of the twenty-first active part on the substrate substrate is located between the orthogonal projections of two adjacent first gate line segments in the same first gate line on the substrate substrate. The eighteenth bridge part is connected to the first gate line and the twenty-first active part through a via hole.

19. The display panel of claim 5, wherein, The control circuit comprises: The ninth transistor has a first electrode connected to the first gate line, a second electrode connected to the gate electrode of the second transistor, and a gate electrode connected to the fourth gate line, and the orthogonal projection of the first gate line on the substrate substrate continuously extends along the first direction; The display panel further comprises: The first active layer comprises a ninth active part and a twenty-first active part, the ninth active part is used for forming a channel region of the ninth transistor, and the twenty-first active part is connected to the ninth active part; The orthogonal projection of the twenty-first active part on the substrate substrate is located on one side of the orthogonal projection of the first gate line on the substrate substrate in the second direction. The eighteenth bridge part is connected to the first gate line and the twenty-first active part through a via hole. The pixel driving circuit further comprises a capacitor; 20. The display panel of claim 18 or 19, wherein, The display panel further comprises: The first gate layer is located on the side of the first active layer away from the substrate substrate, and part of the structure of the first gate layer is used for forming the first electrode of the capacitor. The second gate layer is located on the side of the first gate layer away from the substrate substrate, and part of the structure of the second gate layer is used for forming the second electrode of the capacitor, and the first gate line is located on the second gate layer. The display panel further comprises:

21. The display panel of claim 5, wherein, The first source-drain layer is located on the side of the substrate substrate, and the first source-drain layer comprises a first bridge part, and the first bridge part is connected to the gate electrode of the driving transistor and the first electrode of the second transistor through a via hole. The first gate line is located on the first source-drain layer. A plurality of pixel driving circuits distributed in the second direction form a pixel driving circuit row, and one or more adjacent pixel driving circuit rows form a pixel driving circuit group.

22. The display panel of any of claims 1-21, wherein, The display panel comprises a plurality of pixel driving circuit groups, and the pixel driving circuit groups correspondingly arrange a plurality of control circuits; In the same pixel driving circuit group, the control circuit and the pixel driving circuit located in the same pixel driving circuit row are correspondingly arranged. The display panel further comprises:

23. The display panel of claim 22, wherein, ​ A fifth gate line includes fifth gate line segments extending along the first direction and spaced along the first direction, the fifth gate line segments and the pixel drive circuit groups correspondingly arranged, and the fifth gate line segments are connected to the gates of the same type of switching transistor in the same pixel drive circuit row of the pixel drive circuit groups corresponding thereto; The control circuit is connected to the gates of the switching transistors in the pixel drive circuit corresponding thereto through the fifth gate line segment.

24. The display panel of claim 22, wherein, The pixel drive circuit group includes two pixel drive circuit subgroups; In the corresponding pixel drive circuit group and the control circuit, the orthographic projection of the control circuit on the substrate is located between the orthographic projections of the two pixel drive circuit subgroups on the substrate.

25. The display panel of claim 7, wherein, The pixel drive circuit includes one or more switching transistors, and the one or more switching transistors include a second transistor, the first electrode of the second transistor is connected to the gate of a drive transistor, and the second electrode of the second transistor is connected to the second electrode of the drive transistor. The pixel drive circuit further includes a fifth transistor. The first electrode of the fifth transistor is connected to a first power supply line, the second electrode of the fifth transistor is connected to the first electrode of the drive transistor, and the gate of the fifth transistor is connected to an enable signal line. The display panel further includes: A second active layer is located on one side of the substrate, and the second active layer includes a tenth active part, and the tenth active part is used to form a channel region of the tenth transistor. A third gate layer is located on the side of the second active layer away from the substrate, and the third gate layer includes a fifth gate line, and the fifth gate line is used to form a gate of the second transistor. In the same pixel drive circuit row, the orthographic projection of the tenth active part on the substrate is located between the orthographic projection of the fifth gate line on the substrate and the orthographic projection of the enable signal line on the substrate.

26. The display panel of claim 22, wherein, The display panel further includes: a fourth gate line, and the orthographic projection of the fourth gate line on the substrate extends along the second direction; The fourth gate line is used to provide a control signal to the control circuits corresponding to the same pixel drive circuit group.

27. The display panel of claim 26, wherein, The pixel drive circuit group includes two pixel drive circuit subgroups; The orthographic projection of the fourth gate line on the substrate is located between the orthographic projections of the two pixel drive circuit subgroups on the substrate in the same pixel drive circuit group.

28. The display panel of claim 27, wherein, The control circuit is further configured to transmit an off signal to the gate of the switching transistor in response to the control signal; The display panel further includes an off signal line, and the orthographic projection of the off signal line on the substrate extends along the second direction, and the off signal line is used to provide an off signal to the control circuits corresponding to the same pixel drive circuit group. The orthographic projection of the off signal line on the substrate is located between the orthographic projections of the two pixel drive circuit subgroups on the substrate in the same pixel drive circuit group, and the orthographic projection of the off signal line on the substrate is located between the orthographic projection of the fourth gate line on the substrate and the orthographic projection of the pixel drive circuit subgroup on the substrate.

29. A display device comprising: The display device comprises the display panel according to any one of claims 1-28. The display device comprises the display panel according to any one of claims 1-28.

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