Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device capable of achieving miniaturization or high integration. The semiconductor device is provided with a memory cell including first to third vertical transistors. The first to third vertical transistors are sequentially stacked from bottom to top. The first vertical transistor includes a gate electrode between the lower electrode and the upper electrode, the gate electrode surrounding the semiconductor layer. An insulating layer is embedded inside the semiconductor layer, and a top surface of the insulating layer is over a top surface of a region of the semiconductor layer that overlaps the upper electrode. The second and third vertical transistors include gate electrodes inside the semiconductor layer. A lower electrode of the second vertical transistor is on the insulating layer and in contact with the semiconductor layer of the first vertical transistor. A gate electrode of the second vertical transistor and a lower electrode of the third vertical transistor use the same conductive layer.

Description

TECHNICAL FIELD

[0001] One embodiment of the present application relates to a semiconductor device, a memory device, a display device, and an electronic device. Note that one embodiment of the present application relates to a method for manufacturing a semiconductor device.

[0002] Note that one embodiment of the present application is not limited to the technical field described above. Examples of a technical field to which one embodiment of the present application pertains are a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input-output device (e.g., a touch panel), and a driving method or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device generally means a device that utilizes semiconductor characteristics and includes a circuit including a semiconductor element (a transistor, a diode, a photodiode, and the like) and a device including the circuit. Furthermore, a semiconductor device means all devices that can function by utilizing semiconductor characteristics. For example, a semiconductor device includes an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is mounted in a package. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device themselves are semiconductor devices, and each include a semiconductor device in some cases. BACKGROUND

[0004] In recent years, semiconductor devices have been developed, and LSI (Large Scale Integration), a CPU (Central Processing Unit), a memory, and the like are mainly used as semiconductor devices. A CPU is a collection of semiconductor integrated circuits (at least including a transistor and a memory) including a semiconductor element in which a semiconductor wafer is processed into a chip and an electrode serving as a connection terminal is formed.

[0005] A semiconductor circuit (an IC chip) of an LSI, a CPU, a memory, and the like is mounted on a circuit board, e.g., a printed wiring board, and is used as one of components of various electronic devices.

[0006] Furthermore, a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to integrated circuits (ICs), display devices, and the like. As a semiconductor thin film which can be used for transistors, a silicon-based semiconductor material is widely known. As another material, an oxide semiconductor has attracted attention.

[0007] Further, it is known that a transistor using an oxide semiconductor has extremely small off-state current. For example, Patent Document 1 discloses a low-power CPU or the like which utilizes the characteristic of small off-state current of a transistor using an oxide semiconductor. Further, for example, Patent Document 2 discloses a storage device or the like which utilizes the characteristic of small off-state current of a transistor using an oxide semiconductor to achieve long-term retention of stored content.

[0008] In recent years, with the miniaturization and weight reduction of electronic devices, further high-density integration of integrated circuits has been demanded. Further, improvement in productivity of semiconductor devices including integrated circuits has been demanded. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique in which a plurality of memory cells are provided in a stacked manner by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, whereby the density of an integrated circuit is increased. Further, in Patent Document 4, a technique in which channels of transistors using an oxide semiconductor film are arranged in a vertical direction to achieve high-density integration of integrated circuits is also disclosed.

[0009] [Prior Art Documents]

[0010] [Patent Documents]

[0011] [Patent Document 1] Japanese Published Patent Application No. 2012-257187

[0012] [Patent Document 2] Japanese Published Patent Application No. 2011-151383

[0013] [Patent Document 3] International Patent Application Publication No. 2021 / 053473

[0014] [Patent Document 4] Japanese Published Patent Application No. 2013-211537

[0015] [Non-Patent Documents]

[0016] [Non-Patent Document 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72 nm”, IEDM Tech. Dig., 2019, pp. 50-53 SUMMARY

[0017] PROBLEMS TO BE SOLVED BY THE INVENTION

[0018] One of objects of one embodiment of the present application is to provide a semiconductor device capable of miniaturization or high integration and a manufacturing method thereof. Another object of one embodiment of the present application is to provide a semiconductor device with high reliability and a manufacturing method thereof. Another object of one embodiment of the present application is to provide a semiconductor device with high operation speed and a manufacturing method thereof. Another object of one embodiment of the present application is to provide a semiconductor device with low power consumption and a manufacturing method thereof. Another object of one embodiment of the present application is to provide a manufacturing method of a semiconductor device with high yield. Another object of one embodiment of the present application is to provide a novel semiconductor device and a manufacturing method thereof.

[0019] Note that the description of these objects does not preclude the existence of other objects. One embodiment of the present application does not necessarily achieve all the above-described objects. An object other than those described above can be extracted from the description, drawings, and claims.

[0020] Means for solving the technical problem

[0021] One embodiment of the present application is a semiconductor device including a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer, in which the first insulating layer is positioned over the first conductive layer, the second conductive layer is positioned over the first insulating layer, the second insulating layer is positioned over the second conductive layer and the first insulating layer, the third conductive layer is positioned over the second insulating layer, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have a first opening portion reaching the first conductive layer, the third insulating layer is in contact with a side surface of the second conductive layer inside the first opening portion, the first semiconductor layer is in contact with the first conductive layer, the first semiconductor layer is in contact with a top surface of the third conductive layer, the first semiconductor layer has a first region which faces the second conductive layer with the third insulating layer interposed therebetween inside the first opening portion, at least a part of the first region is in contact with the third insulating layer, the fourth insulating layer is positioned inside the first semiconductor layer inside the first opening portion, the fifth insulating layer is provided so as to fill the first opening portion inside the fourth insulating layer and is planarized, the first semiconductor layer has a second region which overlaps with the third conductive layer, and a top surface of the fifth insulating layer is positioned above a top surface of the second region of the first semiconductor layer.

[0022] In the above embodiment, a sixth insulating layer and a seventh insulating layer can be included, in which the sixth insulating layer can cover a side surface of the third conductive layer on a side opposite to a side of the first opening portion, and the seventh insulating layer can be positioned over the sixth insulating layer.

[0023] Further, in the above-described mode, a second semiconductor layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a sixth insulating layer, and a seventh insulating layer can be included, the fourth conductive layer can be positioned on the fifth insulating layer, the fourth conductive layer can be in contact with the second region, the sixth insulating layer can be positioned on the fourth conductive layer, the fifth conductive layer can be positioned on the sixth insulating layer, the sixth insulating layer and the fifth conductive layer can have a second opening portion reaching the fourth conductive layer, the second semiconductor layer can be in contact with the fourth conductive layer and the fifth conductive layer and have a region positioned inside the second opening portion, the seventh insulating layer can be positioned on the second semiconductor layer and inside the second semiconductor layer inside the second opening portion, and the sixth conductive layer can be positioned on the seventh insulating layer and inside the seventh insulating layer inside the second opening portion.

[0024] Further, in the above-described mode, a third semiconductor layer, a seventh conductive layer, an eighth conductive layer, an eighth insulating layer, and a ninth insulating layer can be included, the eighth insulating layer can be positioned on the sixth conductive layer, the seventh conductive layer can be positioned on the eighth insulating layer, the eighth insulating layer and the seventh conductive layer can have a third opening portion reaching the sixth conductive layer, the third semiconductor layer can be in contact with the sixth conductive layer and the seventh conductive layer and have a region positioned inside the third opening portion, the ninth insulating layer can be positioned on the third semiconductor layer and inside the third semiconductor layer inside the third opening portion, and the eighth conductive layer can be positioned on the ninth insulating layer and inside the ninth insulating layer inside the third opening portion.

[0025] Further, in the above-described mode, a ninth conductive layer and a tenth insulating layer can be included, the eighth insulating layer can include an eleventh insulating layer and a twelfth insulating layer on the eleventh insulating layer, the ninth conductive layer can be positioned on the eleventh insulating layer, the twelfth insulating layer can be positioned on the ninth conductive layer and the eleventh insulating layer, the eleventh insulating layer, the ninth conductive layer, and the twelfth insulating layer can have a third opening portion, the tenth insulating layer can be in contact with a side surface of the ninth conductive layer inside the third opening portion, the third semiconductor layer can be in contact with the tenth insulating layer inside the third opening portion, and the third semiconductor layer can have a third region opposing the eighth conductive layer with the ninth insulating layer interposed therebetween and opposing the ninth conductive layer with the tenth insulating layer interposed therebetween.

[0026] Further, in the above-described mode, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer can all use a metal oxide, the metal oxide can contain two or three selected from indium, an element M, and zinc, and the element M can be one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.

[0027] Further, one embodiment of the present application is a method for manufacturing a semiconductor device, including the steps of: forming a first conductive layer; forming a first insulating layer over the first conductive layer; forming a second conductive layer over the first insulating layer; forming a second insulating layer over the second conductive layer and the first insulating layer; forming a third conductive layer over the second insulating layer; forming a first opening portion reaching the first conductive layer in the third conductive layer, the second insulating layer, the second conductive layer, and the first insulating layer; forming a third insulating layer so as to cover the first opening portion; exposing a top surface of the third conductive layer and the first conductive layer by processing the third insulating layer using anisotropic etching; forming a first semiconductor layer so as to cover the third insulating layer and be in contact with the top surface of the third conductive layer and the first conductive layer; forming a fourth insulating layer so as to cover the first semiconductor layer; forming a fifth insulating layer over the fourth insulating layer so as to have a region inside the first opening portion; performing planarization treatment on the fifth insulating layer until at least part of a top surface of the fourth insulating layer is exposed, whereby a sixth insulating layer having a region inside the first opening portion is formed; removing part of the fourth insulating layer to form a seventh insulating layer having a region inside the first opening portion and expose at least part of a top surface of the first semiconductor layer; forming a fourth conductive layer so as to be in contact with a top surface of the sixth insulating layer and a top surface of the first semiconductor layer; forming an eighth insulating layer over the fourth conductive layer; forming a fifth conductive layer over the eighth insulating layer; forming a second opening portion reaching the fourth conductive layer in the fifth conductive layer and the eighth insulating layer; forming a second semiconductor layer so as to cover the second opening portion and be in contact with the fourth conductive layer and the fifth conductive layer; forming a ninth insulating layer so as to cover the second semiconductor layer; and forming a sixth conductive layer over the ninth insulating layer so as to have a region inside the second opening portion.

[0028] Further, in the above embodiment, a tenth insulating layer can be formed over the sixth conductive layer, a seventh conductive layer can be formed over the tenth insulating layer, a third opening portion reaching the sixth conductive layer can be formed in the seventh conductive layer and the tenth insulating layer, a third semiconductor layer can be formed so as to cover the third opening portion and be in contact with the sixth conductive layer and the seventh conductive layer, an eleventh insulating layer can be formed so as to cover the third semiconductor layer, and an eighth conductive layer can be formed over the eleventh insulating layer so as to have a region inside the third opening portion.

[0029] In addition, in the above-described mode, a tenth insulating layer can be formed over the sixth conductive layer, a seventh conductive layer can be formed over the tenth insulating layer, an eleventh insulating layer can be formed over the seventh conductive layer and the tenth insulating layer, an eighth conductive layer can be formed over the eleventh insulating layer, a third opening portion reaching the sixth conductive layer can be formed in the eighth conductive layer, the eleventh insulating layer, the seventh conductive layer, and the tenth insulating layer, a twelfth insulating layer can be formed so as to cover the third opening portion, the top surface of the eighth conductive layer, and the sixth conductive layer can be exposed by processing the twelfth insulating layer by anisotropic etching, a third semiconductor layer can be formed so as to cover the twelfth insulating layer and be in contact with the top surface of the eighth conductive layer and the sixth conductive layer, a thirteenth insulating layer can be formed so as to cover the third semiconductor layer, and a ninth conductive layer can be formed over the thirteenth insulating layer so as to have a region inside the third opening portion.

[0030] In addition, in the above-described mode, at least part of a region of the fourth insulating layer which does not overlap with the sixth insulating layer can be removed by processing the fourth insulating layer after planarization treatment of the fifth insulating layer.

[0031] In addition, in the above-described mode, a fourth opening portion overlapping with the first semiconductor layer can be formed in the fifth insulating layer by planarization treatment of the fifth insulating layer, and a region of the fourth insulating layer which does not overlap with both the fifth insulating layer and the sixth insulating layer can be removed by processing the fourth insulating layer.

[0032] Effects of Invention

[0033] According to one embodiment of the present application, a semiconductor device which can be miniaturized or highly integrated and a method for manufacturing the same can be provided. According to one embodiment of the present application, a semiconductor device with high reliability and a method for manufacturing the same can be provided. According to one embodiment of the present application, a semiconductor device with high operation speed and a method for manufacturing the same can be provided. According to one embodiment of the present application, a semiconductor device with low power consumption and a method for manufacturing the same can be provided. According to one embodiment of the present application, a method for manufacturing a semiconductor device with high yield can be provided. According to one embodiment of the present application, a novel semiconductor device and a method for manufacturing the same can be provided.

[0034] Note that the description is not intended to limit the effects to what can be described using the effects. Thus, effects other than those described above can be extracted from the description, the drawings, and the like. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1A FIG. 1 is a circuit diagram illustrating a structure example of a memory cell. Figures 1B to 1D FIG. 2 is a plan view illustrating a structure example of a semiconductor device.

[0036] Figure 2A and Figure 2B is a cross-sectional view showing a structure example of a semiconductor device.

[0037] Figures 3A to 3D is a plan view showing a structure example of a semiconductor device.

[0038] Figure 4A and Figure 4B is a cross-sectional view showing a structure example of a semiconductor device.

[0039] Figure 5A and Figure 5B is a plan view showing a structure example of a semiconductor device. Figure 5C and Figure 5D is a cross-sectional view showing a structure example of a semiconductor device.

[0040] Figure 6A and Figure 6B is a cross-sectional view showing a structure example of a semiconductor device.

[0041] Figure 7A is a circuit diagram showing a structure example of a memory cell. Figure 7B is a plan view showing a structure example of a semiconductor device. Figure 7C and Figure 7D is a cross-sectional view showing a structure example of a semiconductor device.

[0042] Figure 8A and Figure 8B is a cross-sectional view showing a structure example of a semiconductor device.

[0043] Figure 9A and Figure 9B is a cross-sectional view showing a structure example of a semiconductor device.

[0044] Figure 10A and Figure 10B is a cross-sectional view showing a structure example of a semiconductor device.

[0045] Figure 11A and Figure 11B is a cross-sectional view showing a structure example of a semiconductor device.

[0046] Figure 12A and Figure 12B is a cross-sectional view showing a structure example of a semiconductor device.

[0047] Figure 13A and Figure 13B is a cross-sectional view showing a structure example of a semiconductor device.

[0048] Figure 14A and Figure 14B is a cross-sectional view showing a structure example of a semiconductor device.

[0049] Figure 15A Figure 15B is a cross-sectional view showing a structure example of a semiconductor device.

[0050] Figure 16A Figure 16B is a cross-sectional view showing a structure example of a semiconductor device.

[0051] Figures 17A to 17D is a cross-sectional view showing a manufacturing method example of a semiconductor device.

[0052] Figures 18A to 18C is a cross-sectional view showing a manufacturing method example of a semiconductor device.

[0053] Figures 19A to 19C is a cross-sectional view showing a manufacturing method example of a semiconductor device.

[0054] Figure 20A Figure 20B is a cross-sectional view showing a manufacturing method example of a semiconductor device.

[0055] Figure 21A Figure 21B is a cross-sectional view showing a manufacturing method example of a semiconductor device.

[0056] Figure 22 is a cross-sectional view showing a manufacturing method example of a semiconductor device.

[0057] Figure 23 is a cross-sectional view showing a manufacturing method example of a semiconductor device.

[0058] Figure 24 is a cross-sectional view showing a manufacturing method example of a semiconductor device.

[0059] Figures 25A to 25D is a cross-sectional view showing a deposition method of a metal oxide.

[0060] Figures 26A to 26D is a cross-sectional view showing a deposition method of a metal oxide.

[0061] Figure 27 is a cross-sectional view showing a structure example of a semiconductor device.

[0062] Figure 28 is a cross-sectional view showing a structure example of a semiconductor device.

[0063] Figure 29 is a block diagram showing a structure example of a semiconductor device.

[0064] Figure 30A Figure 30B is a perspective view showing a structure example of a semiconductor device. ​​​​​

[0065] Figure 31 is a block diagram illustrating a CPU.

[0066] Figure 32A and Figure 32B is a perspective view showing a structure example of a semiconductor device.

[0067] Figure 33A and Figure 33B is a perspective view showing a structure example of a semiconductor device.

[0068] Figure 34A and Figure 34B is a diagram showing a hierarchy of a storage device.

[0069] Figure 35A and Figure 35B is a diagram showing one example of an electronic component.

[0070] Figures 36A to 36C is a diagram showing one example of a large computer. Figure 36D is a diagram showing one example of a space device. Figure 36E is a diagram showing one example of a storage system that can be used for a data center. DETAILED DESCRIPTION

[0071] Embodiments are described in detail with reference to the accompanying drawings. Note that the present application is not limited to the following description, and it is readily apparent to those skilled in the art that the present application can be changed in various ways without departing from the spirit and scope of the present application. Therefore, the present application should not be interpreted as being limited to the content below.

[0072] Note that, in the drawings used in the following description of the present application, the same symbols are used throughout the drawings to designate the same portions or portions having the same function, and repeated description is omitted. Further, the same hatching pattern is used when designating portions having the same function, and a symbol is not particularly added.

[0073] Further, in order to facilitate understanding, the position, size, range, and the like of each constituent element shown in the drawings are not necessarily to scale or the like. Therefore, the disclosed application is not necessarily limited to the position, size, range, and the like disclosed in the drawings.

[0074] Note that, in this specification and the like, the ordinal numbers "first", "second", and the like are added to constituents only for convenience and do not limit the number of constituents or the order in which the constituents appear (e.g., the order in which steps are performed or the order in which layers are formed). Further, the ordinal number added to a constituent in a certain portion in the specification or like does not necessarily have to be the same as the ordinal number added to the same constituent in another portion in the specification or like or in a claim.

[0075] A transistor is one of semiconductor elements, and functions such as amplification of current or voltage, switching operation of on or off, and the like can be implemented. The transistor in this specification includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).

[0076] In this specification and the like, a transistor in which an oxide semiconductor or a metal oxide is used for a semiconductor layer and a transistor including an oxide semiconductor or a metal oxide in a channel formation region is referred to as an OS transistor. Further, a transistor including silicon in a channel formation region is referred to as an Si transistor.

[0077] In this specification and the like, a transistor refers to an element including at least three terminals of a gate, a drain, and a source. A transistor has a region where a channel is formed between a drain (a drain terminal, a drain region, or a drain electrode) and a source (a source terminal, a source region, or a source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region where current flows.

[0078] Further, the functions of the source and the drain are sometimes interchangeable with each other in the case of using different polarities of transistors or in the case where the direction of current flowing in a circuit is changed, and the like. Therefore, the source and the drain can be interchangeable with each other in this specification.

[0079] Note that an impurity of a semiconductor refers to, for example, an element other than the main components of a semiconductor. For example, an element with a concentration lower than 0.1 atomic% can be regarded as an impurity. In the case where an impurity is contained, for example, an increase in the defect state density of a semiconductor or a decrease in crystallinity, or the like is sometimes caused. When a semiconductor is an oxide semiconductor, as an impurity which changes the characteristics of the semiconductor, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor are given. Specifically, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen are given. In addition, water sometimes functions as an impurity. Furthermore, for example, the inclusion of an impurity causes formation of an oxygen vacancy (also referred to as V O

[0080] Note that in this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0081] ​For example, the content of elements such as hydrogen, oxygen, carbon, and nitrogen in the membrane can be analyzed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less or 1 atomic% or less). When comparing elemental contents, it is more preferable to use a combined analysis of SIMS and XPS.

[0082] Furthermore, depending on the situation or state, the "film" and "layer" can be interchanged. For example, a "conductive layer" can be changed into a "conductive film." Similarly, an "insulating film" can be changed into an "insulating layer."

[0083] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than or equal to -10 degrees and less than 10 degrees. Therefore, it also includes states where the angle is greater than or equal to -5 degrees and less than 5 degrees. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than or equal to -20 degrees and less than 20 degrees. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than or equal to 80 degrees and less than 100 degrees. Therefore, it also includes states where the angle is greater than or equal to 85 degrees and less than 95 degrees. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than or equal to 70 degrees and less than 110 degrees.

[0084] In this specification, "electrical connection" includes connections made via "elements that have a certain electrical function." Here, "elements that have a certain electrical function" are not particularly limited as long as they can transmit and receive electrical signals between the connected objects. For example, "elements that have a certain electrical function" include, in addition to electrodes or wiring, switching elements such as transistors, resistors, coils, and other elements with various functions.

[0085] Furthermore, in this specification and other materials, unless otherwise specified, off-state current refers to the leakage current between the source and drain when the transistor is in the off state (also known as the non-conducting state or the blocked state). Unless otherwise specified, in an n-channel transistor, the off state refers to the voltage V between the gate and source. gs Below the threshold voltage V th (V in p-channel transistor) gs Higher than V th ) state.

[0086] In this specification and the like, a normally-on characteristic refers to a state where a channel exists even if no voltage is applied to a gate, and current flows through a transistor. Furthermore, a normally-off characteristic refers to a state where no current flows through a transistor when no potential is applied to a gate or a ground potential is supplied to a gate.

[0087] In this specification and the like, a tapered shape refers to a shape in which at least a part of a side surface of a component is obliquely provided with respect to a substrate surface or a formed surface of the component. For example, it is preferable that an angle (also referred to as a taper angle) formed by the oblique side surface of the component and the substrate surface or the formed surface of the component be greater than 0 degrees and less than 90 degrees. Note that the side surface of the component, the substrate surface, and the formed surface of the component do not necessarily have to be completely flat, and can be an approximately planar shape with a slight curvature or an approximately planar shape with slight irregularities.

[0088] In this specification and the like, in the case where it is stated that A is positioned on B, at least a part of A is positioned on B. Thus, for example, it can be stated that A includes a region positioned on B. Similarly, in the case where it is stated that A is in contact with B or A overlaps with B, at least a part of A is in contact with B or overlaps with B. Thus, it can be stated that A has a region in contact with B or A has a region overlapping with B. Similarly, in this specification and the like, in the case where it is stated that A covers B, at least a part of A covers B. Thus, for example, it can be stated that A includes a region covering B.

[0089] In this specification and the like, disconnection refers to a phenomenon in which a layer, a film, or an electrode is disconnected due to the shape (e.g., a step or the like) of a formed surface thereof.

[0090] Note that, in the drawings of this specification and the like, arrows indicating an X direction, a Y direction, and a Z direction are attached. Note that, in this specification and the like, the "X direction" refers to a direction along the X axis, and the forward and reverse directions thereof are not distinguished unless explicitly indicated. The same applies to the "Y direction" and the "Z direction". Furthermore, the X direction, the Y direction, and the Z direction are directions intersecting with each other. For example, the X direction, the Y direction, and the Z direction are directions orthogonal to each other.

[0091] (Embodiment 1)

[0092] In this embodiment, a semiconductor device of one embodiment of the present application and a method for manufacturing the semiconductor device will be described.

[0093] One embodiment of the present application relates to a semiconductor device provided with a memory cell including a first transistor, a second transistor, and a third transistor. The first transistor, the second transistor, and the third transistor are provided in this order from the bottom. The first transistor, the second transistor, and the third transistor have regions overlapping with each other.

[0094] In this specification and the like, a semiconductor device provided with a memory unit is also referred to as a memory device.

[0095] The source and drain electrodes of the first to third transistors are located at different levels, and thus current flowing through the semiconductor layer flows in the vertical direction. In other words, it can be said that the channel length direction has a component of the vertical direction. Thus, the first to third transistors can also be referred to as a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel type transistor, or the like. Here, in the vertical transistor, the lower electrode of the source and drain electrodes is referred to as a lower electrode, and the upper electrode is referred to as an upper electrode. The vertical transistor can be provided with the source electrode, the semiconductor layer, and the drain electrode in a manner of being stacked over one another.

[0096] The upper electrode of the first transistor and the lower electrode of the second transistor can be formed using the same conductive layer. Further, the gate electrode of the second transistor and the lower electrode of the third transistor can be formed using the same conductive layer. As described above, the first to third transistors can be vertical transistors and be provided in a stacked manner, and the other of the source and drain electrodes of the first transistor and one of the source and drain electrodes of the second transistor can be electrically connected. Further, the gate electrode of the second transistor and one of the source and drain electrodes of the third transistor can be electrically connected.

[0097] As described above, the area occupied by the memory unit can be reduced, for example, as compared to the case where two or three of the first transistor, the second transistor, and the third transistor are formed on the same formed surface and the first to third transistors are so-called planar transistors. As described above, a semiconductor device capable of miniaturization or high integration can be provided.

[0098] Here, the gate electrode of the first transistor is provided between the lower electrode of the first transistor and the upper electrode of the first transistor. The gate electrode of the first transistor is provided so as to surround the semiconductor layer of the first transistor. The semiconductor layer of the first transistor has a recess portion overlapping with the lower electrode of the first transistor. The recess portion is filled with an insulating layer. The conductive layer serving also as the upper electrode of the first transistor and the lower electrode of the second transistor is provided over the insulating layer. Thus, the first transistor and the second transistor can be vertical transistors and be provided in a stacked manner, and the other of the source and drain electrodes of the first transistor and one of the source and drain electrodes of the second transistor can be electrically connected.

[0099] By providing the insulating layer in the recess of the semiconductor layer of the first transistor, the conductive layer can be prevented from contacting the channel formation region of the first transistor. Further, by providing the insulating layer so as to fill the recess of the semiconductor layer of the first transistor, the conductive layer can be prevented from entering the inside of the recess, whereby the electric field of the conductive layer can be prevented from being applied to the channel formation region of the first transistor. As described above, a semiconductor device with high reliability can be implemented.

[0100] <Structure Example 1 of Semiconductor Device>

[0101] A structure example of a semiconductor device of one embodiment of the present application is described below. Specifically, a structure example of a memory cell included in a semiconductor device of one embodiment of the present application and a structure example of a transistor included in the memory cell are described.

[0102] Figure 1A is a circuit diagram illustrating a structure example of a memory cell 10. The memory cell 10 includes a transistor 100, a transistor 200, and a transistor 300.

[0103] One of the source and the drain of the transistor 100 is electrically connected to a wiring RBL. The other of the source and the drain of the transistor 100 is electrically connected to one of the source and the drain of the transistor 200. The gate of the transistor 100 is electrically connected to a wiring RWL. The other of the source and the drain of the transistor 200 is electrically connected to a wiring PL. The gate of the transistor 200 is electrically connected to one of the source and the drain of the transistor 300. The other of the source and the drain of the transistor 300 is electrically connected to a wiring WBL.

[0104] The transistor 300 can be a dual-gate transistor including two gates (a first gate and a second gate). In this case, the first gate of the transistor 300 can be referred to as a front gate or simply a gate, and the second gate can be referred to as a back gate. Alternatively, the first gate can be referred to as a back gate, and the second gate can be referred to as a front gate or simply a gate. In the following description, the first gate is referred to as a front gate or simply a gate, and the second gate is referred to as a back gate. Figure 1A In the example illustrated in FIG. 1, the gate of the transistor 300 is electrically connected to a wiring WWL, and the back gate is electrically connected to a wiring BGL.

[0105] The wiring WWL and the wiring RWL are used as word lines. The wiring WWL is supplied with a signal used to control on / off of the transistor 300. The wiring RWL is supplied with a signal used to control on / off of the transistor 100.

[0106] The wiring WBL is used as a bit line. The wiring WBL is supplied with a data signal supplied to the memory cell 10. In a case where the transistor 300 is in an on state, data corresponding to the potential of the wiring WBL is written to the memory cell 10. In a case where the transistor 300 is made to be in an off state, the data written to the memory cell 10 is held. Specifically, the gate potential of the transistor 200 is held. Thus, the wiring WWL supplied with a signal that controls the on / off of the transistor 300 can be referred to as a write word line and the wiring WBL can be referred to as a write bit line.

[0107] The wiring RBL is used as a bit line. The wiring PL is used as a power supply line and is supplied with a power supply potential. As described above, in writing data to the memory cell 10, the gate potential of the transistor 200 becomes a potential corresponding to the data. In this state, when the transistor 100 is made to be in an on state, a current having a magnitude corresponding to the gate potential of the transistor 200 flows between the wiring RBL and the wiring PL. Thus, the potential of the wiring RBL becomes a potential corresponding to the data held in the memory cell 10. As described above, the data held in the memory cell 10 can be read out. This readout can be a non-destructive readout. Thus, the wiring RWL supplied with a signal that controls the on / off of the transistor 100 can be referred to as a read word line and the wiring RBL can be referred to as a read bit line.

[0108] By controlling the potential of the wiring BGL electrically connected to the back gate of the transistor 300, the threshold voltage of the transistor 300 can be controlled. For example, by supplying the wiring BGL with a potential lower than the source potential or a potential lower than 0 V (preferably, a negative potential), the threshold voltage of the transistor 300 can be shifted in the positive direction to be always off. Thus, the gate potential of the transistor 200 can be held for a long period. Thus, the data written to the memory cell 10 can be held for a long period.

[0109] Figure 1B is a plan view that shows a structure example of the transistor 100. Figure 1C is a plan view that shows a structure example of the transistor 200. Figure 1D is a plan view that shows a structure example of the transistor 300. In addition, in Figures 1B to 1D part of the constituent elements are omitted in the plan view. Part of the constituent elements is also omitted in the plan views below.

[0110] Figure 2A is a cross-sectional view taken along the dot-dash line A1-A2 shown in Figures 1B to 1D . Figure 2B is a cross-sectional view taken along the dot-dash line B1-B2 shown in Figures 1B to 1D . Figure 2A and Figure 2B show a structure example of the memory cell 10.

[0111] The storage unit 10 includes an insulating layer 110 over a substrate (not shown), the transistor 100, the insulating layer 180a, and the insulating layer 181 over the insulating layer 110, an insulating layer 180b over the insulating layer 180a, an insulating layer 181 A over the insulating layer 180b, an insulating layer 183 over the insulating layer 181, an insulating layer 183 A over the insulating layer 181 A, the transistor 200 over the transistor 100, an insulating layer 280 over the transistor 100 and the insulating layer 183 A, the transistor 300 over the transistor 200, an insulating layer 380a over the transistor 200 and the insulating layer 280, and an insulating layer 380b over the insulating layer 380a. That is, the transistor 100, the transistor 200, and the transistor 300 are provided in this order from the bottom. The transistor 100, the transistor 200, and the transistor 300 are provided so as to have regions overlapping with one another.

[0112] In addition, the storage unit 10 can include a capacitor. For example, the conductive layer 320 or another conductive layer electrically connected to the conductive layer 320 can be used as one electrode of the capacitor. In addition, for example, a conductive layer provided in the same formed surface as the conductive layer 320 or a conductive layer provided in the same formed surface as the conductive layer 355 can be used as the other electrode of the capacitor. In this case, one electrode of the capacitor is electrically connected to the gate of the transistor 200 and one of the source and the drain of the transistor 300. In addition, for example, the other electrode of the capacitor can be supplied with a power supply potential.

[0113] The insulating layer 180a, the insulating layer 180b, the insulating layer 280, the insulating layer 380a, and the insulating layer 380b are used as interlayer films. Here, the insulating layer 180a and the insulating layer 180b are collectively referred to as an insulating layer 180, and the insulating layer 380a and the insulating layer 380b are collectively referred to as an insulating layer 380.

[0114] The transistor 100 includes the conductive layer 120a, the conductive layer 120b over the conductive layer 120a, the conductive layer 155 over the insulating layer 180a, the conductive layer 140a over the insulating layer 180b, the conductive layer 140b over the conductive layer 140a, the insulating layer 135, the semiconductor layer 130, the conductive layer 220a over the semiconductor layer 130, and the conductive layer 220b over the conductive layer 220a. Here, the conductive layer 120a and the conductive layer 120b are collectively referred to as a conductive layer 120, the conductive layer 140a and the conductive layer 140b are collectively referred to as a conductive layer 140, and the conductive layer 220a and the conductive layer 220b are collectively referred to as a conductive layer 220.

[0115] The transistor 200 includes the conductive layer 220a, the conductive layer 220b over the conductive layer 220a, the conductive layer 240a over the insulating layer 280, the conductive layer 240b over the conductive layer 240a, the semiconductor layer 230, the insulating layer 250 over the semiconductor layer 230, the conductive layer 320a over the insulating layer 250, and the conductive layer 320b over the conductive layer 320a. Here, the conductive layer 240a and the conductive layer 240b are collectively referred to as a conductive layer 240, and the conductive layer 320a and the conductive layer 320b are collectively referred to as a conductive layer 320.

[0116] The transistor 300 includes the conductive layer 320a, the conductive layer 320b over the conductive layer 320a, the conductive layer 355 over the insulating layer 380a, the conductive layer 340a over the insulating layer 380b, the conductive layer 340b over the conductive layer 340a, the insulating layer 335, the semiconductor layer 330, the insulating layer 350 over the semiconductor layer 330, the conductive layer 365a over the insulating layer 350, and the conductive layer 365b over the conductive layer 365a. Here, the conductive layer 340a and the conductive layer 340b are collectively referred to as a conductive layer 340, and the conductive layer 365a and the conductive layer 365b are collectively referred to as a conductive layer 365.

[0117] In addition, the conductive layer 120, the conductive layer 140, the conductive layer 220, the conductive layer 240, the conductive layer 320, the conductive layer 340, and the conductive layer 365 can each have a single-layer structure or a stacked-layer structure of two or more layers. Note that although the conductive layer 155 and the conductive layer 355 each have a single-layer structure in the transistors 100, 200, and 300, Figure 2A and Figure 2B The conductive layer 155 and the conductive layer 355 each have a single-layer structure in the transistors 100, 200, and 300, but the conductive layer 155 and the conductive layer 355 can each have a stacked-layer structure of two or more layers.

[0118] In the transistor 100, the conductive layer 120 is used as one of a source electrode and a drain electrode, the conductive layer 140 and the conductive layer 220 are used as the other of the source electrode and the drain electrode, the conductive layer 155 is used as a gate electrode, and the insulating layer 135 is used as a gate insulating layer. Note that the conductive layer 220 can not be included in the components of the transistor 100.

[0119] In the transistor 200, the conductive layer 220 is used as one of a source electrode and a drain electrode, the conductive layer 240 is used as the other of the source electrode and the drain electrode, the conductive layer 320 is used as a gate electrode, and the insulating layer 250 is used as a gate insulating layer. In the transistor 300, the conductive layer 320 is used as one of a source electrode and a drain electrode, the conductive layer 340 is used as the other of the source electrode and the drain electrode, the conductive layer 365 is used as a first gate electrode, the conductive layer 355 is used as a second gate electrode, the insulating layer 350 is used as a first gate insulating layer, and the insulating layer 335 is used as a second gate insulating layer. That is, the transistor 300 can be a dual-gate transistor. Here, the conductive layer 365 is also used as a gate wiring.

[0120] For example, the conductive layer 365 can be used as a gate electrode, and the conductive layer 355 can be used as a back gate electrode. In this case, the insulating layer 350 is used as a gate insulating layer, and the insulating layer 335 is used as a back gate insulating layer. Further, the conductive layer 365 can be used as a back gate electrode, and the conductive layer 355 can be used as a gate electrode. In this case, the insulating layer 350 can be used as a back gate insulating layer, and the insulating layer 335 can be used as a gate insulating layer.

[0121] As described above, the other of the source and drain electrodes of the transistor 100 and one of the source and drain electrodes of the transistor 200 can be formed using the same conductive layer 220. Thus, the other of the source and drain electrodes of the transistor 100 is electrically connected to one of the source and drain electrodes of the transistor 200. Further, the gate electrode of the transistor 200 and one of the source and drain electrodes of the transistor 300 can be formed using the same conductive layer 320. Thus, the gate electrode of the transistor 200 is electrically connected to one of the source and drain electrodes of the transistor 300.

[0122] At least part of the conductive layer 120 is used as a wiring RBL as illustrated in FIG. 1A. At least part of the conductive layer 155 is used as a wiring RWL as illustrated in FIG. 1A. At least part of the conductive layer 240 is used as a wiring PL as illustrated in FIG. 1A. At least part of the conductive layer 355 is used as a wiring BGL as illustrated in FIG. 1A. At least part of the conductive layer 340 is used as a wiring WBL as illustrated in FIG. 1A. At least part of the conductive layer 365 is used as a wiring WWL as illustrated in FIG. 1A. Figure 1A Figure 1A At least part of the conductive layer 155 is used as a wiring RWL as illustrated in FIG. 1A. At least part of the conductive layer 240 is used as a wiring PL as illustrated in FIG. 1A. At least part of the conductive layer 355 is used as a wiring BGL as illustrated in FIG. 1A. At least part of the conductive layer 340 is used as a wiring WBL as illustrated in FIG. 1A. At least part of the conductive layer 365 is used as a wiring WWL as illustrated in FIG. 1A. Figure 1A Figure 1A At least part of the conductive layer 240 is used as a wiring PL as illustrated in FIG. 1A. At least part of the conductive layer 355 is used as a wiring BGL as illustrated in FIG. 1A. At least part of the conductive layer 340 is used as a wiring WBL as illustrated in FIG. 1A. At least part of the conductive layer 365 is used as a wiring WWL as illustrated in FIG. 1A. Figure 1A Figure 1A At least part of the conductive layer 340 is used as a wiring WBL as illustrated in FIG. 1A. At least part of the conductive layer 365 is used as a wiring WWL as illustrated in FIG. 1A.

[0123] The insulating layer 180a is positioned over the conductive layer 120 and the insulating layer 110. The insulating layer 180a is provided so as to cover the top surface of the conductive layer 120b, the side surface of the conductive layer 120b, the side surface of the conductive layer 120a, and the top surface of the insulating layer 110.

[0124] The conductive layer 155 is positioned over the insulating layer 180a. The insulating layer 180b is positioned over the conductive layer 155 and the insulating layer 180a. The insulating layer 180b is provided so as to cover the top surface of the conductive layer 155, the side surface of the conductive layer 155, and the top surface of the insulating layer 180a.

[0125] The conductive layer 140 is positioned over the insulating layer 180b. Further, as described above, the insulating layer 180b is positioned over the insulating layer 180a, and the insulating layer 180a is positioned over the conductive layer 120. As described above, the insulating layer 180a and the insulating layer 180b serving as interlayer films are provided between the conductive layer 120 and the conductive layer 140.

[0126] ​​​The conductive layer 140 and the conductive layer 220, which serve as the other of the source electrode and the drain electrode of the transistor 100, are positioned over the conductive layer 120, which serves as one of the source electrode and the drain electrode of the transistor 100. Thus, the conductive layer 120 can be regarded as a lower electrode of the transistor 100, and the conductive layer 140 and the conductive layer 220 can be regarded as an upper electrode of the transistor 100.

[0127] The insulating layer 180a, the conductive layer 155, the insulating layer 180b, and the conductive layer 140 have an opening portion 190 reaching the conductive layer 120. As described above, the conductive layer 120 includes the conductive layer 120a and the conductive layer 120b over the conductive layer 120a. Figure 2A Figure 2B An example is shown in which the conductive layer 120b has a recess portion overlapping with the opening portion 190. In other words, the conductive layer 120 has a recess portion, a bottom surface of which corresponds to a bottom surface of the recess portion of the conductive layer 120b, and a side surface of which corresponds to a side surface of the recess portion of the conductive layer 120b. Here, a bottom portion of the opening portion 190 includes the bottom surface of the recess portion of the conductive layer 120b. A side wall of the opening portion 190 includes the side surface of the recess portion of the conductive layer 120b, a side surface of the insulating layer 180a, a side surface of the conductive layer 155, a side surface of the insulating layer 180b, a side surface of the conductive layer 140a, and a side surface of the conductive layer 140b.

[0128] Figure 2A Figure 2B An example is shown in which the conductive layer 120b has a first recess portion and a second recess portion which is located outside the first recess portion and has a shallow depth. In forming the opening portion 190, the second recess portion is provided in the conductive layer 120b, and then, in processing the insulating layer 135, the first recess portion is provided in the conductive layer 120b. Thus, in the conductive layer 120b, the second recess portion is located outside the first recess portion. Figure 2A Figure 2B In the example shown in FIG. 6B, a side surface of the first recess portion of the conductive layer 120b aligns with a side surface of the opening portion 190 of the insulating layer 180a. In the example shown in FIG. 6C, a side surface of the second recess portion of the conductive layer 120b aligns with a side surface of the opening portion 190 of the insulating layer 180a. In the example shown in FIG. 6D, a side surface of the first recess portion of the conductive layer 120b aligns with a side surface of the opening portion 190 of the insulating layer 180a, and a side surface of the second recess portion of the conductive layer 120b aligns with a side surface of the opening portion 190 of the insulating layer 180a. In the example shown in FIG. 6E, a side surface of the first recess portion of the conductive layer 120b aligns with a side surface of the opening portion 190 of the insulating layer 180a, and a side surface of the second recess portion of the conductive layer 120b aligns with a side surface of the opening portion 190 of the insulating layer 180a. In the example shown in FIG. 6F, a side surface of the first recess portion of the conductive layer 120b aligns with a side surface of the opening portion 190 of the insulating layer 180a, and a side surface of the second recess portion of the conductive layer 120b aligns with a side surface of the opening portion 190 of the insulating layer 180a. In the example shown in FIG. 6G, a side surface of the first recess portion of the conductive layer 120b aligns with a side surface of the opening portion 190 of the insulating layer 180a, and a side surface of the second recess portion of the conductive layer 120b aligns with a side surface of the opening portion 190 of the insulating layer 180a. In the example shown in FIG. 6H, a side surface of the first recess portion of the conductive layer 120b aligns with a side surface of the opening portion 190 of the insulating layer 180a, and a side surface of the second recess portion of the conductive layer 120b aligns with a side surface of the opening portion 190 of the insulating layer 180a.

[0129] ​​​The opening portion 190 includes an opening portion of the insulating layer 180a, an opening portion of the conductive layer 155, an opening portion of the insulating layer 180b, an opening portion of the conductive layer 140a, and an opening portion of the conductive layer 140b. In other words, the opening portion in the region where the insulating layer 180a overlaps with the conductive layer 120a is part of the opening portion 190, the opening portion in the region where the conductive layer 155 overlaps with the conductive layer 120a is another part of the opening portion 190, the opening portion in the region where the insulating layer 180b overlaps with the conductive layer 120a is part of the opening portion 190, the opening portion in the region where the conductive layer 140a overlaps with the conductive layer 120a is another part of the opening portion 190, and the opening portion in the region where the conductive layer 140b overlaps with the conductive layer 120a is another part of the opening portion 190. Further, the shape and size of the opening portion 190 of each layer can be different when viewed in plan. Further, when the top surface shape of the opening portion 190 is circular, the opening portion in each layer can be concentric or can not be concentric. For example, at least one of the centers of the opening portions in each layer can not overlap with the centers of the opening portions in the other layers.

[0130] At least part of the constituent elements of the transistor 100 is arranged inside the opening portion 190. Specifically, the insulating layer 135 and the semiconductor layer 130 are each arranged so that at least part thereof is positioned inside the opening portion 190.

[0131] The insulating layer 135 has at least a region positioned between the semiconductor layer 130 and the conductive layer 155. The insulating layer 135 is in contact with the side surface of the conductive layer 155 inside the opening portion 190. The insulating layer 135 is formed so as to cover the opening portion 190 and have a region positioned over the conductive layer 140 after the formation of the opening portion 190, and details thereof will be described later. Then, the insulating layer 135 is processed by anisotropic etching, for example, until the top surface of the conductive layer 140 is exposed. Thus, the region of the insulating layer 135 positioned over the top surface of the conductive layer 140 and the region positioned over the bottom surface of the opening portion 190 can be removed, and the insulating layer 135 can be left only on the side surface inside the opening portion 190.

[0132] Here, by forming the insulating layer 135 after the formation of the conductive layer 140, as compared to the case where the conductive layer 140 is not formed and the insulating layer 135 is formed, it is possible to inhibit the anisotropic etching of the insulating layer 135 after the region of the insulating layer 135 positioned outside the opening portion 190 is removed. Thus, for example, the side surface of the conductive layer 155 on the side of the opening portion 190 can be prevented from being exposed. Thus, for example, the conductive layer 155 can be prevented from being in contact with the semiconductor layer 130. Thus, a semiconductor device with high reliability can be achieved. Note that the transistor 100 can not include the conductive layer 140. In that case, the number of manufacturing steps of the transistor 100 can be reduced.

[0133] In Figure 2A and Figure 2B In the insulating layer 135 contacts the bottom surface and the side surface of the recess (specifically, the second recess) of the conductive layer 120b, and contacts the side surface of the insulating layer 180a, the side surface of the conductive layer 155, the side surface of the insulating layer 180b, the side surface of the conductive layer 140a, and the side surface of the conductive layer 140b inside the opening portion 190. The semiconductor layer 130 contacts the bottom surface and the side surface of the recess (specifically, the first recess) of the conductive layer 120b, the insulating layer 135, and the top surface of the conductive layer 140b. By providing the conductive layer 120b with the recess, the area where the semiconductor layer 130 contacts the conductive layer 120b can be increased. Thus, the contact resistance between the semiconductor layer 130 and the conductive layer 120b can be reduced.

[0134] The insulating layer 135 is provided along at least a portion of the side wall of the opening portion 190. The semiconductor layer 130 has a region opposing the conductive layer 155 inside the opening portion 190 with the insulating layer 135 interposed therebetween. At least a portion of the region of the semiconductor layer 130 contacts the insulating layer 135. The conductive layer 155 is provided so as to surround the semiconductor layer 130 with the insulating layer 135 interposed therebetween.

[0135] As described above, the conductive layer 155 is used as the gate electrode of the transistor 100, and the insulating layer 135 is used as the gate insulating layer of the transistor 100. Thus, the above-described region of the semiconductor layer 130 opposing the conductive layer 155 with the insulating layer 135 interposed therebetween is used as the channel formation region of the transistor 100. The region of the semiconductor layer 130 contacting the conductive layer 120 is used as one of the source region and the drain region of the transistor 100. In addition, the region of the semiconductor layer 130 contacting at least one of the conductive layer 140 and the conductive layer 220 is used as the other of the source region and the drain region of the transistor 100. That is, the channel formation region of the transistor 100 is sandwiched between the source region and the drain region.

[0136] The portion of the semiconductor layer 130 arranged inside the opening portion 190 reflects the shape of the opening portion 190. Specifically, the semiconductor layer 130 is arranged along the bottom and the side wall of the opening portion 190. Thus, the portion of the semiconductor layer 130 overlapping with the opening portion 190 is provided with a recess.

[0137] The insulating layer 181 is positioned inside the opening portion 190 on the inner side of the semiconductor layer 130. Further, the insulating layer 183 is positioned inside the opening portion 190 on the inner side of the insulating layer 181. The insulating layer 183 is positioned on the insulating layer 181. The insulating layer 181 is provided along the semiconductor layer 130. As described above, the position of the semiconductor layer 130 overlapping with the opening portion 190 is provided with a recess. Thus, the position of the insulating layer 181 overlapping with the opening portion 190 is also provided with a recess. The insulating layer 183 is provided so as to fill the opening portion 190 on the inner side of the insulating layer 181. Specifically, the insulating layer 183 is provided so as to fill the recess of the insulating layer 181. The insulating layer 183 is a planarized layer.

[0138] The conductive layer 220 is positioned on the insulating layer 183. Further, the conductive layer 220 is in contact with the region of the semiconductor layer 130 overlapping with the conductive layer 140.

[0139] By providing the insulating layer 181, the conductive layer 220 can be prevented from being in contact with the channel formation region of the semiconductor layer 130. Further, by providing the insulating layer 183 so as to fill the opening portion 190, the conductive layer 220 can be prevented from entering the inside of the opening portion 190. Thus, the electric field of the conductive layer 220 can be prevented from being applied to the channel formation region of the transistor 100. Therefore, the threshold voltage of the transistor 100 can be prevented from being varied due to the potential of the conductive layer 220. Further, the transistor 100 can be prevented from being in an on state in a period other than the period in which data held by the storage unit 10 is read. Also, the transistor 100 can be prevented from being in an off state in the period in which data held by the storage unit 10 is read. As described above, the semiconductor device including the storage unit 10 can have high reliability.

[0140] The top surface of the insulating layer 183 is positioned above the top surface of the region of the semiconductor layer 130 overlapping with the conductive layer 140. The top surface of the insulating layer 183 can be positioned, for example, at a position higher than the top surface of the region of the semiconductor layer 130 overlapping with the conductive layer 140 by the thickness of the insulating layer 181. In other words, the difference between the height of the top surface of the insulating layer 183 from the reference surface and the height of the top surface of the region of the semiconductor layer 130 overlapping with the conductive layer 140 from the reference surface can be, for example, the thickness of the insulating layer 181 or a value around the thickness. Similarly, the top surface of the insulating layer 183A is positioned above the top surface of the region of the semiconductor layer 130 overlapping with the conductive layer 140.

[0141] As the reference surface, for example, the top surface of the substrate or the interlayer film such as the insulating layer 110 can be used. The same applies to the following description.

[0142] In manufacturing the memory cell 10, after the semiconductor layer 130 is formed, a first insulating film which becomes the insulating layer 181 and a second insulating film which becomes the insulating layer 183 on the first insulating film are deposited, the details of which will be described later. Next, the second insulating film is subjected to a planarization treatment until at least a part of the top surface of the first insulating film is exposed, thereby forming the insulating layer 183. As the planarization treatment, a planarization treatment using a chemical mechanical polishing (CMP) method (also referred to as a CMP treatment) is preferable. Then, the first insulating film is processed. For example, a region of the first insulating film which does not overlap both the insulating layer 183 and the conductive layer 140 is removed. Thus, the insulating layer 181 is formed so as to overlap the insulating layer 183, and a region of the semiconductor layer 130 which overlaps the conductive layer 140 is exposed.

[0143] Here, when the second insulating film is deposited after the first insulating film is not deposited, for example, the second insulating film is subjected to a planarization treatment until at least a part of the top surface of the semiconductor layer 130 is exposed, the semiconductor layer 130 is sometimes subjected to the planarization treatment together with the second insulating film. Thus, a region of the semiconductor layer 130 which contacts the conductive layer 140 is sometimes removed. In addition, it is difficult to control the thickness of a region of the semiconductor layer 130 which overlaps the conductive layer 140. Thus, the reliability of the semiconductor device sometimes decreases.

[0144] Therefore, by depositing the second insulating film after the first insulating film is deposited, and then subjecting the second insulating film to a planarization treatment until at least a part of the top surface of the first insulating film is exposed, it is possible to prevent the semiconductor layer 130 from being subjected to the planarization treatment. Thus, it is possible to realize a semiconductor device with high reliability. In the case where the second insulating film is subjected to a planarization treatment until at least a part of the top surface of the first insulating film is exposed, the top surface of the insulating layer 183 is, for example, located at a position higher than the top surface of a region of the semiconductor layer 130 which overlaps the conductive layer 140 by the thickness of the insulating layer 181. Note that the top surface of the insulating layer 183A is, for example, located at a position higher than the top surface of a region of the semiconductor layer 130 which overlaps the conductive layer 140 by the thickness of the insulating layer 181A.

[0145] Note that, for example, the shortest distance from the top surface of the insulating layer 110 to the top surface of the conductive layer 120b which contacts the insulating layer 180a is preferably greater than the shortest distance from the top surface of the insulating layer 110 to the bottom surface of the insulating layer 181 inside the opening portion 190. Thus, it is possible to further increase the contact area of the side surface of the conductive layer 120b with the semiconductor layer 130, and thus it is possible to further reduce the contact resistance of the conductive layer 120b with the semiconductor layer 130. Thus, it is possible to increase the on-state current of the transistor 100.

[0146] Figure 3Ais a plan view showing a structure example of the semiconductor layer 130, the conductive layer 140, the insulating layer 181, the insulating layer 183, the insulating layer 181A, and the insulating layer 183A. Figure 3B is a plan view in which the semiconductor layer 130 in Figure 3A is omitted. As shown in Figure 3A and Figure 3B , the insulating layer 181A and the insulating layer 183A provided on the insulating layer 181A are provided in a manner of surrounding the semiconductor layer 130 and the conductive layer 140. Specifically, the insulating layer 181A and the insulating layer 183A are provided in a manner of surrounding, in plan view, the side surface of the semiconductor layer 130 located outside the opening portion 190 and the side surface of the conductive layer 140 on the opposite side of the side surface on the opening portion 190 side. The insulating layer 181A is provided, for example, in a manner of contacting the side surface of the semiconductor layer 130 located outside the opening portion 190 and the side surface of the conductive layer 140 on the opposite side of the side surface on the opening portion 190 side.

[0147] As shown in Figure 3A , it can be considered that the insulating layer 181A and the insulating layer 183A have the opening portion 191 overlapping the semiconductor layer 130. Further, as shown in Figure 3B , it can be considered that the insulating layer 181A and the insulating layer 183A have the opening portion 191 overlapping the conductive layer 140 and the opening portion 190. Also, it can be considered that the opening portion 191 has the island-shaped insulating layer 181 and the insulating layer 183 provided inside.

[0148] In this specification and the like, an island-shaped layer refers to a layer provided in a manner of being surrounded by an opening portion in plan view. For example, the insulating layer 181 and the insulating layer 183 are provided in a manner of being surrounded by the opening portion 191 in plan view, and thus can be said to be island-shaped layers.

[0149] The opening portion 191 includes an opening portion that the insulating layer 181A has and an opening portion that the insulating layer 183A has. In other words, the opening portion in the region where the insulating layer 181A overlaps the semiconductor layer 130 is part of the opening portion 191, and the opening portion in the region where the insulating layer 183A overlaps the semiconductor layer 130 is another part of the opening portion 191. Further, the shape and size of the opening portion 191 of each layer in plan view can also be different.

[0150] By employing the structure in which the memory cell 10 includes the insulating layer 181 A and the insulating layer 183 A, the insulating layer 181 and the insulating layer 183 can be formed without using photolithography, details of which will be described later. Thus, by employing the structure in which the memory cell 10 includes the insulating layer 181 A and the insulating layer 183 A, the number of manufacturing steps of the semiconductor device can be reduced as compared with the structure in which the memory cell 10 does not include the insulating layer 181 A and the insulating layer 183 A. Thus, the manufacturing cost of the semiconductor device can be reduced, and thus a semiconductor device at a low cost can be provided.

[0151] The insulating layer 181 and the insulating layer 181 A can be formed using the same process and the same material, details of which will be described later. In addition, the insulating layer 183 and the insulating layer 183 A can be formed using the same process and the same material.

[0152] As described above, the conductive layer 220 is positioned over the insulating layer 183. The conductive layer 220 is provided so as to cover the top surface of the insulating layer 183 and the side surface of the insulating layer 181 positioned outside the opening portion 190. The conductive layer 220 is in contact with a region of the semiconductor layer 130 overlapping with the conductive layer 140.

[0153] The insulating layer 280 is positioned over the conductive layer 220 and the insulating layer 180b. Specifically, the insulating layer 280 is positioned over the conductive layer 220, the conductive layer 140, the semiconductor layer 130, the insulating layer 181 A, and the insulating layer 183 A. The insulating layer 280 is provided so as to cover the top surface of the conductive layer 220b, the side surface of the conductive layer 220b, the side surface of the conductive layer 220a, the top surface of the semiconductor layer 130, the side surface of the insulating layer 181 A, and the top surface of the insulating layer 183 A.

[0154] The conductive layer 240 is positioned over the insulating layer 280. In addition, as described above, the insulating layer 280 is positioned over the conductive layer 220. Thus, the insulating layer 280 serving as an interlayer film is provided between the conductive layer 220 and the conductive layer 240.

[0155] The conductive layer 240 serving as the other of the source and drain electrodes of the transistor 200 is positioned over the conductive layer 220 serving as one of the source and drain electrodes of the transistor 200. Thus, the conductive layer 220 can be regarded as a lower electrode of the transistor 200, and the conductive layer 240 can be regarded as an upper electrode of the transistor 200.

[0156] Both the insulating layer 280 and the conductive layer 240 have an opening portion 290 reaching the conductive layer 220. As described above, the conductive layer 220 includes the conductive layer 220a and the conductive layer 220b over the conductive layer 220a. Figure 2A and Figure 2BAn example is shown in which the conductive layer 220b has a recess that overlaps with the opening portion 290. In other words, the conductive layer 220 has a recess whose bottom surface corresponds to the bottom surface of the recess of the conductive layer 220b and whose side surface corresponds to the side surface of the recess of the conductive layer 220b. Here, the bottom of the opening portion 290 includes the bottom surface of the recess of the conductive layer 220b. In addition, the side wall of the opening portion 290 includes the side surface of the recess of the conductive layer 220b, the side surface of the insulating layer 280, the side surface of the conductive layer 240a, and the side surface of the conductive layer 240b. In addition, Figure 2A and Figure 2B An example is shown in which the opening portion 290 overlaps with the opening portion 190.

[0157] The opening portion 290 includes the opening portion of the insulating layer 280 and the opening portion of the conductive layer 240. In other words, the opening portion in the region where the insulating layer 280 overlaps with the conductive layer 220a is part of the opening portion 290, the opening portion in the region where the conductive layer 240a overlaps with the conductive layer 220a is another part of the opening portion 290, and the opening portion in the region where the conductive layer 240b overlaps with the conductive layer 220a is another part of the opening portion 290. Further, the shape and size of the opening portion 290 of each layer can be different when viewed from above. Further, when the shape of the opening portion 290 viewed from above is circular, the opening portions in each layer can be concentric or can not be concentric. For example, at least one of the centers of the opening portions in each layer can not overlap with the centers of the opening portions in the other layers.

[0158] At least a part of the constituent elements of the transistor 200 is arranged inside the opening portion 290. Specifically, the semiconductor layer 230 and the insulating layer 250 are each arranged so that at least a part thereof is positioned inside the opening portion 290.

[0159] The semiconductor layer 230 is in contact with the bottom surface and the side surface of the recess of the conductive layer 220, the opening portion 290 on the side of the insulating layer 280, the conductive layer 240a, and the conductive layer 240b, and the top surface of the conductive layer 240b. By providing the conductive layer 220b with a recess, the area where the semiconductor layer 230 is in contact with the conductive layer 220b can be increased. Thus, the contact resistance between the semiconductor layer 230 and the conductive layer 220b can be reduced.

[0160] Here, for example, the shortest distance from the top surface of the insulating layer 110 to the top surface of the conductive layer 220b in contact with the insulating layer 280 is preferably greater than the shortest distance from the top surface of the insulating layer 110 to the bottom surface of the insulating layer 250 inside the opening portion 290. Thus, the contact area of the side surface of the conductive layer 220b with the semiconductor layer 230 can be further increased, and thus the contact resistance of the conductive layer 220b with the semiconductor layer 230 can be further reduced. Thus, the on-state current of the transistor 200 can be increased.

[0161] Further, for example, the shortest distance from the top surface of the insulating layer 110 to the top surface of the conductive layer 220b contacting the insulating layer 280 is more preferably the shortest distance from the top surface of the insulating layer 110 to the bottom surface of the conductive layer 320a inside the opening portion 290, and is further preferably greater than the shortest distance. Thus, the gate electric field is easily applied to the channel formation region of the semiconductor layer 230, and thus the electric characteristics of the transistor 200 can be improved. Furthermore, the gate electric field is also easily applied to the region of the semiconductor layer 230 contacting the conductive layer 220b, and thus the on-state current of the transistor 200 can be increased. Further, the electric characteristics of the transistor 200 can be improved regardless of whether the conductive layer 220 or the conductive layer 240 is used as a drain electrode.

[0162] The portion of the semiconductor layer 230 positioned inside the opening portion 290 reflects the shape of the opening portion 290. Specifically, the semiconductor layer 230 is provided along the bottom and the side wall of the opening portion 290. Thus, the position of the semiconductor layer 230 overlapping with the opening portion 290 is provided with a recess.

[0163] The insulating layer 250 is positioned on the semiconductor layer 230 and the insulating layer 280. The insulating layer 250 is positioned inside the semiconductor layer 230 inside the opening portion 290. The insulating layer 250 is provided so as to cover the top surface and the side surface of the semiconductor layer 230, the side surface of the conductive layer 240b, the side surface of the conductive layer 240a, and the top surface of the insulating layer 280. The insulating layer 250 can have a region in contact with the semiconductor layer 230. The insulating layer 250 can have a region in contact with the semiconductor layer 230 inside the opening portion 290, for example.

[0164] The insulating layer 250 is provided along the semiconductor layer 230. As described above, the position of the semiconductor layer 230 overlapping with the opening portion 290 is provided with a recess. Thus, the position of the insulating layer 250 overlapping with the opening portion 290 is also provided with a recess.

[0165] The conductive layer 320 is positioned on the insulating layer 250. The conductive layer 320 is positioned inside the insulating layer 250 inside the opening portion 290. The conductive layer 320 is provided so as to fill the opening portion 290 inside the insulating layer 250. Specifically, the conductive layer 320 is provided so as to fill the recess of the insulating layer 250. Figure 2A and Figure 2B An example in which the conductive layer 320a is planarized is shown.

[0166] The conductive layer 320 has a region that opposes the semiconductor layer 230 inside the opening portion 290 through the insulating layer 250. This region is used as a channel formation region of the transistor 200. A region of the semiconductor layer 230 that is in contact with the conductive layer 220 is used as one of a source region and a drain region of the transistor 200. A region of the semiconductor layer 230 that is in contact with the conductive layer 240 is used as the other of the source region and the drain region of the transistor 200. That is, like the channel formation region of the transistor 100, the channel formation region of the transistor 200 is sandwiched between the source region and the drain region.

[0167] At least one layer included in the conductive layer 320 is provided in the opening portion 290. In the case where the conductive layer 320 has a stacked-layer structure, as the transistor 200 is miniaturized and the diameter of the opening portion 290 is smaller, it is more difficult to arrange all the layers included in the conductive layer 320 in the opening portion 290. Figure 2A and Figure 2B The conductive layer 320 is illustrated as having a two-layer structure, and only the conductive layer 320a is provided in the opening portion 290 and the conductive layer 320b over the conductive layer 320a is provided at a position overlapping with the opening portion 290. Note that depending on the diameter of the opening portion 290 and the thickness of the conductive layer 320a, both the conductive layer 320a and the conductive layer 320b are sometimes positioned in the opening portion 290.

[0168] The insulating layer 380a is positioned over the conductive layer 320 and the insulating layer 250. The insulating layer 380a is provided so as to cover the top surface of the conductive layer 320b, the side surface of the conductive layer 320b, the side surface of the conductive layer 320a, and the top surface of the insulating layer 250.

[0169] The conductive layer 355 is positioned over the insulating layer 380a. The insulating layer 380b is positioned over the conductive layer 355 and the insulating layer 380a. The insulating layer 380b is provided so as to cover the top surface of the conductive layer 355, the side surface of the conductive layer 355, and the top surface of the insulating layer 380a.

[0170] The conductive layer 340 is positioned over the insulating layer 380b. Note that as described above, the insulating layer 380b is positioned over the insulating layer 380a, and the insulating layer 380a is positioned over the conductive layer 320. As described above, the insulating layer 380a and the insulating layer 380b serving as interlayer films are provided between the conductive layer 320 and the conductive layer 340.

[0171] The conductive layer 340 serving as the other of a source electrode and a drain electrode of the transistor 300 is positioned over the conductive layer 320 serving as one of the source electrode and the drain electrode of the transistor 300. Thus, the conductive layer 320 can be regarded as a lower electrode of the transistor 300, and the conductive layer 340 can be regarded as an upper electrode of the transistor 300.

[0172] The insulating layer 380a, the conductive layer 355, the insulating layer 380b, and the conductive layer 340 have an opening portion 390 reaching the conductive layer 320. As described above, the conductive layer 320 includes the conductive layer 320a and the conductive layer 320b over the conductive layer 320a. Figure 2A and Figure 2B An example is shown in which the conductive layer 320b has a recess portion overlapping with the opening portion 390. In other words, the conductive layer 320 has a recess portion whose bottom surface corresponds to the bottom surface of the recess portion of the conductive layer 320b and whose side surface corresponds to the side surface of the recess portion of the conductive layer 320b. Here, the bottom of the opening portion 390 includes the bottom surface of the recess portion of the conductive layer 320b. The side wall of the opening portion 390 includes the side surface of the recess portion of the conductive layer 320b, the side surface of the insulating layer 380a, the side surface of the conductive layer 355, the side surface of the insulating layer 380b, the side surface of the conductive layer 340a, and the side surface of the conductive layer 340b. Note that, Figure 2A and Figure 2B An example is shown in which the opening portion 390 overlaps with the opening portion 190 and the opening portion 290.

[0173] Figure 2A and Figure 2B An example is shown in which the conductive layer 320b has a first recess portion and a second recess portion which is located outside the first recess portion and has a shallow depth. In forming the opening portion 390, the second recess portion is provided in the conductive layer 320b, and then, in processing the insulating layer 335, the first recess portion is provided in the conductive layer 320b. Thus, in the conductive layer 320b, the first recess portion is provided in the opening portion 390. Figure 2A and Figure 2B In the conductive layer 320b, the side surface of the first recess portion is aligned with the side surface of the opening portion 390 of the insulating layer 380a. In addition, the side surface of the second recess portion of the conductive layer 320b is aligned with the side surface of the opening portion 390 of the insulating layer 380a, for example.

[0174] The opening 390 includes openings in insulating layer 380a, conductive layer 355, insulating layer 380b, conductive layer 340a, and conductive layer 340b. In other words, the opening in the region where insulating layer 380a overlaps with conductive layer 320a is part of opening 390; the opening in the region where conductive layer 355 overlaps with conductive layer 320a is another part of opening 390; the opening in the region where insulating layer 380b overlaps with conductive layer 320a is part of opening 390; the opening in the region where conductive layer 340a overlaps with conductive layer 320a is another part of opening 390; and the opening in the region where conductive layer 340b overlaps with conductive layer 320a is another part of opening 390. Furthermore, the shape and size of the openings 390 in each layer may differ when viewed from above. Furthermore, when the opening 390 is circular in plan view, the openings in each layer may or may not be concentric circles. For example, at least one of the centers of the openings in each layer may not overlap with the centers of the openings in other layers.

[0175] At least a portion of the constituent elements of transistor 300 are disposed inside opening 390. Specifically, insulating layer 335, semiconductor layer 330, insulating layer 350 and conductive layer 365 are all disposed such that at least a portion of them are located inside opening 390.

[0176] The insulating layer 335 has a region located between the semiconductor layer 330 and the conductive layer 355. The insulating layer 335 is in contact with the side of the conductive layer 355 inside the opening 390.

[0177] exist Figure 2A and Figure 2B In the first recess of the conductive layer 320b, the insulating layer 335 contacts the bottom and side surfaces of the recess (specifically, the second recess) of the conductive layer 320b, and also contacts the side surfaces of the insulating layer 380a, the conductive layer 355, the insulating layer 380b, the conductive layer 340a, and the conductive layer 340b inside the opening 390. The semiconductor layer 330 contacts the bottom and side surfaces of the recess (specifically, the first recess) of the conductive layer 320b, the insulating layer 335, and the top surface of the conductive layer 340b. By having a recess in the conductive layer 320b, the contact area between the semiconductor layer 330 and the conductive layer 320b can be increased. Therefore, the contact resistance between the semiconductor layer 330 and the conductive layer 320b can be reduced.

[0178] Here, for example, a shortest distance from the top surface of the insulating layer 110 to the top surface of the conductive layer 320b that contacts the insulating layer 380a is preferably greater than a shortest distance from the top surface of the insulating layer 110 to the bottom surface of the insulating layer 350 inside the opening portion 390. Thus, the contact area of the side surface of the conductive layer 320b with the semiconductor layer 330 can be further increased, and thus the contact resistance of the conductive layer 320b with the semiconductor layer 330 can be further reduced. Thus, the on-state current of the transistor 300 can be increased.

[0179] Further, for example, a shortest distance from the top surface of the insulating layer 110 to the top surface of the conductive layer 320b that contacts the insulating layer 380 is more preferably greater than or equal to a shortest distance from the top surface of the insulating layer 110 to the bottom surface of the conductive layer 365a inside the opening portion 390, and is further preferably greater than the shortest distance. Thus, a gate electric field is easily applied to the channel formation region of the semiconductor layer 330, and thus the electric characteristics of the transistor 300 can be improved. Furthermore, a gate electric field is also easily applied to the region of the semiconductor layer 330 that contacts the conductive layer 320b, and thus the on-state current of the transistor 200 can be increased. Further, the electric characteristics of the transistor 300 can be improved regardless of whether the conductive layer 320 or the conductive layer 340 is used as a drain electrode.

[0180] The insulating layer 335 is provided along at least part of the side wall of the opening portion 390. The semiconductor layer 330 has a region that faces the conductive layer 355 with the insulating layer 335 interposed therebetween inside the opening portion 390. At least part of the region of the semiconductor layer 330 contacts the insulating layer 335. The conductive layer 355 is provided in a manner surrounding the semiconductor layer 330 with the insulating layer 335 interposed therebetween.

[0181] The insulating layer 350 is positioned over the semiconductor layer 330 and the insulating layer 380b. The insulating layer 350 is positioned inside the semiconductor layer 330 inside the opening portion 390. The insulating layer 350 is provided in a manner covering the top surface and the side surface of the semiconductor layer 330, the side surface of the conductive layer 340b, the side surface of the conductive layer 340a, and the top surface of the insulating layer 380b. The insulating layer 350 can have a region in contact with the semiconductor layer 330. The insulating layer 350 can have, for example, a region in contact with the semiconductor layer 330 inside the opening portion 390.

[0182] The insulating layer 350 is provided along the semiconductor layer 330. As described above, the semiconductor layer 330 provided at a position overlapping with the opening portion 390 is provided with a recess. Thus, the insulating layer 350 provided at a position overlapping with the opening portion 390 is also provided with a recess.

[0183] The conductive layer 365 is positioned on the insulating layer 350. The conductive layer 365 is positioned inside the insulating layer 350 inside the opening portion 390. The conductive layer 365 is provided so as to fill the opening portion 390 inside the insulating layer 350. Specifically, the conductive layer 365 is provided so as to fill the recess of the insulating layer 350.

[0184] The conductive layer 365 has a region which opposes the semiconductor layer 330 inside the opening portion 390 through the insulating layer 350. This region is used as a channel formation region of the transistor 300. In addition, a region of the semiconductor layer 330 which contacts the conductive layer 320 is used as one of a source region and a drain region of the transistor 300. In addition, a region of the semiconductor layer 330 which contacts the conductive layer 340 is used as the other of the source region and the drain region of the transistor 300. That is, like the channel formation regions of the transistors 100 and 200, the channel formation region of the transistor 300 is interposed between the source region and the drain region.

[0185] The conductive layer 355 is provided so as to oppose the conductive layer 365 which is used as a gate electrode of the transistor 300 through the insulating layer 335, the semiconductor layer 330, and the insulating layer 350. Thus, the semiconductor layer 330 has a region which opposes the conductive layer 365 through the insulating layer 350 and opposes the conductive layer 355 through the insulating layer 335.

[0186] The conductive layer 355 is provided so as to surround at least part of the channel formation region of the transistor 300 through the insulating layer 335. Thus, the conductive layer 355 is used as a back gate electrode of the transistor 300. Thus, by controlling the potential of the conductive layer 355, the threshold voltage of the transistor 300 can be controlled. For example, by supplying a potential lower than the source potential or a potential lower than 0 V (preferably, a negative potential) to the conductive layer 355, the threshold voltage of the transistor 300 can be shifted in the positive direction and made to be always off. Thus, as described above, the gate potential of the transistor 200 can be held for a long period. Thus, data written to the memory cell 10 can be held for a long period.

[0187] At least one layer which constitutes the conductive layer 365 is provided inside the opening portion 390. In the case where the conductive layer 365 has a stacked-layer structure, as the transistor 300 is miniaturized and the diameter of the opening portion 390 is smaller, it is more difficult to arrange all the layers which constitute the conductive layer 365 in the opening portion 390. Figure 2A and Figure 2B An example is shown in which the conductive layer 365 has a two-layer structure, only the conductive layer 365a is provided inside the opening portion 390, and the conductive layer 365b on the conductive layer 365a is provided at a position overlapping with the opening portion 390. Note that depending on the diameter of the opening portion 390 and the thickness of the conductive layer 365a, both the conductive layer 365a and the conductive layer 365b are sometimes positioned inside the opening portion 390.

[0188] The semiconductor layer 130 including the channel formation region of the transistor 100, the semiconductor layer 230 including the channel formation region of the transistor 200, and the semiconductor layer 330 including the channel formation region of the transistor 300 can each include a metal oxide (also referred to as an oxide semiconductor) used as a semiconductor. In this case, the transistor 100, the transistor 200, and the transistor 300 can be referred to as OS transistors.

[0189] In an OS transistor, when oxygen vacancies (V O ) and impurities exist in the channel formation region of an oxide semiconductor, electrical characteristics easily vary and reliability can be reduced. Furthermore, hydrogen in the vicinity of an oxygen vacancy forms a defect (hereinafter referred to as V O H) in which hydrogen enters an oxygen vacancy, and an electron serving as a carrier can be generated. Thus, when oxygen vacancies are included in the channel formation region of an oxide semiconductor, an OS transistor easily has a normally-on characteristic. Thus, in the channel formation region of an oxide semiconductor, it is preferable to reduce oxygen vacancies and impurities as much as possible. In other words, it is preferable that the carrier concentration of the channel formation region in an oxide semiconductor be reduced and be i-type (intrinsic) or substantially i-type.

[0190] On the other hand, the source region and the drain region of an OS transistor are preferably regions in which the carrier concentration is increased due to a larger number of oxygen vacancies, a larger number of V O H, or a higher concentration of impurities such as hydrogen, nitrogen, and a metal element, whereby the resistance is reduced. That is, the source region and the drain region of an OS transistor are preferably regions in which the carrier concentration is higher and the resistance is lower than in the channel formation region.

[0191] In the case where the transistor 100 is an OS transistor, the conductive layer 120b and the conductive layer 140b preferably use a conductive material including oxygen. By this means, the contact resistance between the semiconductor layer 130 and the conductive layer 120b and the contact resistance between the semiconductor layer 130 and the conductive layer 140b can be reduced. Similarly, in the case where the transistor 200 is an OS transistor, the conductive layer 220b and the conductive layer 240b preferably use a conductive material including oxygen. Furthermore, in the case where the transistor 300 is an OS transistor, the conductive layer 320b and the conductive layer 340b preferably use a conductive material including oxygen.

[0192] When the conductive layer 120 and the conductive layer 140 have a stacked structure, it is preferable that a conductive material including oxygen be used for the layer having the largest contact area with the semiconductor layer 130 in the stacked structure, so that the contact resistance with the semiconductor layer 130 can be reduced. Thus, for example, a conductive material including oxygen is preferably used for the conductive layer 120b and the conductive layer 140b. The same applies to the conductive layer 220, the conductive layer 240, the conductive layer 320, and the conductive layer 340.

[0193] Alternatively, in the case where the conductive layer 120 and the conductive layer 140 have a stacked structure, the use of a conductive material containing oxygen for the layer closest to the channel formation region in the stacked structure can reduce the contact resistance with the semiconductor layer 130, and can shorten the current path between the source and the drain, thereby increasing the on-state current of the transistor 100. Thus, for example, the conductive layer 120b and the conductive layer 140a are preferably formed using a conductive material containing oxygen. The same applies to the conductive layer 220, the conductive layer 240, the conductive layer 320, and the conductive layer 340. Specifically, the conductive layer 220b, the conductive layer 240a, the conductive layer 320b, and the conductive layer 340a are preferably formed using a conductive material containing oxygen.

[0194] As the conductive material containing oxygen, a metal oxide having conductivity (also referred to as an oxide conductor) is preferably used.

[0195] Figure 2A and Figure 2B A structure in which the end portion of the conductive layer 140a, the end portion of the conductive layer 140b, and the end portion of the semiconductor layer 130 are aligned on the outer side of the opening portion 190 is shown. Note that Figure 2A and Figure 2B A structure in which the end portion of the conductive layer 240a, the end portion of the conductive layer 240b, and the end portion of the semiconductor layer 230 are aligned on the outer side of the opening portion 290 is shown. Note that Figure 2A and Figure 2B A structure in which the end portion of the conductive layer 340a, the end portion of the conductive layer 340b, and the end portion of the semiconductor layer 330 are aligned on the outer side of the opening portion 390 is shown. As the example of the manufacturing method described later, by processing the conductive layer 140a, the conductive layer 140b, and the semiconductor layer 130 using the same mask, the above end portions of these layers can have the structure shown in Figure 2A and Figure 2B Note that by processing the conductive layer 240a, the conductive layer 240b, and the semiconductor layer 230 using the same mask, the above end portions of these layers can have the structure shown in Figure 2A and Figure 2B Note that by processing the conductive layer 340a, the conductive layer 340b, and the semiconductor layer 330 using the same mask, the above end portions of these layers can have the structure shown in Figure 2A and Figure 2BThe illustrated structure. Thereby, the number of masks required for manufacturing the semiconductor device can be reduced, and thus is preferable. Note that the present application is not limited to this. For example, in the X direction or the Y direction, any of the end portion of the semiconductor layer 130, the end portion of the conductive layer 140a, and the end portion of the conductive layer 140b can be positioned on the inner side or the outer side of the other. Similarly, for example, in the X direction or the Y direction, any of the end portion of the semiconductor layer 230, the end portion of the conductive layer 240a, and the end portion of the conductive layer 240b can be positioned on the inner side or the outer side of the other. Further, any of the end portion of the semiconductor layer 330, the end portion of the conductive layer 340a, and the end portion of the conductive layer 340b can be positioned on the inner side or the outer side of the other.

[0196] The conductive layer 140 has an opening portion 190 in a region overlapping with the conductive layer 120. Further, the conductive layer 140 is preferably not positioned inside the opening portion 190 that the insulating layer 180b has, for example. That is, the conductive layer 140 preferably has no region in contact with a side surface of the insulating layer 180b inside the opening portion 190. By employing such a structure, the opening portion 190 can be formed at once in the conductive layer 140, the insulating layer 180b, the conductive layer 155, and the insulating layer 180a. Further, when the side surface of the conductive layer 140, the side surface of the insulating layer 180b, the side surface of the conductive layer 155, and the side surface of the insulating layer 180a are aligned inside the opening portion 190, the thickness of the insulating layer 135, the semiconductor layer 130, and the like provided inside the opening portion 190 can be made uniform. Further, the insulating layer 135, the semiconductor layer 130, and the like can be prevented from being broken due to a step of the conductive layer 140 and the insulating layer 180b, and the like.

[0197] The conductive layer 240 and the conductive layer 340 are the same. Specifically, for example, it is preferable that the conductive layer 240 has an opening portion 290 in a region overlapping with the conductive layer 220 and is not positioned inside the opening portion 290 that the insulating layer 280 has. Further, for example, it is preferable that the conductive layer 340 has an opening portion 390 in a region overlapping with the conductive layer 320 and is not positioned inside the opening portion 390 that the insulating layer 380b has.

[0198] Although in the above description, the conductive layer 140, the conductive layer 240, and the conductive layer 340 are described as examples of the conductive layer 140a and the conductive layer 140b, the conductive layer 240a and the conductive layer 240b, and the conductive layer 340a and the conductive layer 340b, respectively, the present application is not limited to this. For example, the conductive layer 140, the conductive layer 240, and the conductive layer 340 can be described as examples of the conductive layer 140a and the conductive layer 140b, the conductive layer 240a and the conductive layer 240b, and the conductive layer 340a and the conductive layer 340b, respectively. Figure 2A and Figure 2BThe side surface of the conductive layer 140 inside the opening portion 190 can be flush with (or can be said to be aligned with, or substantially aligned with) the side surface of the insulating layer 180b inside the opening portion 190, as shown in FIG. 1, but the present application is not limited to this. For example, the side surface of the conductive layer 140 inside the opening portion 190 can be discontinuous with the side surface of the insulating layer 180b inside the opening portion 190. Further, the inclination of the side surface of the conductive layer 140 inside the opening portion 190 can be different from the inclination of the side surface of the insulating layer 180b inside the opening portion 190. At this time, for example, the tapering angle of the side surface of the conductive layer 140 inside the opening portion 190 is preferably smaller than the tapering angle of the side surface of the insulating layer 180b inside the opening portion 190. By adopting such a structure, the coverage of the semiconductor layer 130 to the side surface of the conductive layer 140 inside the opening portion 190 is improved, and thus defects such as voids can be reduced. Further, in the case where the insulating layer 180a and the insulating layer 180b each have a stacked structure, the inclinations of the side surfaces of the respective layers inside the opening portion 190 can be different. Similarly, in the case where the conductive layer 140 has a stacked structure, the inclinations of the side surfaces of the respective layers inside the opening portion 190 can be different. The same applies to the inclinations of the side surfaces of the respective layers inside the opening portion 290 and the inclinations of the side surfaces of the respective layers inside the opening portion 390.

[0199] The transistor 100, the transistor 200, and the transistor 300 each are a vertical transistor. The vertical transistor can have a source electrode, a semiconductor layer, and a drain electrode arranged in a manner of overlapping with each other. Specifically, as shown in FIGS. 1, 2, and 3, the conductive layer 120, the semiconductor layer 130, and the conductive layer 140 can be arranged in a manner of overlapping with each other. Further, the conductive layer 220, the semiconductor layer 230, and the conductive layer 240 can be arranged in a manner of overlapping with each other. Moreover, the conductive layer 320, the semiconductor layer 330, and the conductive layer 340 can be arranged in a manner of overlapping with each other. For example, the conductive layer 120, the semiconductor layer 130, the conductive layer 140, the conductive layer 220, the semiconductor layer 230, the conductive layer 240, the conductive layer 320, the semiconductor layer 330, and the conductive layer 340 can be arranged in a manner of overlapping with each other. Figure 2A Figure 2B The transistor 100, the transistor 200, and the transistor 300 each are a vertical transistor. The vertical transistor can have a source electrode, a semiconductor layer, and a drain electrode arranged in a manner of overlapping with each other. Specifically, as shown in FIGS. 1, 2, and 3, the conductive layer 120, the semiconductor layer 130, and the conductive layer 140 can be arranged in a manner of overlapping with each other. Further, the conductive layer 220, the semiconductor layer 230, and the conductive layer 240 can be arranged in a manner of overlapping with each other. Moreover, the conductive layer 320, the semiconductor layer 330, and the conductive layer 340 can be arranged in a manner of overlapping with each other. For example, the conductive layer 120, the semiconductor layer 130, the conductive layer 140, the conductive layer 220, the semiconductor layer 230, the conductive layer 240, the conductive layer 320, the semiconductor layer 330, and the conductive layer 340 can be arranged in a manner of overlapping with each other.

[0200] ​As described above, in the storage unit 10, the transistor 100, the transistor 200, and the transistor 300 can be provided in a stacked manner. Further, as described above, the transistor 100, the transistor 200, and the transistor 300 can each be a vertical transistor, and the source electrode, the semiconductor layer, and the drain electrode can be provided so as to overlap with one another. Furthermore, by providing the transistor 100, the transistor 200, and the transistor 300 in a stacked manner from the bottom to the top, the same conductive layer can be used for the other of the source electrode and the drain electrode of the transistor 100 and one of the source electrode and the drain electrode of the transistor 200. Further, the same conductive layer can be used for the gate electrode of the transistor 200 and one of the source electrode and the drain electrode of the transistor 300.

[0201] As described above, in the storage unit 10, the transistor 100, the transistor 200, and the transistor 300 can be provided in a stacked manner. Further, as described above, the transistor 100, the transistor 200, and the transistor 300 can each be a vertical transistor, and the source electrode, the semiconductor layer, and the drain electrode can be provided so as to overlap with one another. Furthermore, by providing the transistor 100, the transistor 200, and the transistor 300 in a stacked manner from the bottom to the top, the same conductive layer can be used for the other of the source electrode and the drain electrode of the transistor 100 and one of the source electrode and the drain electrode of the transistor 200. Further, the same conductive layer can be used for the gate electrode of the transistor 200 and one of the source electrode and the drain electrode of the transistor 300.

[0202] Thus, for example, as compared to a case where two or three of the transistor 100, the transistor 200, and the transistor 300 are formed over the same formed surface and the transistor 100, the transistor 200, and the transistor 300 are each a so-called planar transistor, the area occupied by the storage unit can be reduced. Accordingly, a semiconductor device capable of miniaturization or high integration can be provided.

[0203] Figure 3C is a plan view of a cross section taken along the dotted line A3-A4 in FIG. 1A and a cross section taken along the dotted line B3-B4 in FIG. 1A. Figure 2A is a plan view of a cross section taken along the dotted line A3-A4 in FIG. 1A and a cross section taken along the dotted line B3-B4 in FIG. 1A. Figure 2B is a plan view of a cross section taken along the dotted line A5-A6 in FIG. 1B and a cross section taken along the dotted line B5-B6 in FIG. 1B. Figure 3D is a plan view of a cross section taken along the dotted line A5-A6 in FIG. 1B and a cross section taken along the dotted line B5-B6 in FIG. 1B. Figure 2A is a plan view of a cross section taken along the dotted line A5-A6 in FIG. 1B and a cross section taken along the dotted line B5-B6 in FIG. 1B. Figure 2B is a plan view of a cross section taken along the dotted line A5-A6 in FIG. 1B and a cross section taken along the dotted line B5-B6 in FIG. 1B. Figure 3C is a plan view of a cross section taken along the dotted line A5-A6 in FIG. 1B and a cross section taken along the dotted line B5-B6 in FIG. 1B. Figure 3D is a plan view of a cross section taken along the dotted line A5-A6 in FIG. 1B and a cross section taken along the dotted line B5-B6 in FIG. 1B. Figure 4A is an enlarged view of a region including the transistor 100. Figure 2B is an enlarged view of a region including the transistor 100. Figure 4B is an enlarged view of a region including the transistor 300. Figure 2B is an enlarged view of a region including the transistor 300.

[0204] As Figure 3CAs shown, the conductive layer 155 serving as the gate electrode of the transistor 100 is provided with an opening portion 190, and inside the opening portion 190, a concentrically circular insulating layer 183, an insulating layer 181, a semiconductor layer 130, and an insulating layer 135 are provided in this order from the inside. Thus, the entire circumference of the semiconductor layer 130 can be used as a channel formation region when viewed in plan. Further, as shown in FIG. 1B, the conductive layer 155 is provided with a recess portion 195 in the opening portion 190. The recess portion 195 is formed in the conductive layer 155 so as to be recessed from the surface of the conductive layer 155. Thus, the recess portion 195 can be used as a storage capacitor. Figure 3D As shown, the conductive layer 355 serving as the back gate electrode of the transistor 300 is provided with an opening portion 390, and inside the opening portion 390, a concentrically circular conductive layer 365a, an insulating layer 350, a semiconductor layer 330, and an insulating layer 335 are provided in this order from the inside. Thus, the side surface of the conductive layer 365a provided at the center opposes the side surface of the semiconductor layer 330 with the insulating layer 350 interposed therebetween. Thus, the entire circumference of the semiconductor layer 330 is a channel formation region when viewed in plan.

[0205] Thus, for example, the channel width of the transistor 100 is determined in accordance with the outer circumference length of the semiconductor layer 130, and the channel width of the transistor 300 is determined in accordance with the outer circumference length of the semiconductor layer 330. That is, the channel width of the transistor 100 is determined in accordance with the size of the width (diameter in the case where the shape of the opening portion 190 when viewed in plan is circular) of the opening portion 190. Similarly, the channel width of the transistor 300 is determined in accordance with the size of the width (diameter in the case where the shape of the opening portion 390 when viewed in plan is circular) of the opening portion 390. Figure 3C The width D1 of the opening portion 190 and the channel width W1 of the transistor 100 are shown. Further, the width D1 of the opening portion 190 is shown. Figure 3D The width D2 of the opening portion 390 and the channel width W2 of the transistor 300 are shown. Further, the width D2 of the opening portion 390 is shown. Figure 4A The width D1 of the opening portion 190 is shown. Figure 4B The width D2 of the opening portion 390 is shown.

[0206] Further, the width D1 of the opening portion 190 and the width D2 of the opening portion 390 sometimes vary in the depth direction (for example, the Z direction). As the width D1, the shortest distance between the two sides of the opening portion 190 on the side of the conductive layer 155 in a cross section can be used. In other words, as the width D1 of the opening portion 190, the minimum value of the width of the opening portion 190 in the conductive layer 155 can be used. Further, the width of the opening portion 190 at the highest position, the width of the opening portion 190 at the lowest position, the width of the opening portion 190 at the position of the intermediate point of these, or the average of these three widths in the conductive layer 155 can be used as the width D1. Here, an example in which the width of the opening portion 190 of the conductive layer 155 is used to determine the width D1 is shown, but the method of determining the width D1 is not particularly limited. For example, as the width D1, the shortest distance between the two sides of the opening portion 190 on the side of the insulating layer 180a, the insulating layer 180b, the conductive layer 140a, or the conductive layer 140b can be used. Further, the width of the opening portion 190 at the highest position, the width of the opening portion 190 at the lowest position, the width of the opening portion 190 at the position of the intermediate point of these, or the average of these three widths in the insulating layer 180a, the insulating layer 180b, the conductive layer 140a, or the conductive layer 140b can be used as the width D1. Here, as for the width D2, by replacing the conductive layer 155, the opening portion 190, the insulating layer 180a, the insulating layer 180b, the conductive layer 140a, and the conductive layer 140b with the conductive layer 355, the opening portion 390, the insulating layer 380a, the insulating layer 380b, the conductive layer 340a, and the conductive layer 340b, respectively, the description of the width D1 can be referred to.

[0207] In the case where the opening portion 190 and the opening portion 390 are formed using photolithography, the width D1 of the opening portion 190 and the width D2 of the opening portion 390 are limited by the exposure limit of photolithography, and further miniaturization is difficult. Further, the width D1 of the opening portion 190 is set in accordance with the thickness of each of the insulating layer 135, the semiconductor layer 130, the insulating layer 181, and the insulating layer 183 provided inside the opening portion 190. The width D2 of the opening portion 390 is set in accordance with the thickness of each of the insulating layer 335, the semiconductor layer 330, the insulating layer 350, and the conductive layer 365a provided inside the opening portion 390. The width D1 of the opening portion 190 and the width D2 of the opening portion 390 are, for example, preferably 5 nm or more and 100 nm or less, more preferably 5 nm or more and 60 nm or less, still more preferably 10 nm or more and 50 nm or less, further preferably 10 nm or more and 40 nm or less, and yet further preferably 20 nm or more and 30 nm or less. Note that in the case where the opening portion 190 is circular when viewed from above, the width D1 of the opening portion 190 corresponds to the diameter of the opening portion 190, and the channel width W1 can be calculated as "D1 x π". Similarly, in the case where the opening portion 390 is circular when viewed from above, the width D2 of the opening portion 390 corresponds to the diameter of the opening portion 390, and the channel width W2 can be calculated as "D2 x π".

[0208] The channel width of the transistor 200 and the width of the opening portion 290 can be described with reference to the above description of the channel width W2 of the transistor 300 and the width D2 of the opening portion 390. Here, as the width of the opening portion 290, the shortest distance between the two side surfaces of the opening portion 290 of the insulating layer 280 in a cross-sectional view can be used. In other words, as the width of the opening portion 290, the minimum value of the width of the opening portion 290 in the insulating layer 280 can be used. Alternatively, the width of the opening portion 290 at the highest position, the width of the opening portion 290 at the lowest position, the width of the opening portion 290 at the position of the middle point of these, or the average value of these three widths in the insulating layer 280 can be used as the width of the opening portion 290. Here, as the width of the opening portion 290, the shortest distance between the two side surfaces of the opening portion 290 of the insulating layer 280, the conductive layer 240a, or the conductive layer 240b can be used. Alternatively, the width of the opening portion 290 at the highest position, the width of the opening portion 290 at the lowest position, the width of the opening portion 290 at the position of the middle point of these, or the average value of these three widths in the insulating layer 280, the conductive layer 240a, or the conductive layer 240b can be used as the width of the opening portion 290.

[0209] Although this embodiment shows an example where openings 190, 290, and 390 are circular in top view, the invention is not limited thereto. The shapes of openings 190, 290, and 390 in top view can be, for example, circular, elliptical, or other approximate circular shapes, triangles, quadrilaterals (including rectangles, rhombuses, and squares), pentagons, star-shaped polygons, or polygons with rounded corners. The polygons can also be concave polygons (polygons with at least one interior angle exceeding 180 degrees) or convex polygons (polygons with all interior angles less than 180 degrees). Figures 1B to 1D and Figures 3A to 3D As shown, openings 190, 290, and 390 preferably have a circular shape when viewed from above. By making them circular, the machining accuracy during the formation of the openings can be improved, and fine openings can be formed. In this specification, the circular shape is not limited to a perfect circle.

[0210] As mentioned above, Figure 4A It includes Figure 2B A magnified view of the region of transistor 100 shown. Figure 4A In the diagram, regions 130i, 130n1, and 130n2 are shown as areas of semiconductor layer 130. Note that in... Figure 4A In the semiconductor layer 130, the shaded lines of regions 130n1 and 130n2 are, for example, different from the shaded line of region 130i.

[0211] Region 130i is the area inside the opening 190 that faces the conductive layer 155 across the insulating layer 135. At least a portion of region 130i can contact the insulating layer 135. Specifically, the outer surface (on the conductive layer 155 side) of the region of region 130i located inside the opening 190 can contact the insulating layer 135.

[0212] Region 130n1 is the region in contact with conductive layer 120b and its vicinity. Region 130n2 is the region in contact with conductive layer 140b and its vicinity. For example, region 130n2 may include the region of semiconductor layer 130 overlapping conductive layer 140b.

[0213] Region 130i can be the channel formation region of transistor 100. Region 130n1 can be one of the source region and drain region of transistor 100. Region 130n2 can be the other of the source region and drain region of transistor 100. Regions 130n1 and 130n2 are low-resistance regions with a higher carrier concentration than region 130i.

[0214] The conductive layer 220 is disposed in contact with region 130n2. Furthermore, the top surface of the insulating layer 183 is located above the top surface of region 130n2 of the semiconductor layer 130. The top surface of the insulating layer 183 may, for example, be located at a point where it is higher than the top surface of region 130n2 of the semiconductor layer 130 by a thickness of the insulating layer 181. In other words, the difference between the height of the top surface of the insulating layer 183 from the reference surface and the height of the top surface of region 130n2 of the semiconductor layer 130 from the reference surface may, for example, be the thickness of the insulating layer 181 or a value close to it. As described above, the reference surface may, for example, be the substrate surface or the top surface of an interlayer film such as the insulating layer 110. Similarly, the top surface of the insulating layer 183A is located above the top surface of region 130n2 of the semiconductor layer 130.

[0215] By employing a structure where the top surface of the insulating layer 183 is located above the top surface of region 130n2 of the semiconductor layer 130, the reliability of the semiconductor device can be prevented from decreasing due to the manufacturing process of the semiconductor device. Therefore, a highly reliable semiconductor device can be provided.

[0216] As mentioned above, Figure 4B It includes Figure 2B A magnified view of the region of transistor 300 shown. Figure 4B In the diagram, regions 330i, 330n1, and 330n2 are shown as the semiconductor layer 330. Note that in... Figure 4B In the semiconductor layer 330, the shaded lines of regions 330n1 and 330n2 are different from the shaded lines of region 330i.

[0217] Region 330i is the region inside the opening 390 that faces the conductive layer 365a across the insulating layer 350. Region 330n1 is the region in contact with the conductive layer 320b and its vicinity. Region 330n2 is the region in contact with the conductive layer 340b and its vicinity. For example, region 330n2 may include the region of the semiconductor layer 330 overlapping the conductive layer 340b.

[0218] Region 330i can be the channel formation region of transistor 300. Region 330n1 can be one of the source and drain regions of transistor 300. Region 330n2 can be the other of the source and drain regions of transistor 300. Regions 330n1 and 330n2 are low-resistance regions with a higher carrier concentration than region 330i.

[0219] In addition, Figure 4B In the diagram, region 330dg is shown as a region of semiconductor layer 330. Region 330dg is a region that is opposite to conductive layer 365 across insulating layer 350 and opposite to conductive layer 355 across insulating layer 335. Region 330dg can be a region included in region 330i.

[0220] As for the channel formation region, the source region, and the drain region of the transistor 200, the above description of the channel formation region, the source region, and the drain region of the transistor 300 can be referred to by replacing the semiconductor layer 330, the opening 390, the insulating layer 350, the conductive layer 365a, the conductive layer 320b, and the conductive layer 340b with the semiconductor layer 230, the opening 290, the insulating layer 250, the conductive layer 320a, the conductive layer 220b, and the conductive layer 240b, respectively.

[0221] The channel length of a planar transistor is limited by the exposure limit of a photolithography method, and further miniaturization is difficult. In one embodiment of the present application, however, the channel length of the transistor 200 can be set in accordance with the thickness of the insulating layer 280. Further, the channel length of the transistor 300 can be set in accordance with the thickness of the insulating layer 380a, the conductive layer 355, and the insulating layer 380b. Thus, a very fine structure in which the channel lengths of the transistor 200 and the transistor 300 are below the exposure limit of the photolithography method can be realized. Specifically, the channel lengths of the transistor 200 and the transistor 300 can be, for example, greater than or equal to 0.1 nm and less than or equal to 60 nm, greater than or equal to 0.1 nm and less than or equal to 50 nm, greater than or equal to 1 nm and less than or equal to 40 nm, greater than or equal to 1 nm and less than or equal to 30 nm, greater than or equal to 5 nm and less than or equal to 20 nm, or greater than or equal to 5 nm and less than or equal to 10 nm. Further, the channel length of the transistor 100 can be set in accordance with the thickness of the conductive layer 155. Thus, like the channel lengths of the transistor 200 and the transistor 300, the transistor 100 can also have a very fine structure in which the channel length is below the exposure limit of the photolithography method.

[0222] Thus, the on-state current of the transistor 100, the transistor 200, and the transistor 300 included in the memory cell 10 can be greater than that of a planar transistor, for example. Thus, a semiconductor device with high operation speed can be provided.

[0223] Further, one or both of the channel formation region and the source and drain regions can be provided in the opening in the transistor 100, the transistor 200, and the transistor 300. Thus, compared to the case where planar transistors in which the channel formation region, the source region, and the drain region are provided on the XY plane are used as the transistor 100, the transistor 200, and the transistor 300, the area occupied by the memory cell 10 can be reduced. As described above, a semiconductor device capable of miniaturization or high integration can be provided.

[0224] <Materials for Semiconductor Device>

[0225] Materials used for the semiconductor device of this embodiment are described below. Each layer included in the semiconductor device of this embodiment can have a single-layer structure or a stacked-layer structure. Figure 2A and Figure 2B An example in which the conductive layer 120a, the conductive layer 220a, and the conductive layer 320a have a single-layer structure is shown. Further, Figure 4A and Figure 4B An example in which the conductive layer 120a, the conductive layer 220a, and the conductive layer 320a have a stacked-layer structure is shown.

[0226] [Semiconductor Layer]

[0227] As described above, the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 have a channel formation region. The semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 also have a source region and a drain region. The source region and the drain region are low-resistance regions in which the carrier concentration is higher than that of the channel formation region. The semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 can also have a stacked-layer structure of two or more layers. Hereinafter, a material which can be used for the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 when the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 are oxide semiconductor layers is described.

[0228] There is no particular limitation on the crystallinity of the semiconductor material used for the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330, and an amorphous semiconductor, a single crystal semiconductor, or a semiconductor having crystallinity other than a single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or a semiconductor in which part of the semiconductor has a crystal region) can be used. When a single crystal semiconductor or a semiconductor having crystallinity is used, the characteristics of the transistor can be inhibited from being deteriorated, and is thus preferable.

[0229] The band gap of the metal oxide used as a semiconductor is preferably 2.0 eV or more, further preferably 2.5 eV or more. By using a metal oxide having a wide band gap, the off-state current of the transistor can be reduced. The off-state current of the OS transistor is small, so that power consumption of the semiconductor device can be sufficiently reduced. Further, the frequency characteristics of the OS transistor are high, so that the semiconductor device can operate at high speed.

[0230] As for the oxide semiconductor layer which can be used as the semiconductor layer of the transistor of one embodiment of the present application, reference can be made to the description in Embodiment 2. Detailed description thereof is omitted here.

[0231] Further, a transistor using another semiconductor material in the channel formation region can be used for the semiconductor device of this embodiment. As the other semiconductor material, a semiconductor formed of a single element or a compound semiconductor, for example, can be given. As the semiconductor formed of a single element, silicon or germanium, for example, can be given. As the compound semiconductor, gallium arsenide and silicon germanium, for example, can be given. Further, as the compound semiconductor, an organic semiconductor and a nitride semiconductor, for example, can be given. The above oxide semiconductor is one of compound semiconductors. These semiconductor materials can contain impurities as dopants.

[0232] As the semiconductor material that can be used for a transistor, silicon can be given, for example, single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. As the polycrystalline silicon, low-temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon), for example, can be given.

[0233] The semiconductor layer of the transistor can also include a layered material that functions as a semiconductor. The layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds such as van der Waals bonds, which are weaker than covalent bonds and ionic bonds. The layered material has high conductivity in a unit layer, i.e., high two-dimensional conductivity. By using a material that functions as a semiconductor and has high two-dimensional conductivity for the channel formation region, a transistor with a large on-state current can be provided.

[0234] As the above layered material, graphene, silicene, a chalcogenide, and the like, for example, can be given. The chalcogenide is a compound containing an oxygen group element (a group 16 element). Further, as the chalcogenide, a transition metal chalcogenide, a group 13 chalcogenide, and the like can be given. As the transition metal chalcogenide that can be used for the semiconductor layer of the transistor, molybdenum sulfide (typically, MoS2), molybdenum selenide (typically, MoSe2), molybdenum telluride (typically, MoTe2), tungsten sulfide (typically, WS2), tungsten selenide (typically, WSe2), tungsten telluride (typically, WTe2), hafnium sulfide (typically, HfS2), hafnium selenide (typically, HfSe2), zirconium sulfide (typically, ZrS2), zirconium selenide (typically, ZrSe2), and the like, for example, can be given.

[0235] [Insulating layer]

[0236] The insulating layers (insulating layer 110, insulating layer 135, insulating layer 180a, insulating layer 180b, insulating layer 181, insulating layer 181A, insulating layer 183, insulating layer 183A, insulating layer 250, insulating layer 280, insulating layer 335, insulating layer 350, insulating layer 380a, and insulating layer 380b) included in the semiconductor device are preferably all inorganic insulating films. As the inorganic insulating film, for example, an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film can be given. As the oxide insulating film, for example, a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminum oxide film can be given. As the nitride insulating film, for example, a silicon nitride film and an aluminum nitride film can be given. As the oxynitride insulating film, for example, a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, a yttrium oxynitride film, and a hafnium oxynitride film can be given. As the nitride oxide insulating film, for example, a silicon nitride oxide film and an aluminum nitride oxide film can be given. Further, as the insulating layer included in the semiconductor device, an organic insulating film can be used.

[0237] For example, when miniaturization and high integration of a transistor are performed, a problem such as a leakage current might occur due to thinning of a gate insulating layer. By using a high-k material as the gate insulating layer, low voltage driving at the time of transistor operation can be realized while the physical thickness is kept. Further, an equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. On the other hand, by using a material with low relative permittivity for an insulating layer serving as an interlayer film, a parasitic capacitance generated between wirings can be reduced. Thus, it is preferable to select a material depending on the function of the insulating layer. Further, a material with low relative permittivity is also a material with high dielectric strength.

[0238] As a material with high relative permittivity (high-k), for example, an aluminum oxide, a gallium oxide, a hafnium oxide, a tantalum oxide, a zirconium oxide, a hafnium zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium can be given.

[0239] As a material with low relative permittivity, for example, an inorganic insulating material such as a silicon oxide, a silicon oxynitride, and a silicon nitride oxide, a resin such as a polyester, a polyolefin, a polyamide (nylon, aramid, and the like), a polyimide, a polycarbonate, and an acrylic resin can be given. Further, as an inorganic insulating material with low relative permittivity other than the above, for example, a silicon oxide to which fluorine is added, a silicon oxide to which carbon is added, a silicon oxide to which carbon and nitrogen are added, and the like can be given. Further, a porous silicon oxide can be given. Further, these silicon oxides can contain nitrogen.

[0240] Further, as the insulating layer included in the semiconductor device, a material having ferroelectricity can be used. As the material having ferroelectricity, hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0) and the like. Further, as the material having ferroelectricity, a material to which an element J1 (here, the element J1 is one or a plurality of elements selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, and the like) is added to hafnium oxide can be given. Here, the ratio of the number of atoms of hafnium to the number of atoms of the element J1 can be appropriately set, and for example, the ratio of the number of atoms of hafnium to the number of atoms of the element J1 can be set to 1:1 or the vicinity thereof. Further, as the material having ferroelectricity, a material to which an element J2 (here, the element J2 is one or a plurality of elements selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, and the like) is added to zirconium oxide and the like can be given. Here, the ratio of the number of atoms of zirconium to the number of atoms of the element J2 can be appropriately set, and for example, the ratio of the number of atoms of zirconium to the number of atoms of the element J2 can be set to 1:1 or the vicinity thereof. Further, as the material having ferroelectricity, a material having a perovskite structure such as lead titanate (PbTiO X ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate, and the like can be used.

[0241] Further, as the material having ferroelectricity, a metal nitride containing an element M1, an element M2, and nitrogen can be given. Here, the element M1 is one or a plurality of elements selected from aluminum, gallium, indium, and the like. Further, the element M2 is one or a plurality of elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and the like. Further, the ratio of the number of atoms of the element M1 to the number of atoms of the element M2 can be appropriately set. Further, a metal oxide containing the element M1 and nitrogen sometimes has ferroelectricity even if the element M2 is not contained. Further, as the material having ferroelectricity, a material to which an element M3 is added to the above metal nitride can be given. Note that the element M3 is one or a plurality of elements selected from magnesium, calcium, strontium, zinc, cadmium, and the like. Here, the ratio of the number of atoms of the element M1, the element M2, and the element M3 can be appropriately set.

[0242] Further, as the material having ferroelectricity, perovskite-type oxynitride such as SrTaO2N, BaTaO2N, GaFeO3 which is κ-type aluminum oxide, and the like can be given.

[0243] Note that in the above description, examples of the metal oxide and the metal nitride are shown, but the present application is not limited thereto. For example, a metal oxynitride to which nitrogen is added to the above metal oxide or a metal nitride oxide to which oxygen is added to the above metal nitride and the like can be used.

[0244] Further, as a material that can have ferroelectricity, for example, a mixture or a compound composed of a plurality of materials selected from the above-described materials can be used. Further, the insulating layer can have a stacked structure composed of a plurality of materials selected from the above-described materials. Note that the crystal structure (property) of the above-described listed materials can change not only depending on deposition conditions but also depending on various processes, and thus in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material that can have ferroelectricity.

[0245] A metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even if it is processed into a thin film of several nm. Further, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even if its area is small. Thus, by using a metal oxide containing one or both of hafnium and zirconium, miniaturization of a semiconductor device can be achieved.

[0246] In this specification and the like, a material that can have ferroelectricity formed in a layer is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Further, in this specification and the like, a device including a ferroelectric layer, a metal oxide film, or a metal nitride film is sometimes referred to as a ferroelectric device.

[0247] Further, ferroelectricity is considered to be exhibited because oxygen or nitrogen included in a crystal of a ferroelectric layer is displaced by an applied electric field. Further, it is presumed that the exhibition of ferroelectricity depends on the structure of a crystal included in a ferroelectric layer. Thus, in order for an insulating layer to exhibit ferroelectricity, the insulating layer needs to include a crystal. In particular, the insulating layer preferably has a crystal having an orthorhombic crystal structure, whereby ferroelectricity is exhibited. The crystal structure of a crystal included in the insulating layer can be any one or a plurality of selected from an isometric system, a tetragonal system, an orthorhombic system, a monoclinic system, and a hexagonal system. Further, the insulating layer can have an amorphous structure. At this time, the insulating layer can have a composite structure of an amorphous structure and a crystal structure.

[0248] Further, by adding a Group 3 element (also referred to as IIIa element) in the periodic table to the oxide containing one or both of hafnium and zirconium, the concentration of oxygen vacancies in the oxide increases, whereby a crystal having an orthorhombic crystal structure is easily formed. Thus, the proportion of the crystal having an orthorhombic crystal structure increases, and the remanent polarization can be enhanced, so it is preferable. On the other hand, when the amount of the Group 3 element added is too much, the crystallinity of the oxide can decrease, whereby ferroelectricity can not be easily exhibited. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% or more and 10 atomic% or less, more preferably 0.1 atomic% or more and 5 atomic% or less, and further preferably 0.1 atomic% or more and 3 atomic% or less. Here, the content of the Group 3 element refers to the proportion of the number of atoms of the Group 3 element in the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0249] Further, by surrounding the transistor using a metal oxide with an insulating layer having a function of suppressing the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. As the insulating layer having a function of suppressing the permeation of impurities and oxygen, for example, a single layer or a stack of an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used. Specifically, as the material of the insulating layer having a function of suppressing the permeation of impurities and oxygen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, an aluminum nitride, silicon nitride oxide, and a silicon nitride can be used.

[0250] Specifically, as the insulating layer having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, for example, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be given. Further, as the insulating layer having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, for example, an oxide containing aluminum and hafnium (hafnium aluminate) can be given. Further, as the insulating layer having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, for example, a metal nitride such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon nitride oxide, and silicon nitride can be given.

[0251] Further, an insulating layer in contact with the oxide semiconductor layer, such as a gate insulating layer, or an insulating layer provided in the vicinity of the oxide semiconductor layer preferably has a region containing oxygen which is released by heating (hereinafter referred to as excess oxygen). For example, by bringing the insulating layer having a region containing excess oxygen into contact with or in the vicinity of the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. As the insulating layer in which a region containing excess oxygen is easily formed, silicon oxide, silicon oxynitride, or porous silicon oxide, or the like can be given.

[0252] The insulating layer 110 is used as an interlayer film, and thus its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. Since silicon oxide and silicon oxynitride have thermal stability, they are suitable for use as the insulating layer 110.

[0253] Further, the concentration of impurities such as water and hydrogen in the insulating layer 110 is preferably reduced. By this, the mixing of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 130 can be suppressed.

[0254] As the insulating layer 110, a hydrogen-blocking insulating layer is preferably used. By providing the insulating layer 110 which has hydrogen-blocking properties outside the semiconductor layer 130, the diffusion of hydrogen into the semiconductor layer 130 can be suppressed.

[0255] As a material of the hydrogen-blocking insulating layer, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon nitride oxide, or the like can be given.

[0256] In this specification and the like, a blocking insulating layer refers to an insulating layer having blocking properties. Further, the blocking properties refer to a property of not easily diffusing a corresponding substance (also referred to as a property of not easily transmitting a corresponding substance, a property of low transmittance of a corresponding substance, or a function of suppressing diffusion of a corresponding substance). Further, hydrogen referred to as a corresponding substance refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and a substance which is bonded to hydrogen, and the like. Further, unless particularly stated otherwise, an impurity referred to as a corresponding substance refers to an impurity in a channel formation region or in a semiconductor layer, and refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N2O, NO, NO2, or the like), a copper atom, and the like. Further, oxygen referred to as a corresponding substance refers to at least one of, for example, an oxygen atom and an oxygen molecule. -

[0257] For example, as the insulating layer 110, a silicon nitride film is preferably used.

[0258] ​The insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b preferably each include the hydrogen barrier insulating layer described above. The insulating layer 180a and the insulating layer 180b are provided so as to surround the semiconductor layer 130. By the insulating layer 180a and the insulating layer 180b provided on the outside of the semiconductor layer 130 having hydrogen barrier properties, diffusion of hydrogen into the semiconductor layer 130 can be suppressed. Similarly, by the insulating layer 280a and the insulating layer 280b having hydrogen barrier properties, diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Further, by the insulating layer 380a and the insulating layer 380b having hydrogen barrier properties, diffusion of hydrogen into the semiconductor layer 330 can be suppressed. The insulating layer 180a, the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b, for example, preferably include one or both of an aluminum oxide film and a silicon nitride film.

[0259] Further, silicon nitride has oxygen barrier properties. Thus, by using silicon nitride as the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b, extraction of oxygen from the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 to form excess oxygen vacancies in the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 can be suppressed.

[0260] Further, by using silicon nitride as the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b, excess oxygen can be prevented from being supplied to the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330. Thus, the channel formation region of the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 can be prevented from becoming oxygen-excess, and thus the reliability of the transistor 100, the transistor 200, and the transistor 300 can be improved.

[0261] The insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b preferably include the oxidized insulating film, the oxynitride insulating film, or the insulating layer having a region containing excess oxygen described above.

[0262] For example, the insulating layer having a region containing excess oxygen can be formed by a sputtering method in an atmosphere containing oxygen. Further, by using a sputtering method which does not require a molecule containing hydrogen as a deposition gas, the hydrogen concentration in the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b can be reduced. Thus, by depositing at least a part of the layers which constitute the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b, oxygen can be supplied from the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b to the channel formation region of the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330, and oxygen vacancies and VoH can be reduced.

[0263] In addition, the concentration of impurities such as water and hydrogen in the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b is preferably reduced. Thus, the mixing of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 can be inhibited.

[0264] For example, as the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b, a single-layer structure of a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film is preferably used. Alternatively, for example, as the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b, a three-layer structure in which a silicon nitride film, a silicon oxide film, and a silicon nitride film are sequentially stacked is preferably employed. For example, as the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b, a three-layer structure in which an aluminum oxide film, a silicon oxide film, and an aluminum oxide film are sequentially stacked is preferably employed.

[0265] The insulating layer 250 and the insulating layer 350 preferably have a function of trapping and fixing hydrogen. Thus, the hydrogen concentration in the semiconductor layer 230 and the semiconductor layer 330, particularly, the hydrogen concentration in the channel formation region of the transistor can be reduced. Accordingly, the V O H to make the channel formation region i-type or substantially i-type.

[0266] As a material of the insulating layer having a function of trapping or fixing hydrogen, metal oxides such as an oxide containing hafnium, an oxide containing magnesium, an oxide containing aluminum, an oxide containing aluminum and hafnium (hafnium aluminate), and the like can be given. In addition, these metal oxides can further contain zirconium, and for example, an oxide containing hafnium and zirconium and the like can be given. Here, in the metal oxides having an amorphous structure, since a part of oxygen atoms have a dangling bond, the ability of trapping or fixing hydrogen is high. Therefore, these metal oxides preferably have an amorphous structure. For example, by making these oxides contain silicon, an amorphous structure can be achieved. For example, an oxide containing hafnium and silicon (hafnium silicate) is preferably used. In addition, a part of the metal oxides sometimes has one or both of a crystalline region and a grain boundary.

[0267] In addition, the function of trapping or fixing the corresponding substance can also be said to have a property that the corresponding substance does not easily diffuse. Therefore, the function of trapping or fixing the corresponding substance can also be referred to as a barrier property.

[0268] In the case where the gate insulating layer has a stacked structure, the layer in contact with the semiconductor layer 230 and the layer in contact with the semiconductor layer 330 preferably have a function of trapping and fixing hydrogen. Thereby, hydrogen contained in the semiconductor layer 230 and the semiconductor layer 330 can be more effectively trapped or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 and the semiconductor layer 330 can be reduced. As the layer of the insulating layer 250 in contact with the semiconductor layer 230 and the layer of the insulating layer 350 in contact with the semiconductor layer 330, for example, hafnium silicate and the like are preferably used. In addition, the layer preferably has an amorphous structure.

[0269] By making the layer have an amorphous structure, the formation of grain boundaries can be suppressed. By suppressing the formation of grain boundaries, the planarity of the layer can be improved. Thereby, the thickness distribution of the insulating layer 250 and the insulating layer 350 becomes uniform, and the portion where the thickness is extremely thin can be reduced, and thus the withstand voltage of the insulating layer 250 and the insulating layer 350 can be improved. In addition, the thickness distribution of the film provided on the insulating layer 250 and the film provided on the insulating layer 350 can be made uniform.

[0270] In addition, by suppressing the formation of grain boundaries of the layer, the leakage current due to the defect state of the grain boundary can be reduced. Thereby, the insulating layer 250 and the insulating layer 350 can be used as an insulating film having less leakage current.

[0271] In addition, since hafnium oxide is a high-k material, hafnium silicate becomes a high-k material depending on the silicon content. Therefore, in the case where hafnium oxide or hafnium silicate is used for the gate insulating layer, the gate potential applied at the time of transistor operation can be reduced while the physical thickness of the gate insulating layer is maintained. In addition, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced.

[0272] Thus, as the insulating layer 250 and the insulating layer 350, it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide containing one or both of aluminum and hafnium and having an amorphous structure, and it is further preferable to use aluminum oxide having an amorphous structure.

[0273] Further, as the insulating layer 250 and the insulating layer 350, it is preferable to use a hydrogen barrier insulating layer. By using a hydrogen barrier insulating layer as the insulating layer 250 and the insulating layer 350, diffusion of impurities contained in the conductive layer 320 and the conductive layer 365 to the semiconductor layer 230 and the semiconductor layer 330 can be suppressed. For example, silicon nitride has high hydrogen barrier properties, and thus is suitable for use in the insulating layer 250 and the insulating layer 350. Furthermore, the insulating layer 250 and the insulating layer 350 can include an insulating layer having a thermally stable structure such as silicon oxide or silicon oxynitride.

[0274] By adopting such a structure, a semiconductor device with good electrical characteristics can be provided. Further, a semiconductor device with high reliability can be provided. Further, a semiconductor device in which the electrical characteristics of transistors are less likely to be non-uniform can be provided. Further, a semiconductor device with a large on-state current can be provided.

[0275] Further, the insulating layer 250 and the insulating layer 350 can include an insulating layer having a thermally stable structure such as silicon oxide or silicon oxynitride.

[0276] Further, the insulating layer 250 and the insulating layer 350 can include an insulating layer having a thermally stable structure between a pair of insulating layers having a function of trapping and fixing hydrogen.

[0277] Further, the insulating layer 250 and the insulating layer 350 preferably include an oxygen barrier insulating layer. Thus, oxidation of the conductive layer 240, the conductive layer 320, the conductive layer 340, and the conductive layer 365, and the like can be suppressed. In the case where the insulating layer 250 and the insulating layer 350 have a stacked structure, the layer in contact with the conductive layer 240 and the layer in contact with the conductive layer 340 are preferably an oxygen barrier insulating layer. In particular, the layer in contact with the conductive layer 240, the layer in contact with the conductive layer 320, the layer in contact with the conductive layer 340, and the layer in contact with the conductive layer 365 among the layers constituting the insulating layer 250 and the layers constituting the insulating layer 350 are preferably all oxygen barrier insulating layers.

[0278] By using a hydrogen and oxygen barrier insulating layer as the layer in contact with the conductive layer 320 and the layer in contact with the conductive layer 365 among the insulating layer 250 and the insulating layer 350, oxidation of the conductive layer 320 and the conductive layer 365 can be suppressed. Further, diffusion of oxygen contained in the semiconductor layer 230 and the semiconductor layer 330 to the conductive layer 320 and the conductive layer 365 to form oxygen vacancies in the semiconductor layer 230 and the semiconductor layer 330 can be suppressed.

[0279] As the oxygen barrier insulating layer, for example, an oxide containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium-zinc oxide, silicon nitride, and silicon oxynitride can be given. Further, as the oxide containing one or both of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate) can be given.

[0280] The layer of the insulating layer 250 which is in contact with the conductive layer 240 is preferably less likely to transmit oxygen than at least the insulating layer 280 and the insulating layer 380a. When the layer has oxygen barrier properties, formation of an oxide film on the side surface of the conductive layer 240 due to oxidation of the side surface can be inhibited. Thus, a decrease in on-state current or a decrease in field-effect mobility of the transistor 200 can be inhibited. Similarly, the layer of the insulating layer 350 which is in contact with the conductive layer 340 is preferably less likely to transmit oxygen than at least the insulating layer 380b. Thus, a decrease in on-state current or a decrease in field-effect mobility of the transistor 300 can be inhibited.

[0281] Further, each of the layers which form the insulating layer 250 and the layers which form the insulating layer 350 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 and the insulating layer 350 to be greater than or equal to 1 nm and less than or equal to 20 nm, preferably greater than or equal to 3 nm and less than or equal to 10 nm, a subthreshold swing value (also referred to as S value), which is one of transistor characteristics, can be reduced. The S value means the amount of change in gate voltage when the drain current is changed by one bit at a constant drain voltage in a subthreshold region.

[0282] Further, the thickness of each of the layers which form the insulating layer 250 and the insulating layer 350 is preferably greater than or equal to 0.1 nm and less than or equal to 10 nm, more preferably greater than or equal to 0.1 nm and less than or equal to 5 nm, further preferably greater than or equal to 0.5 nm and less than or equal to 5 nm, still further preferably greater than or equal to 1 nm and less than 5 nm, and yet further preferably greater than or equal to 1 nm and less than or equal to 3 nm. At least part of each of the layers which form the insulating layer 250 and the insulating layer 350 preferably includes a region having the above thickness.

[0283] Further, as the insulating layer 250 and the insulating layer 350, a four-layer structure in which a fourth insulating layer having oxygen barrier property, a first insulating layer containing a material with low relative dielectric constant, a second insulating layer having a function of trapping or fixing hydrogen, and a third insulating layer having hydrogen and oxygen barrier property are sequentially stacked from the side of the semiconductor layer 230 and the side of the semiconductor layer 330 is preferably used. The first insulating layer to the third insulating layer can have the same structure as the layers used for the above-described three-layer structure. The fourth insulating layer is in contact with the semiconductor layer 230 or the semiconductor layer 330. By the fourth insulating layer having oxygen barrier property, the separation of oxygen from the semiconductor layer 230 and the semiconductor layer 330 can be suppressed. As the fourth insulating layer, for example, aluminum oxide is preferably used. Aluminum oxide has a function of trapping or fixing hydrogen, and thus is suitable for the fourth insulating layer in contact with the semiconductor layer 230 and the semiconductor layer 330. Specifically, a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are sequentially stacked from the side of the semiconductor layer 230 and the side of the semiconductor layer 330 is preferably used.

[0284] Further, as the insulating layer 250 and the insulating layer 350, a four-layer structure in which a fourth insulating layer having oxygen barrier property, a first insulating layer containing a material with low relative dielectric constant, a second insulating layer having a function of trapping or fixing hydrogen, and a third insulating layer having hydrogen and oxygen barrier property are sequentially stacked from the side of the semiconductor layer 230 and the side of the semiconductor layer 330 is preferably used. The first insulating layer to the third insulating layer can have the same structure as the layers used for the above-described three-layer structure. The fourth insulating layer is in contact with the semiconductor layer 230 or the semiconductor layer 330. By the fourth insulating layer having oxygen barrier property, the separation of oxygen from the semiconductor layer 230 and the semiconductor layer 330 can be suppressed. As the fourth insulating layer, for example, aluminum oxide is preferably used. Aluminum oxide has a function of trapping or fixing hydrogen, and thus is suitable for the fourth insulating layer in contact with the semiconductor layer 230 and the semiconductor layer 330. Specifically, a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are sequentially stacked from the side of the semiconductor layer 230 and the side of the semiconductor layer 330 is preferably used.

[0285] Typically, the thicknesses of the fourth insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. By using such a structure, a transistor which is miniaturized or highly integrated can also have good electrical characteristics.

[0286] Further, as the insulating layer 250 and the insulating layer 350, a four-layer structure in which a fourth insulating layer having oxygen barrier property, a first insulating layer containing a material with low relative dielectric constant, a second insulating layer having a function of trapping or fixing hydrogen, and a third insulating layer having hydrogen and oxygen barrier property are sequentially stacked from the side of the semiconductor layer 230 and the side of the semiconductor layer 330 is preferably used. The first insulating layer to the third insulating layer can have the same structure as the layers used for the above-described three-layer structure. The fourth insulating layer is in contact with the semiconductor layer 230 or the semiconductor layer 330. By the fourth insulating layer having oxygen barrier property, the separation of oxygen from the semiconductor layer 230 and the semiconductor layer 330 can be suppressed. As the fourth insulating layer, for example, aluminum oxide is preferably used. Aluminum oxide has a function of trapping or fixing hydrogen, and thus is suitable for the fourth insulating layer in contact with the semiconductor layer 230 and the semiconductor layer 330. Specifically, a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are sequentially stacked from the side of the semiconductor layer 230 and the side of the semiconductor layer 330 is preferably used.

[0287] Further, as the insulating layer 110, an insulating layer having a function of trapping or fixing hydrogen described above can be used. Thus, hydrogen in the semiconductor layer 130 can be diffused through the conductive layer 120a and the conductive layer 120b to the insulating layer 110, so that the insulating layer 110 traps or fixes the hydrogen. Accordingly, the concentration of hydrogen in the semiconductor layer 130 can be reduced. For example, as the insulating layer 110, a two-layer structure of a silicon nitride film and a hafnium silicate film over the silicon nitride film can be used.

[0288] The insulating layer 135 and the insulating layer 335 can also be referred to as a side wall, a side wall insulating layer, a side wall protective layer, or the like.

[0289] The insulating layer 135 and the insulating layer 335 preferably include an insulating layer having a region containing oxygen which is released by heating. Thus, oxygen can be supplied from the insulating layer 135 and the insulating layer 335 to the semiconductor layer 130 and the semiconductor layer 330. For example, as the insulating layer 135 and the insulating layer 335, silicon oxide or silicon oxynitride is preferably used.

[0290] Further, the insulating layer 135 and the insulating layer 335 preferably include a hydrogen-blocking insulating layer. Thus, hydrogen can be inhibited from diffusing into the semiconductor layer 130 and the semiconductor layer 330, and the reliability of the transistor 100 and the transistor 300 can be improved. For example, the insulating layer 135 and the insulating layer 335 preferably use aluminum oxide, hafnium oxide, silicon nitride, or silicon nitride oxide.

[0291] In addition, the insulating layer 135 and the insulating layer 335 can use the material described above which can have ferroelectricity.

[0292] For example, as the insulating layer 135 and the insulating layer 335, a single-layer structure of a silicon oxide film, a single-layer structure of a silicon nitride film, a two-layer structure of a silicon oxide film and a silicon nitride film, a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film, a three-layer structure of a silicon nitride film, a silicon oxide film, and a silicon nitride film, or the like can be employed. In the case of employing a two-layer structure of a silicon oxide film and a silicon nitride film, for example, a silicon oxide film is preferably provided on the semiconductor layer 230 side and the semiconductor layer 330 side, and a silicon nitride film is preferably provided on the conductive layer 155 side and the conductive layer 355 side. Thus, oxygen can be efficiently supplied to the semiconductor layer 130 and the semiconductor layer 330, and impurities such as hydrogen can be inhibited from diffusing into the semiconductor layer 130 and the semiconductor layer 330. Alternatively, a silicon nitride film can be provided on the semiconductor layer 230 side and the semiconductor layer 330 side, and a silicon oxide film can be provided on the conductive layer 155 side and the conductive layer 355 side.

[0293] The insulating layer 181 preferably includes a hydrogen-blocking insulating layer. Thus, hydrogen can be inhibited from diffusing into the semiconductor layer 130, and the reliability of the transistor 100 can be improved. For example, the insulating layer 181 preferably uses silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide.

[0294] The insulating layer 181 preferably includes an insulating layer having a region containing oxygen that is released by heating. Thus, oxygen can be supplied to the semiconductor layer 130 from the insulating layer 181. For example, silicon oxide or silicon oxynitride can also be used for the insulating layer 181.

[0295] In the manufacturing process of the semiconductor device of one embodiment of the present application, the insulating layer 183 is subjected to planarization treatment with the insulating layer 181 as a terminal point, the details of which will be described later. Thus, by using a material that reduces the film thickness of the insulating layer 181 in the planarization treatment with the insulating layer 181 as a terminal point for the insulating layer 183, for example, the semiconductor layer 130 can be prevented from being subjected to planarization treatment while the thickness of the insulating layer 181 is reduced, and is thus preferable. In addition, in the manufacturing process of the semiconductor device of one embodiment of the present application, the insulating layer 181A is processed with the insulating layer 183 as a mask, whereby the insulating layer 181 is formed. Thus, when a material with a high etching selectivity with respect to the insulating layer 181 is used for the insulating layer 183, the insulating layer 183 can be prevented from being processed when the insulating layer 181A is processed, and is thus preferable. For example, in the case where silicon nitride is used as the insulating layer 181, silicon oxide is preferably used as the insulating layer 183. Note that the insulating layer 183 can also be formed using silicon oxynitride, aluminum oxide, hafnium oxide, silicon oxynitride, or silicon nitride, for example.

[0296] The insulating layer 181A can be formed using the same material as the insulating layer 181. In addition, the same material as the insulating layer 183 can be used for the insulating layer 183A.

[0297] [Conductive Layer]

[0298] As the conductive layer included in the semiconductor device (the conductive layer 120, the conductive layer 140, the conductive layer 155, the conductive layer 220, the conductive layer 240, the conductive layer 320, the conductive layer 340, the conductive layer 355, the conductive layer 365, and the like), a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above metal element, an alloy in which the above metal elements are combined, and the like are preferably used. As the alloy containing the above metal element, a nitride of the alloy or an oxide of the alloy can be used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are preferably used. In addition, a semiconductor having high conductivity typified by polysilicon containing an impurity element such as phosphorus, a silicide such as nickel silicide, and the like can be used.

[0299] Further, a conductive material containing nitrogen such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing ruthenium, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum, a conductive material containing oxygen such as ruthenium oxide, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel, a material containing a metal element such as titanium, tantalum, or ruthenium, which is not easily oxidized, a conductive material having a function of suppressing diffusion of oxygen, or a material which absorbs oxygen and maintains conductivity is preferable. As the conductive material containing oxygen, an indium oxide containing tungsten oxide, an indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), an indium tin oxide containing titanium oxide, indium tin oxide to which silicon is added (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), an indium zinc oxide containing tungsten oxide, and the like can be given. In this specification and the like, a conductive film deposited using a conductive material containing oxygen is sometimes referred to as an oxide conductive film.

[0300] A conductive material whose main component is tungsten, copper, or aluminum has high conductivity and is therefore preferable.

[0301] Further, a plurality of conductive layers formed of the above-described materials can be stacked. For example, a stacked structure in which a material containing the above-described metal element and a conductive material containing oxygen are combined can be used. Further, a stacked structure in which a material containing the above-described metal element and a conductive material containing nitrogen are combined can be used. Further, a stacked structure in which a material containing the above-described metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined can be used.

[0302] Further, in the case where a metal oxide is used for a channel formation region of a transistor, a stacked structure in which a material containing the above-described metal element and a conductive material containing oxygen are combined is preferably used for a conductive layer used as a gate electrode. In this case, the conductive material containing oxygen is preferably provided on the side of the channel formation region. By providing the conductive material containing oxygen on the side of the channel formation region, oxygen released from the conductive material is easily supplied to the channel formation region.

[0303] The conductive layer 120 and the conductive layer 140 are both conductive layers in contact with the semiconductor layer 130, and thus a conductive material which is not easily oxidized, a conductive material which maintains low resistance even if oxidized, a metal oxide (also referred to as an oxide conductor) having conductivity, or a conductive material having a function of suppressing diffusion of oxygen is preferably used. As the conductive material, a conductive material containing nitrogen and a conductive material containing oxygen can be given, for example. By this, the conductivity of the conductive layer 120 and the conductive layer 140 can be suppressed from decreasing.

[0304] By using a conductive material containing oxygen as the conductive layer 120 or the conductive layer 140, even if the conductive layer 120 or the conductive layer 140 absorbs oxygen, the conductivity can be maintained. Further, when an insulating layer containing oxygen such as hafnium oxide is used as the insulating layer 110, the conductive layer 120 can also maintain the conductivity, and thus is preferable. As the conductive layer 120 and the conductive layer 140, for example, ITO, ITSO, IZO (registered trademark), or the like is preferably used. The conductive layer 220 and the conductive layer 320 can use a material that can be used for the conductive layer 120. The conductive layer 240 and the conductive layer 340 can use a material that can be used for the conductive layer 140.

[0305] Figure 4A An example in which the conductive layer 120 has a three-layer structure of the conductive layer 120al, the conductive layer 120a2 on the conductive layer 120al, and the conductive layer 120b on the conductive layer 120a2 is shown. At this time, for example, as the conductive layer 120al, a conductive material that is not easily oxidized or a conductive material having a function of suppressing diffusion of oxygen is preferably used, as the conductive layer 120a2, a material having high conductivity is preferably used, and as the conductive layer 120b, a conductive material containing oxygen (more preferably, an oxide conductor) is preferably used. Specifically, for example, it is preferable that titanium nitride is used as the conductive layer 120al, tungsten is used as the conductive layer 120a2, and an oxide conductor (for example, ITO, ITSO, or IZO (registered trademark)) is used as the conductive layer 120b. In this case, the titanium nitride is in contact with the insulating layer 110, and the oxide conductor is in contact with the semiconductor layer 130. Further, the oxide conductor is used for the layer closest to the channel formation region of the semiconductor layer 130. The contact resistance of the oxide conductor with the semiconductor layer 130 is lower than that of tungsten, and thus the current path between the source and the drain can be shortened, and thus the on-state current of the transistor can be increased. By adopting such a structure, even if the conductive layer 120 is in contact with the semiconductor layer 130, the conductivity can be maintained. Further, in the case where an oxide insulating layer is used as the insulating layer 110, the conductive layer 120 can be prevented from being excessively oxidized by the insulating layer 110. Further, by using a metal material (in this case, tungsten) having higher conductivity than the oxide conductor and titanium nitride as the conductive layer 120a2, the conductivity of the conductive layer 120 can be increased.

[0306] Figure 4A An example in which the conductive layer 220 has a three-layer structure of the conductive layer 220al, the conductive layer 220a2 on the conductive layer 220al, and the conductive layer 220b on the conductive layer 220a2 is shown. Figure 4BAn example of a three-layer structure in which the conductive layer 320 has the conductive layer 320al, the conductive layer 320a2 over the conductive layer 320al, and the conductive layer 320b over the conductive layer 320a2 is shown. As the conductive layer 220al and the conductive layer 320al, a material that can be used for the conductive layer 120al can be used. As the conductive layer 220a2 and the conductive layer 320a2, a material that can be used for the conductive layer 120a2 can be used. As the conductive layer 220b and the conductive layer 320b, a material that can be used for the conductive layer 120b can be used. Note that the conductive layer 220 can have a single-layer structure. In that case, a material that can be used for the conductive layer 120b can be used for the conductive layer 220.

[0307] Figure 4A An example of a two-layer structure in which the conductive layer 140 has the conductive layer 140a and the conductive layer 140b over the conductive layer 140a is shown. At this time, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 140b and to use a material having higher conductivity than the conductive layer 140b for the conductive layer 140a. Specifically, for example, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or IZO (registered trademark)) for the conductive layer 140b and to use tungsten for the conductive layer 140a. Note that, as the conductive layer 140a, ruthenium, titanium nitride, or tantalum nitride, or the like can be used.

[0308] In the conductive layer 140, the layer mainly in contact with the semiconductor layer 130 is the conductive layer 140b. By using an oxide conductor for the conductive layer 140b, the contact resistance with the semiconductor layer 130 can be reduced, which is preferable. Further, by using a material having higher conductivity than the oxide conductor for the layer constituting the conductive layer 140, the conductivity of the conductive layer 140 can be increased, which is preferable.

[0309] Note that, as the conductive layer 140a, a conductive material containing oxygen can be used, and as the conductive layer 140b, a material having higher conductivity than the conductive layer 140a can be used. At this time, the oxide conductor is used for the layer in the conductive layer 140 closest to the channel formation region of the semiconductor layer 130. Thus, the current path between the source and the drain can be shortened, and the on-state current of the transistor can be increased.

[0310] The conductive layer 240a and the conductive layer 340a can be formed using a material that can be used for the conductive layer 140a. The conductive layer 240b and the conductive layer 340b can be formed using a material that can be used for the conductive layer 140b.

[0311] As the conductive layer 155, the conductive layer 355, and the conductive layer 365, a material having high conductivity such as tungsten is preferably used. Further, as the conductive layer 155, the conductive layer 355, and the conductive layer 365, a conductive material which is not easily oxidized or a conductive material having a function of suppressing diffusion of oxygen, or the like is preferably used. As the conductive material, a conductive material containing nitrogen (for example, titanium nitride, tantalum nitride, or the like) and a conductive material containing oxygen (for example, ruthenium oxide, or the like) can be given, as described above. Thus, the conductivity of the conductive layer 155, the conductive layer 355, and the conductive layer 365 can be suppressed from decreasing.

[0312] Further, as the conductive layer 365, a conductive material containing a metal element and oxygen contained in the metal oxide in which the channel is formed is preferably used. Further, a conductive material containing the above metal element and nitrogen (for example, titanium nitride, tantalum nitride, or the like) can be used. Further, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added can be used. Further, indium gallium zinc oxide containing nitrogen can be used. By using the above material, hydrogen contained in the metal oxide in which the channel is formed can be sometimes trapped. Alternatively, hydrogen mixed from the outside from the insulating layer or the like can be sometimes trapped.

[0313] Figure 4B An example in which the conductive layer 365 has a two-layer structure of the conductive layer 365a and the conductive layer 365b over the conductive layer 365a is shown. At this time, for example, titanium nitride is preferably used as the conductive layer 365a, and tungsten is preferably used as the conductive layer 365b. Alternatively, it is preferable that tantalum nitride be used as the conductive layer 365a, and copper be used as the conductive layer 365b. By adopting such a structure, the conductivity of the conductive layer 365 can be improved.

[0314] Further, the conductive layer 365 can have a stacked-layer structure of three or more layers. The conductive layer 365 can have, for example, a three-layer structure of tantalum nitride, titanium nitride over the tantalum nitride, and tungsten over the titanium nitride.

[0315] Since the conductive layer 365 is a layer serving as a gate wiring, it is preferable to have high conductivity. The conductive layer 365 preferably uses tungsten. For example, a two-layer structure of titanium nitride and tungsten can be employed.

[0316] The conductive layer 155 and the conductive layer 355 preferably use tungsten or tantalum nitride, for example.

[0317] [Substrate]

[0318] As a substrate for forming a transistor, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used, for example. As an insulator substrate, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (a yttria-stabilized zirconia substrate or the like), a resin substrate, or the like can be given. Further, as a semiconductor substrate, a semiconductor substrate using silicon or germanium as a material, or a compound semiconductor substrate formed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like can be given. Further, a semiconductor substrate having an insulator region in the above-described semiconductor substrate, such as an SOI (Silicon On Insulator) substrate or the like can be given. As a conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like can be given. Alternatively, a substrate containing a metal nitride, a substrate containing a metal oxide, or the like can be given. Further, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, or the like can be given. Alternatively, a substrate provided with an element over a substrate can be used. As an element provided over a substrate, a capacitor, a resistor, a switching element, a light-emitting element, a memory element, or the like can be given.

[0319] Structure Example 2 of Semiconductor Device

[0320] Another structure of a semiconductor device according to another embodiment of the present application is described below. Specifically, another structure example of a memory cell 10 included in a semiconductor device according to one embodiment of the present application and a transistor included in the memory cell 10 is described.

[0321] [Memory Cell 10A]

[0322] Figure 5A is a plan view illustrating a structure example of the transistor 100A. Figure 5B is a plan view illustrating a structure example of the transistor 200A. Figure 5C is a cross-sectional view taken along the dotted line A1-A2 illustrated in Figure 5A and Figure 5B . Figure 5D is a cross-sectional view taken along the dotted line B1-B2 illustrated in Figure 5A and Figure 5B . Figure 5C and Figure 5D illustrate a structure example of the memory cell 10A. Here, the transistor 100, the transistor 200, and the transistor 300 included in the memory cell 10A are the transistor 100A, the transistor 200A, and the transistor 300A, respectively. Note that the structure when viewed from above of the transistor 300A can be referred to Figure 1D .

[0323] In the storage unit 10A, the transistor 100A and the transistor 200A do not include the conductive layer 220. At this time, the semiconductor layer 230 is provided so as to cover the top surface of the insulating layer 183 and the side surface of the insulating layer 181 located outside the opening portion 190. Further, the semiconductor layer 230 is provided so as to be in contact with the region of the semiconductor layer 130 overlapping with the conductive layer 140. Thus, even when the transistor 100A and the transistor 200A do not include the conductive layer 220, the other of the source and the drain of the transistor 100A can be electrically connected to one of the source and the drain of the transistor 100B.

[0324] By employing the structure in which the conductive layer 220 is not provided in the storage unit, the number of manufacturing steps of the semiconductor device can be reduced as compared to the case where the structure in which the conductive layer 220 is provided in the storage unit is employed. Thus, the manufacturing cost of the semiconductor device can be reduced, and thus a semiconductor device with low cost can be provided. On the other hand, by employing the structure in which the conductive layer 220 is provided in the storage unit, the width of the opening portion 290 can be reduced as compared to the case where the structure in which the conductive layer 220 is not provided in the storage unit is employed.

[0325] [Storage unit 10B]

[0326] Figure 6A and Figure 6B is a cross-sectional view illustrating a structure example of the storage unit 10B. Figure 6A and Figure 6B respectively illustrate Figure 5C and Figure 5D the opening portion 290 illustrated in FIGS. 10A and 10B does not overlap with the insulating layer 183. Here, the transistor 100, the transistor 200, and the transistor 300 included in the storage unit 10B are the transistor 100B, the transistor 200B, and the transistor 300B, respectively.

[0327] In the storage unit 10B, when the shape of the opening portion 290 in plan view is, for example, circular or quadrangular, at least the center of the opening portion 290 in plan view does not overlap with the insulating layer 183. Further, part of the opening portion 290 can overlap with the insulating layer 183. Even in this case, the top surface of the insulating layer 183 as a whole does not overlap with the opening portion 290.

[0328] Note that although Figure 6A and Figure 6BAn example is shown where opening 390 overlaps with opening 290 but not with opening 190. However, opening 390 may also overlap with opening 190 but not with opening 290. For example, when the shape of opening 390 in top view is, for example, circular or rectangular, the center of opening 390 in top view may overlap with opening 190, opening 290, or may not overlap with both opening 190 and opening 290. The center of opening 390 in top view may also be located between opening 190 and opening 290 in top view. In addition, opening 290 and opening 390 may also be opposite each other in top view, separated by insulating layer 183.

[0329] The contact area between semiconductor layer 130 and semiconductor layer 230 in memory cell 10B can be larger than that in memory cell 10A. This reduces the contact resistance between semiconductor layer 130 and semiconductor layer 230. Conversely, the area occupied by memory cell 10A can be smaller than that of memory cell 10B.

[0330] [Storage Unit 10C]

[0331] Figure 7A This is a circuit diagram showing an example of the structure of a memory cell 10C. Here, the transistors 100, 200, and 300 included in the memory cell 10C are transistor 100C, transistor 200C, and transistor 300C, respectively.

[0332] In memory cell 10C, transistors 200C and 300C are both dual-gate transistors. The first gate of transistor 200C is electrically connected to one of the source and drain of transistor 300C. The second gate of transistor 200C is electrically connected to wiring BGL1. The first gate of transistor 300C is electrically connected to wiring WWL. The second gate of transistor 300C is electrically connected to wiring BGL2. Hereinafter, the first gate of transistor 200C will be simply referred to as the gate of transistor 200C, and the second gate of transistor 200C will be simply referred to as the back gate of transistor 200C. Similarly, the first gate of transistor 300C will be referred to as the back gate of transistor 300C, and the second gate of transistor 300C will be referred to as the back gate of transistor 300C.

[0333] The threshold voltage of transistor 200C can be controlled by controlling the potential of wiring BGL1, which is electrically connected to the back gate of transistor 200C. For example, by supplying wiring BGL1 with a potential greater than the source potential or a positive potential, the on-state current of transistor 200C can be increased. This allows for high-speed reading of data held in memory cell 10C. Alternatively, wiring BG1 can be supplied with the same potential as the gate of transistor 200C. In this case, the gate of transistor 200C can be electrically connected to its back gate.

[0334] The threshold voltage of the transistor 300C can be controlled by controlling the potential of the wiring BGL2 electrically connected to the back gate of the transistor 300C. The threshold voltage of the transistor 300C can be shifted in the positive direction to be normally off characteristics by supplying a potential lower than the source potential or a potential lower than 0 V, preferably a negative potential, to the wiring BGL2. Thus, the gate potential of the transistor 200C can be held for a long period. Accordingly, data written to the storage unit 10C can be held for a long period.

[0335] Figure 7B is a plan view illustrating a structure example of the transistor 200C. Figure 7C is a cross-sectional view taken along the dot-dash line A1-A2 in Figure 7B . Figure 7D is a cross-sectional view taken along the dot-dash line B1-B2 in Figure 7B . Figure 7C and Figure 7D illustrate a structure example of the storage unit 10C. Here, as for the structure in plan view of the transistor 100 and the transistor 300, reference can be made to Figure 1B and Figure 1D , respectively.

[0336] The transistor 200C includes the conductive layer 255 serving as a back gate electrode and the insulating layer 235 serving as a back gate insulating layer. In the storage unit 10C, at least part of the conductive layer 255 is used as the wiring BGL1 illustrated in Figure 7A . Further, at least part of the conductive layer 355 is used as the wiring BGL2 illustrated in Figure 7A .

[0337] The conductive layer 255 is positioned over the insulating layer 280a. The insulating layer 280b is positioned over the conductive layer 255 and the insulating layer 280a. The insulating layer 280b is provided so as to cover the top surface of the conductive layer 255, the side surface of the conductive layer 255, and the top surface of the insulating layer 280a. The conductive layer 255 has an opening portion 290.

[0338] Figure 7C and Figure 7D illustrate an example in which the conductive layer 220b has a first recessed portion and a second recessed portion which is positioned on the outer side of the first recessed portion and shallower than the first recessed portion. In forming the opening portion 290, the second recessed portion is provided in the conductive layer 220b, and then the first recessed portion is provided in the conductive layer 220b in processing the insulating layer 235. Thus, in Figure 7C and Figure 7D , the side surface of the first recessed portion of the conductive layer 220b is aligned with the side surface of the semiconductor layer 230 on one side of the insulating layer 235. Further, the side surface of the second recessed portion of the conductive layer 220b is aligned with, for example, the side surface of the opening portion 290 of the insulating layer 280a on one side.

[0339] The insulating layer 235 is arranged so that at least a part thereof is inside the opening portion 290. The insulating layer 235 has at least a region between the semiconductor layer 230 and the conductive layer 255. The insulating layer 235 is in contact with the side surface of the conductive layer 255 inside the opening portion 290.

[0340] In Figure 7C and Figure 7D the insulating layer 235 is in contact with the bottom surface and the side surface of the recess (specifically, the second recess) of the conductive layer 220b, and is in contact with the side surface of the insulating layer 280a, the side surface of the conductive layer 255, the side surface of the insulating layer 280b, the side surface of the conductive layer 240a, and the side surface of the conductive layer 240b inside the opening portion 290. The semiconductor layer 230 is in contact with the bottom surface and the side surface of the recess (specifically, the first recess) of the conductive layer 220b, the insulating layer 235, and the top surface of the conductive layer 240b. By providing the conductive layer 220b with a recess, the area where the semiconductor layer 230 is in contact with the conductive layer 220b can be increased. Thus, the contact resistance between the semiconductor layer 230 and the conductive layer 220b can be reduced.

[0341] The insulating layer 235 is provided along at least a part of the side wall of the opening portion 290. The semiconductor layer 230 has a region opposite to the conductive layer 255 inside the opening portion 290 with the insulating layer 235 interposed therebetween. At least a part of the region of the semiconductor layer 230 is in contact with the insulating layer 235. The conductive layer 255 is provided so as to surround the semiconductor layer 230 with the insulating layer 235 interposed therebetween.

[0342] The conductive layer 255 is provided so as to be opposite to the conductive layer 320 serving as the gate electrode of the transistor 200C with the insulating layer 235, the semiconductor layer 230, and the insulating layer 250 interposed therebetween. Thus, in the storage unit 10C, the semiconductor layer 230 has a region opposite to the conductive layer 320 with the insulating layer 250 interposed therebetween and opposite to the conductive layer 255 with the insulating layer 235 interposed therebetween.

[0343] The conductive layer 255 is provided so as to surround at least part of the channel formation region of the transistor 200C with the insulating layer 235 interposed therebetween. Thus, the conductive layer 255 functions as a back gate electrode of the transistor 200C. Accordingly, by controlling the potential of the conductive layer 255, the threshold voltage of the transistor 200C can be controlled. For example, by supplying a potential higher than the source potential or a positive potential to the conductive layer 255, the on-state current of the transistor 200C can be increased. Thus, data held in the storage unit 10C can be read at high speed. Further, for example, the same potential as the conductive layer 320 can be supplied to the conductive layer 255. In that case, the conductive layer 255 and the conductive layer 320 can be electrically connected to each other. For example, an opening portion reaching the conductive layer 255 is provided in the insulating layer 280b and the insulating layer 250, the opening portion is filled with a conductive layer serving as a plug, and the conductive layer 320 is provided in contact with the conductive layer, whereby the conductive layer 255 and the conductive layer 320 can be electrically connected to each other.

[0344] The conductive layer 255 can be formed using a material that can be used for the conductive layer 355. The insulating layer 235 can be formed using a material that can be used for the insulating layer 335, for example. The insulating layer 235 preferably includes an insulating layer having a region containing oxygen released by heating, for example. Further, the insulating layer 235 preferably includes a hydrogen barrier insulating layer, for example. In addition, like the insulating layer 335, the insulating layer 235 can be referred to as a side wall, a side wall insulating layer, a side wall protective layer, or the like.

[0345] Although Figures 7B to 7D Although an example is shown in which the conductive layer 255 extends in a direction parallel to the conductive layer 355, one embodiment of the present application is not limited to this, and the conductive layer 255 can extend in a direction different from the conductive layer 355. For example, the conductive layer 355 can extend in the X direction, and the conductive layer 255 can extend in the Y direction.

[0346] [Storage Unit 10D]

[0347] Figure 8A Further, the conductive layer 255 can be electrically connected to the conductive layer 320. For example, an opening portion reaching the conductive layer 255 is provided in the insulating layer 280b and the insulating layer 250, the opening portion is filled with a conductive layer serving as a plug, and the conductive layer 320 is provided in contact with the conductive layer, whereby the conductive layer 255 and the conductive layer 320 can be electrically connected to each other. Figure 8B is a cross-sectional view illustrating a structure example of the storage unit 10D. In the storage unit 10D, Figure 2A and Figure 2BThe insulating layer 180a has a three-layer stacked structure of the insulating layer 180al, the insulating layer 180a2 over the insulating layer 180al, and the insulating layer 180a3 over the insulating layer 180a2. Further, the insulating layer 180b has a three-layer stacked structure of the insulating layer 180bl, the insulating layer 180b2 over the insulating layer 180bl, and the insulating layer 180b3 over the insulating layer 180b2. Further, the insulating layer 280 has an example of a three-layer stacked structure of the insulating layer 280_1, the insulating layer 280_2 over the insulating layer 280_1, and the insulating layer 280_3 over the insulating layer 280_2. Further, the insulating layer 380a has a three-layer stacked structure of the insulating layer 380al, the insulating layer 380a2 over the insulating layer 380al, and the insulating layer 380a3 over the insulating layer 380a2. Further, the insulating layer 380b has a three-layer stacked structure of the insulating layer 380bl, the insulating layer 380b2 over the insulating layer 380bl, and the insulating layer 380b3 over the insulating layer 380b2.

[0348] The transistor 100 included in the storage unit 10D, the transistor 200, and the transistor 300 are each a transistor 100D, a transistor 200D, and a transistor 300D, respectively. As to the structure when viewed from the top of the transistor 100D, the transistor 200D, and the transistor 300D, reference can be made to the structure when viewed from the top of the transistor 100, the transistor 200, and the transistor 300, respectively. Figure 1B Figure 1C Figure 1D

[0349] The insulating layer 180a2 and the insulating layer 180b2 are layers closer to the channel formation region of the semiconductor layer 130 than the insulating layer 180al and the insulating layer 180b3. By using an insulating layer containing oxygen for the insulating layer 180a2 and the insulating layer 180b2, oxygen can be supplied to the semiconductor layer 130.

[0350] The insulating layer 180a2 preferably has a region with a higher oxygen content than at least one of the insulating layer 180al and the insulating layer 180a3. The insulating layer 180b2 preferably has a region with a higher oxygen content than at least one of the insulating layer 180bl and the insulating layer 180b3. By increasing the oxygen content of the insulating layer 180a2 and the insulating layer 180b2, an i-type region can be easily formed in the semiconductor layer 130.

[0351] As the insulating layer 180a2 and the insulating layer 180b2, a film which releases oxygen by heating is more preferably used. Since the insulating layer 180a2 and the insulating layer 180b2 release oxygen by heating in the manufacturing process of the semiconductor device, oxygen can be supplied to the semiconductor layer 130. By supplying oxygen from the insulating layer 180a2 and the insulating layer 180b2 to the semiconductor layer 130, in particular, to the channel formation region of the semiconductor layer 130, oxygen vacancies and V O ​​​H, a transistor with good electric characteristics and high reliability can be realized.

[0352] Further, in order to improve the electric characteristics and the reliability of the OS transistor, it is important to optimize the amount of oxygen supplied to the oxide semiconductor while sufficiently reducing the hydrogen concentration in the oxide semiconductor.

[0353] In particular, in the case where the channel length of the transistor is short, the oxygen vacancy and V O H has a particularly large effect on the electric characteristics and the reliability. Thus, by optimizing the amount of oxygen supplied to the semiconductor layer 130 while sufficiently reducing the hydrogen concentration in the semiconductor layer 130, a transistor with good electric characteristics and high reliability and a short channel length can be realized.

[0354] The insulating layer 180a2 and the insulating layer 180b2 are preferably formed by a deposition method such as a sputtering method or a plasma-enhanced chemical vapor deposition (PECVD) method, respectively. In particular, when a sputtering method is used, hydrogen need not be used as a deposition gas, whereby a film with a very small amount of hydrogen can be realized. Thus, the supply of hydrogen to the semiconductor layer 130 can be inhibited, leading to stabilization of the electric characteristics of the transistor.

[0355] In the case where the amount of oxygen supplied to the semiconductor layer 130 is increased, for example, heat treatment in an oxygen atmosphere or plasma treatment in an oxygen atmosphere is preferably performed after the formation of the insulating layer 180a2 or the insulating layer 180b2. Further, an oxide film can be deposited on the top surface of the insulating layer 180a2 or the insulating layer 180b2 by a sputtering method in an oxygen atmosphere to supply oxygen. Then, the oxide film can be removed. By performing such a process, oxygen can be supplied to the insulating layer 180a2 or the insulating layer 180b2 to increase the amount of oxygen supplied to the semiconductor layer 130.

[0356] In addition, an insulating layer suitable for the insulating layer 180a2 and the insulating layer 180b2 is preferably used as the insulating layer 135. By this means, oxygen can be more efficiently supplied to the semiconductor layer 130.

[0357] Further, the insulating layer 180a2 and the insulating layer 180b2 preferably each use a material with a low relative dielectric constant. By this means, the parasitic capacitance generated between wirings can be reduced. As the insulating layer 180a2 and the insulating layer 180b2, for example, silicon oxide or silicon oxynitride can be used, respectively.

[0358] As the insulating layer 180a1, the insulating layer 180a3, the insulating layer 180b1, and the insulating layer 180b3, an oxygen barrier insulating layer is preferably used. By this means, oxidation of the conductive layer 120, the conductive layer 140, and the conductive layer 155 can be inhibited, and high-resistance change can be inhibited.

[0359] In addition, a hydrogen-blocking insulating layer can be used as the insulating layer 180al, the insulating layer 180a3, the insulating layer 180bl, and the insulating layer 180b3. With such a structure, diffusion of impurities such as hydrogen into the semiconductor layer 130 can be suppressed, and thus is preferable.

[0360] As the insulating layer 180al, the insulating layer 180a3, the insulating layer 180bl, and the insulating layer 180b3 which satisfy the above conditions, a silicon nitride film or an aluminum oxide film is preferably used. In addition, a silicon oxide film is preferably used as the insulating layer 180a2 and the insulating layer 180b2.

[0361] The insulating layer 280_1, the insulating layer 280_2, and the insulating layer 280_3 can each be deposited in the same manner as the insulating layer 180al, the insulating layer 180a2, and the insulating layer 180a3. In addition, the insulating layer 280_1, the insulating layer 280_2, and the insulating layer 280_3 can each be deposited in the same manner as the insulating layer 180bl, the insulating layer 180b2, and the insulating layer 180b3. The insulating layer 380al, the insulating layer 380a2, and the insulating layer 380a3 can each be deposited in the same manner as the insulating layer 180al, the insulating layer 180a2, and the insulating layer 180a3. The insulating layer 380bl, the insulating layer 380b2, and the insulating layer 380b3 can each be deposited in the same manner as the insulating layer 180bl, the insulating layer 180b2, and the insulating layer 180b3.

[0362] [Storage Unit 10E]

[0363] Figure 9A and Figure 9B is a cross-sectional view illustrating a structure example of the storage unit 10E. Figure 9A and Figure 9B respectively illustrate examples in which the insulating layer 235 is arranged inside the opening portion 290 illustrated in Figure 8A and Figure 8B Here, the transistor 100, the transistor 200, and the transistor 300 included in the storage unit 10E are respectively a transistor 100E, a transistor 200E, and a transistor 300E.

[0364] The insulating layer 235 has a region between the semiconductor layer 230 and the insulating layer 280. In addition, the insulating layer 235 is in contact with the semiconductor layer 230 inside the opening portion 290. Specifically, the insulating layer 235 is in contact with at least part of a channel formation region of the semiconductor layer 230. Note that although the insulating layer 235 is in contact with the semiconductor layer 230 in the example of FIG. 5B, the insulating layer 235 can not be in contact with the semiconductor layer 230. Figure 9A and Figure 9B The transistor 200E illustrated in FIG. 5B does not include the conductive layer 255, but the transistor 200E can include the conductive layer 255.

[0365] By providing the insulating layer 235 between the insulating layers 280_1, 280_2, and 280_3 and the semiconductor layer 230, the entire surface of, for example, the outer side (the side opposite to the conductive layer 320) of the channel formation region of the semiconductor layer 230 can be in contact with the same insulating layer. Thus, the characteristics of the channel formation region of the semiconductor layer 230 can be made uniform regardless of the height from the reference plane, in particular. For example, when the insulating layer 235 has a region containing oxygen that is released by heat, oxygen can be supplied uniformly to the entire channel formation region of the semiconductor layer 230. In addition, when the insulating layer 235 includes a hydrogen-blocking insulating layer, hydrogen can be inhibited from diffusing to the entire channel formation region of the semiconductor layer 230. Thus, a highly reliable semiconductor device can be provided.

[0366] Note that although Figures 8A to 9B Although an example in which the insulating layers 180a, 180b, 280, 380a, and 380b have a three-layer stacked structure is described, the insulating layers 180a, 180b, 280, 380a, and 380b can have a two-layer stacked structure or a stacked structure of four or more layers. For example, the insulating layers 180a, 180b, 380a, and 380b can have a two-layer stacked structure, and the insulating layer 280 can have a three-layer stacked structure. In this case, for example, a structure in which the insulating layers 180a3, 180b1, 380a3, and 380b1 are not provided can be employed.

[0367] [Storage Unit 10F]

[0368] Figure 10A and Figure 10B is a cross-sectional view illustrating an example of the structure of the storage unit 10F. In the storage unit 10F, Figure 2A and Figure 2B The conductive layer 120b and the conductive layer 320b each illustrated in FIGS. 10A and 10B have only one recess. Here, the transistors 100, 200, and 300 included in the storage unit 10F are the transistor 100F, the transistor 200F, and the transistor 300F, respectively. Note that the structure when viewed from the top of the transistor 100F, the transistor 200F, and the transistor 300F can be described with reference to FIGS. 10A and 10B, respectively. Figure 1B Figure 1C and Figure 1D .

[0369] In the conductive layer 120b, a recess can be formed in one or both of the formation process of the opening portion 190 and the formation process of the insulating layer 135. For example, in the case where the conductive layer 120b is formed by a sputtering method, a recess can be formed in the formation process of the insulating layer 135. Figure 2A and Figure 2B ​In the transistor 100 shown in FIG. 1A, a recess is formed in the conductive layer 120b in both of the above two processes. In contrast, in the transistor 100F, a recess is not formed in the conductive layer 120b in the formation process of the opening portion 190 and is formed in the formation process of the insulating layer 135. Further, in the conductive layer 320b, a recess can be formed in one or both of the formation process of the opening portion 390 and the formation process of the insulating layer 335. For example, in the transistor 300 shown in FIG. 3A, a recess is formed in the conductive layer 320b in both of the above two processes. In contrast, in the transistor 300F, a recess is not formed in the conductive layer 320b in the formation process of the opening portion 390 and is formed in the formation process of the insulating layer 335. Figure 2A and Figure 2B In the transistor 300 shown in FIG. 3A, a recess is formed in the conductive layer 320b in both of the above two processes. In contrast, in the transistor 300F, a recess is not formed in the conductive layer 320b in the formation process of the opening portion 390 and is formed in the formation process of the insulating layer 335.

[0370] In the transistor 100F, the insulating layer 135 is in contact with the side surface of the insulating layer 180a, the side surface of the conductive layer 155, the side surface of the insulating layer 180b, the side surface of the conductive layer 140a, the side surface of the conductive layer 140b, and the top surface of the conductive layer 120b inside the opening portion 190. Further, the semiconductor layer 130 is in contact with the bottom surface and the side surface of the recess of the conductive layer 120b. In the transistor 300F, the insulating layer 335 is in contact with the side surface of the insulating layer 380a, the side surface of the conductive layer 355, the side surface of the insulating layer 380b, the side surface of the conductive layer 340a, the side surface of the conductive layer 340b, and the top surface of the conductive layer 320b inside the opening portion 390. Further, the semiconductor layer 330 is in contact with the bottom surface and the side surface of the recess of the conductive layer 320b.

[0371] When a recess is formed in the conductive layer 320b in at least one of the formation process of the opening portion 390 and the formation process of the insulating layer 335, the height of the bottom surface of the conductive layer 365a inside the opening portion 390 can be reduced. Thus, a gate electric field is easily applied to the channel formation region of the semiconductor layer 330. Accordingly, the transistor 300F can be a transistor with excellent electric characteristics.

[0372] When a recess is formed in the conductive layer 120b in the formation process of the insulating layer 135, the area where the semiconductor layer 130 is in contact with the conductive layer 120b can be increased, as described above. Thus, the contact resistance between the semiconductor layer 130 and the conductive layer 120b can be reduced. Similarly, when a recess is formed in the conductive layer 320b in the formation process of the insulating layer 335, the area where the semiconductor layer 330 is in contact with the conductive layer 320b can be increased, as described above. Thus, the contact resistance between the semiconductor layer 330 and the conductive layer 320b can be reduced.

[0373] [Memory cell 10G]

[0374] Figure 11A and Figure 11Bis a cross-sectional view illustrating a structure example of the memory cell 10G. In the memory cell 10G, Figure 2A and Figure 2B The insulating layer 135 does not cover the side surface of the conductive layer 140b, and the insulating layer 335 does not cover the side surface of the conductive layer 340b. Here, the transistor 100, the transistor 200, and the transistor 300 included in the memory cell 10G are the transistor 100G, the transistor 200G, and the transistor 300G, respectively. Note that the structure when viewed from above of the transistor 100G, the transistor 200G, and the transistor 300G can be described with reference to Figure 1B , Figure 1C and Figure 1D .

[0375] Figure 11A and Figure 11B The insulating layer 135 is in contact with the bottom surface and the side surface of the recess of the conductive layer 120, and is in contact with the side surface of the insulating layer 180a, the side surface of the conductive layer 155, and the side surface of the insulating layer 180b inside the opening portion 190. In addition, the insulating layer 135 is in contact with the side surface of the conductive layer 140a and is not in contact with the side surface of the conductive layer 140b. Note that Figure 11A and Figure 11B An example is shown in which the insulating layer 135 is in contact with the side surface of the conductive layer 140a on the side of the opening portion 190 as a whole, but part of the side surface of the conductive layer 140a on the side of the opening portion 190 can not be in contact with the insulating layer 135. In addition, Figure 11A and Figure 11B An example is shown in which the insulating layer 335 is in contact with the side surface of the conductive layer 340a on the side of the opening portion 390 as a whole, but part of the side surface of the conductive layer 340a on the side of the opening portion 390 can not be in contact with the insulating layer 335.

[0376] The insulating layer 135 is used as a gate insulating layer of the transistor 100G. Thus, the insulating layer 135 covers at least the entire side surface of the conductive layer 155 on the side of the opening portion 190 and electrically insulates the conductive layer 155 from the semiconductor layer 130. The insulating layer 135 can be in contact with any one or more of the side surface of the insulating layer 180a, the side surface of the insulating layer 180b, the side surface of the conductive layer 140a, and the side surface of the conductive layer 140b inside the opening portion 190, and can cover part or all of each side surface. Similarly, the insulating layer 335 can be in contact with any one or more of the side surface of the insulating layer 380a, the side surface of the insulating layer 380b, the side surface of the conductive layer 340a, and the side surface of the conductive layer 340b inside the opening portion 390, and can cover part or all of each side surface.

[0377] When at least a portion of the side surface of the conductive layer 140b is not covered by the insulating layer 135, this portion can contact the semiconductor layer 130. This increases the contact area between the semiconductor layer 130 and the conductive layer 140. Therefore, the contact resistance between the semiconductor layer 130 and the conductive layer 140 can be reduced, which is preferred. Similarly, when the insulating layer 135 does not cover at least a portion of the side surface of the conductive layer 140b and not at least a portion of the side surface of the conductive layer 140a, this portion contacts the semiconductor layer 130. This increases the contact area between the semiconductor layer 130 and the conductive layer 140. Therefore, the contact resistance between the semiconductor layer 130 and the conductive layer 140 can be reduced, which is preferred.

[0378] Similarly, when at least a portion of the side surface of the conductive layer 340b is not covered by the insulating layer 335, or when the insulating layer 335 does not cover the side surface of the conductive layer 340b and does not cover at least a portion of the side surface of the conductive layer 340a, the contact area between the semiconductor layer 330 and the conductive layer 340 can be increased. This reduces the contact resistance between the semiconductor layer 330 and the conductive layer 340, which is therefore preferable.

[0379] Figures 10A to 11B The structure of the insulating layer 335 shown can also be used, for example, for... Figure 7C , Figure 7D , Figure 9A and Figure 9B The insulating layer 235 is shown.

[0380] [Storage Unit 10H]

[0381] Figure 12A and Figure 12B This is a cross-sectional view showing a structural example of memory cell 10H. In memory cell 10H, in... Figure 2A and Figure 2B An insulating layer 383 and an insulating layer 385 on the insulating layer 383 are provided between the insulating layer 350 and the conductive layer 365a. Additionally, Figure 12A and Figure 12B The width D2 of the opening 390 is shown.

[0382] Here, the transistors 100, 200, and 300 included in the storage cell 10H are transistor 100H, 200H, and 300H, respectively. Note that the top-view structure of transistors 100H, 200H, and 300H can be found in the respective references. Figure 1B , Figure 1C and Figure 1D .

[0383] The insulating layer 383 and the insulating layer 385 are used as interlayer films. The insulating layer 383 is provided with the opening portion 370 reaching the insulating layer 350 at a position overlapping the opening portion 390. The conductive layer 365a is arranged so that at least a part thereof is positioned inside the opening portion 370. Further, the conductive layer 365b can also be arranged so that at least a part thereof is positioned inside the opening portion 370. The conductive layer 365a is in contact with the insulating layer 350 inside the opening portion 370.

[0384] The conductive layer 365a is provided so as to fill at least a part of the opening portion 390 and the opening portion 370.

[0385] In the transistor of one embodiment of the present application, at least one layer included in the conductive layer 365 is provided inside the opening portion 390 and the opening portion 370. In the case where the conductive layer 365 has a stacked-layer structure, as the transistor is more miniaturized and the diameter of the opening portion 390 and the diameter of the opening portion 370 are smaller, it is more difficult to arrange all the layers included in the conductive layer 365 in the opening portion 390 and the opening portion 370. Figure 12A Figure 12B An example is shown in which the conductive layer 365 has a two-layer structure, only the conductive layer 365a is provided inside the opening portion 390, and the conductive layer 365a and the conductive layer 365b are provided in the opening portion 370. Note that depending on the diameter of the opening portion 390 and the thickness of the conductive layer 365a, both the conductive layer 365a and the conductive layer 365b are sometimes positioned inside the opening portion 390. Further, depending on the diameter of the opening portion 370, the thickness of the conductive layer 365a, and the thickness of the conductive layer 365b, only the conductive layer 365a is sometimes positioned inside the opening portion 370.

[0386] The portions of the conductive layer 365a and the conductive layer 365b which do not overlap the opening portion 390 are mainly positioned on the insulating layer 385. Thus, the conductive layer 365 mainly overlaps the conductive layer 340 with the insulating layer 383 and the insulating layer 385 interposed therebetween. By this means, the physical distance between the conductive layer 365 and the conductive layer 340 can be increased, and the parasitic capacitance generated between the conductive layer 365 and the conductive layer 340 can be reduced. Further, the conductive layer 340 and the conductive layer 365 can have a portion which does not overlap with the insulating layer 385 interposed therebetween.

[0387] Figure 12A Figure 12B An example is shown in which the width of the opening portion 370 is smaller than the width D2 of the opening portion 390. The smaller the width of the opening portion 370, the smaller the area in which the conductive layer 340 and the conductive layer 365 overlap without the insulating layer 385 interposed therebetween can be, and the parasitic capacitance generated between the conductive layer 340 and the conductive layer 365 can be reduced, and is thus preferable. For example, the width of the opening portion 370 is preferably equal to or smaller than the width of the opening portion 390.

[0388] ​​Further, the width of the opening portion 370 can be larger than the width of the opening portion 390. In this case, the size relationship between the two widths in the semiconductor device of one embodiment of the present application can be confirmed in one cross section parallel to the Z direction. For example, the width of the opening portion 370 is preferably smaller than the maximum value of the width of the conductive layer 365a and the width of the conductive layer 365b in the Y direction in the cross section parallel to the Z direction. Figure 12B Further, for example, the maximum value of the width of the conductive layer 365 is preferably equal to or smaller than the maximum value of the width of the conductive layer 355 in the Y direction in the cross section parallel to the Z direction. Figure 12B Thus, the area ratio of the portion where the conductive layer 340 and the conductive layer 365 overlap without the insulating layer 385 to the portion where the conductive layer 340 and the conductive layer 365 overlap with the insulating layer 385 can be sufficiently small, and thus the parasitic capacitance generated between the conductive layer 340 and the conductive layer 365 can be reduced.

[0389] That is, the transistor 300H has a structure in which the parasitic capacitance generated between the other of the source and drain electrodes and the gate wiring is reduced. Thus, a semiconductor device with high operation speed can be provided.

[0390] The shape of the opening portion 370 in plan view can be the same as the shape of the opening portion 390 in plan view. The shape of the opening portion 370 in plan view can be, for example, circular.

[0391] The width of the opening portion 370 is sometimes changed in the depth direction. In this case, in particular, the maximum value of the width of the opening portion 370 provided in the insulating layer 383 in a cross section is used as the width of the opening portion 370.

[0392] As the insulating layer 383, a hydrogen-blocking insulating layer is preferably used. Thus, diffusion of hydrogen from above the insulating layer 383 to the semiconductor layer 330 can be suppressed. Since both a silicon nitride film and a silicon oxynitride film have characteristics that impurities (e.g., water and hydrogen) are less likely to be released from themselves and oxygen and hydrogen are less likely to penetrate, they can be suitably used for the insulating layer 383.

[0393] As the insulating layer 383, a silicon nitride deposited by a sputtering method is particularly preferably used. Since the sputtering method does not need to use a molecule containing hydrogen as a deposition gas, the hydrogen concentration of the insulating layer 383 can be reduced. By depositing the insulating layer 383 using the sputtering method, a silicon nitride with high density can be formed.

[0394] Further, as the insulating layer 383, an insulating layer having a function of trapping or fixing hydrogen can be used. With such a structure, diffusion of hydrogen from above the insulating layer 383 to the semiconductor layer 330 can be suppressed, and hydrogen contained in the semiconductor layer 330 can be trapped or fixed. Thus, the hydrogen concentration of the semiconductor layer 330 can be reduced. As the insulating layer 383, aluminum oxide, hafnium oxide, or hafnium silicate can be used.

[0395] Furthermore, the insulating layer 383 can also be a laminated structure of an insulating layer with the function of trapping or fixing hydrogen and a hydrogen barrier insulating layer. For example, the insulating layer 383 can also be a laminated film of aluminum oxide and silicon nitride on the aluminum oxide.

[0396] The insulating layer 385 is used as an interlayer film, and therefore a material with a relatively low permittivity as described above is preferred. For example, the insulating layer 385 preferably has a silicon oxide film.

[0397] [Storage Unit 10I]

[0398] Figure 13A and Figure 13B This is a cross-sectional view showing a structural example of the memory cell 10I. In the memory cell 10I, no... Figure 12A and Figure 12B The conductive layer 365a is shown, and the insulating layer 350 has a conductive layer 360 disposed thereon. Here, the transistors 100, 200, and 300 included in the memory cell 10I are transistor 100I, transistor 200I, and transistor 300I, respectively. Note that the top view structure of transistors 100I, 200I, and 300I can be found in the respective references. Figure 1B , Figure 1C and Figure 1D .

[0399] The conductive layer 360 is used as the gate electrode (first gate electrode) of the transistor 300I. The conductive layer 365 is used as the gate wiring as described above. The conductive layer 360 can, for example, use a material that can be used for the conductive layer 365a. The conductive layer 365 included in the memory cell 10I can, for example, use a material that can be used for the conductive layer 365b.

[0400] Conductive layer 360 is included in the constituent elements of transistor 300I. Conductive layer 365 may not be included in the constituent elements of transistor 300I. Note that conductive layer 365 may also be included in the constituent elements of transistor 300I.

[0401] like Figure 13A and Figure 13B As shown, an opening 370 is provided at the position where the insulating layer 383 overlaps with the opening 390, leading to the semiconductor layer 330. At least a portion of the constituent elements of the transistor 300I is disposed inside the opening 370. Specifically, both the insulating layer 350 and the conductive layer 360 are disposed such that at least a portion of them is located inside the opening 370. The insulating layer 350 is in contact with the semiconductor layer 330 and the insulating layer 383 inside the opening 370.

[0402] The portion of the insulating layer 350 that is disposed inside the opening portion 370 reflects the shape of the opening portion 370. Specifically, the insulating layer 350 is disposed so as to cover the side wall of the opening portion 370 (the side surface of the insulating layer 383). Further, the conductive layer 360 is disposed so as to be embedded in at least a portion of the recess of the insulating layer 350 that reflects the shape of the opening portion 370.

[0403] In the transistor 300I, since the conductive layer 360 does not overlap with the top surface of the conductive layer 340, the parasitic capacitance generated between the conductive layer 340 and the conductive layer 360 can be reduced. As Figure 13A and Figure 13B indicated, the maximum value of the width of the conductive layer 360 in cross section is smaller than the width D2 of the opening portion 390. Thus, when the maximum value of the width of the conductive layer 360 is smaller than the width D2 of the opening portion 390, the parasitic capacitance generated between the conductive layer 360 and the conductive layer 340 can be reduced, which is preferable.

[0404] Figure 13A and Figure 13B An example in which the width of the opening portion 370 coincides with the width of the opening portion 390 (is equal to the width D2) is shown. The width of the opening portion 370 is more preferably equal to or smaller than the width of the opening portion 390. Thus, the conductive layer 360 does not overlap with the top surface of the conductive layer 340, and the parasitic capacitance generated between the conductive layer 360 and the conductive layer 340 can be reduced, which is preferable.

[0405] Although an example in which the conductive layer 360 does not overlap with the top surface of the conductive layer 340 is shown in this embodiment, the conductive layer 360 can have a portion that overlaps with the top surface of the conductive layer 340. The smaller the overlapping portion is, the more the parasitic capacitance generated between the conductive layer 360 and the conductive layer 340 can be reduced, which is preferable. For example, the width of the opening portion 370 is preferably smaller than the width of the short side of the conductive layer 365 (the maximum value of the width of the conductive layer 365 in FIG. 3B). Figure 13B Further, for example, the maximum value of the width of the conductive layer 365 is preferably equal to or smaller than the maximum value of the width of the conductive layer 355 in the Y direction (the width of the short side of the conductive layer 355 in FIG. 3B). Figure 13B

[0406] The height of the top surface of the conductive layer 360 is preferably equal to or substantially equal to the height of the top surface of the insulating layer 385. The conductive layer 365 is provided over the insulating layer 385, the insulating layer 383, and the conductive layer 360, and is in contact with the top surface of the conductive layer 360. The conductive layer 360 and the conductive layer 365 can be said to be electrically connected to each other. The insulating layer 383 and the insulating layer 385 are positioned between the conductive layer 365 and the conductive layer 340. Thus, the physical distance between the conductive layer 365 and the conductive layer 340 can be increased, and the parasitic capacitance generated between the conductive layer 365 and the conductive layer 340 can be reduced.​

[0407] In other words, the transistor 300I has a structure in which the parasitic capacitance between the source electrode and the gate electrode, and the parasitic capacitance between the source electrode and the gate wiring, are reduced. Therefore, a semiconductor device with high operating speed can be provided.

[0408] [Storage Unit 10J]

[0409] FIG. 14A and FIG. 14B This is a cross-sectional view showing a structural example of memory cell 10J. In memory cell 10J, FIG. 2A and FIG. 2B The conductive layer 365 shown has a single-layer structure. Here, the transistors 100, 200, and 300 included in the memory cell 10J are transistor 100J, 200J, and 300J, respectively. Note that the top view structure of transistors 100J, 200J, and 300J can be found in the respective references. FIG. 1B , FIG. 1C and FIG. 1D .

[0410] Similar to the conductive layer 365 included in transistor 300J, the conductive layer used as the gate electrode can also have a single-layer structure. The conductive layer 365 is preferably provided in a manner that embeds the opening 390.

[0411] [10K storage units]

[0412] FIG. 15A and FIG. 15B This is a cross-sectional view showing a structural example of memory cell 10K. In memory cell 10K, conductive layers 365a and 365b are located on both sides... FIG. 2A and FIG. 2B The opening 390 shown is inside the cell. Here, the transistors 100, 200, and 300 included in the memory cell 10K are transistor 100K, 200K, and 300K, respectively. Note that the top view of transistors 100K, 200K, and 300K can be found in the respective references. FIG. 1B , FIG. 1C and FIG. 1D .

[0413] In transistor 300K, conductive layer 365b is located inside opening 390. As described above, depending on the diameter of opening 390 and the thickness of conductive layer 365a, sometimes both conductive layer 365a and conductive layer 365b are also provided inside opening 290.

[0414] The structures of the aforementioned storage cells 10A to 10K can be appropriately combined. For example, insulating layers 235 and conductive layers 255 can be provided in storage cells 10A, 10B, and 10F to 10K. Furthermore, insulating layers 180a, 180b, 280, 380a, and 380b of storage cells 10A, 10B, and 10F to 10K can also have the same stacked structure as storage cells 10D and 10E. Moreover, the structures of storage cells 10A, 10B, 10F, and 10K can also be... FIG. 12A to FIG. 15B The structure of the gate electrode and the structure of the gate insulating layer of the transistor 300 shown are used for transistors 300A to 300G.

[0415] [Transistor 100L and Transistor 100M]

[0416] The following describes other structural examples of transistor 100. Note that the structure of transistor 100L shown below can also be used for transistor 200 and transistor 300. Similarly, the structure of transistor 100M shown below can also be used for transistor 200 and transistor 300.

[0417] FIG. 16A This is a cross-sectional view showing an example structure of a semiconductor device including transistor 100L, and showing... FIG. 4A The example shown is an insulating layer 135 with a two-layer structure. Here, the insulating layer 135 can also have a stacked structure of three or more layers. Note that although in FIG. 16A Although not shown in the figure, insulating layers 235 and 335 may also have a stacked structure of two or more layers, similar to insulating layer 135. In addition, for example, insulating layers 135 and 335 included in memory cells 10A to 10K, and insulating layer 235 included in memory cells 10C and 10E may also have a stacked structure of two or more layers.

[0418] The insulating layer 135 included in transistor 100L includes insulating layer 135a and insulating layer 135b on insulating layer 135a. Preferably, one of insulating layer 135a and insulating layer 135b includes an insulating layer having a region containing oxygen that has been removed by heating. Alternatively, another preferably includes a hydrogen-barrier insulating layer.

[0419] Therefore, oxygen can be supplied from insulating layer 135a or insulating layer 135b to semiconductor layer 130, and hydrogen diffusion into semiconductor layer 130 can be suppressed. Thus, transistor 100L can be a highly reliable transistor.

[0420] Specifically, it is preferable to use a silicon nitride film as the insulating layer 135a and a silicon oxide film as the insulating layer 135b. Alternatively, it is preferable to use a silicon oxide film as the insulating layer 135a and a silicon nitride film as the insulating layer 135b.

[0421] Transistor 100L is shown as an example where an insulating layer 135a is disposed in contact with the bottom and side surfaces of a recess in conductive layer 120b, and an insulating layer 135b is disposed on the insulating layer 135a. For example, by stacking an insulating film that will become insulating layer 135a and an insulating film that will become insulating layer 135b, two insulating films can be formed. FIG. 16A The structure shown includes insulating layers 135a and 135b.

[0422] FIG. 16B This is a cross-sectional view showing an example structure of a semiconductor device including transistor 100M, and showing... FIG. 4A The example shown is an opening 190 with a tapered sidewall. Note that although in FIG. 16B Although not shown in the figure, the sidewalls of opening 290 and opening 390 may also have a tapered shape, similar to the sidewall of opening 190. Furthermore, for example, the sidewalls of openings 190, 290, and 390 included in storage cells 10A to 10K may also have a tapered shape.

[0423] By making the sidewalls of the opening 190 tapered, the coverage of the insulating layer 135, semiconductor layer 130, insulating layer 181, etc., can be improved, thereby reducing defects such as voids. When the sidewalls of the opening 190 have a tapered shape, for example, the tapered angle θ180 of the side of the insulating layer 180a inside the opening 190 is preferably 45 degrees or more and less than 90 degrees. Specifically, when the tapered angle is 80 degrees or more and less than 90 degrees, miniaturization or high integration of the semiconductor device can be achieved, so it is preferred. Furthermore, when the tapered angle is 45 degrees or more or 50 degrees or more and less than 80 degrees, or 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less, the coverage of the film formed inside the opening 190 is improved, so it is preferred.

[0424] Alternatively, for example, the sidewalls of the opening 190 may also have an inverted conical shape. In other words, the cone angle θ180 of the side of the insulating layer 180a inside the opening 190 may also be greater than 90 degrees.

[0425] <Examples of Semiconductor Device Manufacturing Methods>

[0426] Next, a method for manufacturing a semiconductor device according to one aspect of the present invention will be described. Note that, regarding the materials and forming methods of each constituent element, the same parts as those already described are sometimes omitted.

[0427] Note that a thin film (an insulating film, a semiconductor film, a conductive film, or the like) included in the semiconductor device can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0428] As the sputtering method, an RF sputtering method in which a high-frequency power is used as a sputtering power source, a DC sputtering method in which a direct-current power is used, and a pulse DC sputtering method in which a voltage applied to a sputtering target is changed in a pulse manner can be given. The RF sputtering method is mainly used for depositing an insulating film, and the DC sputtering method is mainly used for depositing a metal conductive film. Further, the pulse DC sputtering method is mainly used for depositing a compound such as an oxide, a nitride, or a carbide by a reactive sputtering method.

[0429] Further, the CVD method can be classified into a plasma CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD method using light, and the like. Further, the CVD method can be classified into a metal CVD (MCVD) method, a metal organic CVD (MOCVD) method, and the like depending on a source gas used.

[0430] By using the plasma CVD method, a high-quality film can be obtained at a low temperature. Further, since plasma is not used, the thermal CVD method is a deposition method in which plasma damage to an object to be processed can be reduced. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like), and the like included in a semiconductor device sometimes have charge accumulation due to reception of electric charges from plasma. At this time, the wiring, the electrode, the element, and the like included in the semiconductor device are sometimes damaged by the accumulated electric charges. On the other hand, since the above plasma damage does not occur in the thermal CVD method in which plasma is not used, the yield of the semiconductor device can be improved. Further, in the thermal CVD method, plasma damage at the time of deposition does not occur, so that a film with few defects can be obtained.

[0431] As the ALD method, a thermal ALD method in which only thermal energy is used to cause a precursor and a reactant to react, a PEALD method in which a reactant excited by plasma is used, and the like can be employed.

[0432] The ALD method can deposit atoms one layer at a time, and thus has the following effects: it can deposit an extremely thin film; it can deposit on a structure with a high aspect ratio or a surface with a large step; it can deposit with few defects such as pinholes; it can deposit with high coverage; it can deposit at low temperature; and the like. Furthermore, in the PEALD method, deposition can be performed at a lower temperature by utilizing plasma, and thus is sometimes preferable. In addition, the precursors used in the ALD method sometimes contain elements such as carbon or chlorine. Thus, a film provided by the ALD method sometimes contains more elements such as carbon or chlorine than a film provided by another deposition method. Furthermore, the amount of these elements can be quantified by XPS or SIMS. Note that the deposition method of the metal oxide of one embodiment of the present application utilizes the ALD method, but the amount of carbon and chlorine contained in a film is sometimes small compared to the case where the ALD method is used without employing one or both of the conditions of high substrate temperature at the time of deposition and an impurity removal process.

[0433] The ALD method is different from a deposition method in which particles released from a target are deposited, and is a deposition method in which a film is formed by a reaction at a surface of an object to be processed. Thus, the ALD method is a deposition method which is less affected by the shape of an object to be processed and has good step coverage. In particular, the ALD method has high step coverage and thickness uniformity, and thus is suitable for, for example, a case where a surface of an opening portion with a high aspect ratio is covered.

[0434] The CVD method and the ALD method are different from a sputtering method in which particles released from a target or the like are deposited. Thus, the CVD method and the ALD method are deposition methods which are less affected by the shape of an object to be processed and have good step coverage. In particular, the ALD method has high step coverage and thickness uniformity, and thus the ALD method is suitable for, for example, a case where a surface of an opening portion with a high aspect ratio is covered. However, the deposition rate of the ALD method is slow, and thus the ALD method is sometimes preferably used in combination with another deposition method such as the CVD method which has a high deposition rate.

[0435] Furthermore, when the CVD method is used, a film with an arbitrary composition can be deposited in accordance with the flow ratio of source gases. For example, when the CVD method is used, a film whose composition continuously changes can be deposited by changing the flow ratio of source gases while deposition is performed. When deposition is performed while the flow ratio of source gases is changed, the deposition time can be shortened compared to a case where deposition is performed using a plurality of deposition chambers, because time required for transfer or adjustment of pressure is not needed. Thus, the productivity of semiconductor devices can be improved in some cases.

[0436] When the ALD method is used, a film with an arbitrary composition can be deposited by simultaneously introducing different kinds of precursors. Alternatively, a film with an arbitrary composition can be deposited by controlling the number of cycles of each precursor while different kinds of precursors are introduced.

[0437] In addition, thin films (insulating films, semiconductor films, and conductive films, etc.) constituting semiconductor devices can be formed using wet deposition methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor knife coating, slot coating, roller coating, curtain coating, or doctor blade coating.

[0438] Furthermore, when processing thin films constituting semiconductor devices, methods such as photolithography can be used. Alternatively, nanoimprint lithography, sandblasting, or lift-off methods can also be used to process the thin films. Additionally, thin films of the desired shape can be directly formed using deposition methods that utilize metal masks or similar masking techniques.

[0439] Photolithography typically involves two methods. One method involves forming a resist mask on the thin film to be processed, for example, by etching the film and then removing the resist mask. The other method involves depositing a photosensitive thin film, followed by exposure and development to shape the film into the desired form.

[0440] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm), or a mixture of these rays. Additionally, ultraviolet light, KrF lasers, or ArF lasers can also be used. Furthermore, immersion lithography can also be used. Extreme ultraviolet (EUV) light or X-rays can also be used as the light for exposure. Alternatively, an electron beam can be used instead of the light for exposure. Extreme ultraviolet light, X-rays, or electron beams allow for extremely fine processing and are therefore preferred. Note that when exposure is performed by scanning with a beam such as an electron beam, a photomask is not required.

[0441] As a method for etching thin films, dry etching, wet etching, and sandblasting can be used.

[0442] [Example of a manufacturing method for storage cell 10]

[0443] Next, use FIG. 17A to FIG. 24 The instructions include FIG. 2A and FIG. 2B An example of a method for manufacturing a semiconductor device for the shown memory cell 10. FIG. 17A to FIG. 24 Show side by side along FIG. 2A The cross-sectional view shown is along the dotted line A1-A2 and along... FIG. 2B The cross-sectional view shown is the dotted line B1-B2.

[0444] First, such as FIG. 17AAs shown in FIG. 1, an insulating layer 110 is formed on a substrate (not shown), a conductive layer 120a is formed on the insulating layer 110, and a conductive layer 120b is formed on the conductive layer 120a. Further, an insulating layer 180a is formed on the conductive layer 120b and the insulating layer 110, and a conductive layer 155 is formed on the insulating layer 180a.

[0445] Further, it is preferable to perform a planarization process to planarize the top surface of the insulating layer 180a after the insulating layer 180a is deposited. As the planarization process, it is preferable to use a CMP process. Further, a planarization process using etching (also referred to as a back-etch process) can also be performed. By performing the planarization process of the insulating layer 180a, the surface of the conductive layer 155 can be planarized, and thus the disconnection of the conductive layer 155 can be suppressed. Further, the planarization process can not be performed, in which case the manufacturing cost can be reduced.

[0446] Next, as shown in FIG. 2, an insulating layer 180b is formed on the conductive layer 155 and the insulating layer 180a, a conductive layer 140a is formed on the insulating layer 180b, and a conductive layer 140b is formed on the conductive layer 140a. FIG. 17B Next, as shown in FIG. 3, an opening portion 190 reaching the conductive layer 120 is formed in the conductive layer 140b, the conductive layer 140a, the insulating layer 180b, the conductive layer 155, and the insulating layer 180a. At this time, it is preferable to provide a recess at a position of the conductive layer 120b overlapping the opening portion 190. It is preferable to expose the bottom surface and the side surface of the recess of the conductive layer 120b by forming the opening portion 190.

[0447] FIG. 17C

[0448] In order to perform microfabrication and reduce the size of the transistor, it is preferable to process a part of the conductive layer 120b, a part of the conductive layer 140a, a part of the conductive layer 140b, a part of the conductive layer 155, a part of the insulating layer 180a, and a part of the insulating layer 180b using anisotropic etching when the opening portion 190 is formed. In particular, processing using a dry etching method is suitable for microfabrication, and is therefore preferable. Further, the opening portion 190 can be formed under processing conditions that differ depending on the layers. Further, depending on the materials and processing conditions of the conductive layer 120b, the conductive layer 140a, the conductive layer 140b, the conductive layer 155, the insulating layer 180a, and the insulating layer 180b, the inclination of the side surface of the conductive layer 120b, the inclination of the side surface of the conductive layer 140a, the inclination of the side surface of the conductive layer 140b, the inclination of the side surface of the conductive layer 155, the inclination of the side surface of the insulating layer 180a, and the inclination of the side surface of the insulating layer 180b inside the opening portion 190 can differ.

[0449] ​​Furthermore, for example, according to the formation process of the opening 190, sometimes at least one of the bottom and side surfaces of the recess of the conductive layer 120b, the side surface of the insulating layer 180a, the side surface of the insulating layer 180b, the side surface of the conductive layer 155, the side surface of the conductive layer 140a, and the top and side surfaces of the conductive layer 140b is provided with a halogen-containing region. Examples of such regions include fluorine-containing regions, chlorine-containing regions, or regions containing both fluorine and chlorine. For example, sometimes halogens from the etching gas used in dry etching remain in this region.

[0450] Next, a heat treatment may be performed. For example, the heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower.

[0451] The heat treatment is performed in an atmosphere of nitrogen or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when heat treatment is performed in a mixed atmosphere of nitrogen and oxygen gas, the oxygen gas ratio is preferably set to about 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then heat treatment can be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the detached oxygen. By performing the above-described heat treatment, impurities such as water contained in the insulating layers 180a and 180b can be reduced before the deposition of the semiconductor layer 130.

[0452] Furthermore, the gas used in the above-described heat treatment is preferably of high purity. For example, the water content of the gas used in the above-described heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By using a high-purity gas for heat treatment, the absorption of moisture and the like by the insulating layers 180a and 180b can be prevented as much as possible.

[0453] Next, as FIG. 17D As shown, an insulating layer 135 is formed to cover the opening 190 and has a region located on the conductive layer 140b. The insulating layer 135 is provided to contact the bottom and side surfaces of the recess of the conductive layer 120b, the side surface of the insulating layer 180a, the side surface of the conductive layer 155, the side surface of the insulating layer 180b, the side surface of the conductive layer 140a, and the top and side surfaces of the conductive layer 140b.

[0454] The insulating layer 135 is a layer disposed inside the opening 190, so it is preferably formed using CVD or ALD methods, and more preferably using ALD methods. This allows the insulating layer 135 to be disposed with high coverage.

[0455] Next, as shown in FIG. 1C, the top surface of the conductive layer 140 is exposed by processing the insulating layer 135, and the conductive layer 120 is exposed in the opening portion 190. It is preferable that the bottom surface of the recess of the conductive layer 120b be exposed in the opening portion 190. FIG. 18A

[0456] The insulating layer 135 can be processed without using photolithography. For example, the entire surface of the insulating layer 135 can be processed by anisotropic etching without forming a resist mask. For example, the insulating layer 135 is processed by anisotropic etching until the top surface of the conductive layer 140b is exposed. Thereby, the region of the insulating layer 135 located on the top surface of the conductive layer 140 and the region located on the bottom surface of the opening portion 190 can be removed, and the insulating layer 135 can remain only on the side surface inside the opening portion 190. It is preferable that the insulating layer 135 be processed by anisotropic etching with high anisotropy using a dry etching method.

[0457] Here, by forming the insulating layer 135 after forming the conductive layer 140, compared to the case where the insulating layer 135 is formed without forming the conductive layer 140, it is possible to suppress the continuation of anisotropic etching of the insulating layer 135 after the region of the insulating layer 135 located outside the opening portion 190 is removed. Therefore, for example, it is possible to prevent the side surface of the conductive layer 155 on the side of the opening portion 190 from being exposed. Therefore, for example, it is possible to prevent the conductive layer 155 from contacting the semiconductor layer 130 formed later. Thereby, it is possible to realize a semiconductor device manufacturing method with high yield.

[0458] In addition, as shown in FIG. 1C, when the insulating layer 135 is processed, a portion of the conductive layer 120b can be removed, and a recess can be provided in the conductive layer 120b. FIG. 18A

[0459] Next, as shown in FIG. 1C, the top surface of the conductive layer 140 is exposed by processing the insulating layer 135, and the conductive layer 120 is exposed in the opening portion 190. It is preferable that the bottom surface of the recess of the conductive layer 120b be exposed in the opening portion 190. FIG. 18B

[0460] The semiconductor layer 130 can be deposited, for example, by a sputtering method, an ALD method, a CVD method, a vacuum evaporation method, an MBE method, or a PLD method.

[0461] It is preferable that the semiconductor layer 130 be formed as a film having a thickness as uniform as possible along the bottom surface and the side surface of the recess of the conductive layer 120b, the insulating layer 135, and the top surface of the conductive layer 140b. By depositing using the ALD method, a thin film can be deposited with high controllability. Therefore, it is preferable that the semiconductor layer 130 be deposited using the ALD method.​​​

[0462] Further, when the crystallinity of the semiconductor layer 130 is high, diffusion of impurities in the semiconductor layer 130 is inhibited, and thus the electric characteristics of the transistor are not easily changed, which can improve the reliability. The semiconductor layer 130 is preferably formed by a sputtering method because a layer with high crystallinity can be easily formed compared to the case of using an ALD method.

[0463] In the case where the semiconductor layer 130 is formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the deposited oxide film can be increased. In the case where the above oxide film is deposited by a sputtering method, for example, an In-M-Zn oxide target or the like can be used.

[0464] In the case where the semiconductor layer 130 is formed by a sputtering method, when deposition is performed at a proportion of oxygen contained in the sputtering gas of more than 30 % and less than or equal to 100 %, preferably, more than or equal to 70 % and less than or equal to 100 %, an oxygen-excess oxide semiconductor is formed. A transistor in which an oxygen-excess oxide semiconductor is used for a channel formation region can have high reliability. Note that one embodiment of the present application is not limited to this. When deposition is performed at a proportion of oxygen contained in the sputtering gas of more than or equal to 1 % and less than or equal to 30 %, preferably, more than or equal to 5 % and less than or equal to 20 %, an oxygen-deficient oxide semiconductor is formed. A transistor in which an oxygen-deficient oxide semiconductor is used for a channel formation region can have high field-effect mobility. Further, by performing deposition while heating a substrate, the crystallinity of the semiconductor layer 130 can be increased.

[0465] Further, the method for manufacturing a semiconductor layer can be described in Embodiment 2.

[0466] Next, heat treatment is preferably performed. The heat treatment is preferably performed at a temperature at which the semiconductor layer 130 is not polycrystallized. The temperature of the heat treatment is preferably higher than or equal to 100 °C and lower than or equal to 650 °C, more preferably higher than or equal to 250 °C and lower than or equal to 600 °C, still more preferably higher than or equal to 350 °C and lower than or equal to 550 °C. Details of the heat treatment can be described in the above.

[0467] Further, a gas used in the above heat treatment is preferably highly purified. By performing heat treatment using a highly purified gas, moisture can be prevented from being absorbed by the semiconductor layer 130 as much as possible.

[0468] In this embodiment, as a heat treatment, a process is performed for 1 hour at a nitrogen to oxygen gas flow ratio of 4:1 and a temperature of 450°C. This oxygen-containing heat treatment reduces impurities such as carbon, water, and hydrogen in the semiconductor layer 130. By reducing impurities in the film, the crystallinity of the semiconductor layer 130 is improved, resulting in a denser structure. This increases the crystalline region in the semiconductor layer 130 and reduces in-plane non-uniformity within the crystalline region. Therefore, the in-plane non-uniformity of the transistor's electrical characteristics can be reduced.

[0469] Furthermore, if at least one of the insulating layers 180a, 180b, and 135 contains oxygen, it is preferable to supply oxygen from the oxygen-containing insulating layer to the channel formation region of the semiconductor layer 130 by heat treatment. This reduces oxygen vacancies and VoH.

[0470] Thus, oxygen released by heating (also known as excess oxygen) is sometimes supplied to the semiconductor layer 130 from an insulating layer in contact with or near the semiconductor layer 130. Excess oxygen has the ability to trap electrons, so it readily forms a negative charge. Therefore, a normally-off transistor can be realized by shifting the threshold voltage of the transistor in the positive direction.

[0471] Next, as FIG. 18C As shown, semiconductor layer 130, conductive layer 140a, and conductive layer 140b are processed to remove a portion of semiconductor layer 130, conductive layer 140a, and conductive layer 140b. This exposes a portion of the top surface of insulating layer 180b. Semiconductor layer 130, conductive layer 140a, and conductive layer 140b can be processed using the same mask. This reduces the number of masks required for manufacturing the semiconductor device, and is therefore preferred.

[0472] Next, as FIG. 19A As shown, an insulating layer 181A is formed in a manner that covers the semiconductor layer 130. Specifically, the insulating layer 181A is formed in a manner that covers the semiconductor layer 130, the side surface of the conductive layer 140b, the side surface of the conductive layer 140a, and the top surface of the insulating layer 180b.

[0473] An insulating layer 181A is formed along an opening 190 with a large aspect ratio. Specifically, the insulating layer 181A is formed along a recess in the semiconductor layer 130 formed at a position overlapping the opening 190. Therefore, when depositing the insulating layer 181A, a deposition method with good coverage is preferably used. The insulating layer 181A is preferably deposited using, for example, a CVD method or an ALD method, and more preferably using an ALD method. The insulating layer 181A can be formed in such a way that it has a recess at the position overlapping the opening 190.

[0474] Next, as FIG. 19A As shown, an insulating layer 183A is formed on an insulating layer 181A such that it has a region located inside the opening 190. The insulating layer 183A can be deposited, for example, using CVD, ALD, sputtering, vacuum evaporation, MBE, or PLD methods.

[0475] Next, as FIG. 19B As shown, the insulating layer 183A is planarized until at least a portion of the top surface of the insulating layer 181A is exposed. In other words, the insulating layer 183A is planarized with the insulating layer 181A as the endpoint. This forms an insulating layer 183 having a region located inside the opening 190. Specifically, an insulating layer 183 is formed having a region located inside the recess of the insulating layer 181A. For example, the insulating layer 183 can be formed by filling the recess of the insulating layer 181A. As a planarization process, CMP processing is preferred.

[0476] Even after planarization, some insulating layer 183A remains. For example, insulating layer 183A remains in areas that do not overlap with either the opening 190 or the conductive layer 140. FIG. 3A and FIG. 3B As shown, the insulating layer 183A remains around the semiconductor layer 130 and the conductive layer 140. Specifically, the insulating layer 183A remains around the side outside the opening 190 of the semiconductor layer 130 and the side opposite to the side of the opening 190 of the conductive layer 140 when viewed from above.

[0477] By planarizing the insulating layer 183A, such as... FIG. 3A and FIG. 3B As shown, an opening 191 overlapping with the semiconductor layer 130 is formed, and an island-shaped insulating layer 183 is formed inside the opening 191. In other words, by planarizing the insulating layer 183A, an opening 191 overlapping with the conductive layer 140 and the opening 190 is formed, and an island-shaped insulating layer 183 is formed inside the opening 191.

[0478] Next, as FIG. 19CAs shown in FIG. 17A, a part of the insulating layer 181A is processed to remove a part of the insulating layer 181A. Thus, the insulating layer 181 having a region inside the opening portion 190 is formed. Further, at least a part of the top surface of the semiconductor layer 130 is exposed. For example, the insulating layer 181A can be processed with the insulating layer 183 and the insulating layer 183A as masks. In this case, at least a part of the region of the insulating layer 181A which does not overlap with the insulating layer 183 can be removed. Specifically, a region of the insulating layer 181A which does not overlap with both the insulating layer 183A and the insulating layer 183 can be removed. By the above process, the insulating layer 181 can be formed so as to overlap with the insulating layer 183, and a region of the semiconductor layer 130 overlapping with the conductive layer 140 is exposed.

[0479] After the insulating layer 181 is formed by processing the insulating layer 181A, a part of the insulating layer 181A remains. Specifically, the insulating layer 181A remains in a region overlapping with the insulating layer 183A. By processing the insulating layer 181A, as shown in FIG. 17B, the insulating layer 181 can be formed so as to overlap with the insulating layer 183A, and a region of the semiconductor layer 130 overlapping with the conductive layer 140 is exposed. FIG. 3A and FIG. 3B As shown in FIG. 17A, an opening portion 191 overlapping with the semiconductor layer 130 is formed in the insulating layer 181A, and an island-shaped insulating layer 181 is formed inside the opening portion 191. In other words, by processing the insulating layer 181A, the opening portion 191 overlapping with the conductive layer 140 and the opening portion 190 is formed, and the island-shaped insulating layer 181 is formed inside the opening portion 191.

[0480] As shown in FIG. 17A, an opening portion 191 overlapping with the semiconductor layer 130 is formed in the insulating layer 181A, and an island-shaped insulating layer 181 is formed inside the opening portion 191. In other words, by processing the insulating layer 181A, the opening portion 191 overlapping with the conductive layer 140 and the opening portion 190 is formed, and the island-shaped insulating layer 181 is formed inside the opening portion 191. FIG. 19A to FIG. 19C FIG. 19C As shown in FIG. 17A, an opening portion 191 overlapping with the semiconductor layer 130 is formed in the insulating layer 181A, and an island-shaped insulating layer 181 is formed inside the opening portion 191. In other words, by processing the insulating layer 181A, the opening portion 191 overlapping with the conductive layer 140 and the opening portion 190 is formed, and the island-shaped insulating layer 181 is formed inside the opening portion 191.

[0481] ​Here, when planarizing the insulating layer 183A after depositing the insulating layer 181A without depositing the insulating layer 181A, for example, until at least a portion of the top surface of the semiconductor layer 130 is exposed, sometimes planarization is performed not only on the insulating layer 183A but also on the semiconductor layer 130. As a result, sometimes the area of ​​the semiconductor layer 130 that contacts the conductive layer 140 is removed. Furthermore, it is difficult to control the thickness of the area of ​​the semiconductor layer 130 overlapping the conductive layer 140. As a result, the reliability of the semiconductor device sometimes decreases. Therefore, by depositing the insulating layer 183A after depositing the insulating layer 181A, and then planarizing the insulating layer 183A until at least a portion of the top surface of the insulating layer 181A is exposed, planarization of the semiconductor layer 130 can be prevented. Therefore, a semiconductor device manufacturing method with high yield can be realized.

[0482] like FIG. 19A to FIG. 19C As shown, insulating layers 181 and 183 can be formed without photolithography. That is, insulating layer 183 can be formed through planarization, and insulating layer 181 can be formed by processing using insulating layer 183 as a mask. Therefore, compared to forming insulating layers 181 and 183 using photolithography, the number of manufacturing steps for the semiconductor device can be reduced. This reduces the manufacturing cost of the semiconductor device, thereby providing a low-cost semiconductor device. Alternatively, insulating layers 181 and 183 can also be formed using photolithography. In this case, for example, insulating layers 181A and 183A can be processed such that insulating layers 181A and 183A do not remain on the outer side of conductive layer 140 (the side opposite to opening 190).

[0483] As described above, in the manufacturing process of a semiconductor device according to one aspect of the present invention, the insulating layer 183A undergoes a planarization process ending at the insulating layer 181A. Therefore, by using a material that minimizes the thinning of the insulating layer 181A during the planarization process ending at the insulating layer 181A for the insulating layer 183A, it is preferable to prevent the semiconductor layer 130 from being planarized while simultaneously reducing the thickness of the insulating layer 181A during deposition. Furthermore, in the manufacturing process of a semiconductor device according to one aspect of the present invention, the insulating layer 181A is processed using the insulating layers 183 and 183A as masks. Therefore, when a material with a high etch selectivity relative to the insulating layer 181A is used for the insulating layer 183A, it is preferable to suppress the processing of the insulating layers 183 and 183A during the processing of the insulating layer 181A. For example, if silicon nitride is used as the insulating layer 181A, silicon oxide is preferably used as the insulating layer 183A. Alternatively, for example, the insulating layer 181A before processing can be referred to as the first insulating film, and the insulating layer 183A before planarization can be referred to as the second insulating film.

[0484] Next, as FIG. 20A As shown, a conductive layer 220a is deposited on insulating layer 183, insulating layer 183A, and semiconductor layer 130, and a conductive layer 220b is deposited on conductive layer 220a. Next, as... FIG. 20B As shown, conductive layers 220a and 220b are processed. For example, a portion of conductive layers 220a and 220b is removed such that a portion of the top surface of semiconductor layer 130 and the top surface of insulating layer 183A are exposed. This forms conductive layer 220. Conductive layer 220 can be formed in contact with the top surface of insulating layer 183, the side surface of insulating layer 181, and the top surface of semiconductor layer 130.

[0485] Through the above process, a transistor 100 including a conductive layer 120, a conductive layer 140, a conductive layer 155, a conductive layer 220, a semiconductor layer 130, and an insulating layer 135 can be formed.

[0486] Next, as FIG. 21A As shown, an insulating layer 280 is formed on the conductive layer 220, the semiconductor layer 130 and the insulating layer 183A, a conductive layer 240a is formed on the insulating layer 280 and a conductive layer 240b is formed on the conductive layer 240a.

[0487] Next, as FIG. 21A As shown, an opening 290 reaching the conductive layer 220 is formed in the conductive layer 240b, conductive layer 240a, and insulating layer 280. It is preferable to provide a recess in the conductive layer 220b at a position overlapping the opening 290. Preferably, the bottom and side surfaces of the recess in the conductive layer 220b are exposed by forming the opening 290.

[0488] The opening 290 can be formed using the same method as the opening 190. For example, the processing of the conductive layer 240b and the conductive layer 240a can be performed under the same conditions as the processing of the conductive layer 140b and the conductive layer 140a, respectively. Similarly, the processing of the insulating layer 280 can be performed, for example, under the same conditions as the processing of the insulating layer 180a or the insulating layer 180b.

[0489] Next, as FIG. 21BThe semiconductor layer 230 is formed so as to cover the opening portion 290 and be in contact with the conductive layer 220 and the conductive layer 240, as shown. The semiconductor layer 230 can be formed so as to be in contact with the bottom surface and the side surface of the recess of the conductive layer 220, the opening portion 290 side of the side surface of the conductive layer 240, and the top surface of the conductive layer 240. Specifically, the semiconductor layer 230 can be formed so as to be in contact with the bottom surface and the side surface of the recess of the conductive layer 220b, the insulating layer 280, the opening portion 290 side of the side surface of the conductive layer 240a and the conductive layer 240b, and the top surface of the conductive layer 240b. The semiconductor layer 230 can be formed using the same method as the semiconductor layer 130.

[0490] Next, as shown in FIG. 13B, a portion of the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b is removed by processing the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b. Thereby, a portion of the top surface of the insulating layer 280 is exposed. In the process shown in FIG. 13B, the same mask as in the process shown in FIG. 13A can be used to process the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b. Thereby, the number of masks required for manufacturing the semiconductor device can be reduced, so this is preferable. FIG. 21B FIG. 21B Next, as shown in FIG. 13B, a portion of the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b is removed by processing the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b. Thereby, a portion of the top surface of the insulating layer 280 is exposed. In the process shown in FIG. 13B, the same mask as in the process shown in FIG. 13A can be used to process the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b. Thereby, the number of masks required for manufacturing the semiconductor device can be reduced, so this is preferable.

[0491] Next, as shown in FIG. 13B, a portion of the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b is removed by processing the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b. Thereby, a portion of the top surface of the insulating layer 280 is exposed. In the process shown in FIG. 13B, the same mask as in the process shown in FIG. 13A can be used to process the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b. Thereby, the number of masks required for manufacturing the semiconductor device can be reduced, so this is preferable. FIG. 22 The insulating layer 250 is formed so as to cover the semiconductor layer 230. Specifically, the insulating layer 250 is formed so as to cover the side surface of the semiconductor layer 230, the side surface of the conductive layer 240b, the side surface of the conductive layer 240a, and the top surface of the insulating layer 280b.

[0492] The insulating layer 250 is formed along the opening portion 290 having a large aspect ratio. Specifically, the insulating layer 250 is formed along the recess of the semiconductor layer 230 formed at a position overlapping the opening portion 290. Thereby, when depositing the insulating layer 250, it is preferable to use a deposition method having good coverage. The insulating layer 250 is preferably deposited using a CVD method or an ALD method, for example, and more preferably using an ALD method. The insulating layer 250 can have a recess at a position overlapping the opening portion 290.

[0493] FIG. 22 Next, as shown in FIG. 13B, a portion of the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b is removed by processing the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b. Thereby, a portion of the top surface of the insulating layer 280 is exposed. In the process shown in FIG. 13B, the same mask as in the process shown in FIG. 13A can be used to process the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b. Thereby, the number of masks required for manufacturing the semiconductor device can be reduced, so this is preferable.

[0494] ​​The conductive layer 320a is formed in the middle of the opening portion 290 having a large aspect ratio. Therefore, when the conductive layer 320a is deposited, it is preferable to use a deposition method having good coverage, and more preferably, a CVD method or an ALD method or the like.

[0495] Through the above process, the transistor 200 including the conductive layer 220, the conductive layer 240, the conductive layer 320, the semiconductor layer 230, and the insulating layer 250 can be formed.

[0496] Next, as shown in FIG. 3B, the insulating layer 380a is formed over the conductive layer 320 and the insulating layer 250, and the conductive layer 355 is formed over the insulating layer 380a. Further, it is preferable to perform planarization treatment to planarize the top surface of the insulating layer 380a after the insulating layer 380a is deposited. As the planarization treatment, it is preferable to use CMP treatment. Alternatively, etch-back treatment can be performed. By performing the planarization treatment of the insulating layer 380a, the surface of the conductive layer 355 can be planarized, whereby disconnection of the conductive layer 355 can be suppressed. Further, the planarization treatment can not be performed, in which case manufacturing cost can be reduced. FIG. 23 Next, as shown in FIG. 3C, the insulating layer 380b is formed over the conductive layer 355 and the insulating layer 380a, the conductive layer 340a is formed over the insulating layer 380b, and the conductive layer 340b is formed over the conductive layer 340a.

[0497] FIG. 23 Next, as shown in FIG. 3C, the insulating layer 380b is formed over the conductive layer 355 and the insulating layer 380a, the conductive layer 340a is formed over the insulating layer 380b, and the conductive layer 340b is formed over the conductive layer 340a.

[0498] Next, as shown in FIG. 3D, the opening portion 390 reaching the conductive layer 320 is formed in the conductive layer 340b, the conductive layer 340a, the insulating layer 380b, the conductive layer 355, and the insulating layer 380a. At this time, it is preferable to provide a recess in the conductive layer 320b at a position overlapping with the opening portion 390. It is preferable to expose the bottom surface and the side surface of the recess of the conductive layer 320b by forming the opening portion 390. FIG. 23 The opening portion 390 can be formed using the same method as the opening portion 190. For example, the processing of the conductive layer 340b, the processing of the conductive layer 340a, the processing of the insulating layer 380b, the processing of the conductive layer 355, and the processing of the insulating layer 380a can be performed under the same conditions as the processing of the conductive layer 140b, the processing of the conductive layer 140a, the processing of the insulating layer 180b, the processing of the conductive layer 155, and the processing of the insulating layer 180a, respectively.

[0499]

[0500] ​​Next, an insulating layer 335 is formed to cover the opening 390 and have a region located on the conductive layer 340b. The insulating layer 335 is provided in contact with the bottom and side surfaces of the recess of the conductive layer 320b, the side surface of the insulating layer 380a, the side surface of the conductive layer 355, the side surface of the insulating layer 380b, the side surface of the conductive layer 340a, and the top and side surfaces of the conductive layer 340b. Similar to the insulating layer 135, the insulating layer 335 is preferably formed by CVD or ALD, and more preferably by ALD.

[0501] Next, the top surface of the conductive layer 340 is exposed by processing the insulating layer 335, and the conductive layer 320 is exposed in the opening 390. Preferably, the bottom surface of the recess of the conductive layer 320b is exposed in the opening 390. The processing of the insulating layer 335 can be performed in the same way as the processing of the insulating layer 135.

[0502] Next, as FIG. 23 As shown, a semiconductor layer 330 is formed to cover the opening 390 and to contact the top surface of the conductive layer 340 and the conductive layer 320. The semiconductor layer 330 is formed by covering the opening 390 with an insulating layer 335. The semiconductor layer 330 can be formed to contact the bottom and side surfaces of the recess in the conductive layer 320b, the insulating layer 335, and the top surface of the conductive layer 340b. The semiconductor layer 330 can be formed using the same method as the semiconductor layer 130.

[0503] Next, semiconductor layer 330, conductive layer 340a, and conductive layer 340b are processed to remove a portion of each layer. This exposes a portion of the top surface of insulating layer 380b. Similar to semiconductor layer 130, conductive layer 140a, and conductive layer 140b, semiconductor layer 330, conductive layer 340a, and conductive layer 340b can be processed using the same mask. This reduces the number of masks required to manufacture the semiconductor device, which is preferable.

[0504] Next, as FIG. 24 As shown, an insulating layer 350 is formed to cover the semiconductor layer 330. Specifically, the insulating layer 350 is formed to cover the semiconductor layer 330, the side surface of the conductive layer 340b, the side surface of the conductive layer 340a, and the top surface of the insulating layer 380b. The insulating layer 350 can be formed using the same method as the insulating layer 250.

[0505] Next, as FIG. 24The conductive layer 365a is formed over the insulating layer 350 so as to have a region inside the opening portion 390 as illustrated. Further, the conductive layer 365b is formed over the conductive layer 365a. The conductive layer 365a is preferably formed so as to be embedded in the opening portion 390. Specifically, the conductive layer 365a is preferably formed so as to fill the recess of the insulating layer 350. Note that depending on the diameter of the opening portion 390 and the thickness of the conductive layer 365a, the conductive layer 365b is sometimes formed inside the opening portion 390. The conductive layer 365 can be formed by the same method as the conductive layer 320.

[0506] The transistor 300 including the conductive layer 320, the conductive layer 340, the conductive layer 355, the conductive layer 365, the semiconductor layer 330, the insulating layer 335, and the insulating layer 350 can be formed by the above process. Further, the memory cell 10 including the transistor 100, the transistor 200, and the transistor 300 can be manufactured. Furthermore, the semiconductor device including the memory cell 10 can be manufactured.

[0507] In the case of manufacturing the memory cell 10H, the formation of the insulating layer 350 is performed by the same method as described above. Next, a sacrificial layer is formed so as to have a region inside the opening portion 390. Next, the insulating layer 383 is deposited so as to cover the insulating layer 350 and the sacrificial layer, and the insulating layer 385 is deposited over the insulating layer 383. Next, the insulating layer 385, the insulating layer 383, and the sacrificial layer are subjected to a planarization treatment. Thus, the top surface of the sacrificial layer is exposed, and the top surfaces of the sacrificial layer, the insulating layer 383, and the insulating layer 385 are planarized. Next, the sacrificial layer is removed. Thus, the opening portion 370 is formed in the insulating layer 383. Then, the conductive layer 365 is formed so as to have a region inside the opening portion 390 and the opening portion 370. The memory cell 10H can be manufactured by the above process.

[0508] In the case of manufacturing the memory cell 10I, the formation of the semiconductor layer 330 is performed by the same method as described above. Next, a sacrificial layer is formed so as to have a region inside the opening portion 390. Next, the insulating layer 383 is deposited so as to cover the insulating layer 380b, the conductive layer 240, the semiconductor layer 330, and the sacrificial layer, and the insulating layer 385 is deposited over the insulating layer 383. Next, the insulating layer 385, the insulating layer 383, and the sacrificial layer are subjected to a planarization treatment. Thus, the top surface of the sacrificial layer is exposed, and the top surfaces of the sacrificial layer, the insulating layer 383, and the insulating layer 385 are planarized. Next, the sacrificial layer is removed. Thus, the opening portion 370 is formed in the insulating layer 383.

[0509] Next, the insulating layer 350 is deposited so as to cover the opening portion 370 and the opening portion 390, and the conductive layer 360 is deposited on the insulating layer 350. Next, the conductive layer 360 and the insulating layer 350 are subjected to a planarization treatment. Thus, the top surfaces of the insulating layer 383 and the insulating layer 385 are exposed, and the top surfaces of the conductive layer 360, the insulating layer 350, the insulating layer 383, and the insulating layer 385 are planarized. Then, the conductive layer 365 is formed over the insulating layer 383, the insulating layer 385, and the conductive layer 360. By the above steps, the memory cell 101 can be manufactured.

[0510] The present embodiment can be combined with other embodiments as appropriate. In addition, in the present specification, in the case where a plurality of structural examples are shown in one embodiment, the structural examples can be combined as appropriate.

[0511] (Embodiment 2)

[0512] In this embodiment, an oxide semiconductor layer which can be used as a semiconductor layer of a transistor is described.

[0513] [Oxide Semiconductor Layer]

[0514] The oxide semiconductor layer of one embodiment of the present application preferably contains a metal oxide having crystallinity. As a structure of a metal oxide having crystallinity, a CAAC (c-axis aligned crystal) structure, a poly-crystal structure, and an nc (nano-crystal) structure can be given. By using a metal oxide having crystallinity for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Thus, the reliability of a transistor using the oxide semiconductor layer of one embodiment of the present application can be improved, and the reliability of a semiconductor device in which the transistor is mounted can be improved.

[0515] The oxide semiconductor layer of one embodiment of the present application particularly preferably contains a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals each having a hexagonal rod shape) have c-axis alignment and the plurality of microcrystals are connected without alignment in a-b planes. When a cross-section of an oxide semiconductor layer having a CAAC structure is observed at a high magnification by a transmission electron microscope (TEM), a lattice image in some regions is observed. This indicates that the metal atoms are arranged in a layered manner, and also indicates that the oxide semiconductor layer has a layered crystal structure. Thus, the oxide semiconductor layer having a CAAC structure can be regarded as a layered crystal.

[0516] The crystallinity of the oxide semiconductor layer can be analyzed by X-ray diffraction (XRD), TEM, or electron diffraction (ED), for example. Alternatively, a plurality of the above methods can be combined to perform analysis.

[0517] There is no particular limitation on the crystallinity of the semiconductor material included in the oxide semiconductor layer. For example, the oxide semiconductor layer sometimes includes one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a semiconductor having crystallinity other than a single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor partly having a crystalline region). When the oxide semiconductor layer has crystallinity, the degradation of the transistor characteristics can be suppressed in some cases.

[0518] As the metal oxide included in the oxide semiconductor layer of one embodiment of the present application, for example, an indium oxide, a gallium oxide, and a zinc oxide can be given. The metal oxide of one embodiment of the present application preferably contains at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably contains two or three of indium, an element M, and zinc. Note that the element M is a metal element or a semi-metal element having high bond energy with oxygen, for example, a metal element or a semi-metal element having higher bond energy with oxygen than indium. As the element M, specifically, an aluminum, a gallium, a tin, a yttrium, a titanium, a vanadium, a chromium, a manganese, an iron, a cobalt, a nickel, a zirconium, a molybdenum, a hafnium, a tantalum, a tungsten, a lanthanum, a cerium, a neodymium, a magnesium, a calcium, a strontium, a barium, a boron, a silicon, a germanium, and an antimony, or the like can be given. The element M included in the metal oxide is preferably one or more of the above elements, further preferably one or more o...

Claims

1. A semiconductor device, comprising: First semiconductor layer; First conductive layer; Second conductive layer; Third conductive layer; First insulating layer; Second insulating layer; Third insulating layer; Fourth insulating layer; as well as The fifth insulating layer, The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The second insulating layer is located on the second conductive layer and the first insulating layer. The third conductive layer is located on the second insulating layer. The first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer each have a first opening that reaches the first conductive layer. The third insulating layer is in contact with the side of the second conductive layer inside the first opening. The first semiconductor layer is in contact with the first conductive layer. The first semiconductor layer is in contact with the top surface of the third conductive layer. The first semiconductor layer has a first region inside the first opening that is opposite to the second conductive layer and separated by the third insulating layer. At least a portion of the first region is in contact with the third insulating layer. The fourth insulating layer is located inside the first semiconductor layer within the first opening. The fifth insulating layer is provided and planarized such that it fills the first opening inside the fourth insulating layer. The first semiconductor layer has a second region that overlaps with the third conductive layer. Furthermore, the top surface of the fifth insulating layer is located above the top surface of the second region of the first semiconductor layer.

2. The semiconductor device according to claim 1, further comprising: The sixth insulating layer; as well as The seventh insulating layer, The sixth insulating layer covers the side of the third conductive layer opposite to the side of the first opening. Furthermore, the seventh insulating layer is located on the sixth insulating layer.

3. The semiconductor device according to claim 1, further comprising: Second semiconductor layer; Fourth conductive layer; Fifth conductive layer; Sixth conductive layer; The sixth insulating layer; as well as The seventh insulating layer, The fourth conductive layer is located on the fifth insulating layer. The fourth conductive layer is in contact with the second region. The sixth insulating layer is located on the fourth conductive layer. The fifth conductive layer is located on the sixth insulating layer. The sixth insulating layer and the fifth conductive layer have a second opening that reaches the fourth conductive layer. The second semiconductor layer is in contact with the fourth and fifth conductive layers and has a region located inside the second opening. The seventh insulating layer is located on the second semiconductor layer and inside the second opening, on the inner side of the second semiconductor layer. Furthermore, the sixth conductive layer is located on the seventh insulating layer and inside the second opening, on the inner side of the seventh insulating layer.

4. The semiconductor device according to claim 3, further comprising: Third semiconductor layer; Seventh conductive layer; Eighth conductive layer; Eighth insulating layer; as well as Ninth insulating layer The eighth insulating layer is located on the sixth conductive layer. The seventh conductive layer is located on the eighth insulating layer. The eighth insulating layer and the seventh conductive layer include a third opening extending into the sixth conductive layer. The third semiconductor layer is in contact with the sixth and seventh conductive layers and has a region located inside the third opening. The ninth insulating layer is located on the third semiconductor layer and inside the third opening, on the inner side of the third semiconductor layer. Furthermore, the eighth conductive layer is located on the ninth insulating layer and inside the third opening, situated on the inner side of the ninth insulating layer.

5. The semiconductor device according to claim 4, further comprising: Ninth conductive layer; as well as The tenth insulating layer, The eighth insulating layer includes an eleventh insulating layer and a twelfth insulating layer on the eleventh insulating layer. The ninth conductive layer is located on the eleventh insulating layer. The twelfth insulating layer is located on the ninth conductive layer and the eleventh insulating layer. The eleventh insulating layer, the ninth conductive layer, and the twelfth insulating layer include the third opening. The tenth insulating layer is in contact with the side of the ninth conductive layer inside the third opening. The third semiconductor layer is in contact with the tenth insulating layer inside the third opening. Furthermore, the third semiconductor layer has a third region that is opposite to the eighth conductive layer and opposite to the ninth conductive layer through the ninth insulating layer and through the tenth insulating layer.

6. The semiconductor device according to any one of claims 1 to 5, The first semiconductor layer uses a metal oxide. The metal oxide comprises two or three selected from indium, element M, and zinc. The element M is selected from one or more of the following: aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.

7. The semiconductor device according to any one of claims 3 to 5, Both the first semiconductor layer and the second semiconductor layer use metal oxides. The metal oxide comprises two or three selected from indium, element M, and zinc. The element M is selected from one or more of the following: aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.

8. The semiconductor device according to claim 4 or 5, The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer all use metal oxides. The metal oxide comprises two or three selected from indium, element M, and zinc. The element M is selected from one or more of the following: aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.

9. A method for manufacturing a semiconductor device, comprising the following steps: Form the first conductive layer; A first insulating layer is formed on the first conductive layer; A second conductive layer is formed on the first insulating layer; A second insulating layer is formed on the second conductive layer and the first insulating layer; A third conductive layer is formed on the second insulating layer; A first opening is formed in the third conductive layer, the second insulating layer, the second conductive layer, and the first insulating layer to reach the first conductive layer; A third insulating layer is formed in such a way that it covers the first opening; The top surface of the third conductive layer and the first conductive layer are exposed by processing the third insulating layer using anisotropic etching. A first semiconductor layer is formed in such a manner that it covers the third insulating layer and is in contact with the top surface of the third conductive layer and the first conductive layer; A fourth insulating layer is formed in such a way as to cover the first semiconductor layer; A fifth insulating layer is formed on the fourth insulating layer in such a manner that it has a region located inside the first opening; The fifth insulating layer is planarized until at least a portion of the top surface of the fourth insulating layer is exposed, thereby forming a sixth insulating layer having a region located inside the first opening. A portion of the fourth insulating layer is removed to form a seventh insulating layer having a region located inside the first opening, thereby exposing at least a portion of the top surface of the first semiconductor layer. A fourth conductive layer is formed in such a way that it contacts the top surface of the sixth insulating layer and the top surface of the first semiconductor layer; An eighth insulating layer is formed on the fourth conductive layer; A fifth conductive layer is formed on the eighth insulating layer; A second opening leading to the fourth conductive layer is formed in the fifth conductive layer and the eighth insulating layer; A second semiconductor layer is formed in such a manner that it covers the second opening and is in contact with the fourth conductive layer and the fifth conductive layer; A ninth insulating layer is formed in a manner that covers the second semiconductor layer; as well as A sixth conductive layer is formed on the ninth insulating layer in such a manner that it has a region located inside the second opening.

10. The method for manufacturing a semiconductor device according to claim 9, further comprising the following steps: A tenth insulating layer is formed on the sixth conductive layer; A seventh conductive layer is formed on the tenth insulating layer; A third opening leading to the sixth conductive layer is formed in the seventh conductive layer and the tenth insulating layer; A third semiconductor layer is formed in such a manner that it covers the third opening and is in contact with the sixth and seventh conductive layers; An eleventh insulating layer is formed in such a manner as to cover the third semiconductor layer; as well as An eighth conductive layer is formed on the eleventh insulating layer in such a manner that it has a region located inside the third opening.

11. The method for manufacturing a semiconductor device according to claim 9, further comprising the following steps: A tenth insulating layer is formed on the sixth conductive layer; A seventh conductive layer is formed on the tenth insulating layer; An eleventh insulating layer is formed on the seventh conductive layer and the tenth insulating layer; An eighth conductive layer is formed on the eleventh insulating layer; A third opening leading to the sixth conductive layer is formed in the eighth conductive layer, the eleventh insulating layer, the seventh conductive layer, and the tenth insulating layer. A twelfth insulating layer is formed in such a way as to cover the third opening; The top surface of the eighth conductive layer and the sixth conductive layer are exposed by processing the twelfth insulating layer using anisotropic etching. A third semiconductor layer is formed in such a manner that it covers the twelfth insulating layer and is in contact with the top surface of the eighth conductive layer and the sixth conductive layer; A thirteenth insulating layer is formed in a manner that covers the third semiconductor layer; and A ninth conductive layer is formed on the thirteenth insulating layer in such a manner that it has a region located inside the third opening.

12. The method for manufacturing a semiconductor device according to any one of claims 9 to 11, After planarizing the fifth insulating layer, the fourth insulating layer is processed to remove at least a portion of the area of ​​the fourth insulating layer that does not overlap with the sixth insulating layer.

13. The method for manufacturing a semiconductor device according to any one of claims 9 to 11, By planarizing the fifth insulating layer, a fourth opening overlapping the first semiconductor layer is formed in the fifth insulating layer. Furthermore, by processing the fourth insulating layer, the regions of the fourth insulating layer that do not overlap with either the fifth or sixth insulating layer are removed.

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