Phase change memory cell with crystal structure aligned to seed layer

Abstract

A phase change memory cell includes: an insulating layer; the first electrode is embedded in the insulating layer, and the outer end of the first electrode is partially flush with the outer surface of the insulating layer; a second electrode larger than the first electrode and spaced apart from the first electrode; a crystalline phase change material layer having homogeneous components; and a highly oriented seed layer. The crystal structure of the homogeneous phase change material layer is associated with the crystal structure of the highly oriented seed layer. The homogeneous composition phase change material layer and the highly oriented seed layer are located at least partially between the first electrode and the second electrode.

Description

Background Technology

[0001] This invention generally relates to the electrical, electronic and computer fields, and more particularly to phase-change memory (PCM).

[0002] Phase-change memory (PCM) employs a phase-change material (also abbreviated as PCM; those skilled in the art will understand from the context whether it refers to "memory" or "material"), which can exist in two phases, namely a (poly)crystalline phase and an amorphous phase. An exemplary class of phase-change materials includes germanium-antimony-tellurium (GST) alloys, which are a type of phase-change material from the general group of chalcogenide glasses. GST225 (Ge2Sb2Te5) is a non-limiting example. A phase-change memory cell can store bits (0 or 1) by changing the phase of the phase-change material. Typical devices have a phase-change material sandwiched between two contacts. If the phase-change material is in the crystalline phase, it is relatively conductive and carries a relatively large current. If the phase-change material is in the amorphous phase, it is relatively resistive and carries a relatively low current. Phase-change memory is non-volatile; once the material is crystalline, it remains crystalline; once the material is amorphous, it remains amorphous (as long as the material remains below its crystallization temperature).

[0003] One prior art “mushroom-shaped” PCM cell comprises a polycrystalline PCM region and may or may not have a raised liner. Another prior art “mushroom-shaped” PCM cell comprises a superlattice (alternating layers of two different phase change materials, or alternating layers of a phase change material and TiTe2). It is known that single-crystal PCM devices need to be grown on a Si(111) substrate, where the substrate acts as a growth template. Summary of the Invention

[0004] The present invention provides a phase change memory cell having a crystal structure aligned to a seed layer. In one aspect, an exemplary phase change memory cell includes: an insulating layer; a first electrode embedded in the insulating layer, wherein the outer end of the first electrode is partially flush with the outer surface of the insulating layer; a second electrode larger than the first electrode and spaced apart from the first electrode; a homogeneous crystalline phase change material layer; and a highly oriented seed layer. The crystal structure of the homogeneous phase change material layer is related to the crystal structure of the highly oriented seed layer, and the homogeneous phase change material layer and the highly oriented seed layer are at least partially located between the first and second electrodes.

[0005] Optionally, the homogeneous phase change material layer and the highly oriented seed layer are different materials.

[0006] Optionally, the seed layer has an out-of-plane crystal axis, and the homogeneous phase change material layer has an out-of-plane crystal axis aligned with the out-of-plane crystal axis of the seed layer.

[0007] In another embodiment, the phase-change memory array of these phase-change memory cells includes multiple horizontal lines; multiple vertical lines intersecting the multiple horizontal lines at multiple cell locations; multiple phase-change memory cells located at each of the multiple cell locations; and multiple transistors associated with each of the multiple phase-change memory cells. Each phase-change memory cell includes: an insulating layer; a first electrode embedded in the insulating layer, wherein the outer end of the first electrode is partially flush with the outer surface of the insulating layer; a second electrode larger than the first electrode and spaced apart from the first electrode; a homogeneous crystalline phase-change material layer; and a highly oriented seed layer, wherein the crystal structure of the homogeneous phase-change material layer is related to the crystal structure of the highly oriented seed layer. The homogeneous phase-change material layer and the highly oriented seed layer are at least partially located between the first electrode and the second electrode.

[0008] In another aspect, a method of forming a phase-change memory cell includes providing a starting structure comprising a substrate, an insulating layer outside the substrate, and a first electrode embedded in the insulating layer. The outer end of the first electrode is partially flush with the outer surface of the insulating layer. Further steps include depositing a highly oriented seed layer on the outer surface of the insulating layer and the outer end of the first electrode; epitaxially growing a homogeneous crystalline phase-change material layer on the highly oriented seed layer; and depositing a top electrode material on the homogeneous crystalline phase-change material layer.

[0009] In another aspect, another method of forming a phase change memory cell includes providing a starting structure comprising a substrate, an insulating layer outside the substrate, and a first electrode embedded in the insulating layer. The outer end of the first electrode is partially flush with the outer surface of the insulating layer. Further steps include depositing an amorphous phase change material layer on the outer surface of the insulating layer and the outer end of the first electrode; depositing a highly oriented seed layer on the outer surface of the amorphous phase change material layer at a temperature below the crystallization temperature of the first amorphous phase change material layer to produce the resulting structure; and annealing the resulting structure at a temperature above the crystallization temperature of the first amorphous phase change material layer to induce solid-phase crystallization of the amorphous phase change material layer by serving as a template for the seed layer.

[0010] In another aspect, a further method of forming a phase-change memory cell includes providing a starting structure comprising a substrate, an insulating layer outside the substrate, and a first electrode embedded in the insulating layer. The outer end of the first electrode is partially flush with the outer surface of the insulating layer, and the insulating layer is amorphous. Further steps include preparing the outer surface of the amorphous insulating layer to induce the orientation of a subsequently epitaxially grown homogeneous crystalline phase-change material layer; epitaxially growing the homogeneous crystalline phase-change material layer on the prepared outer surface of the amorphous insulating layer at a temperature that causes the homogeneous crystalline phase-change material layer to grow crystallinely; and depositing a top electrode material on the homogeneous crystalline phase-change material layer.

[0011] In a further aspect, a hardware description language (HDL) design structure is encoded on a machine-readable data storage medium. The HDL design structure includes elements that, when processed in a computer-aided design system, generate machine-executable representations of phase-change memory cells and / or arrays, as described.

[0012] As used herein, "facilitating" an action includes performing an action, making an action easier, assisting in performing an action, or causing an action to be performed. Therefore, by way of example and not limitation, instructions executed on a processor can facilitate an action performed by a semiconductor processing device by sending appropriate data or commands to cause or assist in performing the action. Where an actor facilitates an action by performing actions other than the action itself, the action is still performed by an entity or combination of entities.

[0013] The techniques disclosed herein can provide substantially beneficial technical effects. Some embodiments may not have these potential advantages, and these potential advantages are not necessary for all embodiments. As examples only and not limitations, one or more embodiments may provide one or more of the following:

[0014] Phase-change memory with low reset current (e.g., due to the presence of van der Waals gaps);

[0015] With large R RESET / R SET The window (i.e., the high resistance ratio in two different states, SET and RESET – depending on the application, the higher resistance (R) RESET For example, greater than the lower resistance R SET Phase-change memory (10 times, or preferably more than 100 times);

[0016] It has high programmability (i.e., a large number of SET-RESET cycles before device failure, depending on the application, e.g., at least 10 before failure). 9 Phase-change memory (with multiple cycles);

[0017] Phase-change memory with good retention (e.g., the programmed state is retained for at least 10 years if the device operates within the appropriate temperature range);

[0018] Phase-change memories with low resistance drift (due to their epitaxial structure—which maintains a low or no change in resistance level during the time required to retain stored data when the device is in a given resistive state—are particularly useful when using devices with intermediate states to store more than one bit or for simulating artificial intelligence (AI) computations) and

[0019] The use of epitaxial materials reduces device variability compared to polycrystalline materials.

[0020] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments of the invention, which is read in conjunction with the accompanying drawings. Attached Figure Description

[0021] The following figures are presented by way of example only and not as a limitation, wherein similar reference numerals (where used) indicate corresponding elements throughout multiple views, and wherein:

[0022] Figure 1 An embodiment of a phase-change memory cell according to one aspect of the present invention is shown;

[0023] Figure 2 An illustration of a PCM switching region according to one aspect of the invention is shown. Figure 1 Examples;

[0024] Figure 3 An embodiment of a phase-change memory cell according to one aspect of the present invention is shown;

[0025] Figure 4 An embodiment of a phase-change memory cell according to one aspect of the present invention is shown;

[0026] Figure 5 An embodiment of a phase-change memory cell according to one aspect of the present invention is shown;

[0027] Figure 6 An embodiment of a phase-change memory cell according to one aspect of the present invention is shown;

[0028] Figure 7 An embodiment of a phase-change memory cell according to one aspect of the present invention is shown;

[0029] Figure 8 An embodiment of a phase-change memory cell according to one aspect of the present invention is shown;

[0030] Figure 9 An embodiment of a phase-change memory cell according to one aspect of the present invention is shown;

[0031] Figure 10A-10D An embodiment of the invention is shown, comprising manufacturing according to... Figure 3 A series of exemplary steps of a phase-change memory cell in an embodiment;

[0032] Figure 11 The epitaxial growth of PCM on a seed layer including van der Waals gaps is shown according to various aspects of the present invention.

[0033] Figure 12A and Figure 12B Alternative seed layer positions according to various aspects of the invention are shown;

[0034] Figure 13 A cross switch array of a PCM unit according to one aspect of the present invention is shown;

[0035] Figure 14 A computing environment (e.g., for implementing, according to embodiments of the present invention) is described. Figure 15 The design process); and

[0036] Figure 15 It is a flowchart of the design process used in semiconductor design, manufacturing and / or testing.

[0037] It should be understood that the elements in the accompanying drawings are shown for simplicity and clarity. Common but well-known elements that may be useful or necessary in commercially feasible embodiments may not be shown in order to facilitate a more unobstructed observation of the illustrated embodiments. Detailed Implementation

[0038] The inventive principles described herein will be understood in the context of the illustrative embodiments. Furthermore, it will be apparent to those skilled in the art, based on the teachings given herein, that many modifications can be made to the illustrated embodiments, all of which are within the scope of the claims. That is, no limitation is intended or should be inferred with respect to the embodiments shown and described herein.

[0039] One or more embodiments advantageously provide a PCM cell having a homogeneous single-crystal phase change material layer, the crystal plane of which is aligned with the crystal plane of a seed layer. A single-crystal PCM is considered to be templated by a seed layer such that the PCM layer mimics at least one aspect of the sequence provided by the seed layer. Exemplary phase change memories include, for example, a homogeneous phase change material layer having an out-of-plane crystal axis aligned with the out-of-plane crystal axis of the crystallized seed layer. The seed layer may include, for example, Ti. x Te y or Sb x Te yThe seed layer can be first, last, or intermediate. One or more embodiments provide a single-crystal homogeneous phase change material layer on a non-planar electrode substrate having an out-of-plane crystal axis perpendicular to the substrate. Exemplary methods of forming a phase change memory (PCM) include preparing a surface (e.g., charging the substrate with Ar sputtering or an electron beam), then crystallizing and depositing a seed layer at a first optimized temperature, followed by crystallizing and depositing a phase change material layer (wherein the crystal structure is aligned with the seed layer) at a second optimized temperature. For example, a TiTe2 seed layer can be deposited at a substrate temperature of 150°C to 250°C, and a GST225 PCM layer can be deposited at a temperature of 150°C to 250°C. In yet another example, both the TiTe2 layer and the GST225 layer are deposited at the same temperature (e.g., 200°C). For example, forming a lower electrode embedded in an insulating material, depositing a thin (0.25-5 nm) crystalline seed layer having a crystallization z-axis orientation perpendicular to the substrate, depositing a crystalline phase change material layer having an orientation z-axis aligned with the seed layer z-axis, and depositing a top electrode material. In another example, a first amorphous PCM layer is deposited; a seed layer, which is a highly oriented crystalline layer, is deposited at a temperature below the crystallization temperature of the first amorphous PCM layer; and annealing is performed at a temperature above the crystallization temperature of the first PCM layer, thereby inducing top-down solid-state crystallization of the first PCM layer using the seed layer as a template. Regarding the "highly oriented" crystalline layer, in practice, the seed layer (or subsequent PCM layer) is not a perfect single crystal, but a polycrystalline layer, where almost all the polycrystals are oriented in the same direction. Furthermore, the polycrystals are typically very large. "Large" means that the size of the polycrystal is many times the size of the device. Therefore, in one or more embodiments, the highly oriented seed layer is not a single crystal; instead, it has microcrystals, but they are all mostly oriented in the same way, at least in one dimension / axis. In two adjacent microcrystals, the atomic layers will be parallel to the substrate, but the two microcrystals can be rotated relative to each other, so that the atomic layers do not necessarily need to be aligned relative to other axes. In one or more embodiments, alignment along at least one direction is sufficient. Note that the use of a template according to one or more embodiments may be particularly advantageous for back-end processing when access to a crystalline Si(111) substrate, required by some prior art, is unavailable. In other words, a “highly oriented” crystalline film is a layer composed of polycrystalline domains, all of which are closely aligned with each other (in one or more directions). Experimentally, this can be observed using X-ray diffraction. When the film is polycrystalline with all domains (or crystallites) randomly oriented, almost none of the crystallites will match the diffraction conditions, and no diffraction peaks will be observed. However, in a highly oriented crystalline film, most of the crystallites will match the diffraction conditions (on a specific beam orientation), and clear diffraction peaks will be observed. Under the constraint of perfect alignment of all crystallites, the material will approach that of a single-crystal film.Note that there can be an arrangement of microcrystals in which all microcrystals have atomic planes parallel to the substrate surface, but each microcrystal is rotated to a certain degree of randomness within the plane. In this case, diffraction from atomic planes parallel to the surface will show good crystallinity (strong diffraction peaks), but diffraction from asymmetric planes (e.g., atomic planes at an angle to the surface) will resemble random polycrystalline materials (no diffraction peaks).

[0040] Note that the epitaxial process of growing homogeneous single crystal layers can be called "homogeneous epitaxy," while the growth of superlattices can be called "heterogeneous epitaxy."

[0041] Some prior art devices require a Si(111) substrate as a seed template for a homogeneous single-crystal phase transition layer; conversely, one or more embodiments are independent of substrate orientation and at least to some extent independent of the substrate material (because the charge deposited on the substrate surface (e.g., by Ar sputtering) contributes to the orientation of the seed layer, so it is unclear how much the epitaxy would change if the top surface of the substrate were highly conductive and could not retain the charge). This is not a problem for PCM devices because the bottom electrode is embedded in silicon nitride or silicon oxide, which acts as an insulator and retains the charge well. Some prior art devices utilize superlattice structures, while one or more embodiments employ bulk homogeneous polycrystalline PCM materials; such as GST225 or other stoichiometry or Sb2Te3 or other stoichiometry, with optional doping (e.g., dopants: SiC, Si, SiO2, SiN). In one or more embodiments, the seed layer can be as thick as 5 nm and as thin as a single monolayer to minimize the impact on electrical properties.

[0042] By way of example only and not limitation, an exemplary configuration of a seed layer + homogeneous phase change material for an exemplary PCM cell includes:

[0043] Seed layer 0.25-5nm TiTe2 / PCM layer 1-100nm Sb2Te3

[0044] Seed layer 0.25-5nm TiTe2 / PCM layer 1-100nm Ge2Sb2Te5

[0045] Seed layer 0.25-5nm Sb2Te3 / PCM layer 1-100nm Ge2Sb2Te5

[0046] First seed layer: 0.25-5nm TiTe2 / Second seed layer: 1-5nm Sb2Te3 / PCM layer: 1-100nm Ge2Sb2Te5

[0047] PCM layer 1-100nm Ge2Sb2Te5 / seed layer 0.25-5nm TiTe2 (top-down crystallization, with a seed layer on top of the PCM).

[0048] Suitablely, any of the above embodiments may optionally include a dopant (e.g., C, SiC, Si, SiN, Ta) contained in the seed layer, PCM layer, or both. x O y (N, O). Suitablely, any of the above embodiments may optionally have a modified stoichiometry in the seed layer, PCM layer, or both. The effect of doping on epitaxy generally depends on the dopant used. For example, carbon is known to slow the crystallization of amorphous GST, but may be incorporated during epitaxial growth. Oxygen can inhibit epitaxy because it can lead to the formation of an oxide layer of amorphous GST (thus essentially negating the template effect). The use of carbon and / or silicon doping is currently considered potentially useful because they only replace Ge.

[0049] Now for reference Figure 1 The embodiment includes an inner insulating layer 301A, a bottom electrode 303, a seed layer 305 (in this case, not a PCM), a homogeneous crystalline PCM layer 307, a top electrode 309, and an outer insulating layer 301B. Below the inner insulating layer 301A may be, for example, an interconnect layer 397 and a silicon substrate 399 having circuitry composed of transistors (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs), as will be apparent to those skilled in the art given the teachings herein). In the depicted exemplary embodiment, the crystalline PCM layer 307 and the seed layer 305 are z-axis aligned. In this respect, for example, a crystalline material 307 is grown on the seed layer 305 at a high temperature (e.g., 180°C to 200°C). The PCM is epitaxially grown on the highly oriented seed layer 305. In some cases, the high temperature may be higher than the crystallization temperature of the PCM layer 307; however, this is not a necessary condition. In practice, typically, the growth temperature may be lower than the crystallization temperature of the PCM. Since the crystallization temperature of PCM is defined for the spontaneous crystallization of amorphous PCM, and in this case, PCM is grown using template epitaxy, it is acceptable, but not necessary, to use a growth temperature higher than the above-mentioned temperature.

[0050] Note that all illustrated embodiments, including Figure 6 and 7 In some embodiments, layers 397 and 399 may be included, but for ease of explanation, these are only used in specific embodiments. Figure 1As shown in the diagram. In one or more embodiments, the process begins with layers 399, 397, 301A and a lower electrode 303 flush with the top layer of 301A. Then, layers 305, 307, and 309 are deposited as capping layers, and a device stack is fabricated from layers 305, 307, and 309 using patterning / photolithography. Insulating layers 301B are deposited on the sides, which can typically be the same or different material from 301A (regions 301A and 301B are separated by dashed lines accordingly).

[0051] In one or more embodiments, a homogeneous crystalline material with van der Waals gaps is epitaxially grown on a seed layer without using / forming a multilayer or superlattice.

[0052] Seed layer 305 can be deposited at a sufficiently high temperature to allow it to crystallize. The wafer is then allowed to cool, and PCM layer 307 is deposited at a sufficiently low temperature (e.g., room temperature) such that PCM layer 307 is amorphous. The wafer is then annealed at a sufficiently high temperature (e.g., 200°C for GST 225), thereby allowing the PCM layer 307 to be solid-state grown into an ordered crystal by using seed layer 305 as a template. The remaining fabrication steps remain the same.

[0053] Figure 2 It shows Figure 1 In one embodiment, a dome of amorphous PCM material 311 has been formed. Note that the seed layer disappears below region 311, while the seed / template layer 305 remains below the crystalline homogeneous PCM layer 307. The dome and the bottom electrode together form a "mushroom shape," comprising the bottom electrode as the "stem" of the mushroom and region 311 as the "dome." Note that using the surrounding crystalline PCM material as a template, the dome of the amorphous PCM can recrystallize during a SET pulse. In one or more embodiments, because material 307 is homogeneous, the same composition is maintained regardless of how much material is melted during melting and recrystallization. In contrast, in the prior art using multilayer / superlattices, if the first two layers are melted during a RESET, the mixed material will have a mixture of these two layers. Assuming another RESET melt produces a larger dome, melting the first three layers together—this would result in a different composition. Advantageously, in one or more embodiments of the invention, the PCM material is homogeneous, and the RESET will not change the composition of the PCM.

[0054] Regarding RESET, this operation typically involves applying a high current pulse to the device (“high” means providing sufficient energy to melt the PCM adjacent to the bottom electrode). The RESET pulse is rapidly quenched / turned off to force the melt to cool rapidly and then solidify in an amorphous phase. If the current pulse gradually tapers (by having a long trailing edge), the melt will solidify in a crystalline phase because it will have enough time to crystallize. Note that, given the teachings of this article, a person skilled in the art can use known techniques such as coupled thermoelectric finite element analysis to determine the current and waveform required for a particular geometry. The maximum current density is where the bottom electrode 303 meets the material 307. The material melts, forming a dome 311. Line 312 represents the current density. If the pulse is plotted as a function of time, quenching means a sudden drop in the trailing edge of the pulse. This sudden drop causes the molten material to cool rapidly without crystallizing. The effect is that the bottom electrode (which is one of the contacts) is covered by a dome 311 of (high-resistance) amorphous material, which blocks the current. A FOM (Factor of Quality) for a PCM device is the lowest possible RESET current. One technique is to make the bottom electrode 303 as small as possible, as discussed elsewhere in this document. Another approach is to use a doped PCM, in which additives such as oxygen and / or nitrogen are incorporated. These additives typically "modify" the grain boundaries between grains in a polycrystalline material. This has the effect of making the material more resistive and reducing the reset current.

[0055] In one or more embodiments, when using rapid quenching for melting and recrystallization, a second, weaker pulse can be applied, annealing the material above the crystallization temperature but without melting it. In another approach, a RESET pulse is used, but without an abrupt trailing edge; instead, slow cooling is employed to recrystallize the PCM. Figure 2 Even when the material melts near the bottom electrode 303, the molten material will be seen on top of 307, which remains crystalline, acting as a template and following that template during recrystallization. Furthermore, regarding "rapid" quenching, it must be fast enough for the melt to solidify in an amorphous phase. This varies depending on the PCM material used. For example, for GST 225, the trailing edge of the RESET pulse is on the order of several nanoseconds. Additionally, regarding "weaker" pulses, they are defined as pulses that will cause the PCM material to crystallize. For example, for GST225, this is typically a pulse with a long trailing edge of tens of nanoseconds or longer. Again, given the teachings of this paper, those skilled in the art can use known techniques such as coupled thermoelectric finite element analysis to determine the required current and waveform for a particular geometry.

[0056] exist Figure 3In this embodiment, one embodiment includes an inner insulating layer 301A and an outer insulating layer 301B, a bottom electrode 303, a seed layer 305 (in this case, not a PCM), a homogeneous crystalline PCM layer 307, and a top electrode 309. In the depicted exemplary embodiment, the crystalline PCM layer 307 and the seed layer 305 are aligned along their z-axis. In this embodiment, the seed layer 305 is located outside the PCM layer 307. Having a seed layer 305 on top of layer 307 has certain advantages. Having a seed layer on the bottom between the bottom electrode 303 and layer 307 can affect the contact between the bottom electrode and the PCM layer. In many cases, the seed layer itself is not a PCM. Figure 3 In this process, direct contact between the bottom electrode and the epitaxial PCM layer is desirable.

[0057] Now for reference Figure 10A-10D .exist Figure 10A In this process, amorphous PCM 307A is deposited on the inner insulating layer 301A. The deposition of PCM at, for example, room temperature produces amorphous PCM. Typically, to obtain amorphous PCM, the substrate temperature should be maintained below the crystallization temperature of the PCM material. For example, for GST 225, the crystallization temperature is approximately 165°C. Figure 10B In this process, a highly oriented seed layer 305 is deposited on top of the amorphous PCM 307A. Figure 10C During the annealing step, solid-state epitaxy is performed, meaning that PCM 307A crystallizes from the top down—note the crystalline PCM 307C and the remaining amorphous portion of 307A. The completion of this process produces… Figure 10D The fully crystalline PCM 307C is used, with the upper electrode 309 on top. Note that after the amorphous PCM deposition, a sputtering cleaning step can optionally be used to remove oxides that may form during the temperature rise to the seed layer deposition temperature. Furthermore, this sputtering cleaning can deposit charge into the PCM layer surface, which can help orient the seed layer. Advantageously, the bottom electrode 303 is in direct contact with the PCM 307C, and no interface exists. Figure 1 Compared to the embodiment with a seed layer 305 at the bottom of the PCM 307 (which requires cycling before use), Figure 10D The structure in the document is ready for use.

[0058] In one or more embodiments, the bottom electrode 303 is significantly smaller than the top electrode 309, and the top electrode 309 extends over the entire cell. Figure 2In this design, the dome 311 is formed at the bottom because the current density is highest there. The highest current density is located directly above the bottom electrode 303. Generally, a smaller diameter for the bottom electrode 303 is preferable (higher current density means lower reset current). The diameter of the bottom electrode 303 should generally be the minimum achievable with a given technology (in the current technology, the diameter of the bottom electrode is approximately 30 nm; it will change (decrease) as manufacturing technology advances). Typically, in one or more embodiments, the bottom electrode 303 has a diameter of 30-40 nm (20 nm is considered better if available under specific technology nodes and process conditions), and the top electrode 309 has a diameter of several hundred nm.

[0059] Figure 4 It is usually similar to Figure 1 In this embodiment, in addition to using a double seed layer, it includes a crystalline (non-PCM) seed layer 305 outside the inner insulating layer 301A and a crystalline (PCM) seed layer 313 outside the crystalline (non-PCM) seed layer 305 and inside the PCM 307. Therefore, Figure 4 An embodiment with a crystalline non-PCM seed layer and a subsequent crystalline PCM seed layer is shown.

[0060] Note that the seed material can typically be PCM, but is not necessarily limited to PCM. In one or more non-limiting exemplary embodiments, Sb2Te3, which is PCM, is used as the seed layer.

[0061] Figure 5 One embodiment is shown in which a separate seed layer is not used. Instead, the entire crystalline homogeneous PCM layer 307 is grown as, for example, Sb₂Te₃. In this respect, the seed layer is PCM. Figure 5 In an exemplary embodiment, the surface of the deposited layer 307 is amorphous (e.g., Si3N4 or SiO2) and therefore cannot serve as a template. It is worth noting that some prior art devices use the surface of a (crystalline) Si(111) substrate as a template for PCM layer growth. It should also be noted that Sb2Te3 is not necessarily the optimal PCM for all applications; in our experiments with other configurations, we used TiTe2 as a seed layer (which is not a PCM and therefore cannot be used as a template). Figure 5 Layer 307 in the embodiment). Figure 5 In the example, layer 307 is a PCM that has the property of acting as a seed layer, meaning it grows as a highly oriented layer. Typically, for applications using a single seed layer (i.e., different from...) Figure 5 and Figure 7 In an embodiment of the above, the seed layer may be PCM or non-PCM.

[0062] Figure 6One embodiment is shown, in which the bottom electrode is part of a stack of layers, and the device is constructed on the side. Note the inner insulating layer 601A and the outer insulating layer 601B (the inner and outer layers may be the same or different materials); the bottom electrode 603 having a laterally right-extending portion 603L; a seed layer 613 (the seed layer 613 may be PCM or non-PCM); a crystalline homogeneous PCM layer 607; and a top electrode 609. In the exemplary embodiment depicted, the z-axis of the crystalline PCM layer 607 and the seed layer 605 are aligned. Figure 6 The embodiments are advantageous, for example, in providing a very narrow bottom electrode in at least one dimension (controlled by deposition rather than photolithography). For fabrication Figure 6 In some embodiments, for example, the process begins with the lower electrode 603 and the inner insulator 601A, extending to the dashed line 604 (and layers 397, 399). At this point, the surface represented by the dashed line 604 will extend across the entire width. A thin (e.g., 5 nm) capping layer of conductor 603L is then deposited on top of 601A, and additional insulator 601A is added until… Figure 6 The upper surface depicted (at this point, the outermost surface between 601A and 601B will extend across the entire width). At this stage, there is a stack with 601A, having a vertical contact 603 and an embedded thin contact layer 603L overlapping the top of this contact and extending across the entire width. This stack is patterned as ridges, like continuous fins from left to right, and the fins are "cut" to form a face 606 on which layers 613, 607, and 609 will be deposited. This structure is very narrow in the direction perpendicular to the page. The lateral protrusion 603L starting from electrode 603 will have an area equal to the layer thickness (controlled by deposition) multiplied by the width of the ridge entering the page (controlled by photolithography). This allows control of one dimension of the electrode by deposition rather than photolithography. Part 603 can be... Figure 1 It is made in the same manner, but can be larger, because the dimension of the protrusion 603L is controlled in this embodiment. The protrusion 603L can also extend to the left side. The upper surface of 601A can be aligned with or recessed below the bottom of layer 613.

[0063] Figure 7 It shows something similar to Figure 6 In addition to the embodiments, as shown in the example Figure 5 Unlike other methods, which use a separate seed layer, this method grows an entire homogeneous crystalline PCM layer 607, for example, Sb₂Te₃. In this respect, the seed layer is PCM. Figure 7 In an exemplary embodiment, the surface of the deposited layer 607 is amorphous (e.g., Si3N4 or SiO2), and therefore cannot act as a template. Figure 7 In the example, layer 607 is a PCM that has the property of acting as a seed layer, which means that it grows as a highly oriented layer. Figure 7 The remainder of the manufacturing of the embodiments can be similar to Figure 6 The manufacture of.

[0064] Figure 8 An embodiment with a lateral electrode 309L is shown. Note the inner insulating layer 301A and outer insulating layer 301B, bottom electrode 303, seed layer 305, homogeneous crystalline PCM layer 307, and lateral electrode 309L. In the depicted exemplary embodiment, the z-axis of the crystalline PCM layer 307 and the seed layer 305 are aligned. Note that for illustrative convenience and generality, only a single lateral electrode 309L is depicted on the left side. However, a lateral electrode may also be provided on the right side of the PCM layer 307. In practice, the PCM layer 307 can be patterned as a mesa structure, and contacts can be formed to the sidewalls of the mesa. In a non-limiting example, if the PCM layer 307 is patterned as a disk (when viewed from above), then the contacts would be a ring around the PCM mesa.

[0065] Figure 9 An embodiment with a lateral crystallization seed layer 305L is shown. Note the inner insulating layer 301A and outer insulating layer 301B, bottom electrode 303, lateral crystallization seed layer 305L, crystalline homogeneous PCM layer 307L, and top electrode 309. In the depicted exemplary embodiment, the z-axis of the crystalline PCM layer 307L and the lateral crystallization seed layer 305L are aligned. To fabricate this structure, the PCM layer 307L is first deposited as an amorphous film (e.g., by deposition at room temperature) (e.g., electrode material 309 may also be deposited at this time). The PCM layer and electrode material are patterned (e.g., square or rectangular when viewed from above) to obtain mesa, for example, by reactive ion etching. Each mesa sidewall is cleaned (e.g., by Ar sputtering) and the seed layer 305L is deposited. For example, the seed layer can be deposited from the left at an angle of, for example, 45 degrees, so that it only coats the left sidewall (or the right sidewall if angled to the right) (the mesa prevents material deposition on the opposite sidewall). The wafer is then annealed, allowing solid-state epitaxy of the PCM layer 307, which is templated by the seed layer 305. If the seed layer is present on both sides, the amorphous material will grow and crystallize from each side and meet at undesirable seams or boundaries. If growth from both sides is desired, the bottom electrode can be shifted from the center of the cell by a certain amount so that it is not close to the seam or boundary.

[0066] Figure 11 This describes certain novel aspects of one or more embodiments. One or more embodiments use known phase change materials, but are epitaxially grown on a seed layer. In one or more embodiments, PCM 307, 307L, 607 are ordered crystalline materials, rather than PCM microcrystals with many random orientations. Prior art “crystalline” phase change materials are actually polycrystalline. Figure 11 Sb₂Te₃ epitaxially grown on a substrate (not shown) having a seed layer (not shown), comprising atomic layers separated by van der Waals gaps 1101, is illustrated. An epitaxially grown PCM with van der Waals gaps 1101 is obtained by using a nucleation / seed layer (nucleation layer and seed layer are synonyms herein). Therefore, while some prior art requires the substrate to be a template, one or more embodiments do not require the substrate itself to be a template, but rather use a seed layer on the substrate. Figure 11 In the example, the material is epitaxially grown by covalent bonds, and after a certain number of atomic layers, it alternatively forms a “satisfactory layer” which is attached to the next layer not by covalent bonds but by van der Waals forces, thus creating a distinct gap. We have found instances where the formation of van der Waals interfaces / gap increases thermal resistance and electrical resistance. The location of the van der Waals gaps can depend on the material composition. For example, for Sb2Te3, this would occur every five (5) atomic planes between the two Te planes. For GST225, this occurs at nine atomic planes, also between the Te planes. Thus, typically, in one or more embodiments, van der Waals gaps appear between the Te planes, and depending on the PCM composition, they can be between about five and about nine atomic planes.

[0067] When it is desirable to avoid the formation of epitaxial (crystalline) GST, deposition can be performed at room temperature. For example, 100 nm of GST225 can be deposited on 2.6 nm of TiTe2 at 25 °C, and the GST will be in an amorphous form. On the other hand, to form epitaxial (crystalline) GST, deposition can be performed at an optimized temperature. For example, 100 nm of GST225 can be deposited on 2.6 nm of TiTe2 at 200 °C, and the GST will be in an epitaxial (crystalline) form, thereby advantageously reducing the RESET current. If desired, for example at Figure 4 In this process, a second seed layer is utilized and deposited at an optimized temperature. For example, 100 nm of GST225 can be deposited on 2.6 nm TiTe2 at 180 °C, while 5 nm of Sb3Te2 is deposited on top of the TiTe2, and the GST will be in epitaxial (crystalline) form. Therefore, one or more embodiments provide a reduction in RESET current without requiring alternating layers / superlattices. It is noteworthy that in one or more embodiments, the SET resistance is not reduced, but rather has a higher resistance due to the van der Waals gap. Furthermore, PCM devices with low SET resistance are undesirable because they require a higher current to reset.

[0068] Now for reference Figure 12A and 12B In one or more embodiments, the seed layer can be placed anywhere, as long as it is in contact with the amorphous PCM. For example, it can be placed inside the PCM layer. Figure 12A ) or its sidewalls ( Figure 12B ).exist Figure 12A In the diagram, note the inner insulating layer 301A, the bottom electrode 303, the intermediate seed layer 305M, and the lower amorphous PCM layer 307A-1 and upper amorphous PCM layer 307A-2, which will grow into a crystalline form, with the template formed on the seed layer 305M. (Compare) Figures 12B to 9 .exist Figure 12B Note the inner insulating layer 301A, bottom electrode 303, lateral (on the sidewall) crystallization seed layer 305L and amorphous PCM layer 307A, which will grow into a crystalline form, with the template formed on the seed layer 305L.

[0069] It is worth noting that one or more embodiments use a highly oriented crystalline layer and a PCM template on that layer. Alternatively, one or more embodiments use (111) oriented crystals.

[0070] Therefore, it can be understood that, in one aspect, a phase change memory includes a homogeneous phase change material layer having an out-of-plane crystal axis aligned with the out-of-plane crystal axis of a seed layer. The seed layer can be, for example, Ti. x Te y Sb x Te y In one or more embodiments, a single-crystal homogeneous phase change material layer is provided on a non-planar electrode substrate, wherein the out-of-plane crystal axis is perpendicular to the substrate. In another aspect, a method of forming a phase change memory (PCM) includes: charging a substrate with Ar sputtering, followed by crystallization deposition of a seed layer at an optimized temperature, and subsequently crystallization deposition of a phase change material layer at an optimized temperature. Based on the teachings herein, those skilled in the art can select an appropriate temperature depending on the material and whether an amorphous or crystalline form is desired.

[0071] Now for reference Figure 13 View 1299 illustrates a phase-change memory array; only a 2×2 array is shown, but any suitable number of cells can be used. A suitable word line 1279 selects which bit to read or write. The word line is connected to the gate of transistor 1277. The gate of the transistor provides an electrical switching function. The drain of the transistor is connected to one terminal of memory element 1275 (e.g., a PCM according to any of the disclosed embodiments), while the other terminal of the memory element is connected to the corresponding bit line 1273. The source of the switch (transistor) is grounded.

[0072] There are many methods to read bits. For example, the bit line is charged to a certain voltage and then kept floating, while the word line is set high. This turns on a switch, allowing current to flow from the bit line through the memory element to ground. If the memory element is in the RESET phase, the bit line will remain charged because a small current will flow due to the high resistance of the PCM. However, if the PCM is in the SET phase, the bit line will discharge because the PCM is at a low resistance, and the voltage on the bit line will be close to zero. A sense amplifier can be used to detect the voltage on the bit line to determine whether the bit being read is "0" or "1".

[0073] To write to this bit, you select it by applying a voltage to the word line and then pulse the bit line with a SET or RESET pulse.

[0074] Note that read operations are typically performed at low voltages to avoid accidental bit writes; given the teachings herein, those skilled in the art can heuristically select an appropriate voltage.

[0075] View 1297 shows a cross-switch array for AI computing; the general structure of such an array using memory cells of the prior art is known from the following IBM research paper: Abu Sebastian, Manuel Le Gallo, Geoffrey W. Burr, Sangbum Kim, Matthew Brightssky, and Evangelos Eleftheriou, “Tutorial: Brain-inspired computing using phase-change memory devices,” Journal of Applied Physics 124, no. 11 (September 21, 2018), pages 111101-1 to 111101-1. A voltage is applied to input line 1206, and the current from each PCM element 1202 (e.g., the PCM according to any of the disclosed embodiments) is summed in output line 1210. The current in each element is V(j) × G(k,j), where G is the conductance of element (k,j). The conductance is 1 / R, or 1 divided by the resistance of the PCM element.

[0076] Therefore, as a result, output line 1210 is the sum of the products of the input voltage and the conductance of the array elements. This multiplicative accumulation (MAC) is a very common operation in artificial neural network computations, so cross-switch arrays can be used to accelerate AI computations. Note that transistor 1203 is used to prevent read current from flowing through another bit in the SET phase to another output line. Suppressing unwanted current flow in unselected cells is called "latent path" current.

[0077] Matrices and vectors are often implied to weighting, peripheral circuits, etc., as are familiar to those skilled in the art.

[0078] Memory devices with large arrays can be implemented on a single chip. Within the constraints of manufacturing processes and design specifications, any number of cells 1202 or 1275 can be employed. View 1297 is an example simulating an AI application (multiplying matrix 1295 by x vector 1293 to obtain output vector b 1291). Matrix and vector typically indicate weighting, peripheral circuitry, etc., familiar to those skilled in the art. Controller (e.g., known digital circuitry) and power supply 1289 are coupled to the array and peripheral circuitry in a known manner—cross-switch arrays are themselves well-known; given the teachings given herein, those skilled in the art can implement this array with appropriate peripheral circuitry, controller, and power supply, incorporating the PCM cells of the present invention as disclosed herein.

[0079] Semiconductor device fabrication involves various steps in the device patterning process. For example, the fabrication of a semiconductor chip can begin with, for instance, multiple device patterns generated by CAD (Computer-Aided Design), followed by an effort to replicate these patterns onto a substrate. The replication process can include the use of various exposure techniques and various subtractive (etching) and / or additive (deposition) material processing steps. For example, in a photolithography process, a layer of photoresist material can first be applied on top of a substrate and then selectively exposed according to one or more predetermined device patterns. Portions of the photoresist exposed to light or other ionizing radiation (e.g., ultraviolet light, electron beams, X-rays, etc.) may undergo some changes in their solubility in certain solutions. The photoresist can then be developed in a developer solution, thereby removing unirradiated (in negative resists) or irradiated (in positive resists) portions of the resist layer to produce a photoresist pattern or photomask. Subsequently, the photoresist pattern or photomask can be replicated or transferred onto the substrate beneath the photoresist pattern.

[0080] Many techniques exist that are used by those skilled in the art to remove material at various stages of semiconductor structure formation. These processes are generally referred to as “etching” as used herein. Etching includes, for example, wet etching, dry etching, chemical oxide removal (COR) etching, ion polishing, and reactive ion etching (RIE) techniques, all of which are known techniques for removing selected material during semiconductor structure formation. Standard Clean 1 (SC1) contains a strong base, typically ammonium hydroxide, and hydrogen peroxide. SC2 contains a strong acid, such as hydrochloric acid, and hydrogen peroxide. The techniques and applications of etching are well understood by those skilled in the art; therefore, a more detailed description of these processes is not provided herein.

[0081] Although the overall manufacturing method and the resulting structure are novel, certain individual processing steps required to implement this method can utilize conventional semiconductor manufacturing techniques and tools. These techniques and tools are already familiar to those skilled in the art in the context of the teachings presented herein. Furthermore, one or more processing steps and tools for manufacturing semiconductor devices are described in numerous readily available publications, including, for example: James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition, Prentice Hall, 2001. st The following two documents are incorporated herein by reference: (Prentice Hall, 2001) and (PH Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008). It should be emphasized that while some individual processing steps are described herein, these steps are merely illustrative, and those skilled in the art will be familiar with several equally suitable alternatives that will be applicable.

[0082] It should be understood that the various layers and / or regions shown in the accompanying drawings may not be drawn to scale. Furthermore, for ease of interpretation, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure. This does not imply that un-explicitly shown semiconductor layers are omitted in actual integrated circuit devices.

[0083] Based on the discussion so far, it will be understood that, generally speaking, an exemplary phase-change memory cell includes (inner) insulating layers 301A, 601A; and first electrodes 303, 603 / 603L embedded in the (inner) insulating layers. The outer ends of the first electrodes are connected to the outer surface of the (inner) insulating layer (e.g., Figure 1 The upper surface of the middle Figure 6 The surface of the facets is partially flush with the first electrode. It also includes second electrodes 309 and 609, which are larger than the first electrode and spaced apart from it. It further includes homogeneous crystalline phase change material layers 307, 307L, and 607; and highly oriented seed layers 305, 305 / 313, and 613. The crystal structure of the homogeneous phase change material layers is related to the crystal structure of the highly oriented seed layers. The homogeneous phase change material layers and the highly oriented seed layers are at least partially located between the first and second electrodes.

[0084] The crystal structure of a PCM is related to the seed layer in that if the seed layer is known, then the PCM layer will be known. The PCM layer uses the seed layer as a template. In one or more embodiments, there is alignment along at least one direction.

[0085] As used herein, in a homogeneous layer, the atomic concentrations of the different elements constituting the film are uniform throughout the film. Experimentally, this can be verified using SIMS (Secondary Ion Mass Spectrometry). In this method, an ion beam is used to sputter the film, and the mass of the sputtered elements is measured. This allows for obtaining a depth map of the elemental concentrations within the film. If the film consists of multiple layers with different compositions, such as prior art superlattice structures, SIMS will show variations in composition during film sputtering. On the other hand, a homogeneous film will show a constant elemental composition in the depth map.

[0086] In one or more embodiments, for example, besides Figure 5 and Figure 7 In all exemplary embodiments other than those described above, the homogeneous phase change material layer and the highly oriented seed layer have different materials.

[0087] Optionally, in any or all of the disclosed embodiments, the seed layer has an out-of-plane crystal axis, and the homogeneous phase change material layer has an out-of-plane crystal axis aligned with the out-of-plane crystal axis of the seed layer. Refer to the description of the Z-axis.

[0088] In one or more embodiments, for example, except Figure 5 and Figure 7 In all exemplary embodiments other than Ti, the seed layer may optionally be selected from Ti. x Te y and Sb x Te y A group that is formed.

[0089] Optionally, in any or all of the disclosed embodiments, the homogeneous phase change material layer includes van der Waals gaps.

[0090] In one or more embodiments, for example, except Figure 5 and Figure 7 In all other exemplary embodiments, the homogeneous phase change material layer and the seed layer each have a (111) crystal orientation.

[0091] Optionally, in any or all of the disclosed embodiments, the homogeneous phase change material is selected from GST and Sb. x Te y The group consisting of. Optionally, in such an embodiment, the seed layer and the homogeneous phase change material are selected from the group consisting of:

[0092] A 0.25-5nm TiTe2 seed layer and a 1-100nm Sb2Te3 homogeneous crystalline phase change material layer;

[0093] A 0.25-5nm TiTe2 seed layer and a 1-100nm Ge2Sb2Te5 homogeneous crystalline phase change material layer; and

[0094] A seed layer of 0.25-5nm Sb2Te3 and a homogeneous crystalline phase change material layer of 1-100nm Ge2Sb2Te5.

[0095] For example, refer to Figure 1 In some embodiments, the seed layer 305 is typically planar and outside the (inner) insulating layer 301A; the homogeneous phase change material layer 307 is typically planar and outside the seed layer; and the second electrode 309 is typically planar and outside the homogeneous phase change material layer.

[0096] For example, refer to Figure 3 In some embodiments, the homogeneous phase change material layer 307 is typically planar and located outside the (inner) insulating layer 301A; the seed layer 305 is typically planar and located outside the homogeneous phase change material layer; and the second electrode 309 is typically planar and located outside the seed layer.

[0097] For example, refer to Figure 4In some embodiments, seed layer 305 comprises a first seed layer of non-phase change material and a second seed layer 313 of phase change material. The first seed layer 305 is generally planar and located outside the (inner) insulating layer 301A; the second seed layer 313 is generally planar and located outside the first seed layer; the homogeneous phase change material layer 307 is generally planar and located outside the second seed layer; and the second electrode 309 is generally planar and located outside the homogeneous phase change material layer. Optionally, in such embodiments, the first seed layer comprises 0.25-5 nm TiTe2, the second seed layer comprises 1-5 nm Sb2Te3, and the homogeneous phase change material layer comprises 1-100 nm Ge2Sb2Te5.

[0098] For example, refer to Figure 6 In some embodiments, the first electrode has a generally vertical portion 603 and a horizontal (lateral) protrusion 603L; the (inner) insulating layer 601A has a stepped region (facet 606), and the horizontal protrusion of the first electrode extends to the surface of the stepped region. Furthermore, a seed layer 613 is located outside the (inner) insulating layer, contacting the horizontal protrusion 603L and the stepped region of the first electrode. A homogeneous phase change material layer 607 is located outside the seed layer; and the second electrode 609 is located outside the homogeneous phase change material layer.

[0099] For example, refer to Figure 6 In some embodiments, the seed layer 305 is outside the (inner) insulating layer 301A; the homogeneous phase change material layer 307 is outside the seed layer 305; and the second electrode 309L is located on at least one side of the homogeneous phase change material layer and the seed layer.

[0100] For example, refer to Figure 6 In some embodiments, the homogeneous phase change material layer 307L is outside the (inner) insulating layer 301A; the second electrode 309 is located outside the homogeneous phase change material layer; and the seed layer 305L is located on the side of the homogeneous phase change material layer (and preferably only on one side).

[0101] For example, refer to Figure 12A In some embodiments, the homogeneous phase change material layer is outside the (inner) insulating layer 301A; the second electrode 309 ( Figure 12A Not illustrated in the image; see example. Figure 1 and Figure 3 (Any of the other embodiments) is outside the homogeneous phase change material layer; and the seed layer 305M is inside the homogeneous phase change material layer. Note that Figure 12A The results show that before crystallization, the homogeneous phase change material layers in amorphous form were present at 307A-1 and 307A-2.

[0102] In any embodiment, the second electrode is larger than the first electrode because the second electrode has a cross-sectional area that is at least six times the cross-sectional area of ​​the first electrode.

[0103] In another aspect, reference Figure 13 The phase-change memory array includes multiple horizontal lines 1206 or 1279; multiple vertical lines 1210 or 1273 intersecting the multiple horizontal lines at multiple cell locations; and multiple phase-change memory cells 1202 or 1275 located at each of the multiple cell locations. Multiple transistors 1203, 1277 are associated with each of the multiple phase-change memory cells. Each phase-change memory cell can be any embodiment disclosed herein. Optionally, a controller 1289 may be provided to control reads, writes, MAC calculations, etc.

[0104] In another aspect, an exemplary method of operation includes providing array 1299 and using a controller to cause a first subset of the cells to store logic 1 and a second subset of the cells to store logic 0; and reading out the stored logic 1 and 0. Alternatively, an exemplary method of operation includes providing array 1297 and using a controller to cause MAC calculations to be performed.

[0105] In a further aspect, an exemplary method of forming a phase-change memory cell includes providing a starting structure including a substrate, an insulating layer outside the substrate, and a first electrode embedded in the insulating layer. The outer end of the first electrode is partially flush with the outer surface of the insulating layer. Further steps include depositing a highly oriented seed layer on the outer surface of the insulating layer and the outer end of the first electrode; epitaxially growing a homogeneous crystalline phase-change material layer on the highly oriented seed layer; and depositing a top electrode material on the homogeneous crystalline phase-change material layer. In one or more embodiments, for example, a thin (0.25-5 nm) seed layer having a crystal z-axis orientation perpendicular to the substrate is deposited, and a crystalline phase-change material layer having an orientation z-axis aligned with the z-axis of the seed layer is deposited. In one or more embodiments, the substrate may be charged using Ar sputtering prior to the crystallization deposition of the seed layer.

[0106] In a further aspect, another exemplary method of forming a phase change memory cell includes providing a starting structure, including a substrate, an insulating layer outside the substrate, and a first electrode embedded in the insulating layer. The outer end of the first electrode is partially flush with the outer surface of the insulating layer. Further steps include depositing an amorphous phase change material layer (e.g., at room temperature) on the outer surface of the insulating layer and the outer end of the first electrode; depositing a highly oriented seed layer on the outer surface of the amorphous phase change material layer at a temperature below the crystallization temperature of the first amorphous phase change material layer to produce the resulting structure; and annealing the resulting structure at a temperature above the crystallization temperature of the first amorphous phase change material layer, thereby inducing solid-phase crystallization of the amorphous phase change material layer by using the seed layer as a template. Optionally, a sputtering cleaning step can be used after the amorphous PCM deposition to remove oxides that may form during the temperature rise to the deposition temperature of the seed layer. Furthermore, this sputtering cleaning can deposit charge into the surface of the PCM layer, which can help orient the seed layer.

[0107] In a further aspect, another exemplary method of forming a phase-change memory cell includes providing a starting structure including a substrate, an insulating layer outside the substrate, and a first electrode embedded in the insulating layer. The outer end of the first electrode is partially flush with the outer surface of the insulating layer, and the insulating layer is amorphous. Further steps include preparing the outer surface of the amorphous insulating layer such that it aligns with the subsequently epitaxially grown homogeneous crystalline phase-change material layer; epitaxially growing the homogeneous crystalline phase-change layer on the prepared outer surface of the amorphous insulating layer at a temperature that allows the homogeneous crystalline phase-change layer to grow crystallinely; and depositing a top electrode material on the homogeneous crystalline phase-change material layer. Thus, in one or more such "seedless" embodiments: (i) an amorphous surface is prepared; and (ii) a PCM is deposited at a temperature (e.g., 150°C to 250°C) that allows the PCM to grow crystallinely. Preparing the amorphous surface may include, for example, depositing charges in the surface of the amorphous layer and selecting a PCM material to be organized in a highly oriented configuration during deposition. An example of such a PCM material is Sb₂Te₃.

[0108] Those skilled in the art will understand that the exemplary structures discussed above can be distributed as follows: as bare dies in their original form (i.e., a single wafer with multiple unpackaged chips), in package form, or incorporated as components of intermediate or final products that benefit from phase-change memory cells having crystal structures aligned with seed layers in a phase-change memory array.

[0109] The integrated circuits according to aspects of the present invention can be used in virtually any application and / or electronic system, wherein phase-change memory cells having a crystal structure aligned with a seed layer in the like of a phase-change memory array will be advantageous. Given the teachings of this disclosure provided herein, those skilled in the art will be able to conceive of other implementations and applications of the embodiments disclosed herein.

[0110] Now should refer to Figure 14 It describes a computing environment according to embodiments of the present invention (e.g., for implementing, etc.) Figure 15 (Design process).

[0111] Various aspects of this disclosure are described by narrative text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in embodiments of a computer program product (CPP). With respect to any flowchart, depending on the technology involved, operations may be performed in a different order than that shown in a given flowchart. For example, similarly, depending on the technology involved, two operations shown in consecutive flowchart blocks may be performed in reverse order, as a single integrated step, simultaneously, or in a manner that at least partially overlaps in time.

[0112] Computer Program Product Embodiment (“CPP Embodiment” or “CPP”) is a term used in this disclosure to describe any collection of one or more storage media (also referred to as “media”) collectively included in a collection of one or more storage devices, the collection of one or more storage devices collectively including machine-readable code corresponding to instructions and / or data for performing computer operations specified in a given CPP claim. A “storage device” is any tangible device capable of holding and storing instructions used by a computer processor. Without limitation, a computer-readable storage medium can be an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include: magnetic disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disc (DVD), memory sticks, floppy disks, mechanical encoding devices (such as punched cards or pits / platforms formed in the main surface of the disk), or any suitable combination of the foregoing. Computer-readable storage media, as used in this disclosure, should not be construed as storing transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides, optical pulses through fiber optic cables, electrical signals communicated through wires, and / or other transmission media. As those skilled in the art will understand, data is typically moved at certain incidental points in time during normal operation of the storage device, such as during access, defragmentation, or garbage collection; however, this does not make the storage device transient, because the data is not transient when it is stored.

[0113] Computing environment 100 includes examples of environments for executing at least some of the computer code involved in performing the methods of the present invention, such as system 200 for control of semiconductor design and / or semiconductor manufacturing (see...). Figure 15In addition to frame 200, computing environment 100 includes, for example, a computer 101, a wide area network (WAN) 102, an end-user equipment (EUD) 103, a remote server 104, a public cloud 105, and a private cloud 106. In this embodiment, computer 101 includes a processor set 110 (including processing circuitry 120 and cache 121), communication infrastructure 111, volatile memory 112, persistent storage device 113 (including operating system 122 and frame 200, as described above), peripheral device set 114 (including user interface (UI) device set 123, storage device 124, and Internet of Things (IoT) sensor set 125), and network module 115. Remote server 104 includes a remote database 130. Public cloud 105 includes a gateway 140, a cloud orchestration module 141, a host physical machine set 142, a virtual machine set 143, and a container set 144.

[0114] Computer 101 can take the form of a desktop computer, laptop computer, tablet computer, smartphone, smartwatch or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device now known or to be developed in the future capable of running programs, accessing networks, or querying databases such as remote database 130. As well understood in the field of computer technology, and depending on the technology, the execution of computer-implemented methods can be distributed across multiple computers and / or multiple locations. On the other hand, in this presentation of computing environment 100, detailed discussion focuses on a single computer, specifically computer 101, to keep the presentation as concise as possible. Computer 101 can reside in the cloud, even... Figure 14 It is not shown to be in the cloud. On the other hand, computer 101 does not need to be in the cloud unless it can be indicated with certainty in some way.

[0115] Processor set 110 includes one or more computer processors of any type now known or to be developed in the future. Processing circuitry 120 may be distributed across multiple packages, such as multiple cooperating integrated circuit chips. Processing circuitry 120 may implement multiple processor threads and / or multiple processor cores. Cache 121 is memory located within the processor chip package and is typically used for data or code that should be readily accessible by the threads or cores running on processor set 110. Cache memory is typically organized into multiple levels based on its relative proximity to the processing circuitry. Alternatively, some or all of the cache in the processor set may be located “off-chip.” In some computing environments, processor set 110 may be designed to work with qubits and perform quantum computing.

[0116] Computer-readable program instructions are typically loaded onto computer 101 to cause the processor set 110 of computer 101 to perform a series of operational steps to implement a computer-implemented method, such that the instructions thus executed instantiate the method specified in the computer-implemented flowcharts and / or descriptive descriptions included in this document (collectively, the “method of the invention”). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 121 and other storage media discussed below. The program instructions and associated data are accessed by processor set 110 to control and direct the execution of the method of the invention. In computing environment 100, at least some of the instructions for performing the method of the invention may be stored in persistent storage device 113 in block 200.

[0117] Communication structure 111 is a signal transmission path that allows various components of computer 101 to communicate with each other. Typically, this structure consists of switches and conductive paths, such as switches and conductive paths that form buses, bridges, physical input / output ports, etc. Other types of signal communication paths can be used, such as fiber optic communication paths and / or wireless communication paths.

[0118] Volatile memory 112 is any type of volatile memory now known or to be developed in the future. Examples include dynamic random access memory (RAM) or static RAM. Typically, volatile memory 112 is characterized by random access, but this is not necessary unless explicitly stated otherwise. In computer 101, volatile memory 112 is located in a single package and is internal to computer 101; however, alternatively or additionally, volatile memory may be distributed across multiple packages and / or located externally relative to computer 101.

[0119] The persistent storage device 113 is any form of non-volatile storage for a computer, now known or to be developed in the future. The non-volatility of this storage device means that the stored data is retained regardless of whether power is supplied to the computer 101 and / or directly to the persistent storage device 113. The persistent storage device 113 may be a read-only memory (ROM), but typically at least a portion of persistent storage allows for data writing, data deletion, and data rewriting. Some common forms of persistent storage include hard disks and solid-state storage devices. The operating system 122 may take several forms, such as various known proprietary operating systems or operating systems employing an open-source portable operating system interface type with a kernel. The code included in box 200 generally includes at least some of the computer code involved in performing the methods of the present invention.

[0120] Peripheral device set 114 includes a collection of peripheral devices for computer 101. Data communication connections between peripheral devices and other components of computer 101 can be implemented in various ways, such as Bluetooth connectivity, near field communication (NFC) connectivity, connections made by cables (such as Universal Serial Bus (USB) type cables), plug-in connections (e.g., Secure Digital (SD) cards), connections made via local area communication networks, and even connections made via wide area networks such as the Internet. In various embodiments, UI device set 123 may include components such as displays, speakers, microphones, wearable devices (such as goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. Storage device 124 is external storage, such as an external hard drive, or a pluggable storage device, such as an SD card. Storage device 124 can be permanent and / or volatile. In some embodiments, storage device 124 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer 101 requires a large amount of storage (e.g., where computer 101 locally stores and manages a large database), the storage device can be provided by a peripheral storage device designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 125 consists of sensors that can be used in IoT applications. For example, one sensor could be a thermometer, while another could be a motion detector.

[0121] Network module 115 is a collection of computer software, hardware, and firmware that allows computer 101 to communicate with other computers via WAN 102. Network module 115 may include hardware such as a modem or Wi-Fi transceiver, software for packetizing and / or unpacking communications over the network, and / or web browser software for transmitting data over the Internet. In some embodiments, the network control and network forwarding functions of network module 115 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN), the control and forwarding functions of network module 115 are performed on physically separate devices, such that the control function manages several different network hardware devices. Computer-readable program instructions for performing the methods of the present invention can typically be downloaded to computer 101 from an external computer or external storage device via a network adapter card or network interface included in network module 115.

[0122] WAN 102 is any wide area network (e.g., the Internet) capable of transmitting computer data over non-local distances using any technology known now or developed in the future for transmitting computer data. In some embodiments, WAN 102 may be replaced by and / or supplemented by a local area network (LAN) designed to transmit data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include computer hardware such as copper transmission cables, fiber optic cables, wireless transmission equipment, routers, firewalls, switches, gateway computers, and edge servers.

[0123] End User Equipment (EUD) 103 is any computer system used and controlled by an end user (e.g., a customer of the enterprise operating computer 101) and can take any of the forms discussed above in conjunction with computer 101. EUD 103 typically receives helpful and useful data from the operation of computer 101. For example, assuming computer 101 is designed to provide recommendations to the end user, these recommendations are typically transmitted from network module 115 of computer 101 to EUD 103 via WAN 102. In this way, EUD 103 can display or otherwise present the recommendations to the end user. In some embodiments, EUD 103 can be a client device, such as a thin client, a heavy client, a mainframe computer, a desktop computer, etc.

[0124] Remote server 104 is any computer system that provides at least some data and / or functionality to computer 101. Remote server 104 can be controlled and used by the same entity operating computer 101. Remote server 104 represents a machine that collects and stores helpful and useful data used by other computers, such as computer 101. For example, if computer 101 is designed and programmed to provide recommendations based on historical data, that historical data can be provided to computer 101 from a remote database 130 of remote server 104.

[0125] Public cloud 105 is any computer system that can be used by multiple entities, providing on-demand availability of computer system resources and / or other computing capabilities (particularly data storage (cloud storage) and computing power) without direct, active management by the user. Cloud computing typically leverages resource sharing to achieve scalability consistency and economy. Direct and active management of the computing resources of public cloud 105 is performed by the computer hardware and / or software of cloud orchestration module 141. The computing resources provided by public cloud 105 are typically implemented by virtual computing environments running on various computers constituting host physical set 142, which is the entirety of physical computers in and / or available to the public cloud 105. Virtual computing environments (VCEs) typically take the form of virtual machines from virtual machine set 143 and / or containers from container set 144. It should be understood that these VCEs can be stored as images and can be transferred between various physical machine hosts as images or after the VCEs are instantiated. Cloud orchestration module 141 manages the transfer and storage of images, deploys new instantiations of VCEs, and manages active instantiation of VCE deployments. Gateway 140 is a collection of computer software, hardware, and firmware that allow public cloud 105 to communicate via WAN 102.

[0126] Now, we will provide some further explanation of Virtualized Computing Environments (VCEs). A VCE can be stored as an "image." A new active instance of a VCE can be instantiated from this image. Two common types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature where the kernel allows multiple isolated user-space instances, called containers, to exist. From the perspective of the programs running within them, these isolated user-space instances typically appear as real computers. Computer programs running on a regular operating system can utilize all the resources of that computer, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, programs running within a container can only use the contents of the container and the devices allocated to the container; this is a characteristic known as containerization.

[0127] Private cloud 106 is similar to public cloud 105, except that computing resources are available only to a single enterprise. While private cloud 106 is depicted as communicating with WAN 102, in other embodiments, private cloud may be completely disconnected from the internet and accessible only via a local / private network. A hybrid cloud is a combination of multiple clouds of different types (e.g., private, community, or public cloud types) typically implemented by different providers. Each of the multiple clouds remains a separate and discrete entity, but the larger hybrid cloud architecture is bound together by standardization or proprietary technology that enables orchestration, management, and / or data / application portability across the multiple component clouds. In this embodiment, public cloud 105 and private cloud 106 are both part of a larger hybrid cloud.

[0128] Exemplary design process for semiconductor design, manufacturing, and / or testing

[0129] One or more embodiments utilize computer-aided semiconductor integrated circuit design simulation, testing, placement, and / or fabrication. In this respect, Figure 15 A block diagram of an exemplary design flow 700 used, for example, in semiconductor IC logic design, simulation, testing, placement, and manufacturing is shown. Design flow 700 includes processes, machines, and / or mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of the design structures and / or devices, such as those that can be analyzed using the techniques disclosed herein. Design structures processed and / or generated by design flow 700 may be encoded on a machine-readable storage medium to include data and / or instructions that, when executed on a data processing system or otherwise processed, generate logically, structurally, mechanically, or otherwise functionally equivalent representations of hardware components, circuits, devices, or systems. Machines include, but are not limited to, any machine used in the IC design process, such as for designing, manufacturing, or simulating circuits, components, devices, or systems. For example, machines may include: lithography machines, machines and / or apparatus for generating masks (e.g., electron beam writers), computers or apparatus for simulating design structures, any means for manufacturing or testing processes, or any machine for programming a functionally equivalent representation of a design structure to any medium (e.g., a machine for programming programmable gate arrays).

[0130] Design flow 700 can vary depending on the type of representation being designed. For example, design flow 700 for building application-specific integrated circuits (ASICs) may differ from design flow 700 for designing standard components or design flow 700 for instantiating designs into programmable arrays such as programmable gate arrays (PGAs) or field-programmable gate arrays (FPGAs) provided by companies such as Altera or Xilinx.

[0131] Figure 15Several such design structures are described, including an input design structure 720 preferably processed by design process 710. Design structure 720 can be a logical simulation design structure generated and processed by design process 710 to produce a logically equivalent functional representation of a hardware device. Design structure 720 may also, or alternatively, include data and / or program instructions that generate a functional representation of the physical structure of the hardware device when processed by design process 710. Whether representing functional and / or structural design features, design structure 720 can be generated using electronic computer-aided design (ECAD) implemented by a core developer / designer. When encoded on a gate array or storage medium, design structure 720 can be accessed and processed by one or more hardware and / or software modules within design process 710 to simulate or otherwise functionally represent electronic components, circuits, electronic or logic modules, devices, equipment, or systems. Thus, design structure 720 may include files or other data structures, including human- and / or machine-readable source code, compiled structures, and computer-executable code structures, which, when processed by a design or simulation data processing system, functionally simulate or otherwise represent a circuit or other level of hardware logic design. Such data structures may include hardware description language (HDL) design entities or other data structures that conform to and / or are compatible with low-level HDL design languages ​​such as Verilog and VHDL and / or high-level design languages ​​such as C or C++.

[0132] Design process 710 preferably employs and integrates hardware and / or software modules for synthesizing, transforming, or otherwise processing design / simulation functional equivalents of components, circuits, devices, or logic structures to generate a netlist 780 that may contain design structures such as design structure 720. Netlist 780 may include, for example, compiled or otherwise processed data structures representing lists of wires, discrete components, logic gates, control circuits, I / O devices, models, etc., describing connections to other elements and circuits in the integrated circuit design. Netlist 780 may be synthesized using an iterative process, wherein netlist 780 is resynthesized once or multiple times according to design specifications and parameters for the device. As with other design structure types described herein, netlist 780 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array (FPGA). The medium may be a non-volatile storage medium, such as a disk or optical disc drive, a programmable gate array, compact flash memory, or other flash memory. Alternatively, the medium may be system or cache memory, buffer space, or other suitable memory.

[0133] Design process 710 may include hardware and software modules for processing various input data structure types, including netlist 780. Such data structure types may reside, for example, within library elements 730 and include a set of commonly used components, circuits, and devices, including models, layouts, and symbolic representations for a given manufacturing technology (e.g., different technology nodes, 32nm, 45nm, 90nm, etc.). Data structure types may also include design specifications 740, feature data 750, verification data 760, design rules 770, and test data files 785 that may include input test patterns, output test results, and other test information. Design process 710 may also include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and compression molding. Those skilled in the art of mechanical design can understand the extent to which possible mechanical design tools and applications are used in design process 710 without departing from the scope of the invention. Design process 710 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, placement, and routing operations.

[0134] Design process 710 employs and combines logic and physical design tools, such as HDL compilers and simulation model building tools, to process design structure 720 along with some or all of the depicted supporting data structures and any additional mechanical design or data (if applicable) to generate a second design structure 790. Design structure 790 resides on a storage medium or programmable gate array in a data format used for data exchange of mechanical devices and structures (e.g., information stored in IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format used to store or present such mechanical design structures). Similar to design structure 720, design structure 790 preferably includes one or more files, data structures, or other computer-coded data or instructions residing on a data storage medium and, when processed by an ECAD system, producing one or more IC designs, etc., in a logically or otherwise functionally equivalent form. In one embodiment, design structure 790 may include a compiled executable HDL simulation model that functionally simulates the device to be analyzed.

[0135] Design structure 790 may also employ data formats and / or symbol data formats used for exchanging layout data for integrated circuits (e.g., information stored in GDSII (GDS2), GL1, OASIS, mapping files, or any other suitable format used to store such design data structures). Design structure 790 may include information such as symbol data, mapping files, test data files, design content files, manufacturing data, layout parameters, wires, metal layers, vias, shapes, data for routing through the production line, and any other data (e.g., .lib files) required by the manufacturer or other designer / developer to produce the device or structure as described herein. Design structure 790 may then proceed to stage 795, where, for example, design structure 790: is fabricated, released to manufacturing, released to a mask room, sent to another design room, sent back to the customer, etc.

[0136] The embodiments described herein are intended to provide a general understanding of various embodiments and are not intended to serve as a complete description of all elements and features of apparatuses and systems that may utilize the circuitry and techniques described herein. Many other embodiments will become apparent to those skilled in the art based on the teachings herein; other embodiments may be utilized and derived therefrom, allowing for structural and logical substitutions and changes without departing from the scope of this disclosure. It should also be noted that in some alternative implementations, some steps of the exemplary method may occur in a different order than shown in the figures. For example, two steps shown consecutively may actually be performed substantially simultaneously, or certain steps may sometimes be performed in reverse order, depending on the functionality involved. The figures are also merely representative and not drawn to scale. Accordingly, the specification and figures should be considered illustrative rather than restrictive.

[0137] In this document, if more than one embodiment is actually shown, the embodiment is referred to individually and / or collectively by the term "embodiment" for convenience only and is not intended to limit the scope of this application to any single embodiment or inventive concept. Therefore, although specific embodiments have been illustrated and described herein, it should be understood that arrangements for achieving the same purpose may substitute for the illustrated specific embodiment(s); that is, this disclosure is intended to cover any and all adaptations or variations of the various embodiments. Combinations of the above embodiments, as well as other embodiments not specifically described herein, will become apparent to those skilled in the art from the teachings herein.

[0138] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising” and / or “including” as used in this specification specify the presence of stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. Terms such as “bottom,” “top,” “up,” “above,” “below,” and “under” are used to indicate the relative positioning of elements or structures relative to each other, rather than relative height. If a layer of a structure is described herein as being “above” another layer, it will be understood that there may or may not be an intermediate element or layer between the two specified layers. If a layer is described as being “directly on” another layer, it indicates direct contact between the two layers. As used herein and in the appended claims, “about” means within plus or minus ten percent.

[0139] The corresponding structures, materials, actions, and equivalents of any means or steps plus functional elements in the following claims are intended to include any structures, materials, or actions for performing functions in combination with other elements described as specifically described. Various embodiments have been presented for purposes of illustration and description, but are not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the invention. The embodiments chosen and described are intended to best explain the principles and practical application, and to enable others skilled in the art to understand the various embodiments with various modifications suitable for the particular purpose contemplated.

[0140] An abstract is provided to comply with 37 CFR § 1.76(b), which requires that the reader quickly determine the nature of the technical disclosure. It is understood that this abstract is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, it can be seen that various features are grouped together in a single embodiment for the purpose of fluent disclosure. This method of disclosure should not be construed as reflecting an intention that the claimed embodiment requires more features than expressly recited in each claim. Rather, as reflected in the appended claims, the claimed subject matter may comprise fewer than all features of a single embodiment. Therefore, the following claims are thereby incorporated into the detailed description, wherein each claim is independently claimed as a separate subject matter.

[0141] Given the teachings provided herein, those skilled in the art will be able to conceive of other implementations and applications of the techniques and disclosed embodiments. Although illustrative embodiments have been described herein with reference to the accompanying drawings, it should be understood that the illustrative embodiments are not limited to those precise embodiments, and various other changes and modifications can be made therein by those skilled in the art without departing from the scope of the appended claims.

Claims

1. A phase-change memory cell, comprising: Insulating layer; A first electrode is embedded in the insulating layer, wherein the outer end of the first electrode is partially flush with the outer surface of the insulating layer. The second electrode is larger than the first electrode and is spaced apart from the first electrode; A homogeneous crystalline phase change material layer; as well as A highly oriented seed layer, wherein the crystal structure of the homogeneous phase change material layer is related to the crystal structure of the highly oriented seed layer; The homogeneous phase change material layer and the highly oriented seed layer are located at least partially between the first electrode and the second electrode.

2. The phase change memory cell according to claim 1, wherein the homogeneous phase change material layer and the highly oriented seed layer are made of different materials.

3. The phase change memory cell according to claim 2, wherein the seed layer has an out-of-plane crystal axis, and the homogeneous phase change material layer has an out-of-plane crystal axis aligned with the out-of-plane crystal axis of the seed layer.

4. The phase-change memory cell according to claim 3, wherein the seed layer is selected from Ti. x Te y and Sb x Te y A group consisting of...

5. The phase change memory cell of claim 3, wherein the homogeneous phase change material layer comprises van der Waals gaps.

6. The phase change memory cell according to claim 3, wherein the homogeneous phase change material layer and the seed layer each have a crystal orientation.

7. The phase change memory unit according to claim 3, wherein the homogeneous phase change material is selected from GST and Sb. x Te y A group consisting of [groups].

8. The phase change memory cell of claim 7, wherein the seed layer and the homogeneous phase change material are selected from the group consisting of: The seed layer of 0.25-5nm TiTe2 and the homogeneous crystalline phase change material layer of 1-100nm Sb2Te3; The seed layer of 0.25-5 nm TiTe2 and the homogeneous crystalline phase change material layer of 1-100 nm Ge2Sb2Te5; and The seed layer of 0.25-5nm Sb2Te3 and the homogeneous crystalline phase change material layer of 1-100nm Ge2Sb2Te5.

9. The phase-change memory cell according to claim 3, wherein: The seed layer is typically planar and located outside the insulating layer; The homogeneous phase change material layer is typically planar and located outside the seed layer; and The second electrode is typically planar and located outside the homogeneous phase change material layer.

10. The phase-change memory cell according to claim 3, wherein: The homogeneous phase change material layer is typically planar and located outside the insulating layer; The seed layer is typically planar and located outside the homogeneous phase change material layer; as well as The second electrode is typically planar and located outside the seed layer.

11. The phase change memory cell according to claim 3, wherein the seed layer comprises a first seed layer of non-phase change material, and the phase change memory cell further comprises a second seed layer of phase change material, wherein: The first seed layer is typically planar and located outside the insulating layer; The second seed layer is typically planar and located outside the first seed layer; The homogeneous phase change material layer is typically planar and located outside the second seed layer; and The second electrode is typically planar and located outside the homogeneous phase change material layer.

12. The phase change memory cell of claim 11, wherein the first seed layer comprises 0.25-5 nm TiTe2, the second seed layer comprises 1-5 nm Sb2Te3, and the homogeneous phase change material layer comprises 1-100 nm Ge2Sb2Te5.

13. The phase-change memory cell according to claim 3, wherein: The first electrode has a generally vertical portion and a horizontal protrusion; The insulating layer has a stepped region, and the horizontal protrusion of the first electrode extends to the surface of the stepped region. The seed layer is outside the insulating layer and contacts the horizontal protrusion and the stepped region of the first electrode; The homogeneous phase change material layer is located outside the seed layer; and The second electrode is located outside the homogeneous phase change material layer.

14. The phase-change memory cell according to claim 3, wherein: The seed layer is outside the insulating layer; The homogeneous phase change material layer is located outside the seed layer; and The second electrode is located on at least one side of the homogeneous phase change material layer and the seed layer.

15. The phase-change memory cell according to claim 3, wherein: The homogeneous phase change material layer is located outside the insulating layer; The second electrode is located outside the homogeneous phase change material layer; and The seed layer is located on one side of the homogeneous phase change material layer.

16. The phase-change memory cell according to claim 3, wherein: The homogeneous phase change material layer is located outside the insulating layer of the substrate; The second electrode is located outside the homogeneous phase change material layer; as well as The seed layer is located within the homogeneous phase change material layer.

17. The phase-change memory cell of claim 3, wherein the second electrode is larger than the first electrode in that the second electrode has a cross-sectional area at least 6 times that of the first electrode.

18. A phase-change memory array, comprising: Multiple horizontal lines; Multiple vertical lines, which intersect multiple horizontal lines at multiple unit positions; Multiple phase-change memory cells located at each of the plurality of cell locations; as well as Multiple transistors associated with each of the plurality of phase-change memory cells; Each of the phase-change memory cells includes: Insulating layer; A first electrode is embedded in the insulating layer, wherein the outer end of the first electrode is partially flush with the outer surface of the insulating layer. The second electrode is larger than the first electrode and is spaced apart from the first electrode; A homogeneous crystalline phase change material layer; and A highly oriented seed layer, wherein the crystal structure of the homogeneous phase change material layer is related to the crystal structure of the highly oriented seed layer; The homogeneous phase change material layer and the highly oriented seed layer are located at least partially between the first electrode and the second electrode.

19. The phase change memory array of claim 18, wherein the homogeneous phase change material layer and the highly oriented seed layer are made of different materials.

20. The phase change memory array of claim 19, wherein the seed layer has an out-of-plane crystal axis, and the homogeneous phase change material layer has an out-of-plane crystal axis aligned with the out-of-plane crystal axis of the seed layer.

21. The phase change memory array of claim 20, wherein the homogeneous phase change material layer comprises van der Waals gaps.

22. The phase change memory array according to claim 21, wherein the homogeneous phase change material layer and the seed layer each have a crystal orientation.

23. A method for forming a phase-change memory cell, comprising: A starting structure is provided, the starting structure including a substrate, an insulating layer outside the substrate, and a first electrode embedded in the insulating layer, wherein the outer end of the first electrode is partially flush with the outer surface of the insulating layer; A highly oriented seed layer is deposited on the outer surface of the insulating layer and the outer end of the first electrode; A homogeneous crystalline phase change material layer is epitaxially grown on the highly oriented seed layer; and A top electrode material is deposited on the homogeneous crystalline phase change material layer.

24. A method for forming a phase-change memory cell, comprising: A starting structure is provided, the starting structure including a substrate, an insulating layer outside the substrate, and a first electrode embedded in the insulating layer, wherein the outer end of the first electrode is partially flush with the outer surface of the insulating layer; An amorphous phase change material layer is deposited on the outer surface of the insulating layer and the outer end of the first electrode; A highly oriented seed layer of crystals is deposited on the outer surface of the amorphous phase change material layer at a temperature lower than the crystallization temperature of the first amorphous phase change material layer to produce the resulting structure. as well as The obtained structure is annealed at a temperature higher than the crystallization temperature of the first amorphous phase change material layer to induce solid-phase crystallization of the amorphous phase change material layer by using the seed layer as a template.

25. A method for forming a phase-change memory cell, comprising: A starting structure is provided, the starting structure including a substrate, an insulating layer outside the substrate, and a first electrode embedded in the insulating layer, wherein the outer end of the first electrode is partially flush with the outer surface of the insulating layer, and the insulating layer is amorphous; Prepare the outer surface of the amorphous insulating layer so as to orient the subsequently epitaxially grown homogeneous crystalline phase change material layer; At a temperature that allows the homogeneous crystalline phase change layer to grow in a crystalline manner, a homogeneous crystalline phase change material layer is epitaxially grown on the outer surface of the prepared amorphous insulating layer; and A top electrode material is deposited on the homogeneous crystalline phase change material layer.

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